CN114783382B

CN114783382B - Pixel circuit, driving method thereof, display panel and display device

Info

Publication number: CN114783382B
Application number: CN202210303724.8A
Authority: CN
Inventors: 王苗; 宋江; 肖云升; 青海刚
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-03-24
Filing date: 2022-03-24
Publication date: 2023-12-26
Anticipated expiration: 2042-03-24
Also published as: CN114783382A

Abstract

According to the pixel circuit, the driving method thereof, the display panel and the display device, the auxiliary control circuit is coupled with the compensation node, so that the auxiliary control circuit can respond to the signal of the second scanning signal end to provide the auxiliary voltage of the auxiliary signal end to the compensation node. The auxiliary voltage is related to the data voltage, so that the voltage of the compensation node is related to the data voltage after the auxiliary voltage is provided to the compensation node, the voltage of the grid electrode of the light-emitting driving transistor can be reduced, and the voltage stability of the grid electrode of the light-emitting driving transistor is improved due to leakage current generated in a leakage current path formed by the first threshold compensation circuit and the second threshold compensation circuit. Particularly, after the pixel circuit is applied to the display panel, the flicker problem of the display panel is reduced when the display panel is driven by a lower refresh frequency.

Description

Pixel circuit, driving method thereof, display panel and display device

Technical Field

The disclosure relates to the field of display technology, and in particular relates to a pixel circuit, a driving method thereof, a display panel and a display device.

Background

Electroluminescent diodes such as organic light emitting diodes (Organic Light Emitting Diode, OLED), quantum dot light emitting diodes (Quantum Dot Light Emitting Diodes, QLED), micro light emitting diodes (Micro Light Emitting Diode, micro LED) and the like have the advantages of self luminescence, low energy consumption and the like, and are one of hot spots in the application research field of current electroluminescent display devices. In general, a pixel circuit is used in an electroluminescent display device to drive an electroluminescent diode to emit light.

Disclosure of Invention

The pixel circuit, the driving method thereof, the display panel and the display device provided by the embodiment of the disclosure can improve the voltage stability of the grid electrode of the light-emitting driving transistor. Especially, when the display panel is driven with a lower refresh frequency after the pixel circuit is applied to the display panel, the Flicker (Flicker) problem of the display panel is reduced.

The pixel circuit provided by the embodiment of the disclosure comprises:

a light emitting device;

a light emitting driving transistor having a first electrode coupled to the light emitting device and configured to generate an operating current for driving the light emitting device to emit light according to a data voltage;

a data input circuit coupled to the light emitting driving transistor, and configured to input a data voltage applied to a data signal terminal in response to a signal of a first scan signal terminal;

A first threshold compensation circuit coupled to the first pole of the light-emitting drive transistor and the compensation node, and configured to turn on the first pole of the light-emitting drive transistor and the compensation node in response to a signal of the first scan signal terminal;

a second threshold compensation circuit coupled to the gate of the light emitting drive transistor and the compensation node, and configured to turn on the gate of the light emitting drive transistor and the compensation node in response to a signal of the first scan signal terminal;

an auxiliary control circuit coupled to the compensation node, and configured to provide an auxiliary voltage of an auxiliary signal terminal to the compensation node in response to a signal of a second scan signal terminal; wherein the auxiliary voltage is related to the data voltage.

In some examples, the auxiliary control circuit includes a first transistor;

the grid electrode of the first transistor is coupled with the second scanning signal end, the first electrode of the first transistor is coupled with the auxiliary signal end, and the second electrode of the first transistor is coupled with the compensation node.

In some examples, the first threshold compensation circuit includes a second transistor; the grid electrode of the second transistor is coupled with the first scanning signal end, the first electrode of the second transistor is coupled with the first electrode of the light-emitting driving transistor, and the second electrode of the second transistor is coupled with the compensation node;

and/or the second threshold compensation circuit comprises a third transistor; the grid electrode of the third transistor is coupled with the first scanning signal end, the first electrode of the third transistor is coupled with the compensation node, and the second electrode of the second transistor is coupled with the grid electrode of the light-emitting driving transistor.

In some examples, the data input circuit includes a fourth transistor; the grid electrode of the fourth transistor is coupled with the first scanning signal end, the first electrode of the fourth transistor is coupled with the data signal end, and the second electrode of the fourth transistor is coupled with the second electrode of the light-emitting driving transistor.

In some examples, the pixel circuit further comprises: a light emission control circuit; wherein the light emission control circuit is configured to supply a signal of a first power supply terminal to a second electrode of the light emission driving transistor in response to a signal of a first light emission control signal terminal, and to turn on the first electrode of the light emission driving transistor with the light emitting device;

And/or, the pixel circuit further comprises: a storage circuit configured to store a voltage input to a gate of the light-emitting drive transistor;

and/or, the pixel circuit further comprises: initializing a circuit; wherein the initialization circuit is configured to supply a signal of a first initialization signal terminal to the gate of the light-emitting driving transistor in response to a signal of a reset signal terminal;

and/or, the pixel circuit further comprises: a light emission adjusting circuit; wherein the light emission adjusting circuit is configured to supply a signal of a second initialization signal terminal to the light emitting device in response to a signal of a second light emission control signal terminal.

In some examples, the light emission control circuit includes a fifth transistor and a sixth transistor; wherein, the grid electrode of the fifth transistor is coupled with the first light-emitting control signal end, the first electrode of the fifth transistor is coupled with the first power end, and the second electrode of the fifth transistor is coupled with the second electrode of the light-emitting driving transistor; the gate of the sixth transistor is coupled to the first light emitting control signal terminal, the first electrode of the sixth transistor is coupled to the first electrode of the light emitting driving transistor, and the second electrode of the sixth transistor is coupled to the light emitting device.

And/or the memory circuit comprises: a storage capacitor; the first electrode plate of the storage capacitor is coupled with the grid electrode of the light-emitting driving transistor, and the second electrode plate of the storage capacitor is coupled with the second electrode of the light-emitting driving transistor;

and/or the initialization circuit includes a seventh transistor; wherein, the grid electrode of the seventh transistor is coupled with the reset signal end, the first electrode of the seventh transistor is coupled with the first initialization signal end, and the second electrode of the seventh transistor is coupled with the grid electrode of the light-emitting driving transistor;

and/or, the light-emitting adjusting circuit includes an eighth transistor; the gate of the eighth transistor is coupled to the second light-emitting control signal terminal, the first electrode of the eighth transistor is coupled to the second initialization signal terminal, and the second electrode of the eighth transistor is coupled to the light-emitting device.

The display panel provided by the embodiment of the disclosure comprises:

a plurality of sub-pixels; wherein each of the sub-pixels includes the pixel circuit described above.

In some examples, the display panel further comprises:

a plurality of auxiliary signal lines; wherein, the auxiliary signal end of the pixel circuit in a row of sub-pixels is coupled with an auxiliary signal line;

A plurality of data signal lines; the data signal end of the pixel circuit in one row of sub-pixels is coupled with one data signal line;

a plurality of second scanning signal lines; the second scanning signal end of the pixel circuit in one row of sub-pixels is coupled with one second scanning signal line.

In some examples, the display panel further comprises:

a plurality of auxiliary input circuits, wherein one auxiliary input circuit corresponds to one column of sub-pixels, and the auxiliary input circuits are respectively coupled with auxiliary signal lines and data signal lines coupled with the corresponding sub-pixels;

the auxiliary input circuit is configured to generate an auxiliary voltage according to a data voltage on the data signal line when the data signal terminal coupled through the data signal line is applied with the data voltage, and to input the generated auxiliary voltage to the coupled auxiliary signal line.

In some examples, the auxiliary input circuit includes:

an auxiliary drive transistor having a gate coupled to a corresponding data signal terminal, a first pole coupled to a corresponding auxiliary signal line, and configured to generate an auxiliary current according to a data voltage on the data signal line;

And a control circuit coupled to the first pole of the auxiliary driving transistor, configured to adjust a voltage of the first pole of the auxiliary driving transistor according to the auxiliary current, and input the adjusted voltage as the auxiliary voltage onto the coupled auxiliary signal line.

In some examples, the control circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

a first end of the first resistor is coupled with a first reference signal end, and a second end of the first resistor is coupled with a first pole of the auxiliary driving transistor and the auxiliary signal line;

a first end of the second resistor is coupled with the first reference signal end, and a second end of the second resistor is coupled with a second pole of the auxiliary driving transistor;

a first end of the third resistor is coupled with a second pole of the auxiliary driving transistor, and a second end of the third resistor is coupled with a first pole of the auxiliary driving transistor;

a first end of the fourth resistor is coupled with a first pole of the auxiliary driving transistor, and a second end of the fourth resistor is coupled with a grid electrode of the auxiliary driving transistor;

the first end of the fifth resistor is coupled to the second reference signal end, and the second end of the fifth resistor is coupled to the first pole of the auxiliary driving transistor.

In some examples, the auxiliary input circuit further comprises: a sixth resistor; wherein the data signal line is coupled with the gate of the auxiliary driving transistor through the sixth resistor;

and/or, the auxiliary input circuit further comprises: an auxiliary control transistor and a seventh resistor; the first pole of the auxiliary driving transistor is coupled with the corresponding auxiliary signal line through the auxiliary control transistor, and the grid electrode of the auxiliary transistor is coupled with the third reference signal end through the seventh resistor.

The display device provided by the embodiment of the disclosure comprises the display panel.

The driving method for the pixel circuit provided by the embodiment of the disclosure comprises the following steps:

a data writing stage, wherein the data input circuit responds to the signal of the first scanning signal end and inputs the data voltage loaded to the data signal end; the first threshold compensation circuit responds to the signal of the first scanning signal end and conducts the first pole of the light-emitting driving transistor and the compensation node; the second threshold compensation circuit responds to the signal of the first scanning signal end and conducts the grid electrode of the light-emitting driving transistor and the compensation node;

An auxiliary stage, in which the auxiliary control circuit responds to the signal of the second scanning signal terminal and provides the auxiliary voltage of the auxiliary signal terminal to the compensation node;

and in the light-emitting stage, the light-emitting driving transistor generates working current for driving the light-emitting device to emit light according to the data voltage, and drives the light-emitting device to emit light.

In some examples, prior to the data writing phase, further comprising: an initialization stage, in which the initialization circuit responds to the signal of the reset signal terminal and provides the signal of the first initialization signal terminal to the grid electrode of the light-emitting driving transistor; the light-emitting adjusting circuit responds to the signal of the second light-emitting control signal end and provides the signal of the second initialization signal end to the light-emitting device;

and/or, the lighting phase comprises: a light emitting sub-stage and a light emitting adjustment sub-stage;

in the light emitting sub-stage, the light emission control circuit is configured to supply a signal of a first power supply terminal to a second electrode of the light emission driving transistor in response to a signal of a first light emission control signal terminal, and to turn on the first electrode of the light emission driving transistor with the light emitting device; the light-emitting driving transistor generates working current for driving the light-emitting device to emit light according to the data voltage and drives the light-emitting device to emit light;

In the light emission adjustment sub-stage, the light emission adjustment circuit supplies a signal of a second initialization signal terminal to the light emitting device in response to a signal of a second light emission control signal terminal.

According to the pixel circuit, the driving method thereof, the display panel and the display device, the auxiliary control circuit is coupled with the compensation node, so that the auxiliary control circuit can respond to the signal of the second scanning signal end to provide the auxiliary voltage of the auxiliary signal end to the compensation node. The auxiliary voltage is related to the data voltage, so that the voltage of the compensation node is related to the data voltage after the auxiliary voltage is provided to the compensation node, the voltage of the grid electrode of the light-emitting driving transistor can be reduced, and the voltage stability of the grid electrode of the light-emitting driving transistor is improved due to leakage current generated in a leakage current path formed by the first threshold compensation circuit and the second threshold compensation circuit. Especially, when the display panel is driven with a lower refresh frequency after the pixel circuit is applied to the display panel, the Flicker (Flicker) problem of the display panel is reduced.

Drawings

FIG. 1 is a schematic diagram of some configurations of pixel circuits in an embodiment of the disclosure;

FIG. 2 is a schematic diagram of other structures of a pixel circuit according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of still other structures of pixel circuits in an embodiment of the disclosure;

FIG. 4 is a timing diagram of some signals in an embodiment of the present disclosure;

FIG. 5 is a timing diagram of other signals in an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of still other configurations of pixel circuits in an embodiment of the disclosure;

FIG. 7 is a schematic diagram of some structures of a display panel according to an embodiment of the disclosure;

FIG. 8 is a schematic view of other structures of a display panel according to an embodiment of the disclosure;

FIG. 9 is a schematic diagram of some configurations of auxiliary input circuits in embodiments of the present disclosure;

FIG. 10 is a schematic diagram of other configurations of auxiliary input circuits in an embodiment of the present disclosure;

fig. 11 is a schematic diagram of still other structures of auxiliary input circuits in an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. And embodiments of the disclosure and features of embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the dimensions and shapes of the various figures in the drawings do not reflect true proportions, and are intended to illustrate the present disclosure only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

The pixel circuit provided in the embodiment of the disclosure, as shown in fig. 1, may include:

a light emitting device L;

a light emitting driving transistor M0, a first electrode of the light emitting driving transistor M0 being coupled to the light emitting device L, and the light emitting driving transistor M0 being configured to generate an operating current for driving the light emitting device L to emit light according to the data voltage;

A data input circuit 10 coupled to the light emitting driving transistor M0, and the data input circuit 10 is configured to input a data voltage applied to the data signal terminal DA in response to a signal of the first scan signal terminal GA 1;

a first threshold compensation circuit 20 coupled to the first pole of the light emitting driving transistor M0 and the compensation node N0, and the first threshold compensation circuit 20 is configured to turn on the first pole of the light emitting driving transistor M0 and the compensation node N0 in response to the signal of the first scan signal terminal GA 1;

a second threshold compensation circuit 30 coupled to the gate of the light emitting driving transistor M0 and the compensation node N0, and the second threshold compensation circuit 30 is configured to turn on the gate of the light emitting driving transistor M0 and the compensation node N0 in response to the signal of the first scan signal terminal GA 1;

an auxiliary control circuit 40 coupled to the compensation node N0, and the auxiliary control circuit 40 is configured to provide an auxiliary voltage of the auxiliary signal terminal VF to the compensation node N0 in response to the signal of the second scan signal terminal GA 2; wherein the auxiliary voltage is related to the data voltage.

According to the pixel circuit provided by the embodiment of the disclosure, the auxiliary control circuit is coupled with the compensation node, so that the auxiliary control circuit responds to the signal of the second scanning signal end and provides the auxiliary voltage of the auxiliary signal end to the compensation node. The auxiliary voltage is related to the data voltage, so that the voltage of the compensation node is related to the data voltage after the auxiliary voltage is provided to the compensation node, the voltage of the grid electrode of the light-emitting driving transistor can be reduced, and the voltage stability of the grid electrode of the light-emitting driving transistor is improved due to leakage current generated in a leakage current path formed by the first threshold compensation circuit and the second threshold compensation circuit. Especially, when the display panel is driven with a lower refresh frequency after the pixel circuit is applied to the display panel, the Flicker (Flicker) problem of the display panel is reduced.

For example, a display panel may have multiple refresh frequencies: 240Hz, 120Hz, 90Hz, 60Hz, 30Hz, 1Hz and the like, wherein 240Hz can be used as the maximum refresh frequency, 120Hz, 90Hz, 60Hz, 30Hz and 1Hz can be used as the lower refresh frequency, and after the pixel circuit provided by the embodiment of the disclosure is applied to the display panel, the Flicker (Flicker) problem of the display panel is reduced when the display panel is driven by adopting the lower refresh frequency.

In practice, in the embodiment of the present disclosure, the first electrode of the light emitting device L is coupled to the first electrode of the light emitting driving transistor M0, and the second electrode of the light emitting device L is coupled to the second power source terminal VSS. The first electrode of the light emitting device L may be a positive electrode thereof, and the second electrode may be a negative electrode thereof. Also, the light emitting device L is typically an electroluminescent diode, and for example, the light emitting device L may include: at least one of a Micro light emitting diode (Micro Light Emitting Diode, micro LED), an organic light emitting diode (Organic Light Emitting Diode, OLED), and a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED). In addition, the light emitting device L generally has a light emission threshold voltage, and emits light when a voltage across the light emitting device L is equal to or higher than the light emission threshold voltage. In practical applications, the specific structure of the light emitting device L may be designed and determined according to practical application environments, which is not limited herein.

In implementation, in the embodiment of the present disclosure, as shown in fig. 1, the light-emitting driving transistor M0 may be a P-type transistor; the second electrode of the light-emitting driving transistor M0 is the source electrode thereof, the first electrode of the light-emitting driving transistor M0 is the drain electrode thereof, and when the light-emitting driving transistor M0 is in a saturated state, a current flows from the source electrode of the light-emitting driving transistor M0 to the drain electrode thereof. Of course, the light-emitting driving transistor M0 may be an N-type transistor, and is not limited thereto.

In particular implementations, in embodiments of the present disclosure, as shown in fig. 1, the pixel circuit may further include: a light emission control circuit 50; wherein the light emission control circuit 50 is configured to supply a signal of the first power supply terminal to the second electrode of the light emission driving transistor M0 in response to the signal of the first light emission control signal terminal EM1, and to turn on the first electrode of the light emission driving transistor M0 with the light emitting device L.

In particular implementations, in embodiments of the present disclosure, as shown in fig. 1, the pixel circuit may further include: a storage circuit 60, wherein the storage circuit 60 is configured to store a voltage input to the gate of the light emission driving transistor M0.

In implementation, in an embodiment of the present disclosure, as shown in fig. 2, the pixel circuit may further include: an initialization circuit 70; wherein the initialization circuit 70 is configured to supply a signal of the first initialization signal terminal VINIT1 to the gate of the light emitting driving transistor M0 in response to a signal of the reset signal terminal RES.

In implementation, in an embodiment of the present disclosure, as shown in fig. 2, the pixel circuit may further include: a light emission adjustment circuit 80; wherein the light emission adjusting circuit 80 is configured to supply the signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to the signal of the second light emission control signal terminal EM 2.

In particular implementations, in embodiments of the present disclosure, as shown in fig. 3, the auxiliary control circuit 40 may include a first transistor M1; the gate of the first transistor M1 is coupled to the second scan signal terminal GA2, the first pole of the first transistor M1 is coupled to the auxiliary signal terminal VF, and the second pole of the first transistor M1 is coupled to the compensation node N0.

Illustratively, as shown in fig. 3, the first transistor M1 may be configured as a P-type transistor, and the first transistor M1 is turned on under control of a low level of a signal loaded at the second scan signal terminal GA2 and turned off under control of a high level of a signal loaded at the second scan signal terminal GA 2. Alternatively, the first transistor M1 may be an N-type transistor, and the first transistor M1 is turned on under the control of the high level of the signal applied to the second scan signal terminal GA2 and turned off under the control of the low level of the signal applied to the second scan signal terminal GA 2.

In particular implementations, in embodiments of the present disclosure, as shown in fig. 3, the first threshold compensation circuit 20 may include a second transistor M2; the gate of the second transistor M2 is coupled to the first scan signal terminal GA1, the first electrode of the second transistor M2 is coupled to the first electrode of the light-emitting driving transistor M0, and the second electrode of the second transistor M2 is coupled to the compensation node N0.

Illustratively, as shown in fig. 3, the second transistor M2 may be set as a P-type transistor, and the second transistor M2 is turned on under control of a low level of a signal loaded by the first scan signal terminal GA1 and turned off under control of a high level of a signal loaded by the first scan signal terminal GA 1. Alternatively, the second transistor M2 may be an N-type transistor, and the second transistor M2 is turned on under the control of the high level of the signal loaded at the first scan signal terminal GA1 and turned off under the control of the low level of the signal loaded at the first scan signal terminal GA 1.

In particular implementations, in the presently disclosed embodiment, as shown in fig. 3, the second threshold compensation circuit 30 includes a third transistor M3; the gate of the third transistor M3 is coupled to the first scan signal terminal GA1, the first pole of the third transistor M3 is coupled to the compensation node N0, and the second pole of the second transistor M2 is coupled to the gate of the light-emitting driving transistor M0.

Illustratively, as shown in fig. 3, the third transistor M3 may be configured as a P-type transistor, and the third transistor M3 is turned on under control of a low level of a signal loaded at the first scan signal terminal GA1 and turned off under control of a high level of a signal loaded at the first scan signal terminal GA 1. Alternatively, the third transistor M3 may be an N-type transistor, and the third transistor M3 is turned on under control of a high level of the signal loaded at the first scan signal terminal GA1 and turned off under control of a low level of the signal loaded at the first scan signal terminal GA 1.

In particular implementations, in the presently disclosed embodiment, as shown in fig. 3, the data input circuit 10 includes a fourth transistor M4; the gate of the fourth transistor M4 is coupled to the first scan signal terminal GA1, the first pole of the fourth transistor M4 is coupled to the data signal terminal DA, and the second pole of the fourth transistor M4 is coupled to the second pole of the light-emitting driving transistor M0.

Illustratively, as shown in fig. 3, the fourth transistor M4 may be set as a P-type transistor, and the fourth transistor M4 is turned on under control of a low level of a signal loaded by the first scan signal terminal GA1 and turned off under control of a high level of a signal loaded by the first scan signal terminal GA 1. Alternatively, the fourth transistor M4 may be an N-type transistor, and the fourth transistor M4 is turned on under the control of the high level of the signal applied to the first scan signal terminal GA1 and turned off under the control of the low level of the signal applied to the first scan signal terminal GA 1.

In particular implementation, in the presently disclosed embodiment, as shown in fig. 3, the light emission control circuit 50 includes a fifth transistor M5 and a sixth transistor M6; the gate of the fifth transistor M5 is coupled to the first light emitting control signal terminal EM1, the first pole of the fifth transistor M5 is coupled to the first power terminal, and the second pole of the fifth transistor M5 is coupled to the second pole of the light emitting driving transistor M0; the gate of the sixth transistor M6 is coupled to the first light emitting control signal terminal EM1, the first electrode of the sixth transistor M6 is coupled to the first electrode of the light emitting driving transistor M0, and the second electrode of the sixth transistor M6 is coupled to the light emitting device L. Specifically, the second electrode of the sixth transistor M6 is coupled to the first electrode of the light emitting device L.

Illustratively, as shown in fig. 3, the fifth transistor M5 may be set as a P-type transistor, and the fifth transistor M5 is turned on under control of a low level of the signal loaded by the first light emitting control signal terminal EM1 and turned off under control of a high level of the signal loaded by the first light emitting control signal terminal EM 1. Alternatively, the fifth transistor M5 may be an N-type transistor, and the fifth transistor M5 is turned on under the control of the high level of the signal applied to the first light emitting control signal terminal EM1 and turned off under the control of the low level of the signal applied to the first light emitting control signal terminal EM 1.

Illustratively, as shown in fig. 3, the sixth transistor M6 may be set as a P-type transistor, and the sixth transistor M6 is turned on under the control of the low level of the signal loaded by the first light emitting control signal terminal EM1 and turned off under the control of the high level of the signal loaded by the first light emitting control signal terminal EM 1. Alternatively, the sixth transistor M6 may be an N-type transistor, and the sixth transistor M6 is turned on under the control of the high level of the signal applied to the first light emitting control signal terminal EM1 and turned off under the control of the low level of the signal applied to the first light emitting control signal terminal EM 1.

In particular implementations, in embodiments of the present disclosure, as shown in fig. 3, the memory circuit 60 may include: a storage capacitor CST; the first electrode of the storage capacitor CST is coupled to the gate of the light emitting driving transistor M0, and the second electrode of the storage capacitor CST is coupled to the second electrode of the light emitting driving transistor M0.

In particular implementations, in embodiments of the present disclosure, as shown in fig. 3, the initialization circuit 70 may include a seventh transistor M7; the gate of the seventh transistor M7 is coupled to the reset signal terminal RES, the first pole of the seventh transistor M7 is coupled to the first initialization signal terminal VINIT1, and the second pole of the seventh transistor M7 is coupled to the gate of the light emitting driving transistor M0.

Illustratively, as shown in fig. 3, the seventh transistor M7 may be set as a P-type transistor, and the seventh transistor M7 is turned on under control of a low level of the signal applied to the reset signal terminal RES and turned off under control of a high level of the signal applied to the reset signal terminal RES. Alternatively, the seventh transistor M7 may be an N-type transistor, and the seventh transistor M7 is turned on under control of a high level of a signal applied to the reset signal terminal RES and turned off under control of a low level of a signal applied to the reset signal terminal RES. Further, as shown in fig. 3, the seventh transistor M7 may employ a single gate structure.

In particular implementations, in the presently disclosed embodiments, as shown in fig. 3, the light emission regulating circuit 80 includes an eighth transistor M8; the gate of the eighth transistor M8 is coupled to the second light-emitting control signal terminal EM2, the first electrode of the eighth transistor M8 is coupled to the second initialization signal terminal VINIT2, and the second electrode of the eighth transistor M8 is coupled to the light-emitting device L.

Illustratively, as shown in fig. 3, the eighth transistor M8 may be set as a P-type transistor, and the eighth transistor M8 is turned on under the control of the low level of the signal applied to the second light emission control signal terminal EM2 and turned off under the control of the high level of the signal applied to the second light emission control signal terminal EM 2. Alternatively, the eighth transistor M8 may be an N-type transistor, and the eighth transistor M8 is turned on under the control of the high level of the signal applied to the second emission control signal terminal EM2 and turned off under the control of the low level of the signal applied to the second emission control signal terminal EM 2.

In the embodiment of the disclosure, as shown in fig. 3 and 4, when the fifth to eighth transistors M8 are P-type transistors, the phases of the signal loaded by the second light emission control signal terminal EM2 and the signal loaded by the first light emission control signal terminal EM1 may be opposite.

The above is merely an example of a specific structure of each circuit in the pixel circuit provided in the embodiment of the disclosure, and in implementation, the specific structure of the circuit is not limited to the above structure provided in the embodiment of the disclosure, but may be other structures known to those skilled in the art, which are all within the protection scope of the disclosure, and are not specifically limited herein.

For example, in order to reduce the manufacturing process, in the embodiment of the present disclosure, as shown in fig. 3, the first to eighth transistors M8M1 to M8 may be P-type transistors. Of course, the first to eighth transistors M8 may be N-type transistors, which may be designed and determined according to practical application environments, and are not limited herein.

Note that the transistor mentioned in the above embodiments of the present disclosure may be a thin film transistor (Thin Film Transistor, TFT) or a metal oxide semiconductor field effect transistor (Metal Oxide Scmiconductor, MOS), which is not limited herein.

In a specific implementation, the first pole of the transistor can be used as the source electrode and the second pole can be used as the drain electrode according to the type of the transistor and the signal of the grid electrode; or conversely, the first electrode of the transistor is taken as the drain electrode thereof, and the second electrode is taken as the source electrode thereof, which can be designed and determined according to practical application environments, and specific distinction is not made here.

In an embodiment of the present disclosure, the voltage Vdd of the first power terminal is generally positive, and the voltage Vss of the second power terminal is generally grounded or negative. In practical applications, specific values of the voltage Vdd of the first power supply terminal and the voltage Vss of the second power supply terminal may be designed and determined according to practical application environments, which is not limited herein.

The embodiment of the disclosure also provides a driving method for a pixel circuit, which may include the steps of:

in the data writing stage, the data input circuit 10 inputs the data voltage applied to the data signal terminal DA in response to the signal of the first scan signal terminal GA 1; the first threshold compensation circuit 20 turns on the first pole of the light emitting driving transistor M0 and the compensation node N0 in response to the signal of the first scan signal terminal GA 1; the second threshold compensation circuit 30 turns on the gate of the light emitting driving transistor M0 and the compensation node N0 in response to the signal of the first scan signal terminal GA 1;

An auxiliary stage in which the auxiliary control circuit 40 responds to the signal of the second scan signal terminal GA2 to provide the auxiliary voltage of the auxiliary signal terminal VF to the compensation node N0;

in the light emitting stage, the light emitting driving transistor M0 generates an operating current for driving the light emitting device L to emit light according to the data voltage, and drives the light emitting device L to emit light.

In some embodiments of the present disclosure, prior to the data writing phase, it may further include: in the initialization stage, the initialization circuit 70 supplies a signal of the first initialization signal terminal VINIT1 to the gate of the light emitting driving transistor M0 in response to a signal of the reset signal terminal RES; the light emission adjusting circuit 80 supplies a signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to a signal of the second light emission control signal terminal EM 2.

In some embodiments of the present disclosure, the lighting phase comprises: a light emitting sub-stage and a light emitting adjustment sub-stage; wherein, in the light emitting sub-stage, the light emission control circuit 50 is configured to supply a signal of the first power supply terminal to the second electrode of the light emission driving transistor M0 in response to the signal of the first light emission control signal terminal EM1, and to turn on the first electrode of the light emission driving transistor M0 with the light emitting device L; the light emission driving transistor M0 generates an operating current for driving the light emitting device L to emit light according to the data voltage, and drives the light emitting device L to emit light. In the light emission adjustment sub-stage, the light emission adjustment circuit 80 supplies a signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to a signal of the second light emission control signal terminal EM 2.

The following describes the operation of the pixel circuit according to the embodiment of the present disclosure with reference to the signal timing diagram shown in fig. 4, taking the structure of the pixel circuit shown in fig. 3 as an example. The initialization phase T1, the data writing phase T2, the auxiliary phase T3, and the light emitting phase T4 in the signal timing diagram shown in fig. 4 are mainly selected. The light emitting stage T4 includes a light emitting sub-stage T41, a light emitting adjustment sub-stage T42, and a light emitting sub-stage T43. And RES represents a signal loaded to the reset signal terminal RES, GA1 represents a signal loaded to the first scan signal terminal GA1, GA2 represents a signal loaded to the second scan signal terminal GA2, EM1 represents a signal loaded to the first light emitting control signal terminal EM1, EM2 represents a signal loaded to the second light emitting control signal terminal EM2, DA represents a signal loaded to the data signal terminal DA, VF represents a signal loaded to the auxiliary signal terminal VF.

In the initialization stage T1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The first transistor M1 is turned off under control of the high level of the signal ga 2. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned on under the control of the low level of the signal res to supply the signal loaded by the first initialization signal terminal VINIT1 to the gate of the light emitting driving transistor M0 to initialize the gate of the light emitting driving transistor M0. The eighth transistor M8 is turned on under the control of the low level of the signal em2 to supply the signal loaded by the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L.

In the data writing phase T2, the first transistor M1 is turned off under control of the high level of the signal ga 2. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned off under control of a high level of the signal res. The eighth transistor M8 is turned on under the control of the low level of the signal em2 to supply the signal loaded by the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on under the control of the low level of the signal ga 1. Since the second transistor M2 and the third transistor M3 are turned on, the light emitting driving transistor M0 forms a diode connection structure. The data signal end DA loads the data voltage, and charges the grid electrode of the light emitting driving transistor M0 through the conducted fourth transistor M4 and the light emitting driving transistor M0 forming a diode connection structure until the grid electrode voltage of the light emitting driving transistor M0 becomes Vda+Vth ₁ (Vda represents the data voltage, vth ₁ Representing the threshold voltage of the light emitting drive transistor M0).

In the auxiliary phase T3, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned off under control of a high level of the signal res. The eighth transistor M8 is turned on under the control of the low level of the signal em2 to supply the signal loaded by the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L. The first transistor M1 is turned on under the control of the low level of the signal ga2 to supply the auxiliary voltage Vvf applied to the auxiliary signal terminal VF to the compensation node N0, so that the voltage of the compensation node N0 is the auxiliary voltage related to the data voltage Vda. Therefore, the voltage of the gate electrode of the light emitting driving transistor M0 can be reduced, and the voltage stability of the gate electrode of the light emitting driving transistor M0 is improved due to the leakage current occurring in the leakage current path formed by the second transistor M2 and the third transistor M3. Particularly, after the pixel circuit is applied to the display panel, the flicker problem of the display panel is reduced when the display panel is driven by a lower refresh frequency.

In the light emitting sub-stage T41, the first transistor M1 is turned off under control of the high level of the signal ga 2. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under control of the high level of the signal ga 1. The seventh transistor M7 is turned off under control of a high level of the signal res. The eighth transistor M8 is turned off under control of the high level of the signal em 2. The fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the signal em 1. The turned-on fifth transistor M5 supplies the signal of the first power terminal to the second pole of the light emitting driving transistor M0, so that the voltage of the second pole of the light emitting driving transistor M0 is Vdd. Since the gate voltage of the light-emitting driving transistor M0 is Vda+Vth ₁ The operating current IL generated by the light-emitting driving transistor M0 is: il=k ₁ (Vda+Vth ₁ -Vdd-Vth ₁ ) ² ＝K ₁ (Vda-Vdd) ² . The turned-on sixth transistor M6 turns on the first electrode of the light emission driving transistor M0 and the first electrode of the light emitting device L, thereby supplying the operating current IL to the light emitting device L to drive the light emitting device L to emit light. And, K ₁ Is the structural constant of the light emitting driving transistor M0.

In the light emission adjustment sub-stage T42, the first transistor M1 is turned off under control of the high level of the signal ga 2. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under control of the high level of the signal ga 1. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned off under control of a high level of the signal res. The eighth transistor M8 is turned on under the control of the low level of the signal em2 to supply the signal loaded by the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L, thereby turning off the light emitting device L and stopping light emission.

In the light emitting sub-stage T43, the first transistor M1 is turned off under control of the high level of the signal ga 2. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under control of the high level of the signal ga 1. The seventh transistor M7 is turned off under control of a high level of the signal res. The eighth transistor M8 is turned off under control of the high level of the signal em 2. The fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the signal em 1. The turned-on fifth transistor M5 supplies the signal of the first power terminal to the second pole of the light emitting driving transistor M0, so that the voltage of the second pole of the light emitting driving transistor M0 is Vdd. Since the gate voltage of the light-emitting driving transistor M0 is Vda+Vth ₁ The operating current IL generated by the light-emitting driving transistor M0 is: il=k [ vda+vth ₁ -Vdd-Vth ₁ ] ² ＝K[Vda-Vdd] ² . The turned-on sixth transistor M6 turns on the first electrode of the light emission driving transistor M0 and the first electrode of the light emitting device L, thereby supplying the operating current IL to the light emitting device L to drive the light emitting device L to emit light.

The luminance of the light emitting device L may be adjusted by providing a light emission adjustment sub-stage in the light emission stage. And, the light emitting sub-stage and the light emitting adjustment sub-stage included in the light emitting stage are alternately arranged. The specific number of the light emitting sub-stages and the light emitting adjustment sub-stages included in the light emitting stage may be determined according to the actual application demand, and is not limited herein.

The disclosed embodiments provide other signal timing diagrams of pixel circuits, as shown in fig. 5, which are modified for implementation in the above embodiments. Only the differences between the present embodiment and the above-described embodiments are described below, and their details are not repeated here.

In the embodiment of the present disclosure, the initialization stage may include a first initialization stage and a second initialization stage. Wherein the first initialization stage and the second initialization stage are alternately arranged. Also, the number of the first initialization stage and the second initialization stage may be the same. For example, the first initialization stage and the second initialization stage may be set to 3 respectively. Of course, the number of the first initialization stage and the second initialization stage may be determined according to the requirements of the actual application.

In the embodiment of the present disclosure, in the first initialization stage, the initialization circuit 70 supplies a signal of the first initialization signal terminal VINIT1 to the gate of the light emitting driving transistor M0 in response to a signal of the reset signal terminal RES. The light emission adjusting circuit 80 supplies a signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to a signal of the second light emission control signal terminal EM 2.

In the embodiment of the present disclosure, in the second initialization stage, the data input circuit 10 supplies the reset voltage applied to the data signal terminal DA to the second pole of the light emitting driving transistor M0 in response to the signal of the first scan signal terminal GA 1. The light emission adjusting circuit 80 supplies a signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to a signal of the second light emission control signal terminal EM 2.

The following describes the operation of the pixel circuit according to the embodiment of the present disclosure with reference to the signal timing diagram shown in fig. 5, taking the structure of the pixel circuit shown in fig. 3 as an example. The initialization phase T1, the data writing phase T2, the auxiliary phase T3, and the light emitting phase T4 in the signal timing diagram shown in fig. 5 are mainly selected. The initialization phase T1 includes a first initialization phase T11, a second initialization phase T12, a first initialization phase T13, a second initialization phase T14, and a first initialization phase T15. The light emitting stage T4 includes a light emitting sub-stage T41, a light emitting adjustment sub-stage T42, and a light emitting sub-stage T43. And RES represents a signal loaded to the reset signal terminal RES, GA1 represents a signal loaded to the first scan signal terminal GA1, GA2 represents a signal loaded to the second scan signal terminal GA2, EM1 represents a signal loaded to the first light emitting control signal terminal EM1, EM2 represents a signal loaded to the second light emitting control signal terminal EM2, DA represents a signal loaded to the data signal terminal DA, VF represents a signal loaded to the auxiliary signal terminal VF.

In the first initialization stage T11, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The first transistor M1 is turned off under control of the high level of the signal ga 2. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned on under the control of the low level of the signal res to supply the signal loaded by the first initialization signal terminal VINIT1 to the gate of the light emitting driving transistor M0 to initialize the gate of the light emitting driving transistor M0. The eighth transistor M8 is turned on under the control of the low level of the signal em2 to supply the signal loaded by the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L.

In the second initialization stage T12, the first transistor M1 is turned off under the control of the high level of the signal ga 2. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned off under control of a low level of the signal res. The second transistor M2, the third transistor M3 and the fourth transistor M4 are turned on under the control of the low level of the signal ga1 to supply the reset voltage applied by the data signal terminal DA to the gate, the first pole and the second pole of the light emitting driving transistor M0 to initialize the gate, the first pole and the second pole of the light emitting driving transistor M0. The eighth transistor M8 is turned on under the control of the low level of the signal em2 to supply the signal loaded by the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L.

In the first initialization stage T13, the working process of the pixel circuit in the stage T13 is substantially the same as that in the stage T11, and will not be described herein.

In the second initialization stage T14, the operation of the pixel circuit in the stage T14 is substantially the same as that in the stage T12, and will not be described herein.

In the first initialization stage T15, the working process of the pixel circuit in the stage T15 is substantially the same as that in the stage T11, and will not be described herein.

The working processes of the pixel circuit in the data writing stage T2, the auxiliary stage T3 and the light emitting stage T4 are substantially the same as those in the above embodiment, and will not be described herein.

The embodiments of the present disclosure provide other schematic structural diagrams of the pixel circuit, as shown in fig. 6, which are modified for implementation in the above embodiments. Only the differences between the present embodiment and the above-described embodiments are described below, and their details are not repeated here.

In some embodiments of the present disclosure, the seventh transistor M7 may also be provided in a dual gate structure. For example, as shown in fig. 6, the seventh transistor M7 may include a first sub-transistor and a second sub-transistor. The gate of the first sub-transistor and the gate of the second sub-transistor are both coupled to the reset signal terminal RES, the first pole of the first sub-transistor is coupled to the first initialization signal terminal VINIT1, the second pole of the first sub-transistor is coupled to the first pole of the second sub-transistor, and the second pole of the second sub-transistor is coupled to the gate of the light emitting driving transistor M0. For example, the first and second sub-transistors may each be provided as a P-type transistor, which is turned on by a low level control of the signal of the reset signal terminal RES and is turned off by a high level control of the signal of the reset signal terminal RES.

Note that, the signal timing diagrams corresponding to the pixel circuits shown in fig. 6 are shown in fig. 4 and 5. The operation of the pixel circuit shown in fig. 6 may be substantially the same as that of the above embodiment, and will not be described herein.

Embodiments of the present disclosure also provide a display panel, as shown in fig. 7, which may include a display area and a non-display area. The display region may include a plurality of pixel units arranged in an array. Illustratively, each pixel cell includes a plurality of differently colored sub-pixels spx. Any of the pixel circuits described above may be included in each sub-pixel. For example, the pixel unit may include red, green, and blue sub-pixels, so that color mixing can be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may include red, green, blue and white sub-pixels, so that color mixing can be performed by red, green, blue and white to realize color display. Of course, in practical application, the emission color of the sub-pixels in the pixel unit may be designed and determined according to the practical application environment, which is not limited herein. The following description will take a pixel unit including red, green and blue sub-pixels as an example.

In some embodiments of the present disclosure, as shown in fig. 8, the display panel may further include: a plurality of auxiliary signal lines VFS, a plurality of data signal lines DAS, a plurality of reset signal lines RESS, a plurality of first light emission control signal lines EMS1, a plurality of second light emission control signal lines EMS2, a plurality of first scan signal lines GAS1, and a plurality of second scan signal lines GAS2. The auxiliary signal terminal VF of the pixel circuit in one row of sub-pixels is coupled to an auxiliary signal line VFs, so as to transmit an auxiliary voltage to the auxiliary signal terminal VF through the auxiliary signal line VFs. And, the data signal terminal DA of the pixel circuit in a column of the sub-pixels is coupled to one data signal line DAs to transmit the data voltage and the reset voltage to the data signal terminal DA through the data signal line DAs. And, the reset signal terminal RES of the pixel circuit in one row of the sub-pixels is coupled to one reset signal line RESs to transmit a signal to the reset signal terminal RES through the reset signal line RESs. The first scan signal terminal GA1 of the pixel circuit in one row of sub-pixels is coupled to one first scan signal line GAs1 to transmit signals to the first scan signal terminal GA1 through the first scan signal line GAs 1. And, the second scan signal terminal GA2 of the pixel circuits in one row of sub-pixels is coupled to one second scan signal line GAs2 to transmit signals to the second scan signal terminal GA2 through the second scan signal line GAs2. Also, the first light emitting control signal terminal EM1 of the pixel circuit in one row of sub-pixels is coupled to one first light emitting control signal line EMs1 to transmit a signal to the first light emitting control signal terminal EM1 through the first light emitting control signal line EMs 1. And, the second emission control signal terminal EM2 of the pixel circuit in one row of sub-pixels is coupled to one second emission control signal line EMs2, so as to transmit a signal to the second emission control signal terminal EM2 through the second emission control signal line EMs 2.

In an embodiment of the present disclosure, as shown in fig. 8, the display panel may further include: a plurality of auxiliary input circuits 100. The plurality of auxiliary input circuits 100 may be disposed in a non-display area. One auxiliary input circuit 100 corresponds to one row of sub-pixels, and the auxiliary input circuits 100 are respectively coupled to the auxiliary signal lines VFS and the data signal lines DAS of the corresponding sub-pixels. And, the auxiliary input circuit 100 is configured to generate an auxiliary voltage according to the data voltage on the data signal line DAS when the data signal terminal DA coupled thereto is applied with the data voltage through the data signal line DAS, and input the generated auxiliary voltage to the auxiliary signal line VFS coupled thereto.

In the disclosed embodiment, as shown in fig. 9, the auxiliary input circuit 100 may include: an auxiliary drive transistor Mf and a control circuit 110. The gate of the auxiliary driving transistor Mf is coupled to the corresponding data signal terminal DA, the first pole of the auxiliary driving transistor Mf is coupled to the corresponding auxiliary signal line VFS, and the auxiliary driving transistor Mf is configured to generate an auxiliary current according to the data voltage on the data signal line DAs. The control circuit 110 is coupled to the first pole of the auxiliary driving transistor Mf, and the control circuit 110 is configured to adjust the voltage of the first pole of the auxiliary driving transistor Mf according to the auxiliary current, and input the adjusted voltage as an auxiliary voltage onto the coupled auxiliary signal line VFS. The auxiliary driving transistor Mf may be configured as a P-type transistor, for example. The second pole of the auxiliary driving transistor Mf is the source thereof, the first pole of the auxiliary driving transistor Mf is the drain thereof, and when the auxiliary driving transistor Mf is in a saturated state, a current flows from the source of the auxiliary driving transistor Mf to the drain thereof. Of course, the auxiliary driving transistor Mf may be an N-type transistor, which is not limited herein.

In the embodiment of the present disclosure, as shown in fig. 10, the control circuit 110 includes: the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5;

a first end of the first resistor R1 is coupled to the first reference signal terminal VREF1, and a second end of the first resistor R1 is coupled to the first pole of the auxiliary driving transistor Mf;

the first end of the second resistor R2 is coupled with the first reference signal end VREF1, and the second end of the second resistor R2 is coupled with the second pole of the auxiliary driving transistor Mf;

the first end of the third resistor R3 is coupled with the second pole of the auxiliary driving transistor Mf, and the second end of the third resistor R3 is coupled with the first pole of the auxiliary driving transistor Mf;

the first end of the fourth resistor R4 is coupled with the first pole of the auxiliary driving transistor Mf, and the second end of the fourth resistor R4 is coupled with the grid electrode of the auxiliary driving transistor Mf;

the first end of the fifth resistor R5 is coupled to the second reference signal terminal VREF2, and the second end of the fifth resistor R5 is coupled to the first pole of the auxiliary driving transistor Mf.

In the embodiment of the present disclosure, as shown in fig. 11, the auxiliary input circuit 100 may further include: a sixth resistor R6; the data signal line DAS is coupled to the gate of the auxiliary driving transistor Mf through a sixth resistor R6.

In the embodiment of the present disclosure, as shown in fig. 11, the auxiliary input circuit 100 may further include: an auxiliary control transistor Mc and a seventh resistor R7; the first pole of the auxiliary driving transistor Mf is coupled to the corresponding auxiliary signal line VFS through the auxiliary control transistor Mc, and the gate of the auxiliary transistor is coupled to the third reference signal terminal VREF3 through the seventh resistor R7. For example, the auxiliary control transistor Mc may be set to a P-type transistor, and the signal of the third reference signal terminal VREF3 may be set to a low level signal of direct current, so that the auxiliary control transistor Mc may be controlled to be continuously turned on. Alternatively, the auxiliary control transistor Mc may be set to an N-type transistor, and the signal of the third reference signal terminal VREF3 may be set to a high level signal of direct current, so that the auxiliary control transistor Mc may be controlled to be continuously turned on.

Illustratively, the fifth resistor R5 may have a resistance value that is greater than the resistance value of the fourth resistor R4. For example, the resistance value of the fifth resistor R5 may be made much larger than the resistance value of the fourth resistor R4. Of course, in practical applications, the resistance value of the fifth resistor R5 and the resistance value of the fourth resistor R4 may be determined according to the requirements of practical applications, which are not limited herein.

Illustratively, the resistance value of the second resistor R2, the resistance value of the sixth resistor R6, and the resistance value of the seventh resistor R7 may be substantially the same. Of course, in practical applications, the resistance value of the second resistor R2, the resistance value of the sixth resistor R6, and the resistance value of the seventh resistor R7 may be determined according to the requirements of the practical applications, and are not limited herein.

For example, the resistance value of the first resistor R1 and the resistance value of the third resistor R3 may be substantially the same. Of course, in practical applications, the resistance value of the first resistor R1 and the resistance value of the third resistor R3 may be determined according to the requirements of practical applications, which is not limited herein.

Illustratively, the signal of the first reference signal terminal VREF1 may be a low voltage of direct current, and the signal of the second reference signal terminal VREF2 may be a high voltage of direct current. Of course, in practical applications, specific voltage values of the signal of the first reference signal terminal VREF1 and the signal of the second reference signal terminal VREF2 may be determined according to requirements of practical applications, which are not limited herein.

The following will take the configuration shown in fig. 11 as an example. When the data voltage Vda is applied to the data signal line DAS, the auxiliary driving transistor Mf can generate auxiliary current Id by the interaction of the first resistor R1 to the sixth resistor R6, id=K ₂ *(Vda-VN ₂ -Vth ₂ ) ² . Since the auxiliary control transistor Mc is normally on, the voltage at the second end of the first resistor R1 can be adjusted by the auxiliary current Id, that is, the voltage value of the auxiliary voltage on the auxiliary signal line VFS can be adjusted. So that the voltage of the auxiliary voltage on the auxiliary signal line VFS can be correlated with the current data voltage Vda. In this way, in the auxiliary phase T3, the voltage of the compensation node N0 can be made to be an auxiliary voltage related to the data voltage Vda. Therefore, the voltage of the gate electrode of the light emitting driving transistor M0 can be reduced, and the voltage stability of the gate electrode of the light emitting driving transistor M0 is improved due to the leakage current occurring in the leakage current path formed by the second transistor M2 and the third transistor M3. In particular, after the pixel circuit is applied to the display panel, the pixel circuit is displayedWhen the panel is driven by a lower refresh frequency, the flicker problem of the display panel is reduced.

The embodiment of the disclosure also provides a display device, which comprises the display panel provided by the embodiment of the disclosure. The principle of the display device for solving the problems is similar to that of the display panel, so that the implementation of the display device can be referred to the implementation of the display panel, and the repetition is omitted herein.

In specific implementation, in the embodiment of the disclosure, the display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are those of ordinary skill in the art and will not be described in detail herein, nor should they be considered as limiting the present disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A display panel, comprising:

a plurality of sub-pixels; wherein each of the sub-pixels includes a pixel circuit;

wherein the pixel circuit includes:

a light emitting device; a light emitting driving transistor having a first electrode coupled to the light emitting device and configured to generate an operating current for driving the light emitting device to emit light according to a data voltage; a data input circuit coupled to the light emitting driving transistor, and configured to input a data voltage applied to a data signal terminal in response to a signal of a first scan signal terminal; a first threshold compensation circuit coupled to the first pole of the light-emitting drive transistor and the compensation node, and configured to turn on the first pole of the light-emitting drive transistor and the compensation node in response to a signal of the first scan signal terminal; a second threshold compensation circuit coupled to the gate of the light emitting drive transistor and the compensation node, and configured to turn on the gate of the light emitting drive transistor and the compensation node in response to a signal of the first scan signal terminal; an auxiliary control circuit coupled to the compensation node, and configured to provide an auxiliary voltage of an auxiliary signal terminal to the compensation node in response to a signal of a second scan signal terminal; wherein the auxiliary voltage is related to the data voltage; wherein the auxiliary control circuit comprises a first transistor; the grid electrode of the first transistor is coupled with the second scanning signal end, the first electrode of the first transistor is coupled with the auxiliary signal end, and the second electrode of the first transistor is coupled with the compensation node;

The display panel further includes:

a plurality of second scanning signal lines; the second scanning signal end of the pixel circuit in one row of sub-pixels is coupled with one second scanning signal line;

the auxiliary input circuit is configured to generate an auxiliary voltage according to the data voltage on the data signal line when the data signal terminal coupled through the data signal line is loaded with the data voltage, and input the generated auxiliary voltage to the coupled auxiliary signal line;

wherein the auxiliary input circuit comprises:

2. The display panel of claim 1, wherein the first threshold compensation circuit comprises a second transistor; the grid electrode of the second transistor is coupled with the first scanning signal end, the first electrode of the second transistor is coupled with the first electrode of the light-emitting driving transistor, and the second electrode of the second transistor is coupled with the compensation node;

3. The display panel of claim 1, wherein the data input circuit comprises a fourth transistor; the grid electrode of the fourth transistor is coupled with the first scanning signal end, the first electrode of the fourth transistor is coupled with the data signal end, and the second electrode of the fourth transistor is coupled with the second electrode of the light-emitting driving transistor.

4. A display panel according to any one of claims 1-3, wherein the pixel circuit further comprises: a light emission control circuit; wherein the light emission control circuit is configured to supply a signal of a first power supply terminal to a second electrode of the light emission driving transistor in response to a signal of a first light emission control signal terminal, and to turn on the first electrode of the light emission driving transistor with the light emitting device;

5. The display panel according to claim 4, wherein the light-emission control circuit includes a fifth transistor and a sixth transistor; wherein, the grid electrode of the fifth transistor is coupled with the first light-emitting control signal end, the first electrode of the fifth transistor is coupled with the first power end, and the second electrode of the fifth transistor is coupled with the second electrode of the light-emitting driving transistor; a gate of the sixth transistor is coupled to the first light emitting control signal terminal, a first electrode of the sixth transistor is coupled to the first electrode of the light emitting driving transistor, and a second electrode of the sixth transistor is coupled to the light emitting device;

6. A display panel according to any one of claims 1-3, wherein the control circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

7. The display panel of claim 6, wherein the auxiliary input circuit further comprises: a sixth resistor; wherein the data signal line is coupled with the gate of the auxiliary driving transistor through the sixth resistor;

and/or, the auxiliary input circuit further comprises: an auxiliary control transistor and a seventh resistor; the first pole of the auxiliary driving transistor is coupled with the corresponding auxiliary signal line through the auxiliary control transistor, and the grid electrode of the auxiliary control transistor is coupled with the third reference signal end through the seventh resistor.

8. A display device comprising the display panel according to any one of claims 1-7.

9. A driving method for the display panel according to any one of claims 1 to 7, comprising:

10. The driving method of claim 9, further comprising, prior to the data writing phase: an initialization stage in which an initialization circuit supplies a signal of a first initialization signal terminal to a gate of the light-emitting driving transistor in response to a signal of a reset signal terminal; the light-emitting adjusting circuit responds to the signal of the second light-emitting control signal end and provides the signal of the second initialization signal end for the light-emitting device;

in the light emitting sub-stage, a light emission control circuit is configured to supply a signal of a first power supply terminal to a second electrode of the light emission driving transistor in response to a signal of a first light emission control signal terminal, and to turn on the first electrode of the light emission driving transistor with the light emitting device; the light-emitting driving transistor generates working current for driving the light-emitting device to emit light according to the data voltage and drives the light-emitting device to emit light;