CN114783382A

CN114783382A - Pixel circuit, driving method thereof, display panel and display device

Info

Publication number: CN114783382A
Application number: CN202210303724.8A
Authority: CN
Inventors: 王苗; 宋江; 肖云升; 青海刚
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-03-24
Filing date: 2022-03-24
Publication date: 2022-07-22
Anticipated expiration: 2042-03-24
Also published as: CN114783382B

Abstract

The pixel circuit, the driving method thereof, the display panel and the display device provided by the embodiment of the disclosure can enable the auxiliary control circuit to respond to the signal of the second scanning signal terminal by setting the auxiliary control circuit coupled to the compensation node, so as to provide the auxiliary voltage of the auxiliary signal terminal to the compensation node. Since the auxiliary voltage is related to the data voltage, the voltage of the compensation node can be related to the data voltage after the auxiliary voltage is provided to the compensation node, so that the voltage of the gate of the light emitting driving transistor can be reduced. Particularly, after the pixel circuit is applied to the display panel, when the display panel is driven by adopting a lower refreshing frequency, the flicker problem of the display panel is reduced.

Description

Pixel circuit, driving method thereof, display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, a display panel, and a display device.

Background

Electroluminescent Diodes such as Organic Light Emitting Diodes (OLEDs), Quantum Dot Light Emitting Diodes (QLEDs), Micro Light Emitting Diodes (Micro LEDs), and the like have the advantages of self-luminescence, low energy consumption, and the like, and are one of the hotspots in the application research field of the current electroluminescent display device. In general, an electroluminescent display device employs a pixel circuit to drive an electroluminescent diode to emit light.

Disclosure of Invention

The pixel circuit, the driving method thereof, the display panel and the display device provided by the embodiment of the disclosure can improve the voltage stability of the grid of the light-emitting driving transistor. Especially, after the pixel circuit is applied to the display panel, when the display panel is driven by adopting a lower refreshing frequency, the problem of Flicker of the display panel is reduced.

The pixel circuit provided by the embodiment of the disclosure comprises:

a light emitting device;

a light emission driving transistor having a first electrode coupled to the light emitting device and configured to generate an operating current for driving the light emitting device to emit light according to a data voltage;

a data input circuit coupled to the light emission driving transistor and configured to input a data voltage applied to a data signal terminal in response to a signal of a first scan signal terminal;

a first threshold compensation circuit coupled to the first pole of the light emission driving transistor and a compensation node, and configured to turn on the first pole of the light emission driving transistor and the compensation node in response to a signal of the first scan signal terminal;

a second threshold compensation circuit coupled to the gate electrode of the light emission driving transistor and the compensation node, and configured to turn on the gate electrode of the light emission driving transistor and the compensation node in response to a signal of the first scan signal terminal;

an auxiliary control circuit coupled to the compensation node and configured to provide an auxiliary voltage of an auxiliary signal terminal to the compensation node in response to a signal of a second scan signal terminal; wherein the auxiliary voltage is related to the data voltage.

In some examples, the auxiliary control circuit includes a first transistor;

the gate of the first transistor is coupled to the second scan signal terminal, the first pole of the first transistor is coupled to the auxiliary signal terminal, and the second pole of the first transistor is coupled to the compensation node.

In some examples, the first threshold compensation circuit includes a second transistor; wherein a gate electrode of the second transistor is coupled to the first scan signal terminal, a first electrode of the second transistor is coupled to a first electrode of the light emission driving transistor, and a second electrode of the second transistor is coupled to the compensation node;

and/or the second threshold compensation circuit comprises a third transistor; wherein a gate electrode of the third transistor is coupled to the first scan signal terminal, a first electrode of the third transistor is coupled to the compensation node, and a second electrode of the second transistor is coupled to a gate electrode of the light emission driving transistor.

In some examples, the data input circuit includes a fourth transistor; wherein a gate of the fourth transistor is coupled to the first scan signal terminal, a first pole of the fourth transistor is coupled to the data signal terminal, and a second pole of the fourth transistor is coupled to the second pole of the light emitting driving transistor.

In some examples, the pixel circuit further includes: a light emission control circuit; wherein the light emission control circuit is configured to supply a signal of a first power source terminal to a second pole of the light emission driving transistor and to turn on the first pole of the light emission driving transistor with the light emitting device in response to a signal of a first light emission control signal terminal;

and/or, the pixel circuit further comprises: a storage circuit configured to store a voltage input to a gate of the light emission driving transistor;

and/or, the pixel circuit further comprises: initializing a circuit; wherein the initialization circuit is configured to supply a signal of a first initialization signal terminal to the gate of the light emission driving transistor in response to a signal of a reset signal terminal;

and/or, the pixel circuit further comprises: a light emission adjusting circuit; wherein the light emission adjusting circuit is configured to provide a signal of a second initialization signal terminal to the light emitting device in response to a signal of a second light emission control signal terminal.

In some examples, the light emission control circuit includes a fifth transistor and a sixth transistor; wherein a gate of the fifth transistor is coupled to the first light-emitting control signal terminal, a first pole of the fifth transistor is coupled to the first power terminal, and a second pole of the fifth transistor is coupled to the second pole of the light-emitting driving transistor; a gate of the sixth transistor is coupled to the first light emission control signal terminal, a first pole of the sixth transistor is coupled to the first pole of the light emission driving transistor, and a second pole of the sixth transistor is coupled to the light emitting device.

And/or, the memory circuit comprises: a storage capacitor; the first electrode plate of the storage capacitor is coupled with the grid electrode of the light-emitting driving transistor, and the second electrode plate of the storage capacitor is coupled with the second pole of the light-emitting driving transistor;

and/or, the initialization circuit comprises a seventh transistor; wherein a gate of the seventh transistor is coupled to the reset signal terminal, a first pole of the seventh transistor is coupled to the first initialization signal terminal, and a second pole of the seventh transistor is coupled to the gate of the light emission driving transistor;

and/or, the luminescence adjustment circuit comprises an eighth transistor; a gate of the eighth transistor is coupled to the second light emitting control signal terminal, a first pole of the eighth transistor is coupled to the second initialization signal terminal, and a second pole of the eighth transistor is coupled to the light emitting device.

The display panel provided by the embodiment of the disclosure comprises:

a plurality of sub-pixels; wherein each of the sub-pixels includes the pixel circuit.

In some examples, the display panel further comprises:

a plurality of auxiliary signal lines; wherein, the auxiliary signal terminal of the pixel circuit in a row of sub-pixels is coupled with an auxiliary signal line;

a plurality of data signal lines; wherein, the data signal end of the pixel circuit in a column of sub-pixels is coupled with a data signal line;

a plurality of second scanning signal lines; the second scanning signal end of the pixel circuit in one row of sub-pixels is coupled with one second scanning signal line.

In some examples, the display panel further comprises:

a plurality of auxiliary input circuits, wherein one auxiliary input circuit corresponds to a row of sub-pixels, and the auxiliary input circuits are respectively coupled with an auxiliary signal line and a data signal line which are coupled with the corresponding sub-pixels;

the auxiliary input circuit is configured to generate an auxiliary voltage according to a data voltage on the data signal line when a data voltage is applied to a coupled data signal terminal through the data signal line, and input the generated auxiliary voltage to the coupled auxiliary signal line.

In some examples, the auxiliary input circuit includes:

an auxiliary driving transistor, a gate of which is coupled to a corresponding data signal terminal, a first pole of which is coupled to a corresponding auxiliary signal line, and which is configured to generate an auxiliary current according to a data voltage on the data signal line;

and the control circuit is coupled with the first pole of the auxiliary driving transistor, and is configured to adjust the voltage of the first pole of the auxiliary driving transistor according to the auxiliary current and input the adjusted voltage as the auxiliary voltage to a coupled auxiliary signal line.

In some examples, the control circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;

a first terminal of the first resistor is coupled to a first reference signal terminal, and a second terminal of the first resistor is coupled to a first electrode of the auxiliary driving transistor and the auxiliary signal line;

a first terminal of the second resistor is coupled to the first reference signal terminal, and a second terminal of the second resistor is coupled to a second pole of the auxiliary driving transistor;

a first terminal of the third resistor is coupled to the second pole of the auxiliary driving transistor, and a second terminal of the third resistor is coupled to the first pole of the auxiliary driving transistor;

a first terminal of the fourth resistor is coupled to the first pole of the auxiliary driving transistor, and a second terminal of the fourth resistor is coupled to the gate of the auxiliary driving transistor;

a first terminal of the fifth resistor is coupled to a second reference signal terminal, and a second terminal of the fifth resistor is coupled to the first pole of the auxiliary driving transistor.

In some examples, the auxiliary input circuit further comprises: a sixth resistor; wherein the data signal line is coupled to the gate of the auxiliary driving transistor through the sixth resistor;

and/or, the auxiliary input circuit further comprises: an auxiliary control transistor and a seventh resistor; the first electrode of the auxiliary driving transistor is coupled to the corresponding auxiliary signal line through the auxiliary control transistor, and the gate of the auxiliary transistor is coupled to the third reference signal terminal through the seventh resistor.

The display device provided by the embodiment of the disclosure comprises the display panel.

The driving method for the pixel circuit provided by the embodiment of the disclosure comprises the following steps:

a data writing stage in which the data input circuit inputs a data voltage loaded to a data signal terminal in response to a signal of a first scan signal terminal; the first threshold compensation circuit turns on the first electrode of the light emission driving transistor and the compensation node in response to a signal of the first scan signal terminal; the second threshold compensation circuit turns on the gate of the light emission driving transistor and the compensation node in response to a signal of the first scan signal terminal;

an auxiliary stage, wherein the auxiliary control circuit responds to the signal of the second scanning signal terminal and provides an auxiliary voltage of an auxiliary signal terminal to the compensation node;

and in the light-emitting stage, the light-emitting driving transistor generates working current for driving the light-emitting device to emit light according to the data voltage so as to drive the light-emitting device to emit light.

In some examples, before the data writing phase, further comprising: an initialization stage in which the initialization circuit supplies a signal of a first initialization signal terminal to the gate of the light emission driving transistor in response to a signal of a reset signal terminal; the light emitting adjusting circuit responds to a signal of a second light emitting control signal end and provides a signal of a second initialization signal end to the light emitting device;

and/or, the lighting phase comprises: a luminescence sub-stage and a luminescence modulator sub-stage;

in the light emission sub-phase, the light emission control circuit is configured to supply a signal of a first power supply terminal to the second pole of the light emission driving transistor and to turn on the first pole of the light emission driving transistor with the light emitting device in response to a signal of a first light emission control signal terminal; the light-emitting driving transistor generates working current for driving the light-emitting device to emit light according to the data voltage and drives the light-emitting device to emit light;

in the light emission adjusting sub-stage, the light emission adjusting circuit supplies a signal of a second initialization signal terminal to the light emitting device in response to a signal of a second light emission control signal terminal.

The pixel circuit, the driving method thereof, the display panel and the display device provided by the embodiment of the disclosure can enable the auxiliary control circuit to respond to the signal of the second scanning signal terminal by setting the auxiliary control circuit coupled to the compensation node so as to provide the auxiliary voltage of the auxiliary signal terminal to the compensation node. Since the auxiliary voltage is related to the data voltage, the voltage of the compensation node can be related to the data voltage after the auxiliary voltage is provided to the compensation node, so that the voltage of the gate of the light emitting driving transistor can be reduced. Especially, after the pixel circuit is applied to the display panel, when the display panel is driven by adopting a lower refreshing frequency, the Flicker problem of the display panel is reduced.

Drawings

FIG. 1 is a schematic diagram of some configurations of a pixel circuit according to an embodiment of the present disclosure;

FIG. 2 is another schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram of some signals in an embodiment of the present disclosure;

FIG. 5 is a timing diagram of further signals in an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 7 is a diagram illustrating some structures of a display panel according to an embodiment of the present disclosure;

FIG. 8 is another schematic structural diagram of a display panel according to an embodiment of the disclosure;

FIG. 9 is a diagram illustrating some configurations of auxiliary input circuits in an embodiment of the present disclosure;

FIG. 10 is another schematic diagram of an auxiliary input circuit according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram of further structures of the auxiliary input circuit in the embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. And the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to schematically illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

The pixel circuit provided in the embodiment of the present disclosure, as shown in fig. 1, may include:

a light emitting device L;

a light emitting driving transistor M0, a first pole of the light emitting driving transistor M0 is coupled with the light emitting device L, and the light emitting driving transistor M0 is configured to generate an operating current for driving the light emitting device L to emit light according to the data voltage;

a data input circuit 10 coupled to the light emission driving transistor M0, the data input circuit 10 being configured to input a data voltage applied to a data signal terminal DA in response to a signal of a first scan signal terminal GA 1;

a first threshold compensation circuit 20 coupled to the first pole of the light emission driving transistor M0 and the compensation node N0, and the first threshold compensation circuit 20 is configured to turn on the first pole of the light emission driving transistor M0 and the compensation node N0 in response to a signal of the first scan signal terminal GA 1;

a second threshold compensation circuit 30 coupled to the gate of the light emission driving transistor M0 and the compensation node N0, and the second threshold compensation circuit 30 is configured to turn on the gate of the light emission driving transistor M0 and the compensation node N0 in response to a signal of the first scan signal terminal GA 1;

an auxiliary control circuit 40 coupled to the compensation node N0, and the auxiliary control circuit 40 is configured to provide an auxiliary voltage of the auxiliary signal terminal VF to the compensation node N0 in response to a signal of the second scan signal terminal GA 2; wherein the auxiliary voltage is related to the data voltage.

The pixel circuit provided by the embodiment of the disclosure may be configured with an auxiliary control circuit coupled to the compensation node, so that the auxiliary control circuit responds to a signal of the second scan signal terminal to provide an auxiliary voltage of the auxiliary signal terminal to the compensation node. Since the auxiliary voltage is related to the data voltage, the voltage of the compensation node can be related to the data voltage after the auxiliary voltage is provided to the compensation node, so that the voltage of the gate of the light emitting driving transistor can be reduced. Especially, after the pixel circuit is applied to the display panel, when the display panel is driven by adopting a lower refreshing frequency, the Flicker problem of the display panel is reduced.

For example, the display panel may have multiple refresh rates: the pixel circuit provided by the embodiment of the disclosure is applied to a display panel, and then when the display panel is driven at a lower refresh frequency, the Flicker (Flicker) problem of the display panel is reduced.

In implementation, in this embodiment, a first electrode of the light emitting device L is coupled to the first electrode of the light emitting driving transistor M0, and a second electrode of the light emitting device L is coupled to the second power source terminal VSS. The first electrode of the light emitting device L may be an anode thereof, and the second electrode may be a cathode thereof. Also, the light emitting device L is generally an electroluminescent diode, and for example, the light emitting device L may include: at least one of Micro Light Emitting Diodes (Micro LEDs), Organic Light Emitting Diodes (OLEDs), and Quantum Dot Light Emitting Diodes (QLEDs). In addition, the light emitting device L generally has a light emission threshold voltage, and light emission is performed when the voltage across the light emitting device L is greater than or equal to the light emission threshold voltage. In practical applications, the specific structure of the light emitting device L may be designed and determined according to practical application environments, and is not limited herein.

In specific implementation, in the embodiment of the present disclosure, as shown in fig. 1, the light emitting driving transistor M0 may be a P-type transistor; the second electrode of the light-emitting driving transistor M0 is the source thereof, the first electrode of the light-emitting driving transistor M0 is the drain thereof, and when the light-emitting driving transistor M0 is in a saturation state, current flows from the source to the drain of the light-emitting driving transistor M0. Of course, the light emission driving transistor M0 may be an N-type transistor, and is not limited herein.

In specific implementation, in this disclosed embodiment, as shown in fig. 1, the pixel circuit may further include: a light emission control circuit 50; wherein the light emission control circuit 50 is configured to supply a signal of the first power source terminal to the second pole of the light emission driving transistor M0 and to turn on the first pole of the light emission driving transistor M0 and the light emitting device L in response to a signal of the first light emission control signal terminal EM 1.

In specific implementation, in this embodiment of the disclosure, as shown in fig. 1, the pixel circuit may further include: a storage circuit 60, wherein the storage circuit 60 is configured to store the voltage input to the gate of the light-emission driving transistor M0.

In specific implementation, in this disclosed embodiment, as shown in fig. 2, the pixel circuit may further include: an initialization circuit 70; wherein the initialization circuit 70 is configured to supply the signal of the first initialization signal terminal VINIT1 to the gate of the light-emitting driving transistor M0 in response to the signal of the reset signal terminal RES.

In specific implementation, in this embodiment of the disclosure, as shown in fig. 2, the pixel circuit may further include: a light emission adjusting circuit 80; wherein the light emission adjusting circuit 80 is configured to provide a signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to a signal of the second light emission control signal terminal EM 2.

In particular implementation, in the disclosed embodiment, as shown in fig. 3, the auxiliary control circuit 40 may include a first transistor M1; the gate of the first transistor M1 is coupled to the second scan signal terminal GA2, the first pole of the first transistor M1 is coupled to the auxiliary signal terminal VF, and the second pole of the first transistor M1 is coupled to the compensation node N0.

For example, as shown in fig. 3, the first transistor M1 may be provided as a P-type transistor, and the first transistor M1 is turned on under the control of a low level of a signal loaded on the second scan signal terminal GA2 and is turned off under the control of a high level of a signal loaded on the second scan signal terminal GA 2. Alternatively, the first transistor M1 may be provided as an N-type transistor, and the first transistor M1 is turned on under the control of a high level of a signal applied to the second scan signal terminal GA2 and turned off under the control of a low level of a signal applied to the second scan signal terminal GA 2.

In particular implementation, in an embodiment of the present disclosure, as shown in fig. 3, the first threshold compensation circuit 20 may include a second transistor M2; the gate of the second transistor M2 is coupled to the first scan signal terminal GA1, the first pole of the second transistor M2 is coupled to the first pole of the light-emitting driving transistor M0, and the second pole of the second transistor M2 is coupled to the compensation node N0.

For example, as shown in fig. 3, the second transistor M2 may be provided as a P-type transistor, and the second transistor M2 is turned on under the control of a low level of a signal loaded on the first scan signal terminal GA1 and is turned off under the control of a high level of a signal loaded on the first scan signal terminal GA 1. Alternatively, the second transistor M2 may be provided as an N-type transistor, and the second transistor M2 is turned on under the control of the high level of the signal applied from the first scan signal terminal GA1 and turned off under the control of the low level of the signal applied from the first scan signal terminal GA 1.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 3, the second threshold compensation circuit 30 includes a third transistor M3; the gate of the third transistor M3 is coupled to the first scan signal terminal GA1, the first pole of the third transistor M3 is coupled to the compensation node N0, and the second pole of the second transistor M2 is coupled to the gate of the light-emitting driving transistor M0.

Illustratively, as shown in fig. 3, the third transistor M3 may be provided as a P-type transistor, and the third transistor M3 is turned on under the control of a low level of a signal loaded on the first scan signal terminal GA1 and is turned off under the control of a high level of a signal loaded on the first scan signal terminal GA 1. Alternatively, the third transistor M3 may be provided as an N-type transistor, and the third transistor M3 may be turned on under the control of the high level of the signal applied from the first scan signal terminal GA1 and turned off under the control of the low level of the signal applied from the first scan signal terminal GA 1.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 3, the data input circuit 10 includes a fourth transistor M4; the gate of the fourth transistor M4 is coupled to the first scan signal terminal GA1, the first pole of the fourth transistor M4 is coupled to the data signal terminal DA, and the second pole of the fourth transistor M4 is coupled to the second pole of the light-emitting driving transistor M0.

For example, as shown in fig. 3, the fourth transistor M4 may be provided as a P-type transistor, and the fourth transistor M4 is turned on under the control of a low level of a signal loaded on the first scan signal terminal GA1 and is turned off under the control of a high level of a signal loaded on the first scan signal terminal GA 1. Alternatively, the fourth transistor M4 may be provided as an N-type transistor, and the fourth transistor M4 is turned on under the control of the high level of the signal applied from the first scan signal terminal GA1 and turned off under the control of the low level of the signal applied from the first scan signal terminal GA 1.

In concrete implementation, in the embodiment of the present disclosure, as shown in fig. 3, the light emission control circuit 50 includes a fifth transistor M5 and a sixth transistor M6; a gate of the fifth transistor M5 is coupled to the first light emitting control signal terminal EM1, a first electrode of the fifth transistor M5 is coupled to the first power source terminal, and a second electrode of the fifth transistor M5 is coupled to the second electrode of the light emitting driving transistor M0; a gate of the sixth transistor M6 is coupled to the first light emission control signal terminal EM1, a first pole of the sixth transistor M6 is coupled to a first pole of the light emission driving transistor M0, and a second pole of the sixth transistor M6 is coupled to the light emitting device L. Specifically, the second electrode of the sixth transistor M6 is coupled to the first electrode of the light emitting device L.

For example, as shown in fig. 3, the fifth transistor M5 may be provided as a P-type transistor, and the fifth transistor M5 is turned on under the control of a low level of a signal loaded on the first emission control signal terminal EM1 and is turned off under the control of a high level of a signal loaded on the first emission control signal terminal EM 1. Alternatively, the fifth transistor M5 may be provided as an N-type transistor, and the fifth transistor M5 is turned on under the control of a high level of a signal loaded on the first light emission control signal terminal EM1 and turned off under the control of a low level of a signal loaded on the first light emission control signal terminal EM 1.

For example, as shown in fig. 3, the sixth transistor M6 may be provided as a P-type transistor, and the sixth transistor M6 is turned on under the control of a low level of a signal loaded on the first emission control signal terminal EM1 and is turned off under the control of a high level of a signal loaded on the first emission control signal terminal EM 1. Alternatively, the sixth transistor M6 may be provided as an N-type transistor, and the sixth transistor M6 may be turned on under the control of a high level of a signal applied to the first light-emitting control signal terminal EM1 and turned off under the control of a low level of a signal applied to the first light-emitting control signal terminal EM 1.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 3, the storage circuit 60 may include: a storage capacitor CST; the first electrode plate of the storage capacitor CST is coupled to the gate of the light emitting driving transistor M0, and the second electrode plate of the storage capacitor CST is coupled to the second electrode of the light emitting driving transistor M0.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 3, the initialization circuit 70 may include a seventh transistor M7; a gate of the seventh transistor M7 is coupled to the reset signal terminal RES, a first pole of the seventh transistor M7 is coupled to the first initialization signal terminal VINIT1, and a second pole of the seventh transistor M7 is coupled to the gate of the light-emitting driving transistor M0.

For example, as shown in fig. 3, the seventh transistor M7 may be provided as a P-type transistor, and the seventh transistor M7 is turned on under the control of a low level of a signal loaded by the reset signal terminal RES and is turned off under the control of a high level of a signal loaded by the reset signal terminal RES. Alternatively, the seventh transistor M7 may be provided as an N-type transistor, and the seventh transistor M7 may be turned on under the control of a high level of a signal applied to the reset signal terminal RES and turned off under the control of a low level of a signal applied to the reset signal terminal RES. Further, as shown in fig. 3, the seventh transistor M7 may employ a single gate structure.

In particular implementation, in the embodiment of the present disclosure, as shown in fig. 3, the light emission adjusting circuit 80 includes an eighth transistor M8; a gate of the eighth transistor M8 is coupled to the second light emitting control signal terminal EM2, a first pole of the eighth transistor M8 is coupled to the second initialization signal terminal VINIT2, and a second pole of the eighth transistor M8 is coupled to the light emitting device L.

For example, as shown in fig. 3, the eighth transistor M8 may be provided as a P-type transistor, and the eighth transistor M8 is turned on under the control of a low level of a signal loaded on the second light emission control signal terminal EM2 and is turned off under the control of a high level of a signal loaded on the second light emission control signal terminal EM 2. Alternatively, the eighth transistor M8 may be provided as an N-type transistor, and the eighth transistor M8 may be turned on under the control of a high level of a signal applied from the second light emission control signal terminal EM2 and turned off under the control of a low level of a signal applied from the second light emission control signal terminal EM 2.

In the embodiment of the present disclosure, as shown in fig. 3 and 4, when the fifth to eighth transistors M8 are all P-type transistors, the phase of the signal loaded by the second emission control signal terminal EM2 and the phase of the signal loaded by the first emission control signal terminal EM1 may be opposite.

The specific structure of each circuit in the pixel circuit provided by the embodiment of the present disclosure is merely illustrated, and in implementation, the specific structure of the circuit is not limited to the structure provided by the embodiment of the present disclosure, and may be other structures known by those skilled in the art, which are within the protection scope of the present disclosure, and are not limited herein.

For example, in order to reduce the manufacturing process, in practice, in the embodiment of the present disclosure, as shown in fig. 3, the first to eighth transistors M8M1 to M8 may all be P-type transistors. Of course, the first to eighth transistors M8 may be all N-type transistors, which may be designed according to the practical application environment, and are not limited herein.

It should be noted that the Transistor mentioned in the above embodiments of the present disclosure may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), and is not limited herein.

In a specific implementation, a first pole of the transistor can be used as a source electrode and a second pole as a drain electrode of the transistor according to the type of the transistor and a signal of a grid electrode of the transistor; or, conversely, the first pole of the transistor is used as the drain thereof, and the second pole is used as the source thereof, which can be designed according to the practical application environment, and is not particularly distinguished herein.

In this embodiment, the voltage Vdd of the first power source terminal is generally a positive value, and the voltage Vss of the second power source terminal is generally a ground or negative value. In practical applications, the specific values of the voltage Vdd of the first power supply terminal and the voltage Vss of the second power supply terminal can be designed according to practical application environments, and are not limited herein.

The embodiment of the present disclosure also provides a driving method for a pixel circuit, which may include the following steps:

in the data writing phase, the data input circuit 10 inputs the data voltage applied to the data signal terminal DA in response to the signal of the first scan signal terminal GA 1; the first threshold compensation circuit 20 turns on the first pole of the light emission driving transistor M0 and the compensation node N0 in response to the signal of the first scan signal terminal GA 1; the second threshold compensation circuit 30 turns on the gate of the light emission driving transistor M0 and the compensation node N0 in response to the signal of the first scan signal terminal GA 1;

the auxiliary phase, the auxiliary control circuit 40 provides the auxiliary voltage of the auxiliary signal terminal VF to the compensation node N0 in response to the signal of the second scan signal terminal GA 2;

in the light emitting stage, the light emitting driving transistor M0 generates a working current for driving the light emitting device L to emit light according to the data voltage, so as to drive the light emitting device L to emit light.

In some embodiments of the present disclosure, before the data writing phase, the method may further include: in the initialization stage, the initialization circuit 70 supplies a signal of the first initialization signal terminal VINIT1 to the gate of the light-emitting drive transistor M0 in response to the signal of the reset signal terminal RES; the light-emission adjusting circuit 80 supplies a signal of the second initialization signal terminal VINIT2 to the light-emitting device L in response to a signal of the second light-emission control signal terminal EM 2.

In some embodiments of the present disclosure, the lighting phase comprises: a luminescence sub-stage and a luminescence modulator sub-stage; wherein, in the light-emitting sub-phase, the light-emission control circuit 50 is configured to supply a signal of the first power source terminal to the second pole of the light-emitting driving transistor M0 and to turn on the first pole of the light-emitting driving transistor M0 with the light-emitting device L in response to a signal of the first light-emission control signal terminal EM 1; the light emitting driving transistor M0 generates an operating current for driving the light emitting device L to emit light according to the data voltage, and drives the light emitting device L to emit light. In the light emission adjusting sub-stage, the light emission adjusting circuit 80 supplies a signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to a signal of the second light emission control signal terminal EM 2.

The following describes the operation of the pixel circuit provided in the embodiment of the present disclosure with reference to the signal timing diagram shown in fig. 4 by taking the structure of the pixel circuit shown in fig. 3 as an example. The initialization phase T1, the data writing phase T2, the auxiliary phase T3, and the light-emitting phase T4 in the signal timing diagram shown in fig. 4 are mainly selected. The light-emitting phase T4 includes a light-emitting sub-phase T41, a light-emitting modulation sub-phase T42, and a light-emitting sub-phase T43. And RES represents a signal applied to the reset signal terminal RES, GA1 represents a signal applied to the first scan signal terminal GA1, GA2 represents a signal applied to the second scan signal terminal GA2, EM1 represents a signal applied to the first emission control signal terminal EM1, EM2 represents a signal applied to the second emission control signal terminal EM2, DA represents a signal applied to the data signal terminal DA, and VF represents a signal applied to the auxiliary signal terminal VF.

In the initialization period T1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The first transistor M1 is turned off under the control of the high level of the signal ga 2. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned on under the control of the low level of the signal res to supply the signal loaded from the first initialization signal terminal VINIT1 to the gate of the light emitting driving transistor M0 to initialize the gate of the light emitting driving transistor M0. The eighth transistor M8 is turned on by the low level of the signal em2 to supply the signal applied from the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L.

In the data writing period T2, the first transistor M1 is turned off under the control of the high level of the signal ga 2. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned off under the control of the high level of the signal res. The eighth transistor M8 is turned on under the control of the low level of the signal em2 to supply the signal applied from the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on by the low level of the signal ga 1. Since the second transistor M2 and the third transistor M3 are turned on, the light emitting driving transistor M0 forms a diode connection structure. The data signal terminal DA loads the data voltage and passes through the turned-on fourth transistor M4 and a light-emitting driving transistor M0 forming a diode connection structure, the gate of the light-emitting driving transistor M0 is charged until the gate voltage of the light-emitting driving transistor M0 becomes Vda + Vth₁(Vda represents data voltage Vth)₁Representing the threshold voltage of the light emission driving transistor M0).

In the auxiliary phase T3, the second transistor M2, the third transistor M3 and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned off under the control of the high level of the signal res. The eighth transistor M8 is turned on under the control of the low level of the signal em2 to supply the signal applied from the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L. The first transistor M1 is turned on under the control of the low level of the signal ga2 to supply the auxiliary voltage Vvf applied to the auxiliary signal terminal VF to the compensation node N0, so that the voltage at the compensation node N0 becomes an auxiliary voltage according to the data voltage Vda. Therefore, the voltage of the gate of the light emitting driving transistor M0 can be lowered, and the voltage stability of the gate of the light emitting driving transistor M0 can be improved due to the leakage current occurring in the leakage current path formed by the second transistor M2 and the third transistor M3. Particularly, after the pixel circuit is applied to the display panel, when the display panel is driven by adopting a lower refreshing frequency, the flicker problem of the display panel is reduced.

In the light emitting sub-period T41, the first transistor M1 is turned off under the control of the high level of the signal ga 2. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The seventh transistor M7 is turned off under the control of the high level of the signal res. The eighth transistor M8 is turned off under the control of the high level of the signal em 2. And, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the signal em 1. The turned-on fifth transistor M5 supplies the signal of the first power source terminal to the second pole of the light-emitting driving transistor M0 such that the voltage of the second pole of the light-emitting driving transistor M0 is Vdd. The gate voltage of the light emitting driving transistor M0 is Vda + Vth₁The operating current generated by the light emitting driving transistor M0IL is: IL ═ K₁(Vda+Vth₁-Vdd-Vth₁)²＝K₁(Vda-Vdd)². The turned-on sixth transistor M6 turns on the first electrode of the light emitting driving transistor M0 and the first electrode of the light emitting device L, thereby supplying the operating current IL to the light emitting device L to drive the light emitting device L to emit light. And, K₁Is a structural constant of the light emission driving transistor M0.

In the light emission adjusting sub-period T42, the first transistor M1 is turned off under the control of the high level of the signal ga 2. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned off under the control of the high level of the signal res. The eighth transistor M8 is turned on by the low level of the signal em2 to supply the signal applied from the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L, so that the light emitting device L is turned off to stop emitting light.

In the light-emitting sub-period T43, the first transistor M1 is turned off under the control of the high level of the signal ga 2. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The seventh transistor M7 is turned off under the control of the high level of the signal res. The eighth transistor M8 is turned off under the control of the high level of the signal em 2. And, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the signal em 1. The turned-on fifth transistor M5 supplies the signal of the first power source terminal to the second terminal of the light emitting driving transistor M0, so that the voltage of the second terminal of the light emitting driving transistor M0 is Vdd. The gate voltage of the light emitting driving transistor M0 is Vda + Vth₁The operating current IL generated by the light emitting driving transistor M0 is: IL-K [ Vda + Vth₁-Vdd-Vth₁]²＝K[Vda-Vdd]². The turned-on sixth transistor M6 turns on the first electrode of the light emitting driving transistor M0 and the first electrode of the light emitting device L, thereby supplying the operating current IL to the light emitting device L to drive the light emitting device L to emit light.

It should be noted that by providing the light emission adjusting sub-stage in the light emission stage, the luminance of the light emitting device L can be adjusted. And the light-emitting sub-stage and the light-emitting adjusting sub-stage included in the light-emitting stage are alternately arranged. The specific number of the light-emitting sub-stages and the light-emitting adjusting sub-stages included in the light-emitting stage may be determined according to the actual application, and is not limited herein.

The embodiments of the present disclosure provide other timing diagrams of signals of pixel circuits, as shown in fig. 5, which are modified from the embodiments in the foregoing embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the same parts will not be described herein again.

In embodiments of the present disclosure, the initialization phase may include a first initialization phase and a second initialization phase. Wherein the first initialization phase and the second initialization phase are alternately arranged. Also, the number of the first initialization phase and the second initialization phase may be the same. For example, the first initialization phase and the second initialization phase may be set to 3, respectively. Of course, the number of the first initialization phase and the second initialization phase may be determined according to the requirements of the actual application.

In the embodiment of the present disclosure, in the first initialization stage, the initialization circuit 70 supplies a signal of the first initialization signal terminal VINIT1 to the gate of the light emitting driving transistor M0 in response to the signal of the reset signal terminal RES. The light-emission adjusting circuit 80 supplies a signal of the second initialization signal terminal VINIT2 to the light-emitting device L in response to a signal of the second light-emission control signal terminal EM 2.

In the embodiment of the present disclosure, in the second initialization phase, the data input circuit 10 supplies the reset voltage, which is applied to the data signal terminal DA, to the second pole of the light emitting driving transistor M0 in response to the signal of the first scan signal terminal GA 1. The light-emission adjusting circuit 80 supplies a signal of the second initialization signal terminal VINIT2 to the light-emitting device L in response to a signal of the second light-emission control signal terminal EM 2.

The following describes an operation process of the pixel circuit provided in the embodiment of the present disclosure with reference to the signal timing diagram shown in fig. 5 by taking the structure of the pixel circuit shown in fig. 3 as an example. The initialization phase T1, the data writing phase T2, the auxiliary phase T3, and the light-emitting phase T4 in the signal timing diagram shown in fig. 5 are mainly selected. The initialization phase T1 includes a first initialization phase T11, a second initialization phase T12, a first initialization phase T13, a second initialization phase T14, and a first initialization phase T15. The light emission period T4 includes a light emission sub-period T41, a light emission adjustment sub-period T42, and a light emission sub-period T43. And RES represents a signal applied to the reset signal terminal RES, GA1 represents a signal applied to the first scan signal terminal GA1, GA2 represents a signal applied to the second scan signal terminal GA2, EM1 represents a signal applied to the first emission control signal terminal EM1, EM2 represents a signal applied to the second emission control signal terminal EM2, DA represents a signal applied to the data signal terminal DA, and VF represents a signal applied to the auxiliary signal terminal VF.

In the first initialization period T11, the second transistor M2, the third transistor M3 and the fourth transistor M4 are turned off under the control of the high level of the signal ga 1. The first transistor M1 is turned off under the control of the high level of the signal ga 2. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned on under the control of the low level of the signal res to supply the signal loaded from the first initialization signal terminal VINIT1 to the gate of the light emitting driving transistor M0 to initialize the gate of the light emitting driving transistor M0. The eighth transistor M8 is turned on by the low level of the signal em2 to supply the signal applied from the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L.

In the second initialization period T12, the first transistor M1 is turned off under the control of the high level of the signal ga 2. The fifth transistor M5 and the sixth transistor M6 are turned off under the control of the high level of the signal em 1. The seventh transistor M7 is turned off under the control of the low level of the signal res. The second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on under the control of the low level of the signal ga1, so as to provide the reset voltage applied to the data signal terminal DA to the gate, the first pole, and the second pole of the light emitting driving transistor M0, and initialize the gate, the first pole, and the second pole of the light emitting driving transistor M0. The eighth transistor M8 is turned on by the low level of the signal em2 to supply the signal applied from the second initialization signal terminal VINIT2 to the first electrode of the light emitting device L to initialize the light emitting device L.

In the first initialization stage T13, the working process of the pixel circuit in the stage T13 is substantially the same as that in the stage T11, and is not described herein again.

In the second initialization stage T14, the working process of the pixel circuit in the stage T14 is substantially the same as that in the stage T12, and is not described herein again.

In the first initialization stage T15, the working process of the pixel circuit in the stage T15 is substantially the same as that in the stage T11, and is not described herein again.

The working processes of the pixel circuit in the data writing stage T2, the auxiliary stage T3, and the light emitting stage T4 are substantially the same as those in the above embodiments, and are not described herein again.

The embodiments of the present disclosure provide other schematic structural diagrams of a pixel circuit, as shown in fig. 6, which are modified from the implementation in the foregoing embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In some embodiments of the present disclosure, the seventh transistor M7 may also be provided as a double gate structure. For example, as shown in fig. 6, the seventh transistor M7 may include a first sub transistor and a second sub transistor. The gates of the first and second sub-transistors are coupled to the reset signal terminal RES, the first pole of the first sub-transistor is coupled to the first initialization signal terminal VINIT1, the second pole of the first sub-transistor is coupled to the first pole of the second sub-transistor, and the second pole of the second sub-transistor is coupled to the gate of the light-emitting driving transistor M0. Illustratively, the first sub-transistor and the second sub-transistor may each be provided as a P-type transistor which is turned on by a low level of a signal of the reset signal terminal RES and turned off by a high level of the signal of the reset signal terminal RES.

Fig. 4 and 5 show signal timing charts corresponding to the pixel circuit shown in fig. 6. Moreover, the working process of the pixel circuit shown in fig. 6 may be substantially the same as that of the above embodiment, and is not repeated herein.

The disclosed embodiments also provide a display panel, as shown in fig. 7, which may include a display area and a non-display area. The display region may include a plurality of pixel units arranged in an array. Illustratively, each pixel cell includes a plurality of different color sub-pixels spx. Any of the pixel circuits described above may be included in each sub-pixel. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing may be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color display may be realized by performing color mixing of red, green, blue, and white. Of course, in practical applications, the light emitting color of the sub-pixels in the pixel unit may be determined according to practical application environments, and is not limited herein. The following description will take an example in which the pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

In some embodiments of the present disclosure, as shown in fig. 8, the display panel may further include: a plurality of auxiliary signal lines VFS, a plurality of data signal lines DAS, a plurality of reset signal lines RESS, a plurality of first light emission control signal lines EMS1, a plurality of second light emission control signal lines EMS2, a plurality of first scan signal lines GAS1, and a plurality of second scan signal lines GAS 2. The auxiliary signal terminal VF of the pixel circuits in a row of sub-pixels is coupled to an auxiliary signal line VFs, so as to transmit an auxiliary voltage to the auxiliary signal terminal VF through the auxiliary signal line VFs. Also, the data signal terminals DA of the pixel circuits in a column of the sub-pixels are coupled to a data signal line DAs to transmit data voltages and reset voltages to the data signal terminals DA through the data signal line DAs. Also, the reset signal terminal RES of the pixel circuit in one row of the sub-pixels is coupled to one reset signal line RESs to transmit a signal to the reset signal terminal RES through the reset signal line RESs. Also, the first scan signal terminal GA1 of the pixel circuit in a row of sub-pixels is coupled to one first scan signal line GAs1 to transmit a signal to the first scan signal terminal GA1 through the first scan signal line GAs 1. Also, the second scan signal terminal GA2 of the pixel circuit in a row of sub-pixels is coupled to one second scan signal line GAs2 to transmit a signal to the second scan signal terminal GA2 through the second scan signal line GAs 2. Also, the first light emission control signal terminal EM1 of the pixel circuit in one row of sub-pixels is coupled to one first light emission control signal line EMs1 to transmit a signal to the first light emission control signal terminal EM1 through the first light emission control signal line EMs 1. Also, the second emission control signal terminal EM2 of the pixel circuit in one row of sub-pixels is coupled to one second emission control signal line EMs2 to transmit a signal to the second emission control signal terminal EM2 through the second emission control signal line EMs 2.

In the embodiment of the present disclosure, as shown in fig. 8, the display panel may further include: a plurality of auxiliary input circuits 100. The plurality of auxiliary input circuits 100 may be disposed in the non-display area. One auxiliary input circuit 100 corresponds to a row of sub-pixels, and the auxiliary input circuit 100 is coupled to the auxiliary signal line VFS and the data signal line DAS respectively coupled to the corresponding sub-pixels. Also, the auxiliary input circuit 100 is configured to generate an auxiliary voltage according to the data voltage on the data signal line DAS when a data voltage is applied to the coupled data signal terminal DA through the data signal line DAS, and input the generated auxiliary voltage onto the coupled auxiliary signal line VFS.

In the embodiment of the present disclosure, as shown in fig. 9, the auxiliary input circuit 100 may include: an auxiliary drive transistor Mf and a control circuit 110. The gate of the auxiliary driving transistor Mf is coupled to the corresponding data signal terminal DA, the first pole of the auxiliary driving transistor Mf is coupled to the corresponding auxiliary signal line VFS, and the auxiliary driving transistor Mf is configured to generate an auxiliary current according to the data voltage on the data signal line DAs. The control circuit 110 is coupled to the first pole of the auxiliary drive transistor Mf, and the control circuit 110 is configured to adjust a voltage of the first pole of the auxiliary drive transistor Mf according to the auxiliary current and input the adjusted voltage as an auxiliary voltage onto the coupled auxiliary signal line VFS. Illustratively, the auxiliary drive transistor Mf may be provided as a P-type transistor. The second pole of the auxiliary driving transistor Mf is the source thereof, the first pole of the auxiliary driving transistor Mf is the drain thereof, and when the auxiliary driving transistor Mf is in a saturation state, a current flows from the source to the drain of the auxiliary driving transistor Mf. Of course, the auxiliary driving transistor Mf may be an N-type transistor, and is not limited herein.

In the embodiment of the present disclosure, as shown in fig. 10, the control circuit 110 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

a first terminal of the first resistor R1 is coupled to the first reference signal terminal VREF1, and a second terminal of the first resistor R1 is coupled to the first pole of the auxiliary driving transistor Mf;

a first terminal of the second resistor R2 is coupled to the first reference signal terminal VREF1, and a second terminal of the second resistor R2 is coupled to the second pole of the auxiliary driving transistor Mf;

a first terminal of the third resistor R3 is coupled to the second pole of the auxiliary drive transistor Mf, and a second terminal of the third resistor R3 is coupled to the first pole of the auxiliary drive transistor Mf;

a first terminal of the fourth resistor R4 is coupled to the first pole of the auxiliary drive transistor Mf, and a second terminal of the fourth resistor R4 is coupled to the gate of the auxiliary drive transistor Mf;

a first terminal of the fifth resistor R5 is coupled to the second reference signal terminal VREF2, and a second terminal of the fifth resistor R5 is coupled to the first pole of the auxiliary driving transistor Mf.

In the embodiment of the present disclosure, as shown in fig. 11, the auxiliary input circuit 100 may further include: a sixth resistor R6; the data signal line DAS is coupled to the gate of the auxiliary drive transistor Mf through a sixth resistor R6.

In the embodiment of the present disclosure, as shown in fig. 11, the auxiliary input circuit 100 may further include: an auxiliary control transistor Mc and a seventh resistor R7; the first electrode of the auxiliary driving transistor Mf is coupled to the corresponding auxiliary signal line VFS through the auxiliary control transistor Mc, and the gate of the auxiliary transistor is coupled to the third reference signal terminal VREF3 through the seventh resistor R7. For example, the auxiliary control transistor Mc may be set as a P-type transistor, and the signal of the third reference signal terminal VREF3 may be set as a low level signal of direct current, so that the auxiliary control transistor Mc may be controlled to be continuously turned on. Alternatively, the auxiliary control transistor Mc may be an N-type transistor, and the signal of the third reference signal terminal VREF3 may be a high-level signal of direct current, so that the auxiliary control transistor Mc may be controlled to be continuously turned on.

For example, the resistance value of the fifth resistor R5 may be greater than the resistance value of the fourth resistor R4. For example, the resistance value of the fifth resistor R5 may be made much larger than the resistance value of the fourth resistor R4. Of course, in practical applications, the resistance value of the fifth resistor R5 and the resistance value of the fourth resistor R4 may be determined according to the requirements of practical applications, and are not limited herein.

Illustratively, the resistance value of the second resistor R2, the resistance value of the sixth resistor R6, and the resistance value of the seventh resistor R7 may be substantially the same. Of course, in practical applications, the resistance value of the second resistor R2, the resistance value of the sixth resistor R6, and the resistance value of the seventh resistor R7 may be determined according to practical application requirements, and are not limited herein.

For example, the resistance value of the first resistor R1 and the resistance value of the third resistor R3 may be substantially the same. Of course, in practical applications, the resistance value of the first resistor R1 and the resistance value of the third resistor R3 may be determined according to practical application requirements, and are not limited herein.

For example, the signal of the first reference signal terminal VREF1 may be a low voltage of direct current, and the signal of the second reference signal terminal VREF2 may be a high voltage of direct current. Of course, in practical applications, the specific voltage values of the signal of the first reference signal terminal VREF1 and the signal of the second reference signal terminal VREF2 may be determined according to requirements of practical applications, and are not limited herein.

The following description will be given by taking the structure shown in fig. 11 as an example. When the data voltage Vda is applied to the data signal line DAS, the auxiliary drive transistor Mf may generate the auxiliary current Id, where Id is K, by the interaction of the first resistor R1 through the sixth resistor R6₂*(Vda-VN₂-Vth₂)². Since the auxiliary control transistor Mc is normally on, the first current can be adjusted by the action of the auxiliary current IdThe voltage of the second terminal of the resistor R1 may be used to adjust the voltage of the auxiliary voltage on the auxiliary signal line VFS. So that the voltage of the auxiliary voltage on the auxiliary signal line VFS can be related to the current data voltage Vda. Thus, the voltage at the compensation node N0 can be an auxiliary voltage related to the data voltage Vda during the auxiliary phase T3. Therefore, the voltage of the gate of the light emitting driving transistor M0 can be lowered, and the voltage stability of the gate of the light emitting driving transistor M0 can be improved due to the leakage current occurring in the leakage current path formed by the second transistor M2 and the third transistor M3. Particularly, after the pixel circuit is applied to the display panel, when the display panel is driven by adopting a lower refreshing frequency, the flicker problem of the display panel is reduced.

The embodiment of the disclosure also provides a display device, which comprises the display panel provided by the embodiment of the disclosure. The principle of the display device to solve the problem is similar to the display panel, so the implementation of the display device can be referred to the implementation of the display panel, and repeated details are not repeated herein.

In specific implementation, in the embodiment of the present disclosure, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.

The pixel circuit, the driving method thereof, the display panel and the display device provided by the embodiment of the disclosure can enable the auxiliary control circuit to respond to the signal of the second scanning signal terminal by setting the auxiliary control circuit coupled to the compensation node so as to provide the auxiliary voltage of the auxiliary signal terminal to the compensation node. Since the auxiliary voltage is related to the data voltage, the voltage of the compensation node can be related to the data voltage after the auxiliary voltage is provided to the compensation node, so that the voltage of the gate of the light emitting driving transistor can be reduced. Especially, after the pixel circuit is applied to the display panel, when the display panel is driven by adopting a lower refreshing frequency, the problem of Flicker of the display panel is reduced.

It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations as well.

Claims

1. A pixel circuit, comprising:

a light emitting device;

a first threshold compensation circuit coupled to the first electrode of the light emission driving transistor and a compensation node, and configured to turn on the first electrode of the light emission driving transistor and the compensation node in response to a signal of the first scan signal terminal;

2. The pixel circuit according to claim 1, wherein the auxiliary control circuit includes a first transistor;

3. The pixel circuit according to claim 1, wherein the first threshold compensation circuit comprises a second transistor; wherein a gate electrode of the second transistor is coupled to the first scan signal terminal, a first electrode of the second transistor is coupled to a first electrode of the light emitting driving transistor, and a second electrode of the second transistor is coupled to the compensation node;

and/or the second threshold compensation circuit comprises a third transistor; wherein a gate of the third transistor is coupled to the first scan signal terminal, a first pole of the third transistor is coupled to the compensation node, and a second pole of the second transistor is coupled to a gate of the light emission driving transistor.

4. The pixel circuit according to claim 1, wherein the data input circuit includes a fourth transistor; wherein a gate of the fourth transistor is coupled to the first scan signal terminal, a first pole of the fourth transistor is coupled to the data signal terminal, and a second pole of the fourth transistor is coupled to the second pole of the light emitting driving transistor.

5. The pixel circuit according to any of claims 1-4, wherein the pixel circuit further comprises: a light emission control circuit; wherein the light emission control circuit is configured to supply a signal of a first power source terminal to a second pole of the light emission driving transistor and to turn on the first pole of the light emission driving transistor with the light emitting device in response to a signal of a first light emission control signal terminal;

6. The pixel circuit according to claim 5, wherein the light emission control circuit includes a fifth transistor and a sixth transistor; wherein a gate of the fifth transistor is coupled to the first light-emitting control signal terminal, a first pole of the fifth transistor is coupled to the first power terminal, and a second pole of the fifth transistor is coupled to the second pole of the light-emitting driving transistor; a gate of the sixth transistor is coupled to the first light emitting control signal terminal, a first pole of the sixth transistor is coupled to the first pole of the light emitting driving transistor, and a second pole of the sixth transistor is coupled to the light emitting device;

and/or, the luminescence adjustment circuit comprises an eighth transistor; wherein a gate of the eighth transistor is coupled to the second light emission control signal terminal, a first pole of the eighth transistor is coupled to the second initialization signal terminal, and a second pole of the eighth transistor is coupled to the light emitting device.

7. A display panel, comprising:

a plurality of sub-pixels; wherein each of the sub-pixels comprises a pixel circuit according to any one of claims 1-6.

8. The display panel of claim 7, wherein the display panel further comprises:

9. The display panel according to claim 8, wherein the display panel further comprises:

a plurality of auxiliary input circuits, wherein one auxiliary input circuit corresponds to a column of sub-pixels, and the auxiliary input circuits are respectively coupled with an auxiliary signal line and a data signal line which are coupled with the corresponding sub-pixels;

10. The display panel according to claim 9, wherein the auxiliary input circuit comprises:

and the control circuit is coupled with the first pole of the auxiliary driving transistor and is configured to adjust the voltage of the first pole of the auxiliary driving transistor according to the auxiliary current and input the adjusted voltage as the auxiliary voltage to the coupled auxiliary signal line.

11. The display panel according to claim 10, wherein the control circuit comprises: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor;

12. The display panel of claim 11, wherein the auxiliary input circuit further comprises: a sixth resistor; wherein the data signal line is coupled to the gate of the auxiliary driving transistor through the sixth resistor;

and/or, the auxiliary input circuit further comprises: an auxiliary control transistor and a seventh resistor; the first pole of the auxiliary driving transistor is coupled to the corresponding auxiliary signal line through the auxiliary control transistor, and the gate of the auxiliary driving transistor is coupled to the third reference signal terminal through the seventh resistor.

13. A display device characterized by comprising the display panel according to any one of claims 7 to 12.

14. A driving method for the pixel circuit according to any one of claims 1 to 6, comprising:

and in the light emitting stage, the light emitting driving transistor generates working current for driving the light emitting device to emit light according to the data voltage and drives the light emitting device to emit light.

15. The driving method according to claim 14, further comprising, before the data writing phase: an initialization stage in which the initialization circuit supplies a signal of a first initialization signal terminal to the gate of the light emission driving transistor in response to a signal of a reset signal terminal; the light emitting adjusting circuit responds to a signal of a second light emitting control signal end and provides a signal of a second initialization signal end to the light emitting device;

in the light emitting sub-phase, the light emission control circuit is configured to supply a signal of a first power supply terminal to the second pole of the light emission driving transistor and to turn on the first pole of the light emission driving transistor with the light emitting device in response to a signal of a first light emission control signal terminal; the light-emitting driving transistor generates working current for driving the light-emitting device to emit light according to the data voltage and drives the light-emitting device to emit light;