CN117116211A

CN117116211A - Pixel circuit, driving method and display device

Info

Publication number: CN117116211A
Application number: CN202311225744.9A
Authority: CN
Inventors: 王伟婷
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2023-09-21
Filing date: 2023-09-21
Publication date: 2023-11-24

Abstract

The invention relates to the technical field of display, in particular to a pixel circuit, a driving method and a display device, which comprise a first light-emitting unit, a second light-emitting unit, a first driving circuit configured to generate driving current for driving the first light-emitting unit, and a second driving circuit configured to generate driving current for driving the second light-emitting unit, wherein a first power line is used for respectively providing a first power supply signal for the first driving circuit and the second light-emitting unit, a second power line is used for respectively providing a second power supply signal for the second driving circuit and the first light-emitting unit, and in the light-emitting stage of the pixel circuit, the first power supply signal and the second power supply signal are configured to be in voltage high-low jump along with time, and the first light-emitting unit and the second light-emitting unit alternately emit light. The pixel circuit can not only reduce the hysteresis effect, but also prolong the service life of the light-emitting device.

Description

Pixel circuit, driving method and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a driving method, and a display device.

Background

With the development of electronic technology, smart phones are widely used by people, and have become a necessary tool for people to communicate, entertain and learn daily. However, there is a growing demand for display panels, and particularly, display image quality is always an important measure of product quality for consumers and manufacturers. At present, most of display panels are AMOLED (Active-matrix Organic Light-Emitting Diode), and although LTPS (Low Temperature Poly-Silicon) preparation technology is mature, a certain hysteresis effect still exists during operation, so that a problem of ghost appears during OLED (Organic Light-Emitting Diode) display, thereby affecting the visual display of the display panel.

Disclosure of Invention

Accordingly, it is necessary to provide a pixel circuit, a driving method, and a display device for solving the problem that a thin film transistor (Thin Film Transistor, TFT) has a hysteresis effect during operation, which causes a ghost.

A pixel circuit comprises a first light emitting unit, a second light emitting unit, a first driving circuit and a second driving circuit which is symmetrical to the center of the first driving circuit, wherein the first driving circuit is electrically connected with a first pole of the first light emitting unit and is configured to generate driving current for driving the first light emitting unit to emit light, the second driving circuit is electrically connected with a first pole of the second light emitting unit and is configured to generate driving current for driving the second light emitting unit to emit light, a power input end of the first driving circuit and a second pole of the second light emitting unit are respectively connected with a first power line, a power input end of the second driving circuit and a second pole of the first light emitting unit are respectively connected with a second power line, the first power line is used for respectively providing a first power supply signal for the first driving circuit and the second light emitting unit, the second power line is used for respectively providing a second power supply signal for the second driving circuit and the first light emitting unit, the pixel circuit comprises a light emitting stage in the working process of one display frame, the first power supply signal and the second power supply signal are configured to be low in time, and the first power supply signal and the second power supply signal are alternately high in the light emitting stage.

In one embodiment, the first driving circuit and the second driving circuit each include a data writing unit, a storage unit and a driving unit, the data writing unit is connected with a control end of the driving unit, and the data writing unit is configured to write a data signal into the control end of the driving unit according to a first scanning signal; the storage unit is used for storing the voltage at the control end of the driving unit; the driving unit in the first driving circuit is connected between the power input end of the first driving circuit and the first pole of the first light-emitting unit, and the driving unit in the second driving circuit is connected between the power input end of the second driving circuit and the first pole of the second light-emitting unit; the driving unit is configured to generate a driving current according to a voltage of a control terminal of the driving unit.

In one embodiment, optionally, the control terminal of the data writing unit in the first driving circuit and the control terminal of the data writing unit in the second driving circuit are connected to the same first scan line.

In one embodiment, optionally, the data writing unit in the first driving circuit and the data writing unit in the second driving circuit are connected to the same data line.

In one embodiment, the driving unit includes a first transistor, a first pole of the first transistor being a first terminal of the driving unit, a gate of the first transistor being a control terminal of the driving unit, and a second pole of the first transistor being a second terminal of the driving unit; the data writing unit comprises a second transistor, a first electrode of the second transistor is connected with the control end of the driving unit, a grid electrode of the second transistor is connected with the first scanning line, and a second electrode of the second transistor is connected with the data line; the storage unit comprises a storage capacitor, a first end of the storage capacitor in the first driving circuit is connected with a first power line, a first end of the storage capacitor in the second driving circuit is connected with a second power line, a second end of the storage capacitor in the first driving circuit is connected with a control end of the driving unit, and a second end of the storage capacitor in the second driving circuit is connected with a control end of the driving unit.

In one embodiment, the first driving circuit and the second driving circuit each include a data writing unit, a storage unit, a driving unit and a compensation unit, the data writing unit is connected with the first end of the driving unit, and the data writing unit is configured to write a data signal into the first end of the driving unit according to the first scanning signal; the storage unit is used for storing the voltage at the control end of the driving unit; the driving unit in the first driving circuit is connected between the power input end of the first driving circuit and the first pole of the first light-emitting unit, and the driving unit in the second driving circuit is connected between the power input end of the second driving circuit and the first pole of the second light-emitting unit; the driving unit is configured to generate a driving current according to a voltage of a control end of the driving unit; the compensation unit is connected between the control end of the driving unit and the second end of the driving unit, and is configured to perform threshold compensation on the driving unit according to the first scanning signal.

In one embodiment, optionally, the control terminal of the compensation unit in the first driving circuit and the control terminal of the compensation unit in the second driving circuit are connected to the same first scan line.

In one embodiment, the first driving circuit and the second driving circuit further include a first initializing unit and/or a second initializing unit, the first initializing unit in the first driving circuit is connected to the first pole of the first light emitting unit, the first initializing unit in the second driving circuit is connected to the first pole of the second light emitting unit, and the first initializing unit is configured to transmit an initializing signal to the light emitting unit connected thereto according to the second scan signal to initialize the light emitting unit connected thereto; and/or in the same driving circuit, the second initializing unit is respectively connected with the control end of the driving unit and the storage unit, and is configured to transmit an initializing signal to the control end of the driving unit according to the third scanning signal so as to initialize the storage unit.

In one embodiment, optionally, the control terminal of the first initializing unit in the first driving circuit and the control terminal of the first initializing unit in the second driving circuit are connected to the same second scan line.

In one embodiment, optionally, the control terminal of the second initializing unit in the first driving circuit and the control terminal of the second initializing unit in the second driving circuit are connected to the same third scan line.

In one embodiment, optionally, the first initializing unit includes a third transistor, and in the same driving circuit, a first electrode of the third transistor is connected to the light emitting unit connected to the first initializing unit, a gate electrode of the third transistor is connected to the second scan line, and a second electrode of the third transistor is connected to the initializing signal line.

In one embodiment, optionally, the second initializing unit includes a fourth transistor, a first electrode of the fourth transistor is connected to the control terminal of the driving unit and the memory unit respectively in the same driving circuit, a gate of the fourth transistor is connected to the third scan line, and a second electrode of the fourth transistor is connected to the initializing signal line.

In one embodiment, during the lighting period, the first power supply signal and the second power supply signal are configured to have voltage jump with time, and the voltage of the first power supply signal and the voltage of the second power supply signal are opposite.

In one embodiment, optionally, the first driving circuit and the second driving circuit further include a first light emitting control unit and/or a second light emitting control unit, the first light emitting control unit in the first driving circuit is connected between the second end of the driving unit and the first pole of the first light emitting unit, the first light emitting control unit in the second driving circuit is connected between the second end of the driving unit and the first pole of the second light emitting unit, and the first light emitting control unit is configured to turn on or off connection between the second end of the driving unit and the first pole of the light emitting unit to which the first light emitting control unit is connected according to the light emitting control signal; and/or a second light-emitting control unit in the first driving circuit is connected between the first power line and the first end of the driving unit, the second light-emitting control unit in the second driving circuit is connected between the second power line and the first end of the driving unit, and the second light-emitting control unit is configured to switch on or off the connection between the power line connected with the second light-emitting control unit and the first end of the driving unit according to the light-emitting control signal.

In one embodiment, optionally, the control terminal of the first light emitting control unit in the first driving circuit and the control terminal of the first light emitting control unit in the second driving circuit are connected to the same control signal line.

In one embodiment, optionally, the control terminal of the second light emission control unit in the first driving circuit and the control terminal of the second light emission control unit in the second driving circuit are connected to the same control signal line.

In one embodiment, optionally, the first light emitting control unit includes a fifth transistor, in the same driving circuit, a first pole of the fifth transistor is connected to the second terminal of the driving unit, a gate of the fifth transistor is connected to the control signal line, and a second pole of the fifth transistor is connected to the first pole of the light emitting unit connected to the first light emitting control unit.

In one embodiment, optionally, the second light-emitting control unit includes a sixth transistor, in the same driving circuit, a first electrode of the sixth transistor is connected to the first end of the driving unit, a gate electrode of the sixth transistor is connected to the control signal line, and a second electrode of the sixth transistor is connected to a power line connected to the second light-emitting control unit.

A display device comprising a pixel circuit according to any one of the embodiments described above.

In one embodiment, the pixel circuits are plural and arranged in an array.

In one embodiment, optionally, in the same pixel circuit, the first driving circuit and the second driving circuit are arranged in a row direction; the first driving circuit and the second driving circuit are connected to the same data line, the data line extends along the column direction, and the row direction and the column direction intersect.

A driving method of a pixel circuit for driving the pixel circuit according to any one of the above embodiments, the driving method includes configuring a first power supply signal and a second power supply signal received by the pixel circuit to have a voltage which is stepped with time in a light emitting stage, so that the first light emitting unit and the second light emitting unit alternately emit light.

In one embodiment, the pixel circuit further includes a first initialization stage, a data writing stage, and a second initialization stage before the light emitting stage during operation of one display frame, and the driving method further includes configuring the third scan signal as an on voltage and the first scan signal, the second scan signal, and the light emitting control signal as an off voltage during the first initialization stage; in the data writing stage, the first scanning signal is configured to be an on voltage, and the second scanning signal, the third scanning signal and the light-emitting control signal are configured to be an off voltage; in the second initialization stage, the second scanning signal is configured to be a conducting voltage, and the first scanning signal, the third scanning signal and the light-emitting control signal are configured to be a cut-off voltage; in the light emitting stage, the light emission control signal is configured as an on voltage, and the first, second, and third scan signals are configured as off voltages.

In one embodiment, optionally, during the data writing phase, the first power supply signal and the second power supply signal are the same, and during the data writing phase, the voltages of the first power supply signal and the second power supply signal are equal to the voltage of the first power supply signal when the first light emitting unit emits light during the light emitting phase.

In one embodiment, optionally, in the first initialization stage, the first power supply signal and the second power supply signal are the same, and in the first initialization stage, the voltages of the first power supply signal and the second power supply signal are equal to the voltage of the first power supply signal when the first light emitting unit emits light in the light emitting stage.

In one embodiment, optionally, in the second initialization phase, the first power supply signal and the second power supply signal are the same, and in the second initialization phase, the voltages of the first power supply signal and the second power supply signal are equal to the voltage of the second power supply signal when the first light emitting unit emits light in the light emitting phase.

In one embodiment, optionally, during the lighting period, the first power supply signal and the second power supply signal are configured to have voltage step-up and step-down with time, and the voltage of the first power supply signal and the voltage of the second power supply signal are opposite.

The pixel circuit generates driving currents for driving the first light emitting unit and the second light emitting unit to emit light by the first driving circuit and the second driving circuit, respectively. In a light-emitting stage of one display frame of the pixel circuit, the first driving circuit and the second driving circuit alternately output driving currents in the light-emitting stage by setting voltages on the first power line and the second power line to be voltage-to-voltage transitions with time, so that the first light-emitting unit and the second light-emitting unit alternately emit light in the light-emitting stage. On the one hand, the first driving circuit and the second driving circuit work alternately in the light-emitting stage, so that the respective working time of the two driving circuits can be shortened, thereby reducing the hysteresis effect of the driving circuits and reducing the ghost; on the other hand, the two light emitting units alternately emit light, so that it is also possible to reduce the luminance decay of the light emitting units to some extent and to extend the life of the light emitting units.

Drawings

In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the following description will briefly explain the embodiments or the drawings used in the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the present description, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of a pixel circuit according to one embodiment of the present application;

FIG. 3 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present application;

FIG. 4 is a flowchart illustrating a method of driving a pixel according to one embodiment of the application;

FIG. 5 is a timing diagram of a pixel circuit according to one embodiment of the present application;

fig. 6 is a timing diagram of a pixel circuit according to another embodiment of the application.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the application. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

Where the terms "comprising," "having," and "including" are used herein, another component may also be added unless explicitly defined terms such as "only," "consisting of," etc., are used. Unless mentioned to the contrary, singular terms may include plural and are not to be construed as being one in number.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application.

In the present application, unless explicitly specified and limited otherwise, the terms "connected," "coupled," and the like are to be construed broadly, and may be, for example, directly connected or indirectly connected through intermediaries, or may be in communication with each other between two elements or in an interaction relationship between the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

Because a film transistor (TFT) prepared by an LTPS technology has a hysteresis effect in working, so that the problem of TFT ghost appears in OLED (Organic Light-Emitting Diode) display, the control and film quality optimization of film layers such as an active layer p-Si/gate insulating layer GI/capacitance medium layer CI are enhanced in the process aspect, the response speed to an external electric field is enhanced, and hysteresis and ghost are reduced; or adding BSM (Back Side Metal) to improve Back channel effect, reduce electrostatic influence, and stabilize luminescent material operation to improve residual image. In addition, in the aspect of the pixel circuit, the purpose of improving the ghost is generally achieved by reducing the voltage difference between VGMP and VGSP, that is, reducing the voltage difference between the black/white state voltages and reducing the influence of the electric stress of the gate electrode of DTFT (Driving Transistor ). However, the improvement of the TFT hysteresis effect in the aspects of the process and the circuit has the problems of complex process parameters, instability, longer period from TFT preparation to yield test evaluation, larger input cost, slow effect and the like.

Fig. 1 is a schematic diagram of a pixel circuit according to one embodiment of the present application, wherein the pixel circuit may include a first light emitting unit 10, a second light emitting unit 20, a first driving circuit 100, and a second driving circuit 200.

Alternatively, the circuit structures of the first driving circuit 100 and the second driving circuit 200 are the same or similar, alternatively, the circuit structures of the first driving circuit 100 and the second driving circuit 200 are the same, and are symmetrical about the center of symmetry.

The first driving circuit 100 may be electrically connected to the first electrode of the first light emitting unit 10, and the first driving circuit 100 is configured to generate a driving current to drive the first light emitting unit 10 to emit light. The first driving circuit 100 may be used to generate a driving current transmitted to the first electrode of the first light emitting unit 10 to drive the first light emitting unit 10 to emit light. Also, the second driving circuit 200 may be electrically connected to the first electrode of the second light emitting unit 20, and the second driving circuit 200 is configured to generate a driving current to drive the second light emitting unit 20 to emit light. The second driving circuit 200 may be used to generate a driving current transmitted to the first electrode of the second light emitting unit 20 to drive the second light emitting unit 20 to emit light. In the same pixel circuit, the light emission colors of the first light emitting unit 10 and the second light emitting unit 20 are the same.

The power input terminal of the first driving circuit 100 and the second pole of the second light emitting unit 20 may be connected to the first power line, respectively, and the power input terminal of the second driving circuit 200 and the second pole of the first light emitting unit 10 may be connected to the second power line, respectively. The first power line may be used to supply the first power supply signal V1 to the first driving circuit 100 and the second light emitting unit 20, respectively, and the second power line may be used to supply the second power supply signal V2 to the second driving circuit 200 and the first light emitting unit 10, respectively. The first power supply signal V1 may include a first operating voltage ELVDD, which may provide a positive operating voltage to the first driving circuit 100, and the first power supply signal V1 may also include a second operating voltage ELVSS, which may provide a negative operating voltage to the second pole of the second light emitting unit 20. Likewise, the second power supply signal V2 may also include a first operating voltage ELVDD, which may provide a positive operating voltage to the second driving circuit 200, and the second power supply signal V2 may also include a second operating voltage ELVSS, which may provide a negative operating voltage to the second pole of the first light emitting unit 10.

The pixel circuit may include a light emitting phase during operation of one display frame. In this embodiment, the first power supply signal V1 and the second power supply signal V2 may be configured to have a voltage that is stepped up and down with time in the light-emitting stage. That is, the first power supply signal V1 and the second power supply signal V2 are both alternating voltages or pulse voltages in the light emitting stage.

In some embodiments, the first power supply signal V1 and the second power supply signal V2 may be configured to have voltages that jump with time in a lighting stage, and the voltages of the two signals are opposite. That is, the first power supply signal V1 and the second power supply signal V2 are both alternating voltages or pulse voltages in the light emitting stage, but at the same time, the voltages of the first power supply signal V1 and the second power supply signal V2 are opposite. For example, when the first power supply signal V1 is a high voltage, the second power supply signal V2 is a low voltage.

The first power supply signal V1 and the second power supply signal V2 alternately supply power to the first driving circuit 100 and the second driving circuit 200 in the light emitting stage, and the first driving circuit 100 and the second driving circuit 200 alternately output driving currents in response to voltage changes of the first power supply signal V1 and the second power supply signal V2, so that the first light emitting unit 10 and the second light emitting unit 20 can alternately emit light in the light emitting stage. The first light emitting unit 10 and the second light emitting unit 20 do not emit light at the same time, and emit light at different times.

In some embodiments, the technical effect of the first and second power supply signals V1 and V2 forming the high voltage ELVDD/low voltage ELVSS alternating transition may be achieved by timing design of signals, and by corresponding design of signals output from the first and second power supply lines in the light emitting stage.

In some other embodiments, the power input terminal of the first driving circuit 100 and the power input terminal of the second driving circuit 200 may be connected to the power line continuously supplying the high voltage ELVDD, respectively, and the second electrode of the first light emitting unit 10 and the second electrode of the second light emitting unit 20 may be connected to the power line continuously supplying the low voltage ELVSS, respectively. The two driving circuits are connected with different light-emitting control lines, and the light-emitting control signals EM transmitted by the two light-emitting control lines are subjected to signal timing design, so that the voltages of the two light-emitting control signals EM are controlled to be alternately on voltages in the light-emitting stage, and the first light-emitting unit 10 and the second light-emitting unit 20 alternately emit light. For example, in the first half of the light emission period, the first light emitting unit 10 emits light in the first half and the second light emitting unit 20 does not emit light in the first half by setting the voltage of the light emission control signal EM in the first driving circuit 100 to an on voltage and the voltage of the light emission control signal EM in the second driving circuit 200 to an off voltage; in the latter half of the light emission period, the voltage of the light emission control signal EM in the first driving circuit 100 is set to the off voltage, and the voltage of the light emission control signal EM in the second driving circuit 200 is set to the on voltage, so that the first light emitting unit 10 does not emit light in the latter half and the second light emitting unit 20 emits light in the latter half.

Compared with the prior pixel circuit in which only one light emitting unit emits light during the operation of one display frame, the pixel circuit drives the first light emitting unit 10 and the second light emitting unit 20 by using the first driving circuit 100 and the second driving circuit 200 respectively, and simultaneously makes the first power line and the second power line provide voltage signals with opposite voltage levels for high and low jump along with time in the light emitting stage, so that bidirectional display of the two light emitting units in one display frame is formed. On the one hand, the first driving circuit 100 and the second driving circuit 200 work alternately in the light-emitting stage, so that the respective working time of the two driving circuits can be shortened, thereby reducing the hysteresis effect of the driving circuits and reducing the ghost; on the other hand, the two light emitting units alternately emit light, so that it is also possible to reduce the luminance decay of the light emitting units to some extent and to extend the life of the light emitting units.

In one embodiment, the circuit structures of the first driving circuit 100 and the second driving circuit 200 are the same or similar, and the first driving circuit 100 and the second driving circuit 200 may each include a data writing unit 110, a storage unit 120, and a driving unit 130.

In the same driving circuit (e.g., the first driving circuit 100 or the second driving circuit 200), the Data writing unit 110 may be connected to the control terminal of the driving unit 130, and the Data writing unit 110 may be configured to write the Data signal Data to the control terminal of the driving unit 130 according to the first Scan signal Scan 1. The Data writing unit 110 may also be connected to the first Scan line and the Data line, respectively, where the Data writing unit 110 may obtain the first Scan signal Scan1 through the first Scan line and obtain the Data signal Data through the Data line, so that the Data signal Data may be transmitted to the control end of the driving unit 130 according to the first Scan signal S1.

In one embodiment, alternatively, in the same pixel circuit, the first scan signals controlling the data writing units 110 in the two driving circuits may be the same signal, that is, the control terminal of the data writing unit 110 in the first driving circuit 100 and the control terminal of the data writing unit in the second driving circuit 200 are connected to the same first scan line.

In one embodiment, the data writing unit 110 in the first driving circuit 100 and the data writing unit in the second driving circuit 200 are optionally connected to the same data line. In the same pixel circuit, the data lines write the same data voltages to the first and second driving circuits 100 and 200.

A first terminal of the memory cell 120 in the first driving circuit 100 may be connected to a first power line, and a second terminal of the memory cell 120 in the first driving circuit 100 may be connected to a control terminal of the driving unit 130 in the first driving circuit 100. A first terminal of the memory cell 120 in the second driving circuit 200 may be connected to the second power line, and a second terminal of the memory cell 120 in the second driving circuit 200 may be connected to a control terminal of the driving unit 130 in the second driving circuit 200. In the same driving circuit, the memory cell 120 may be used to store the voltage at the control terminal of the driving cell 130.

The driving unit 130 in the first driving circuit 100 may be connected between the power input terminal of the first driving circuit 100 and the first pole of the first light emitting unit 10, the driving unit 130 in the second driving circuit 200 may be connected between the power input terminal of the second driving circuit 200 and the first pole of the second light emitting unit 20, and the driving unit 130 may be configured to generate a driving current according to a voltage at the control terminal of the driving unit 130. The driving current generated by the driving unit 130 in the first driving circuit 100 is transmitted to the first pole of the first light emitting unit 10, so that the first light emitting unit 10 can be driven to emit light, and the driving current generated by the driving unit 130 in the second driving circuit 200 is transmitted to the first pole of the second light emitting unit 20, so that the second light emitting unit 20 can be driven to emit light.

In the pixel circuit provided in the embodiment of the present disclosure, the first driving circuit 100 and the second driving circuit 200 may write the Data signal Data to the control terminal of the driving unit 130 by using the Data writing unit 110 in response to the first scan signal, and the storage unit 120 stores the voltage at the control terminal of the driving unit 130. The driving unit 130 generates a driving current according to a voltage at a control terminal of the driving unit 130 to drive the light emitting unit 10 to emit light using the driving current.

Fig. 2 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application, and the first driving circuit 100 and the second driving circuit 200 in the pixel circuit shown in fig. 2 are driving circuits with a 6T1C structure. In one embodiment, the first driving circuit 100 and the second driving circuit 200 may be any driving circuit capable of outputting a driving current to drive the light emitting unit (e.g., OLED) to emit light, for example, a 7T1C or 4T2C structure, etc.

Referring to fig. 2, in one embodiment, the driving unit 130 may include a first transistor T1, the storage unit 120 may include a storage capacitor C1, and the data writing unit 110 may include a second transistor T2. In fig. 2, the circuit device of the second driving circuit 200 is denoted by ' for distinguishing, for example, the first transistor in the second driving circuit 200 is denoted by T1', the second transistor is denoted by T2', etc. Since the circuit structures of the first driving circuit 100 and the second driving circuit 200 are the same or similar, the working principle of the first driving circuit 100 is mainly described in this embodiment, and the working principle of the second driving circuit 200 may refer to the working principle of the first driving circuit 100, and the repetition is omitted.

In the embodiments of the present disclosure, a transistor refers to an element including at least a gate, a drain, and a source. In this disclosure, the first pole of the transistor may be the drain, the second pole may be the source, or the first pole may be the source, the second pole may be the drain. In the case of using a transistor having opposite polarity, or in the case of a change in current direction during circuit operation, the functions of the "source" and the "drain" may be exchanged with each other. In embodiments of the present disclosure, all or a portion of the first and second poles of the transistors are interchangeable as desired.

The first pole of the first transistor T1 may be used as the first terminal of the driving unit 130, the gate of the first transistor T1 may be used as the control terminal of the driving unit 130, and the second pole of the first transistor T1 may be used as the second terminal of the driving unit 130.

A first pole of the second transistor T2 may be connected to a control terminal of the driving unit 130, for example, to a gate of the first transistor T1, a gate of the second transistor T2 may be connected to the first scan line, and a second pole of the second transistor T2 may be connected to the data line. The second transistor T2 may enter an on or off state according to the first Scan signal Scan1 transmitted by the first Scan line. When the second transistor T2 enters the on state, the Data signal Data transmitted by the Data line may be obtained through the second pole of the second transistor T2, and the Data signal Data may be written into the control terminal of the driving unit 130.

In this embodiment, the control terminal of the data writing unit 110 in the first driving circuit 100 and the control terminal of the data writing unit in the second driving circuit 200 are connected to the same first scan line, which may mean that the first scan line connected to the gate of the second transistor T2 and the first scan line connected to the gate of the second transistor T2' are the same scan line.

In this embodiment, the data writing unit 110 in the first driving circuit 100 and the data writing unit in the second driving circuit 200 are connected to the same data line, which may mean that the data line connected to the second pole of the second transistor T2 and the data line connected to the second pole of the second transistor T2' may be the same data line.

The first end of the storage capacitor C1 in the first driving circuit 100 may be connected to a first power line, the first power line may provide the first power signal V1, and the first end of the storage capacitor C1' in the second driving circuit 200 may be connected to a second power line, and the second power line may provide the second power signal V2. In the same driving circuit, the second terminal of the storage capacitor C1 may be connected to the gate of the first transistor T1. The storage capacitor C1 may be used to store the voltage at the gate of the first transistor T1, i.e., the voltage stored by the storage capacitor C1 is a data signal.

In one embodiment, the first Light Emitting unit 10 and the second Light Emitting unit 20 may be Organic Light Emitting Diodes (OLED), and in practical applications, other devices capable of realizing electroluminescence may be used as the Light Emitting units according to different design requirements. The first light emitting unit 10 may include a light emitting diode D1, and the second light emitting unit 20 may include a light emitting diode D2. In the present embodiment, the first pole of the first light emitting unit 10 and the first pole of the second light emitting unit 20 may be anodes, and the second pole of the first light emitting unit 10 and the second pole of the second light emitting unit 20 may be cathodes. When the driving current generated by the first transistor T1 in the first driving circuit 100 is transmitted to the first pole of the light emitting diode D1, the light emitting diode D1 may emit light with a brightness corresponding to the driving current; when the driving current generated by the first transistor T1' in the second driving circuit 200 is transmitted to the first pole of the light emitting diode D2, the light emitting diode D2 may emit light with a brightness corresponding to the driving current.

Fig. 3 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present application, and the first driving circuit 100 and the second driving circuit 200 in the pixel circuit shown in fig. 3 are driving circuits with a 7T1C structure. In one embodiment, the first driving circuit 100 and the second driving circuit 200 may further include a compensation unit 180.

The Data writing unit 110 may be connected to a first terminal of the driving unit 130, and the Data writing unit 110 may be configured to write the Data signal Data to the first terminal of the driving unit 130 according to the first Scan signal Scan 1. The Data writing unit 110 may also be connected to the first Scan line and the Data line, respectively, and the Data writing unit 110 may acquire the first Scan signal Scan1 through the first Scan line and the Data signal Data through the Data line, so that the Data signal Data may be transmitted to the first end of the driving unit 130 according to the first Scan signal S1.

In one embodiment, the control terminal of the data writing unit in the first driving circuit 100 and the control terminal of the data writing unit in the second driving circuit 200 may be connected to the same first scan line in the same pixel circuit. Alternatively, the data writing unit in the first driving circuit 100 and the data writing unit in the second driving circuit 200 may be connected to the same data line.

A first terminal of the memory cell 120 in the first driving circuit 100 may be connected to a first power line, and a second terminal of the memory cell 120 in the first driving circuit 100 may be connected to a control terminal of the driving unit 130 in the first driving circuit 100. The first terminal of the memory cell 120 in the second driving circuit 200 may be connected to the second power line, and the second terminal of the memory cell 120 in the second driving circuit 200 may be connected to the control terminal 110 of the driving unit 130 in the second driving circuit 200. In the same driving circuit, the memory cell 120 may be used to store the voltage at the control terminal of the driving cell 130.

In the same driving circuit, the compensation unit 180 may be connected between the control terminal of the driving unit 130 and the second terminal of the driving unit 130, and the compensation unit 180 may be configured to perform threshold compensation on the driving unit 130 according to the first Scan signal Scan 1. The compensation unit 180 may also be connected to the first Scan line, and the first Scan signal Scan1 is acquired through the first Scan line, so that the compensation unit 180 may perform threshold compensation on the driving unit 130 according to the first Scan signal Scan 1.

In one embodiment, alternatively, the compensation unit 180 in the first driving circuit 100 and the compensation unit in the second driving circuit 100 may be connected to the same first scan line in the same pixel circuit.

As shown in fig. 3, in one embodiment, a first pole of the first transistor T1 may be used as a first terminal of the driving unit 130, a gate of the first transistor T1 may be used as a control terminal of the driving unit 130, and a second pole of the first transistor T1 may be used as a second terminal of the driving unit 130.

A first pole of the second transistor T2 may be connected to a first pole of the first transistor T1, a gate of the second transistor T2 may be connected to the first scan line, and a second pole of the second transistor T2 may be connected to the data line. The second transistor T2 may enter an on or off state according to the first Scan signal Scan1 transmitted by the first Scan line. When the second transistor T2 enters the on state, the Data signal Data transmitted by the Data line may be obtained through the second pole of the second transistor T2 and written into the first terminal of the driving unit 130.

The first end of the storage capacitor C1 in the first driving circuit 100 may be connected to a first power line, the first power line may continuously provide the first power signal V1, the first end of the storage capacitor C1' in the second driving circuit 200 may be connected to a second power line, and the second power line may continuously provide the second power signal V2. In the same driving circuit, the second terminal of the storage capacitor C1 may be connected to the gate of the first transistor T1. The storage capacitor C1 may be used to store the voltage at the gate of the first transistor T1, that is, the voltage stored in the storage capacitor C1 is the data signal after the threshold compensation.

The compensation unit 180 may include a seventh transistor T7, a first pole of the seventh transistor T7 may be connected to the control terminal of the driving unit 130, a second pole of the seventh transistor T7 may be connected to the second terminal of the driving unit 130, and a gate of the seventh transistor T7 may be connected to the first Scan line (available for transmitting the first Scan signal Scan 1). The seventh transistor T7 may acquire the first Scan signal Scan1 transmitted by the first Scan line through the gate electrode, and the first Scan signal Scan1 may be used to control the seventh transistor T7 to enter an on or off state. The seventh transistor T7 may perform threshold compensation for the driving unit 130 when entering the conductive state according to the first Scan signal Scan 1.

In this embodiment, alternatively, in the same pixel circuit, the control terminal of the compensation unit 180 in the first driving circuit 100 and the control terminal of the compensation unit 180 in the second driving circuit 200 are connected to the same first scan line, which may mean that the first scan line connected to the gate of the seventh transistor T7 and the first scan line connected to the gate of the seventh transistor T7' are the same scan line.

Referring to fig. 2 and 3, in one embodiment, the first driving circuit 100 and the second driving circuit 200 may further include a first initializing unit 140 and/or a second initializing unit 150.

The first initializing unit 140 in the first driving circuit 100 may be connected to the first pole of the first light emitting unit 10, the first initializing unit 140 in the second driving circuit 200 may be connected to the first pole of the second light emitting unit 20, and the first initializing units 140 in the two driving circuits may be further connected to the second Scan line through which the second Scan signal Scan2 is acquired. The first initializing unit 140 may be configured to transmit an initializing signal Vref to the anode of the light emitting diode D1 or the anode of the light emitting diode D2 according to the second Scan signal Scan2 to initialize the anode of the light emitting diode D1 or the anode of the light emitting diode D2.

In one embodiment, alternatively, in the same pixel circuit, the control terminal of the first initializing unit 140 in the first driving circuit 100 and the control terminal of the first initializing unit 140 in the second driving circuit 200 may be connected to the same second scan line.

In the same driving circuit, the second initializing unit 150 may be connected to the control end of the driving unit 130 and the storage unit 120, and the second initializing unit 150 in the two driving circuits may also be connected to a third Scan line, through which the third Scan signal Scan3 is obtained. The second initializing unit 150 may be configured to transmit an initializing signal Vref to a control terminal of the driving unit 130 according to the third Scan signal Scan3 to initialize the memory unit 120.

In one embodiment, alternatively, in the same pixel circuit, the control terminal of the second initializing unit 150 in the first driving circuit 100 and the control terminal of the second initializing unit 150 in the second driving circuit 200 may be connected to the same third scan line.

In one embodiment, the first initializing unit 140 may include a third transistor T3. A first pole of the third transistor T3 in the first driving circuit 100 may be connected to the anode of the light emitting diode D1, a first pole of the third transistor T3' in the second driving circuit 200 may be connected to the anode of the light emitting diode D2, a gate of the third transistor T3 in the two driving circuits may be connected to the second Scan line (which may be used to transmit the second Scan signal Scan 2), and a second pole of the third transistor T3 in the two driving circuits may be connected to the initialization signal line (which may be used to transmit the initialization signal Vref). The third transistor T3 may receive the second Scan signal Scan2 transmitted by the second Scan line through the gate electrode, and the second Scan signal Scan2 may be used to control the third transistor T3 to be turned on or off, so that the third transistor T3 or the third transistor T3' may transmit the initialization signal Vref to the anode of the light emitting diode D1 or the anode of the light emitting diode D2 to reset the anode of the light emitting diode D1 or the anode of the light emitting diode D2 when being turned on according to the second Scan signal Scan 2.

In this embodiment, in the same pixel circuit, the control terminal of the first initializing unit 140 in the first driving circuit 100 and the control terminal of the first initializing unit 140 in the second driving circuit 200 are connected to the same second scan line, which may mean that the second scan line connected to the gate of the third transistor T3 and the second scan line connected to the gate of the third transistor T3' are the same scan line.

In one embodiment, the second initializing unit 150 may include a fourth transistor T4. In the same driving circuit, a first pole of the fourth transistor T4 may be connected to the control terminal of the driving unit 130 and the storage unit 120, respectively, a gate of the fourth transistor T4 is connected to a third Scan line (which may be used to transmit the third Scan signal Scan 3), and a second pole of the fourth transistor T4 is connected to an initialization signal line. The fourth transistor T4 may receive the third Scan signal Scan3 transmitted by the third Scan line through the gate electrode, and the third Scan signal Scan3 may be used to control the fourth transistor T4 to be turned on or off. In the same driving circuit, the fourth transistor T4 may transmit the initialization signal Vref to the control terminal of the driving unit 130 when turned on according to the third Scan signal Scan3 to initialize the control terminal of the driving unit 130 and the memory unit 120.

In this embodiment, in the same pixel circuit, the control terminal of the second initializing unit 150 in the first driving circuit 100 and the control terminal of the second initializing unit 150 in the second driving circuit 200 are connected to the same third scan line, which may mean that the third scan line connected to the gate of the fourth transistor T4 and the third scan line connected to the gate of the fourth transistor T4' are the same scan line.

Referring to fig. 2 and 3, in one embodiment, the first driving circuit 100 and the second driving circuit 200 may further include a first light emission control unit 160 and/or a second light emission control unit 170.

The first light emitting control unit 160 in the first driving circuit 100 may be connected between the third terminal of the driving unit 130 and the first pole of the first light emitting unit 10, and the first light emitting control unit 160 in the second driving circuit 200 may be connected between the third terminal of the driving unit 130 and the first pole of the first light emitting unit 20. The first light emission control unit 160 of the two driving circuits may also be connected to a control signal line (which may be used to transmit the light emission control signal EM).

In one embodiment, the control terminal of the first light emitting control unit 160 in the first driving circuit 100 and the control terminal of the first light emitting control unit 160 in the second driving circuit 200 may be connected to the same control signal line in the same pixel circuit.

In the first driving circuit 100, the first light emitting control unit 160 may be configured to turn on or off a connection between the second end of the driving unit 130 and the first pole of the first light emitting unit 10 according to the light emitting control signal EM. In the second driving circuit 200, the first light emitting control unit 160 may be configured to turn on or off a connection between the second terminal of the driving unit 130 and the first pole of the second light emitting unit 20 according to the light emitting control signal EM.

The second light emission control unit 170 in the first driving circuit 100 may be connected between the first power line and the first end of the driving unit 130, the second light emission control unit 170 in the second driving circuit 200 may be connected between the second power line and the first end of the driving unit 130, and the second light emission control units 170 in the two driving circuits may be further connected with a control signal line (available for transmitting the light emission control signal EM).

In one embodiment, in the same pixel circuit, the control terminal of the second light emission control unit 170 in the first driving circuit 100 and the control terminal of the second light emission control unit 170 in the second driving circuit 200 may be connected to the same control signal line.

The second light emission control unit 170 in the first driving circuit 100 may be configured to turn on or off a connection between the first power line and the first end of the driving unit 130 according to the light emission control signal EM, and the second light emission control unit 170 in the second driving circuit 200 may be configured to turn on or off a connection between the second power line and the first end of the driving unit 130 according to the light emission control signal EM.

In one embodiment, the first light emitting control unit 160 may include a fifth transistor T5. A first pole of the fifth transistor T5 in the same driving circuit may be connected to the second terminal of the driving unit 130, a gate of the fifth transistor T5 may be connected to a control signal line (may be used to transmit the light emission control signal EM), a second pole of the fifth transistor T5 in the first driving circuit 100 may be connected to a first pole (e.g., anode) of the light emitting diode D1, and a second pole of the fifth transistor T5' in the second driving circuit 200 may be connected to a first pole (e.g., anode) of the light emitting diode D2. The fifth transistor T5 may receive the light emission control signal EM transmitted through the control signal line through the gate electrode, and the light emission control signal EM may be used to control the fifth transistor T5 to be turned on or off, so that the first light emission control unit 160 may turn on or off the connection between the second terminal of the driving unit 130 and the first electrode of the light emitting diode according to the light emission control signal EM.

In this embodiment, in the same pixel circuit, the control terminal of the first light emitting control unit 160 in the first driving circuit 100 and the control terminal of the first light emitting control unit 160 in the second driving circuit 200 may be connected to the same control signal line, which may mean that the control signal line connected to the gate of the fifth transistor T5 and the control signal line connected to the gate of the fifth transistor T5' are the same signal line.

In one embodiment, the second light emitting control unit 170 may include a sixth transistor T6, a first pole of the sixth transistor T6 in the same driving circuit may be connected to the first terminal of the driving unit 130, a gate of the sixth transistor T6 may be connected to the control signal line, a second pole of the sixth transistor T6 in the first driving circuit 100 may be connected to the first power line, and a second pole of the sixth transistor T6' in the second driving circuit 200 may be connected to the second power line. The sixth transistor T6 may receive the light emission control signal EM transmitted by the control signal line through the gate electrode, and the light emission control signal EM may also be used to control the on or off of the sixth transistor T6, so that the second light emission control unit 170 may turn on or off a connection between a power line (e.g., a first power line or a second power line) and the first terminal of the driving unit 130 according to the light emission control signal EM.

In the present embodiment, in the same pixel circuit, the control terminal of the second light emission control unit 170 in the first driving circuit 100 and the control terminal of the second light emission control unit 170 in the second driving circuit 200 may be connected to the same control signal line, which may mean that the control signal line connected to the gate of the sixth transistor T6 and the control signal line connected to the gate of the sixth transistor T6' are the same signal line.

In one embodiment, the P-type TFT has a distinct advantage over the N-type TFT in the display technology field, with a better STS (Subthrehold Swing, subthreshold swing) so that low gray levels can be better spread out to achieve higher quality display applications. Therefore, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be P-type transistors, for example, polysilicon thin film transistors. In some other embodiments, the device types of the units in the pixel circuit may also be selected from other suitable functional elements according to practical application requirements. The first, second, third, fourth, fifth, sixth and seventh transistors T1, T2, T3, T4, T5, T6 and T7 may be P-type or N-type transistors.

The embodiment of the invention also provides a display device, which may include the pixel circuit described in any one of the above embodiments.

In one embodiment, the display device may include a plurality of pixel circuits, and the plurality of pixel circuits are arranged in an array in the display device. The display device can be any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In one embodiment, alternatively, the first driving circuits 100 and 200 and the second driving circuit are arranged in the row direction in the same pixel circuit. The first driving circuit 100 and the second driving circuit 200 may be connected to the same data line, and the data line may extend in the column direction. Wherein the row and column directions may intersect, e.g. be perpendicular.

Based on the description of the embodiments of the pixel circuit described above, the present disclosure may also provide a driving method of the pixel circuit. The pixel circuit may include a device (including a distributed system), software (application), a module, a component, a server, a client, or the like using the driving method described in the embodiments of the present specification, in combination with a device implementing hardware as necessary. Based on the same innovative concept, embodiments of the present disclosure provide one or more embodiments of driving methods as described in the following embodiments. Since the implementation of the driving method for solving the problem is similar to that of the pixel circuit, the implementation of the driving method in the embodiment of the present disclosure may refer to the implementation of the pixel circuit, and the repetition is omitted. As used below, the term "unit" or "module" may be a combination of software and/or hardware that implements the intended function. Although the methods described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present application may also provide a method for driving a pixel circuit, and fig. 4 is a schematic flow chart of a method for driving a pixel in one embodiment of the present application, where the method for driving a pixel circuit may include the following step S100.

Step S100: in the light-emitting stage, the first power supply signal and the second power supply signal received by the pixel circuit are configured to be in voltage high-low jump along with time, so that the first light-emitting unit and the second light-emitting unit alternately emit light.

The pixel circuit provided in the above embodiment may include a lighting stage during the operation of one display frame, where the voltage of the first power supply signal V1 and the voltage of the second power supply signal V2 are configured to be changed in a high-low jump manner along with time, and the voltages of the first power supply signal V1 and the second power supply signal V2 are opposite. That is, the first power supply signal V1 and the second power supply signal V2 are both in an alternating voltage or a pulse voltage.

In some embodiments, the first power supply signal V1 and the second power supply signal V2 may be configured to have voltages that jump with time in a lighting stage, and the voltages of the two signals are opposite. That is, the first power supply signal V1 and the second power supply signal V2 are both alternating voltages or pulse voltages in the light emitting stage. At the same time, the voltage levels of the first power supply signal V1 and the second power supply signal V2 may be opposite. For example, when the first power supply signal V1 is a high voltage, the second power supply signal V2 is a low voltage. When the first power supply signal V1 is at a low voltage, the second power supply signal V2 is at a high voltage.

In the driving method of the pixel circuit, the first driving circuit 100 and the second driving circuit 200 respectively drive the first light emitting unit 10 and the second light emitting unit 20, and the voltage signals with opposite voltage levels are formed by making the first power line and the second power line provide the voltage signals with the voltage levels being different with time in the light emitting stage, so that the two light emitting units can display in two directions in one display frame. On the one hand, the first driving circuit 100 and the second driving circuit 200 work alternately in the light-emitting stage, so that the respective working time of the two driving circuits can be shortened, thereby reducing the hysteresis effect of the driving circuits and reducing the ghost; on the other hand, the two light emitting units alternately emit light, so that it is also possible to reduce the luminance decay of the light emitting units to some extent and to extend the life of the light emitting units.

Fig. 5 is a timing diagram of a pixel circuit according to one embodiment of the present application, in fig. 5, scan1 represents a first Scan signal, scan2 represents a second Scan signal, scan3 represents a third Scan signal, EM represents a light emission control signal, V1 represents a first power supply signal, and V2 represents a second power supply signal. In this embodiment, the pixel circuit shown in fig. 2 or fig. 3 is taken as an example, and the operation process of the pixel circuit in one display frame is described in detail with reference to the timing diagram shown in fig. 5. In the pixel circuits shown in fig. 2 or 3, all transistors are P-type transistors, so that the on-voltage of the transistors in the drawings is low, and the off-voltage is high.

In one embodiment, the pixel circuit may include a first initialization phase, a data writing phase, a second initialization phase and a light emitting phase during operation of one display frame,

in the first initialization stage S1, the third Scan signal Scan3 may be configured to be an on voltage, and the first Scan signal Scan1, the second Scan signal Scan2, and the emission control signal EM may be configured to be an off voltage. That is, the fourth transistor T4 and the fourth transistor T4' are controlled to be turned on and the remaining transistors to be turned off in the first initialization stage S1.

Therefore, in the first initialization stage S1, the first driving circuit 100 may transmit the initialization signal Vref to the gate of the first transistor T1 through the fourth transistor T4, and the second driving circuit 200 may transmit the initialization signal Vref to the gate of the first transistor T1 'through the fourth transistor T4'. Since the gate of the first transistor T1 is connected to the storage capacitor C1 and the gate of the first transistor T1' is connected to the storage capacitor C1', the storage capacitor C1 or the storage capacitor C1' may be initialized by the initialization signal Vref. In addition, the initialization signal Vref may also give a negative initial voltage to the gate of the first transistor T1 and the gate of the first transistor T1 'to realize the initialization of the first transistor T1 and the first transistor T1'.

In one embodiment, optionally, in the first initialization stage S1, the first power supply signal V1 and the second power supply signal V2 may be configured as the same signal. Specifically, in the first initialization stage S1, the voltage of the first power supply signal V1 and the voltage of the second power supply signal V2 may be equal to the voltage provided by the first power supply signal V1 when the first light emitting unit 10 emits light in the light emitting stage S4. In the light emitting stage S4, in order to satisfy the relationship between the gate-source voltage difference of the gate electrode and the first electrode of the first transistor T1 and the threshold voltage, and thus to be able to output the driving current to drive the first light emitting unit 10 to emit light, the first power supply signal V1 may be configured to be a high level ELVDD and the second power supply signal V2 may be configured to be a low level ELVSS. In the first initialization stage S1, the voltage of the first power supply signal V1 and the voltage of the second power supply signal V2 may both be the high level ELVDD.

In the data writing stage S2, the first Scan signal Scan1 may be configured to be an on voltage, and the second Scan signal Scan2, the third Scan signal Scan3, and the emission control signal EM may be configured to be an off voltage. At this time, the second transistor T2, the seventh transistor T7, the second transistor T2', the seventh transistor T7' are turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the third transistor T3', the fourth transistor T4', the fifth transistor T5', and the sixth transistor T6' are turned off. .

In one of the embodiments, optionally, in the data writing stage S2, the first power supply signal V1 and the second power supply signal V2 may also be configured as the same signal. Specifically, in the data writing stage S2, the voltage of the first power supply signal V1 and the voltage of the second power supply signal V2 may be equal to the voltage supplied by the first power supply signal V1 when the first light emitting unit 10 emits light in the light emitting stage S4. In the light emitting stage S4, in order to satisfy the relationship between the gate-source voltage difference of the gate electrode and the first electrode of the first transistor T1 and the threshold voltage, and thus to be able to output the driving current to drive the first light emitting unit 10 to emit light, the first power supply signal V1 may be configured to be a high level ELVDD and the second power supply signal V2 may be configured to be a low level ELVSS. In the data writing stage S2, the voltage of the first power supply signal V1 and the voltage of the second power supply signal V2 may both be the high level ELVDD.

In the Data writing stage S2, the second transistor T2 may transmit the threshold-compensated Data signal data+vth to the gate of the first transistor T1, where Vth is the threshold voltage of the first transistor T1. Since the first end of the storage capacitor C1 is connected to the first power line, and the second end of the storage capacitor C1 is connected to the gate of the first transistor T1, the potential at the first end of the storage capacitor C1 in the first driving circuit 100 is ELVDD, and the potential at the second end is data+vth, so that the threshold voltage of the first transistor T1 is compensated, and the voltage stored in the storage capacitor C1 is the difference between ELVDD and data+vth. Similarly, the voltage stored in the storage capacitor C1' in the second driving circuit 200 is also the voltage difference between ELVDD and data+vth. Thus, in the light emitting stage S4, when the first transistor T1 or the first transistor T1 'is turned on, the gate-source voltage Vgs of the first transistor T1 or the first transistor T1' is data+vth.

In the second initialization stage S3, the second Scan signal Scan2 may be configured to be an on voltage (e.g., a low voltage), and the first Scan signal Scan1, the third Scan signal Scan3, and the emission control signal EM may be configured to be an off voltage (e.g., a high voltage), i.e., the third transistor T3 and the third transistor T3' are controlled to be turned on in the second initialization stage S3, and the remaining transistors are turned off.

Therefore, in the second initialization stage S3, the first driving circuit 100 may transmit the initialization signal Vref to the first pole of the light emitting diode D1 through the third transistor T3, and the second driving circuit 200 may transmit the initialization signal Vref to the first pole of the light emitting diode D2 through the third transistor T3'. The first electrode of the light emitting diode D1 and the first electrode of the light emitting diode D2 are initialized by the initialization signal Vref to have a negative voltage, so that the electric signal remaining in the light emitting stage of the previous display frame can be prevented from affecting the light emission.

In one embodiment, optionally, in the second initialization stage S3, the first power supply signal V1 and the second power supply signal V2 may be configured as the same signal. Specifically, in the second initialization stage S3, the voltage of the first power supply signal V1 and the voltage of the second power supply signal V2 may be equal to the voltage provided by the second power supply signal V2 when the first light emitting unit 10 emits light in the light emitting stage S4. In the light emitting stage S4, in order to satisfy the relationship between the gate-source voltage difference of the gate electrode and the first electrode of the first transistor T1 and the threshold voltage, and thus to be able to output the driving current to drive the first light emitting unit 10 to emit light, the first power supply signal V1 may be configured to be a high level ELVDD and the second power supply signal V2 may be configured to be a low level ELVSS. In the second initialization stage S3, the voltage of the first power supply signal V1 and the voltage of the second power supply signal V2 may both be the low level ELVSS.

In the light emitting stage S4, the light emission control signal EM may be configured to an on voltage, and the first Scan signal Scan1, the second Scan signal Scan2, and the third Scan signal Scan3 may be configured to an off voltage. That is, in the light emitting stage S4, the fifth transistor T5, the sixth transistor T6, the fifth transistor T5', the sixth transistor T6' are turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the second transistor T2', the third transistor T3', the fourth transistor T4', and the seventh transistor T7' are turned off.

When the fifth transistor T5, the sixth transistor T6, the fifth transistor T5', and the sixth transistor T6' are turned on according to the emission control signal EM, the first power line in the first driving circuit 100 is turned on with the first pole of the first transistor T1, and the connection between the second pole of the first transistor T1 and the first pole of the light emitting diode D1 is turned on; the connection between the second power line and the first pole of the first transistor T1 'and the connection between the second pole of the first transistor T1' and the first pole of the light emitting diode D2 in the second driving circuit 200 are all turned on.

The first power supply signal V1 provided by the first power supply line is transmitted to the first pole of the first transistor T1 through the sixth transistor T6, if the relationship between the first power supply signal V1 and the second power supply signal V2 is consistent with the relationship between the anode and the cathode of the light emitting diode D1, the relationship between the gate-source voltage difference of the gate and the first pole of the first transistor T1 and the threshold voltage satisfies the conduction condition, the driving current generated by the first transistor T1 may be transmitted to the first pole of the light emitting diode D1 through the fifth transistor T5, and if the relationship between the high-low relationship between the first power supply signal V1 and the second power supply signal V2 is inconsistent with the relationship between the anode and the cathode of the light emitting diode D1, the relationship between the gate-source voltage difference of the gate and the first pole of the first transistor T1 and the threshold voltage does not satisfy the conduction condition, and the driving current cannot be generated by the first transistor T1.

Similarly, the second power supply signal V2 provided by the second power supply line is transmitted to the first pole of the first transistor T1' through the sixth transistor T6', if the relationship between the first power supply signal V1 and the second power supply signal V2 is consistent with the relationship between the anode and the cathode of the light emitting diode D2, the relationship between the gate-source voltage difference of the gate and the first pole of the first transistor T1' and the threshold voltage satisfies the on condition, the driving current generated by the first transistor T1' may be transmitted to the first pole of the light emitting diode D2 through the fifth transistor T5', and if the relationship between the height of the first power supply signal V1 and the second power supply signal V2 is inconsistent with the relationship between the anode and the cathode of the light emitting diode D2, the relationship between the gate-source voltage difference of the gate and the first pole of the first transistor T1' and the threshold voltage does not satisfy the on condition, and the driving current cannot be generated by the first transistor T1 '.

As shown in fig. 5, the first power supply signal V1 and the second power supply signal V2 are both alternating voltages in the lighting stage S4, the voltages of the first power supply signal V1 and the second power supply signal V2 jump at the lighting stage S4, and the voltages of the two power supply signals are opposite. For example, when the voltage of the first power supply signal V1 is the high voltage ELVDD, the voltage of the second power supply signal V1 is the low voltage ELVSS, and when the voltage of the first power supply signal V1 is the low voltage ELVSS, the voltage of the second power supply signal V1 is the high voltage ELVDD. Accordingly, the first and second power supply signals V1 and V2 may alternately emit light of the light emitting diodes D1 and D2.

In the first half light-emitting period a, the first power supply signal V1 is a high voltage ELVDD and the second power supply signal V2 is a low voltage ELVSS as shown in fig. 5 in the light-emitting period S4. The high voltage ELVDD supplied from the first power line is transferred to the first pole of the first transistor T1 through the sixth transistor T6, the high voltage ELVDD supplied from the first power line is also transferred to the second pole of the light emitting diode D2, the low voltage ELVSS supplied from the second power line is transferred to the first pole of the first transistor T1 'through the sixth transistor T6', and the low voltage ELVSS supplied from the second power line is also transferred to the second pole of the light emitting diode D1.

At this time, in the first driving circuit 100, the relationship between the first power supply signal V1 and the second power supply signal V2 is consistent with the corresponding relationship between the anode and the cathode of the light emitting diode D1, and the relationship between the gate-source voltage difference of the gate and the first pole of the first transistor T1 and the threshold voltage satisfies the on condition, so the driving current generated by the first transistor T1 can be transmitted to the first pole of the light emitting diode D1 through the fifth transistor T5 to drive the light emitting diode D1 to emit light. In the second driving circuit 200, the relationship between the first power supply signal V1 and the second power supply signal V2 is not consistent with the correspondence between the anode and the cathode of the light emitting diode D2, and the relationship between the gate-source voltage difference of the gate and the first pole of the first transistor T1' and the threshold voltage does not satisfy the on condition, so that the light emitting diode D2 does not emit light.

In the second half period of the light emitting period b, the first power supply signal V1 is a low voltage ELVSS and the second power supply signal V2 is a high voltage ELVDD. The low voltage ELVSS supplied from the first power line is transferred to the first pole of the first transistor T1 through the sixth transistor T6, the low voltage ELVSS supplied from the first power line is transferred to the second pole of the light emitting diode D2, the high voltage ELVDD supplied from the second power line is transferred to the first pole of the first transistor T1 'through the sixth transistor T6', and the high voltage ELVDD supplied from the second power line is also transferred to the second pole of the light emitting diode D1.

At this time, in the second driving circuit 200, the relationship between the first power supply signal V1 and the second power supply signal V2 is consistent with the corresponding relationship between the anode and the cathode of the light emitting diode D2, and the relationship between the gate-source voltage difference of the gate and the first pole of the first transistor T1' and the threshold voltage satisfies the on condition, so the driving current generated by the first transistor T1' can be transmitted to the first pole of the light emitting diode D2 through the fifth transistor T5' to drive the light emitting diode D2 to emit light. In the first driving circuit 100, the relationship between the first power supply signal V1 and the second power supply signal V2 is not consistent with the correspondence between the anode and the cathode of the light emitting diode D1, and the relationship between the gate-source voltage difference of the gate electrode and the first electrode of the first transistor T1 and the threshold voltage does not satisfy the on condition, so that the light emitting diode D1 does not emit light.

In the pixel circuit, the first driving circuit 100 and the second driving circuit 200 are utilized to drive the light emitting diode D1 and the light emitting diode D2, and the first power supply signal V1 and the second power supply signal V2 are configured to have voltage transitions with time in the light emitting stage S4, and the voltage of the two power supply signals is opposite, so that the light emitting diode D1 and the light emitting diode D2 can alternately emit light in the light emitting stage S4 according to the voltage changes of the first power supply signal V1 and the second power supply signal V2. On one hand, the working time of the driving transistors in the first driving circuit 100 and the second driving circuit 200 can be shortened, and the electric stress of the driving transistors is effectively reduced, so that the hysteresis effect is reduced, and the TFT ghost is reduced; on the other hand, the double OLED alternate light emission can also reduce the brightness attenuation of the OLED device to a certain extent and prolong the service life of the OLED device.

Fig. 6 is a timing diagram of a pixel circuit according to another embodiment of the application, where the first power supply signal V1 and the second power supply signal V2 may also be alternating voltage signals as shown in fig. 6, and the light-emitting phase correspondingly includes two alternating periods, so that the light-emitting diode D1 and the light-emitting diode D2 alternately emit light twice. In some other embodiments, the alternating periods in the light-emitting phases can be set arbitrarily according to the display requirements, and a plurality of alternating periods are correspondingly included in one light-emitting phase, so that two OLEDs uniformly and alternately emit light in the light-emitting phase; the emission times of the two OLEDs may also be uneven to accommodate differences in the performance of the OLED devices.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for a hardware+program class embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, and reference is made to the description of a method embodiment for relevant points.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit of the invention, which are within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims

1. A pixel circuit is characterized by comprising a first light emitting unit, a second light emitting unit, a first driving circuit and a second driving circuit, wherein the first driving circuit is electrically connected with a first pole of the first light emitting unit and is configured to generate a driving current for driving the first light emitting unit to emit light, the second driving circuit is electrically connected with a first pole of the second light emitting unit and is configured to generate a driving current for driving the second light emitting unit to emit light,

the power input end of the first driving circuit and the second pole of the second light emitting unit are respectively connected with a first power line, the power input end of the second driving circuit and the second pole of the first light emitting unit are respectively connected with a second power line, the first power line is used for respectively providing a first power supply signal for the first driving circuit and the second light emitting unit, the second power line is used for respectively providing a second power supply signal for the second driving circuit and the first light emitting unit,

The pixel circuit comprises a light-emitting stage in the working process of one display frame, wherein in the light-emitting stage, the first power supply signal and the second power supply signal are configured to be in voltage high-low jump along with time, and the first light-emitting unit and the second light-emitting unit alternately emit light in the light-emitting stage.

2. The pixel circuit according to claim 1, wherein the first driving circuit and the second driving circuit each include a data writing unit, a storage unit, and a driving unit,

the data writing unit is connected with the control end of the driving unit and is configured to write the data signal into the control end of the driving unit according to a first scanning signal;

the storage unit is used for storing the voltage at the control end of the driving unit;

the driving unit in the first driving circuit is connected between the power input end of the first driving circuit and the first pole of the first light emitting unit, and the driving unit in the second driving circuit is connected between the power input end of the second driving circuit and the first pole of the second light emitting unit; the driving unit is configured to generate a driving current according to a voltage of a control end of the driving unit;

Optionally, the control terminal of the data writing unit in the first driving circuit and the control terminal of the data writing unit in the second driving circuit are connected to the same first scanning line;

optionally, the data writing unit in the first driving circuit and the data writing unit in the second driving circuit are connected to the same data line.

3. The pixel circuit according to claim 2, wherein the driving unit comprises a first transistor, a first pole of the first transistor being a first terminal of the driving unit, a gate of the first transistor being a control terminal of the driving unit, a second pole of the first transistor being a second terminal of the driving unit;

the data writing unit comprises a second transistor, a first electrode of the second transistor is connected with the control end of the driving unit, a grid electrode of the second transistor is connected with a first scanning line, and a second electrode of the second transistor is connected with a data line;

the storage unit comprises a storage capacitor, a first end of the storage capacitor in the first driving circuit is connected with the first power line, a first end of the storage capacitor in the second driving circuit is connected with the second power line, a second end of the storage capacitor in the first driving circuit is connected with a control end of the driving unit, and a second end of the storage capacitor in the second driving circuit is connected with a control end of the driving unit.

4. The pixel circuit according to claim 1, wherein the first driving circuit and the second driving circuit each include a data writing unit, a storage unit, a driving unit, and a compensation unit,

the data writing unit is connected with the first end of the driving unit and is configured to write the data signal into the first end of the driving unit according to a first scanning signal;

the compensation unit is connected between the control end of the driving unit and the second end of the driving unit, and is configured to perform threshold compensation on the driving unit according to the first scanning signal;

optionally, the data writing unit in the first driving circuit and the data writing unit in the second driving circuit are connected to the same data line;

optionally, the control terminal of the compensation unit in the first driving circuit and the control terminal of the compensation unit in the second driving circuit are connected to the same first scan line.

5. The pixel circuit according to any one of claims 1 to 4, wherein the first driving circuit and the second driving circuit further comprise a first initializing unit and/or a second initializing unit,

the first initializing unit in the first driving circuit is connected with a first pole of the first light emitting unit, the first initializing unit in the second driving circuit is connected with a first pole of the second light emitting unit, and the first initializing unit is configured to transmit an initializing signal to the light emitting unit connected thereto according to a second scanning signal to initialize the light emitting unit connected thereto; and/or the number of the groups of groups,

In the same driving circuit, the second initializing unit is respectively connected with the control end of the driving unit and the storage unit, and is configured to transmit the initializing signal to the control end of the driving unit according to a third scanning signal so as to initialize the storage unit;

optionally, the control terminal of the first initializing unit in the first driving circuit and the control terminal of the first initializing unit in the second driving circuit are connected to the same second scanning line;

optionally, a control terminal of the second initializing unit in the first driving circuit and a control terminal of the second initializing unit in the second driving circuit are connected to the same third scanning line;

optionally, the first initializing unit includes a third transistor, in the same driving circuit, a first pole of the third transistor is connected to the light emitting unit connected to the first initializing unit, a gate of the third transistor is connected to the second scan line, and a second pole of the third transistor is connected to the initializing signal line;

optionally, the second initializing unit includes a fourth transistor, in the same driving circuit, a first pole of the fourth transistor is connected to the control end of the driving unit and the storage unit, a gate of the fourth transistor is connected to a third scan line, and a second pole of the fourth transistor is connected to the initializing signal line.

6. The pixel circuit according to any one of claims 1 to 4, wherein in the light emitting phase, the first power supply signal and the second power supply signal are configured to have voltages that jump with time and are opposite in voltage;

optionally, the first and second driving circuits further comprise a first and/or second light emission control unit,

the first light emitting control unit in the first driving circuit is connected between a second end of the driving unit and a first pole of the first light emitting unit, the first light emitting control unit in the second driving circuit is connected between the second end of the driving unit and the first pole of the second light emitting unit, and the first light emitting control unit is configured to turn on or off connection between the second end of the driving unit and the first pole of the light emitting unit to which the first light emitting control unit is connected according to a light emitting control signal; and/or the number of the groups of groups,

the second light emission control unit in the first driving circuit is connected between the first power line and the first end of the driving unit, the second light emission control unit in the second driving circuit is connected between the second power line and the first end of the driving unit, and the second light emission control unit is configured to turn on or off connection between the power line connected with the second light emission control unit and the first end of the driving unit according to the light emission control signal;

Optionally, the control terminal of the first light emitting control unit in the first driving circuit and the control terminal of the first light emitting control unit in the second driving circuit are connected to the same control signal line;

optionally, the control end of the second light emission control unit in the first driving circuit and the control end of the second light emission control unit in the second driving circuit are connected to the same control signal line;

optionally, the first light emitting control unit includes a fifth transistor, in the same driving circuit, a first pole of the fifth transistor is connected to a second end of the driving unit, a gate of the fifth transistor is connected to a control signal line, and a second pole of the fifth transistor is connected to a first pole of the light emitting unit connected to the first light emitting control unit;

optionally, the second light-emitting control unit includes a sixth transistor, in the same driving circuit, a first pole of the sixth transistor is connected to the first end of the driving unit, a gate of the sixth transistor is connected to the control signal line, and a second pole of the sixth transistor is connected to a power line connected to the second light-emitting control unit.

7. A display device comprising the pixel circuit according to any one of claims 1 to 6.

8. The display device according to claim 7, wherein the pixel circuits are plural and arranged in an array;

optionally, in the same pixel circuit, the first driving circuit and the second driving circuit are arranged in a row direction; the first driving circuit and the second driving circuit are connected to the same data line, the data line extends along a column direction, and the row direction and the column direction intersect.

9. A driving method of a pixel circuit for driving the pixel circuit according to any one of claims 1 to 6, characterized by comprising:

and in the light-emitting stage, the first power supply signal and the second power supply signal received by the pixel circuit are configured to be in voltage high-low jump along with time so that the first light-emitting unit and the second light-emitting unit alternately emit light.

10. The driving method of a pixel circuit according to claim 9, wherein the pixel circuit further includes a first initialization stage, a data writing stage, and a second initialization stage before the light-emitting stage during an operation of one display frame, the driving method further comprising:

In the first initialization stage, the third scanning signal is configured to be an on voltage, and the first scanning signal, the second scanning signal and the light emission control signal are configured to be an off voltage;

in the data writing stage, the first scanning signal is configured to be an on voltage, and the second scanning signal, the third scanning signal and the light-emitting control signal are configured to be an off voltage;

in the second initialization stage, the second scanning signal is configured to be an on voltage, and the first scanning signal, the third scanning signal and the light emission control signal are configured to be an off voltage;

in the light emitting stage, the light emitting control signal is configured to be an on voltage, and the first scanning signal, the second scanning signal and the third scanning signal are configured to be off voltages;

optionally, in the data writing stage, the first power supply signal and the second power supply signal are the same, and in the data writing stage, the voltages of the first power supply signal and the second power supply signal are equal to the voltage of the first power supply signal when the first light emitting unit emits light in the light emitting stage;

Optionally, in the first initialization stage, the first power supply signal and the second power supply signal are the same, and in the first initialization stage, the voltages of the first power supply signal and the second power supply signal are equal to the voltage of the first power supply signal when the first light emitting unit emits light in the light emitting stage;

optionally, in the second initialization stage, the first power supply signal and the second power supply signal are the same, and in the second initialization stage, the voltages of the first power supply signal and the second power supply signal are equal to the voltage of the second power supply signal when the first light emitting unit emits light in the light emitting stage;

optionally, in the lighting stage, the first power supply signal and the second power supply signal are configured to have voltage jump with time, and the voltage of the first power supply signal and the voltage of the second power supply signal are opposite.