CN111048573B

CN111048573B - Display panel and display device

Info

Publication number: CN111048573B
Application number: CN201911380403.2A
Authority: CN
Inventors: 朱家柱; 夏志强; 周瑞渊
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2022-08-05
Anticipated expiration: 2039-12-27
Also published as: CN111048573A

Abstract

The invention discloses a display panel and a display device.A first non-display area is internally provided with auxiliary sub-pixels, and second sub-data wires at least close to a second display area are electrically connected with the auxiliary sub-pixels, so that the number of the sub-pixels electrically connected with a first data wire can be increased, and the RC loading of the first data wire is compensated through the auxiliary sub-pixels. Therefore, the difference between the RC loading of the first data line and the RC loading of the second data line can be reduced, and when signals are loaded on the first data line and the second data line, the difference of signal delay can be reduced, so that the difference of voltages of display sub-pixels corresponding to the first data line and the second data line can be reduced, the problem of bright lines can be improved, and the display effect of the display panel can be improved.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the continuous development of display technology, the application range of display panels is wider and wider, and the requirements of people on the display panels are higher and higher. Therefore, how to manufacture a high-quality display panel is an urgent technical problem to be solved by those skilled in the art.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, which are used for improving the picture display effect of the display panel.

The embodiment of the invention provides a display panel, which comprises an array substrate with at least one notch;

the array substrate comprises a display area and a first non-display area; the display area comprises a first display area and a second display area which are arranged along a first direction, and the notch is positioned on one side of the first display area, which is deviated from the second display area; the first non-display area is positioned between the notch and the display area;

the array substrate further comprises a plurality of first data lines and a plurality of second data lines; the plurality of second data lines extend along a second direction and are positioned in the second display area; each first data line comprises a first sub data line positioned in the first display area and a second sub data line positioned in the first non-display area, and the first sub data line and the second sub data line of the same first data line are electrically connected;

the display area also comprises display sub-pixels arranged in an array; one of the second data lines is electrically connected with one column of the display sub-pixels, and a first sub-data line of the same first data line is electrically connected with one column of the display sub-pixels;

the first non-display area further comprises at least one auxiliary sub-pixel; and at least one auxiliary sub-pixel is electrically connected with the second sub-data line at least close to the second display area.

Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the display panel.

The invention has the following beneficial effects:

according to the display panel and the display device provided by the embodiment of the invention, the auxiliary sub-pixels are arranged in the first non-display area, and the second sub-data wires at least close to the second display area are electrically connected with the auxiliary sub-pixels, so that the number of the sub-pixels electrically connected with the first data wires can be increased, and the RC loading of the first data wires is compensated through the auxiliary sub-pixels. Therefore, the difference between the RC loading of the first data line and the RC loading of the second data line can be reduced, and when signals are loaded on the first data line and the second data line, the difference of signal delay can be reduced, so that the difference of voltages of display sub-pixels corresponding to the first data line and the second data line can be reduced, the problem of bright lines can be improved, and the display effect of the display panel can be improved.

Drawings

FIG. 1 is a schematic diagram of a display panel in the related art;

FIG. 2 is a schematic diagram of another display panel in the related art;

FIG. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a specific structure of a display panel according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a first pixel circuit according to an embodiment of the present invention;

FIG. 8 is a timing diagram of signals in an embodiment of the present invention;

FIG. 9 is a diagram illustrating a second pixel circuit according to an embodiment of the present invention;

fig. 10 is a schematic layout structure of a first pixel circuit and a second pixel circuit according to an embodiment of the invention;

fig. 11 is a layout diagram of an active semiconductor layer of a first pixel circuit and an active semiconductor layer of a second pixel circuit in an embodiment of the present invention;

fig. 12 is another layout diagram of the active semiconductor layer of the first pixel circuit and the active semiconductor layer of the second pixel circuit in the embodiment of the present invention;

fig. 13 is a schematic diagram of another layout structure of the first pixel circuit and the second pixel circuit in the embodiment of the invention;

fig. 14 is a schematic view of another layout of the active semiconductor layer of the first pixel circuit and the active semiconductor layer of the second pixel circuit in the embodiment of the present invention;

fig. 15 is a schematic diagram of another layout structure of the first pixel circuit and the second pixel circuit in the embodiment of the invention;

fig. 16 is a schematic view of another layout of the active semiconductor layer of the first pixel circuit and the active semiconductor layer of the second pixel circuit in the embodiment of the present invention;

fig. 17 is a schematic structural diagram of a display device in an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

With the development of display technology, the comprehensive screen has a larger screen occupation ratio and an ultra-narrow frame, and compared with a common display screen, the comprehensive screen can greatly improve the visual effect of a viewer, thereby receiving wide attention. In general, in a display device such as a mobile phone using a full-screen, a front camera, a receiver, and the like are generally provided on a front surface of the display device in order to realize a self-timer function and a call function. In order to realize full-screen display, as shown in a schematic plan view of a display panel shown in fig. 1, a non-display area 1 for disposing a front camera 10, a headphone 20, and the like is generally provided in the display panel. Also, in the display panel shown in fig. 1, the non-display area 1 is located at the upper side of the display panel, which makes it easier for the user to view the non-display area 1.

In order to improve the visual effect, as shown in fig. 2, a non-display area 1 for arranging the front camera 10, the headphone 20 and other devices may be arranged on the left side of the display panel, and due to the existence of the non-display area 1, the number of sub-pixels in each column in an area 2 where the non-display area 1 is located is smaller than that in the remaining area 3, so that the number of sub-pixels connected to the data line D1 in the area 2 and the data line D2 in the remaining area 3 is different, and thus the RC loading (RC loading) of the data line D1 in the area 2 and the data line D2 in the remaining area 3 is different, and thus the delay of the data lines in the area 2 and the remaining area 3 in transmitting data signals is different, so that the voltages input to the sub-pixels are different, and the display abnormality of the display panel is caused. For example, the data line D1 is the data line closest to the area 3 in the area 2, the data line D2 is the data line in the area 3, and since the number of sub-pixels electrically connected to the data line D1 and the data line D2 is different, the voltage of the sub-pixels corresponding to the input data line D1 and the data line D2 is different, so that the bright line recognized by human eyes is more obvious, and the display of the display panel is abnormal.

As the resolution of the display panel is higher and higher, for example, the resolution is 1920 × 1080, which is also often called fhd (full High definition), the voltage writing time of the data signal is usually less than 8 μ s. In this way, in the display panel shown in fig. 2, due to the different delays of the data line D1 and the data line D2, there is a difference in the voltages written into the corresponding sub-pixels, so that the bright lines recognized by human eyes are more obvious, and the display of the display panel is abnormal.

In view of the above, the embodiment of the invention provides a display panel, as shown in fig. 3 and 4, the display panel may include an array substrate having at least one notch 110;

the array substrate may include a display area AA and a first non-display area B1; the display area AA may include a first display area a1 and a second display area a2 arranged along a first direction F1, and the notch 110 is located at a side of the first display area a1 facing away from the second display area a 2; the first non-display area B1 is located between the notch 110 and the display area AA;

the array substrate may further include a plurality of first data lines 210 and a plurality of second data lines 220; wherein the plurality of second data lines 220 extend along the second direction F2 and are located in the second display area a 2; also, each of the first data lines 210 may include a first sub data line 211 located in the first display area a1 and a second sub data line 212 located in the first non-display area B1, the first sub data line 211 and the second sub data line 212 of the same first data line 210 being electrically connected;

the display area may further include display sub-pixels 310 arranged in an array; one second data line 220 is electrically connected to one row of display sub-pixels 310, and the first sub-data line 211 of the same first data line 210 is electrically connected to one row of display sub-pixels 310;

the first non-display region B1 may further include at least one auxiliary subpixel 410; wherein at least the second sub data line 212 near the second display area a2 is electrically connected to at least one auxiliary sub pixel 410.

In the display panel provided in the embodiment of the present invention, the auxiliary sub-pixels are disposed in the first non-display area, and the second sub-data lines at least close to the second display area are electrically connected to the auxiliary sub-pixels, so that the number of the sub-pixels electrically connected to the first data lines can be increased, and the auxiliary sub-pixels compensate for RC loading of the first data lines. Therefore, the difference between the RC loading of the first data line and the RC loading of the second data line can be reduced, and when signals are loaded on the first data line and the second data line, the difference of signal delay can be reduced, so that the difference of voltages of display sub-pixels corresponding to the first data line and the second data line can be reduced, the problem of bright lines can be improved, and the display effect of the display panel can be improved.

It should be noted that, as shown in fig. 3, the display panel may further include a second non-display area, and the second non-display area may surround the display area, so that the second non-display area is disposed on the periphery of the display panel, that is, the second non-display area may be a frame area of the display panel. For example, a gate driving circuit, an electrostatic protection circuit, a current limiting protection circuit, and the like may be disposed in the second non-display region. Of course, in practical applications, the elements disposed in the second non-display area may also be designed and determined according to practical application environments, and are not limited herein.

In addition, since the auxiliary sub-pixels 410 are only disposed in the first non-display region B1, and do not occupy the second non-display region around the display panel, the occupied area of the frame region of the display panel can be reduced, which is beneficial to implementing the narrow frame design of the display panel.

It should be noted that, the number of sub-pixels electrically connected to each second data line 220 in the second display area a2 is substantially the same, and the RC loading electrically connected to each second data line 220 is substantially the same. Also, the above substantially the same may refer to: the difference of the RC loading of any two second data lines 220 in the second display area a2 meets the error tolerance.

It should be noted that, if the number of the sub-pixels electrically connected to the first data line 210 and the second data line 220 is different, the RC loading of any one of the first data lines 210 in the first display area a1 is different from the RC loading of the second data line 220 in the second display area a 2. And, the above different fingers may be: the difference between the RC loading of the first data line 210 and the RC loading of the second data line 220 does not conform to the error tolerance.

In practical implementation, in the embodiment of the present invention, as shown in fig. 5, at least a portion of the second sub-data lines may be electrically connected to the plurality of auxiliary sub-pixels 410. Therefore, the auxiliary sub-pixels 410 can be electrically connected to the plurality of second sub-data lines, so that the RC loading of the plurality of first sub-data lines can be compensated.

For example, as shown in fig. 5, the second sub data lines may be electrically connected to the auxiliary sub pixels 410, respectively. Thus, each second sub data line is electrically connected with the auxiliary sub pixel 410, so that the RC loading of each first sub data line can be compensated.

In practical applications, the shapes of the notches are various, and therefore, the number of the auxiliary sub-pixels electrically connected to each of the second sub-data lines can be designed according to the shapes of the notches in practical applications. For example, in implementation, as shown in fig. 5, the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line may be sequentially decreased in a direction in which the second display area a2 points to the first display area a 1. For example, the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line 211-1 is greater than the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line 211-2, and the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line 211-2 is greater than the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line 211-3. Thus, when the shape of the notch is a trapezoid and the short side of the trapezoid faces the first non-display area B1, the number of display sub-pixels 310 connected to the first data line 210 is sequentially decreased, so that the number of auxiliary sub-pixels connected to the second sub-data lines 211-1 to 211-3 is sequentially decreased, and the number of sub-pixels electrically connected to the first data line 210 is sequentially decreased, thereby enabling the brightness transition, further improving the problem of bright lines, and improving the display effect.

For example, in practical implementation, as shown in fig. 6, the number of the auxiliary sub-pixels 410 electrically connected to the second sub-data line may be sequentially increased along a direction in which the second display area a2 points to the first display area a 1. For example, the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line 211-1 is less than the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line 211-2, and the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line 211-2 is less than the number of auxiliary sub-pixels 410 electrically connected to the second sub-data line 211-3. Thus, when the shape of the notch is a trapezoid, and the short side of the trapezoid faces the first non-display area B1, the number of display sub-pixels 310 connected to the first data line 210 is sequentially decreased, and thus the number of auxiliary sub-pixels connected to the second sub-data lines 211-1 to 211-3 is sequentially increased, so that the number of sub-pixels of the first data line 210 and the second data line 220 can be approximately consistent, thereby further improving the problem of bright lines and enhancing the display effect.

The display panel generally uses a substrate to arrange the first data line 210, the second data line 220, the display sub-pixel 310 and the auxiliary sub-pixel 410, so as to form an array substrate. In specific implementation, the array substrate provided in the embodiment of the present invention may further include a substrate 100 on which the first data line 210, the second data line 220, the display sub-pixel 310, and the auxiliary sub-pixel 410 are disposed. The substrate may be a glass substrate, a flexible substrate, a silicon substrate, or the like, and is not limited thereto. When the display panel is applied to a display device, a camera, an earpiece, and the like are generally disposed, so in order to dispose the camera, the earpiece, and the like, in a specific implementation, in the display panel provided in the embodiment of the present invention, as shown in fig. 3 and 4, the first display area a1 may include two areas separated by an area where the notch 110 is located. The area of the gap 110 may be a hollowed-out area of the substrate. In an actual manufacturing process, the area of the substrate corresponding to the notch 110 is cut off, so that the area of the notch 110 becomes a hollow area, and the display device is provided with a camera, an earphone and other devices. Of course, the area where the notch 110 is located may also be used as a protective cover plate for devices such as a camera and an earphone without cutting, and at this time, the area where the notch 110 is located may be set as a non-hollow area. In addition, in order to make these devices work normally, the non-hollow-out area can also be set as a transparent display area or a non-display area. Of course, the specific arrangement of the notch 110 needs to be determined according to the actual application environment of the display panel, and is not limited herein.

In a specific implementation, in an embodiment of the present invention, the display panel may include: and the pixel units are arranged in the display area in an array mode. Each pixel unit includes a plurality of display sub-pixels 310. The display sub-pixels 310 are also arranged in an array. Illustratively, the pixel unit may include a red display sub-pixel, a green display sub-pixel and a blue display sub-pixel, so that color mixing may be performed by red, green and blue to realize color display. Or, the pixel unit may also include a red display sub-pixel, a green display sub-pixel, a blue display sub-pixel, and a white display sub-pixel, so that color display may be realized by performing color mixing of red, green, blue, and white. Of course, in practical applications, the light emitting color of the display sub-pixel in the pixel unit can be determined according to practical application environments, and is not limited herein.

Electroluminescent Light Emitting Diodes (OLEDs), Quantum Dot Light Emitting Diodes (QLEDs), and the like have the advantages of self-luminescence and low energy consumption, and in specific implementation, the display panel may be an electroluminescent display panel. In an embodiment of the present invention, the display sub-pixel 310 may include an electroluminescent diode on a substrate and a first pixel circuit 311 for driving the electroluminescent diode to emit light. The electroluminescent diode comprises an anode, a light-emitting layer and a cathode which are arranged in a laminated mode. Further, the electroluminescent diode may include: at least one of an OLED and a QLED. Of course, the design may also be determined according to the actual application environment, and is not limited herein.

In specific implementation, as shown in fig. 7, 9 and 10, the display panel may further include: a plurality of gate lines, a plurality of emission control signal lines EM, a first power line PVDD, a plurality of reference voltage signal lines VREF; the gate line, the emission control signal line EM, and the reference voltage signal line VREF may extend along a first direction F1, and the second data line 220 extends along a second direction F2 and is arranged along a first direction F1, respectively. And, a row of sub-pixels may be electrically connected to at least one gate line, a row of sub-pixels is electrically connected to at least one emission control signal line EM, and a row of sub-pixels is electrically connected to a reference voltage signal line VREF. For example, as shown in fig. 7, 9 and 10, one row of sub-pixels may correspond to two gate lines, which may have a first gate line S1 and a second gate line S2, and one row of sub-pixels corresponds to one first gate line S1 and one gate line S2. In addition, one row of sub-pixels spx corresponds to one emission control signal line EM; one row of the subpixels spx corresponds to one reference voltage signal line VREF. Fig. 7 is a schematic structural diagram of the first pixel circuit 311 in the display sub-pixel 310. Fig. 9 is a schematic diagram of a specific structure of the second pixel circuit 411 in the auxiliary sub-pixel 410. Fig. 10 is a schematic diagram showing the Layout (Layout) of the first pixel circuit 311 in the sub-pixel 310 on the substrate.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4, fig. 7 and fig. 10, the first pixel circuit 311 in the display sub-pixel 310 may include: a driving transistor M0, a first light emission control transistor M1, a first data writing transistor M2, an initialization transistor M3, a threshold compensation transistor M4, a reset transistor M5, a second light emission control transistor M6, and a storage capacitor CST;

the gate of the first light emission controlling transistor M1 is electrically connected to the corresponding light emission control signal line EM, the first pole of the first light emission controlling transistor M1 is electrically connected to the first power supply line PVDD, and the second pole of the first light emission controlling transistor M1 is electrically connected to the first pole of the driving transistor M0.

The gate of the first data writing transistor M2 is electrically connected to the corresponding second gate line S2, the first pole of the first data writing transistor M2 is electrically connected to the corresponding second data line 220, and the second pole of the first data writing transistor M2 is electrically connected to the first pole of the driving transistor M0.

The gate of the initialization transistor M3 is electrically connected to the corresponding first gate line S1, the first pole of the initialization transistor M3 is electrically connected to the reference voltage signal line VREF, and the second pole of the initialization transistor M3 is electrically connected to the first pole of the electroluminescent diode L.

The gate of the threshold compensation transistor M4 is electrically connected to the corresponding second gate line S2, the first pole of the threshold compensation transistor M4 is electrically connected to the gate of the driving transistor M0, and the second pole of the threshold compensation transistor M4 is electrically connected to the second pole of the driving transistor M0.

The gate of the reset transistor M5 is electrically connected to the corresponding first gate line S1, the first pole of the reset transistor M5 is electrically connected to the reference voltage signal line VREF, and the second pole of the reset transistor M5 is electrically connected to the gate of the driving transistor M0.

The gate of the second emission control transistor M6 is electrically connected to the corresponding emission control signal line EM, the first pole of the second emission control transistor M6 is electrically connected to the second pole of the driving transistor M0, and the second pole of the second emission control transistor M6 is electrically connected to the first pole of the el diode L.

A first electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor M0, and a second electrode of the storage capacitor CST is electrically connected to the first power supply line PVDD.

The second pole of the electroluminescent diode L is electrically connected to a second supply terminal.

Illustratively, the transistors described above may each be provided as a P-type transistor. Alternatively, the transistors may be all N-type transistors, which is not limited herein. And, the first pole can be set as the source and the second pole as the drain according to the type of the transistor and the type of the voltage loaded on the gate; alternatively, the first pole is set as the drain, and the second pole is set as the source, which may be determined according to the practical application environment, and is not limited herein.

In one embodiment, the voltage of the first power line may be a high voltage, and the voltage of the second power line may be a low voltage or a ground voltage. Of course, in practical applications, the specific value of the voltage may be determined according to practical application environments, and is not limited herein.

In a specific implementation, each of the transistors may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), and is not limited herein.

Fig. 7 shows a signal timing chart of the first pixel circuit 311, as shown in fig. 8. Where S1 represents a signal on the first gate line S1, S2 represents a signal on the second gate line S2, and EM represents a signal on the light emission control signal line EM. It should be noted that the operation process of the first pixel circuit 311 may be substantially the same as that in the related art, and is not described herein again.

It should be noted that the first pixel circuit may also adopt other structures, which may be designed and determined according to the actual application environment, and will not be described herein again.

In practical implementation, as shown in fig. 4 and fig. 9, the auxiliary sub-pixel 410 may only include the second pixel circuit 411, so that an extra electroluminescent diode is not required to be disposed in the auxiliary sub-pixel 410, and thus resource waste may be reduced. In addition, when the light-emitting layer material of the electroluminescent diode is prepared (such as evaporation) no longer needs to be additionally designed, the used mask is additionally designed, so that the process design difficulty and the preparation difficulty can be reduced.

In specific implementation, as shown in fig. 9, the second pixel circuit 411 may be made to include a second data write transistor M20; the second sub data line 212 is electrically connected to the second data writing transistor M20 in the corresponding auxiliary sub pixel 410. Thus, the second sub-data line 212 can be electrically connected to the second data writing transistor M20 to compensate the RC loading of the first data line 210, and the difference between the RC loading of the first data line 210 and the RC loading of the second data line 220 can be reduced, so that when a signal is loaded on the first data line 210 and the second data line 220, the difference of signal delay can be reduced, and thus the difference of voltages input to the display sub-pixels 310 corresponding to the first data line 210 and the second data line 220 can be reduced, thereby improving the problem of bright lines and improving the display effect of the display panel.

In a specific implementation, as shown in fig. 9, the gate of the second data write transistor M20 may be electrically connected to the gate line. For example, as shown in fig. 9, the gate of the second data write transistor M20 may be electrically connected to the second gate line S2. This makes it possible to keep the structural design of the second data write transistor M20 and the first data write transistor M1 consistent. In addition, the RC loading of the second gate line corresponding to the area where the notch 110 is located may also be improved, so that the difference between the delays of inputting the second gate lines may be reduced, and the display effect of the display panel may be further improved.

In concrete implementation, in the embodiment of the present invention, the number of transistors in the first pixel circuit 311 and the second pixel circuit 411 may be made the same. Illustratively, as shown in fig. 7 and 9, the second pixel circuit 411 may further include: a driving transistor M0, a first light emission control transistor M1, an initialization transistor M3, a threshold compensation transistor M4, a reset transistor M5, a second light emission control transistor M6, and a storage capacitor CST. Moreover, the electrical connection manner of the transistors in the first pixel circuit 311 and the second pixel circuit 411 is substantially the same, and is not described herein again.

For example, the following description will be made with reference to fig. 7 and 9 to 11. Fig. 10 is a layout diagram of the first pixel circuit 311 and the second pixel circuit 411. Fig. 11 is a layout diagram of an active semiconductor layer 3111 of the first pixel circuit 311 and an active semiconductor layer 4111 of the second pixel circuit 411. Fig. 10 schematically shows the active semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer. Wherein the first conductive layer may include: a first gate line, a second gate line, and a light emission control signal line EM. The second conductive layer may include: a reference voltage signal line VREF, and a second electrode of the storage capacitor CST. The third conductive layer may include: a DATA line DATA, and a first power line PVDD. It should be noted that the active semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer corresponding to the first pixel circuit 311 and the second pixel circuit 411 may be substantially the same as those in the related art, and are not described herein again. Only the active semiconductor layer 3111 and the active semiconductor layer 4111 will be described below.

In specific implementation, in the embodiment of the present invention, as shown in fig. 10 and 11, the active semiconductor layer 3111 and the active semiconductor layer 4111 may be formed by patterning using a semiconductor material. The active semiconductor layer 3111 may be used to form an active layer of each transistor in the first pixel circuit 311, and each active layer may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the active layer of the first data write transistor M2 includes a first source region, a first drain region, and a first channel region between the first source region and the first drain region; here, the first source region may serve as a first pole of the first data write transistor M2, and the first drain region may serve as a second pole of the first data write transistor M2. The active semiconductor layer 4111 may be used to fabricate active layers of the transistors in the second pixel circuit 411, and each active layer may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the active layer of the second data write transistor M20 includes a second source region, a second drain region, and a second channel region between the second source region and the second drain region; wherein the second source region may serve as a first pole of the second data write transistor M20, and the second drain region may serve as a second pole of the second data write transistor M20.

For example, in specific implementation, as shown in fig. 10 and 11, the active layers of the transistors in the first pixel circuit 311 may be provided integrally. That is, the active semiconductor layer 3111 is provided as a unitary structure. Illustratively, the active semiconductor layer 3111 may be made of amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or the like, respectively. Note that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

For example, in specific implementation, as shown in fig. 10 and 11, the active layers of the transistors in the second pixel circuit 411 may be provided as one body. That is, the active semiconductor layer 4111 may be provided as a unitary structure. Illustratively, the active semiconductor layer 4111 may be made of amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or the like, respectively. Note that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

In practical implementation, in the embodiment of the present invention, as shown in fig. 10 and 11, the orthographic projection of the first functional transistor in the first pixel circuit 311 on the substrate 100 may be the same as the orthographic projection of the first functional transistor in the second pixel circuit 411 on the substrate 100, and the orthographic projection area of the first functional transistor in the second pixel circuit 411 on the substrate 100 may be equal to the orthographic projection area of the first functional transistor in the first pixel circuit 311 on the substrate 100. In this way, the structural arrangement of the first functional transistor in the second pixel circuit 411 in the first functional transistor in the first pixel circuit 311 can be kept approximately consistent, so that the consistency of compensation of the second pixel circuit 411 on the first data line 210 can be better, and the display effect can be further improved.

For example, in practical implementation, in the embodiment of the present invention, the first functional transistor may refer to: transistors which realize the same function in the first pixel circuit 311 and the second pixel circuit 411. For example, the first data writing transistor M2 and the second data writing transistor M20 perform the same function, and both provide the signal on the electrically connected data line to the first pole of the driving transistor M0 when they are in the on state under the control of the signal on their gates. Similarly, the function of the driving transistor M0 in the first pixel circuit 311 and the function of the driving transistor M0 in the second pixel circuit 411 are the same, the function of the first light emission control transistor M1 in the first pixel circuit 311 and the function of the first light emission control transistor M1 in the second pixel circuit 411 are the same, the function of the initialization transistor M3 in the first pixel circuit 311 and the function of the initialization transistor M3 in the second pixel circuit 411 are the same, the function of the threshold compensation transistor M4 in the first pixel circuit 311 and the function of the threshold compensation transistor M4 in the second pixel circuit 411 are the same, the function of the reset transistor M5 in the first pixel circuit 311 and the function of the reset transistor M5 in the second pixel circuit 411 are the same, and the function of the second light emission control transistor M6 in the first pixel circuit 311 and the function of the second light emission control transistor M6 in the second pixel circuit 411 are the same.

For example: by making the shape of the orthographic projection of the first data writing transistor M2 in the first pixel circuit 311 on the substrate 100 the same as the orthographic projection of the second data writing transistor M20 in the second pixel circuit 411 on the substrate 100, and making the area of the orthographic projection of the second data writing transistor M20 in the second pixel circuit 411 on the substrate 100 equal to the area of the orthographic projection of the first data writing transistor M2 in the first pixel circuit 311 on the substrate 100. The structural arrangement of the first data writing transistor M2 and the second data writing transistor M20 can be made more consistent, so that the compensation consistency of the second pixel circuit 411 to the first data line 210 can be made better. The rest transistors are the same, and so on, and are not described herein.

Illustratively, as shown in fig. 11, the orthographic projection of the active layer in the second pixel circuit 411 on the substrate 100 may be made the same shape as the orthographic projection of the active layer in the first pixel circuit 311 on the substrate 100. And the area of the orthographic projection of the active layer in the second pixel circuit 411 on the substrate 100 is made equal to the area of the orthographic projection of the active layer in the first pixel circuit 311 on the substrate 100. For example, the shape of the orthographic projection of the active semiconductor layer 3111 on the substrate 100 may be the same as the shape of the orthographic projection of the active semiconductor layer 4111 on the substrate 100. And the area of the orthographic projection of the active semiconductor layer 3111 on the substrate 100 is made the same as the area of the orthographic projection of the active semiconductor layer 4111 on the substrate 100. This makes it possible to make the second pixel circuit 411 and the first pixel circuit 311 arranged more uniformly, and thus makes it possible to make the second pixel circuit 411 more uniformly compensate the first data line 210.

In an actual process, the same or equal relation among the above features may not be completely the same or equal due to limitations of process conditions or other factors, and some deviation may occur, so long as the same or equal relation substantially satisfies the above conditions, all of which belong to the protection scope of the present invention. For example, the same or equal to described above may be the same or equal to that allowed within an error allowance.

Alternatively, in specific implementation, in the embodiment of the present invention, the shape of the orthographic projection of the first functional transistor in the first pixel circuit 311 on the substrate 100 is the same as the orthographic projection of the first functional transistor in the second pixel circuit 411 on the substrate 100, and the area of the orthographic projection of the first functional transistor in the second pixel circuit 411 on the substrate 100 is smaller than the area of the orthographic projection of the first functional transistor in the first pixel circuit 311 on the substrate 100. The first functional transistor refers to a transistor which can realize the same function in the first pixel circuit 311 and the second pixel circuit 411. For example, the shape of the orthographic projection of the first data writing transistor M2 on the substrate base plate 100 in the first pixel circuit 311 and the orthographic projection of the second data writing transistor M20 on the substrate base plate 100 in the second pixel circuit 411 may be made the same, and the area of the orthographic projection of the first data writing transistor M2 on the substrate base plate 100 in the second pixel circuit 411 is made smaller than the area of the orthographic projection of the second data writing transistor M20 on the substrate base plate 100 in the first pixel circuit 311. For the same reason, the description is omitted here. This can reduce the occupied area of the second pixel circuit 411. Since the area of the first non-display region B1 is smaller, the space between the second sub-data lines 212 is smaller, and the occupied area of the second pixel circuit 411 is reduced, so that the occupied space of the second pixel circuit 411 can be saved, the occupied area of the first non-display region B1 can be reduced, and the area of the display region can be further increased.

Illustratively, as shown in fig. 12, the orthographic projection of the active layer in the second pixel circuit 411 on the base substrate 100 may be made the same shape as the orthographic projection of the active layer in the first pixel circuit 311 on the base substrate 100. And the area of the orthographic projection of the active layer in the second pixel circuit 411 on the substrate 100 is made smaller than the area of the orthographic projection of the active layer in the first pixel circuit 311 on the substrate 100. For example, the shape of the orthographic projection of the active semiconductor layer 3111 on the substrate 100 may be the same as the shape of the orthographic projection of the active semiconductor layer 4111 on the substrate 100. And the area of the orthographic projection of the active semiconductor layer 3111 on the substrate 100 is made the same as the area of the orthographic projection of the active semiconductor layer 4111 on the substrate 100. This can reduce the occupied area of the second pixel circuit 411.

The embodiment of the invention provides another display panel, which has a structure as shown in fig. 13 and 14, and is modified from the above embodiment. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In practical implementation, in the embodiment of the present invention, the second pixel circuit 411 may include only the second data writing transistor. That is, the driving transistor M0, the first light emission control transistor M1, the initialization transistor M3, the threshold compensation transistor M4, the reset transistor M5, the second light emission control transistor M6, and the storage capacitor CST are not provided in the second pixel circuit 411. Thus, not only the RC loading of the first data line 210 can be compensated, but also the occupied area of the second pixel circuit 411 can be further reduced, so that the occupied area of the first non-display area can be reduced.

For example, in practical implementation, in the embodiment of the present invention, as shown in fig. 13 and 14, the orthographic projection of the second data writing transistor on the substrate 100 may have the same area as the orthographic projection of the first data writing transistor on the substrate 100, and the orthographic projection of the second data writing transistor on the substrate 100 may also have the same shape as the orthographic projection of the first data writing transistor on the substrate 100. This allows the structural design of the second data writing transistor and the first data writing transistor to be substantially the same, and thus allows the second pixel circuit 411 to compensate the first data line 210 more uniformly. Thus, not only the RC loading of the first data line 210 can be compensated, but also the occupied area of the second pixel circuit 411 can be further reduced, so that the occupied area of the first non-display area can be reduced.

Illustratively, in practical implementation, in the embodiment of the present invention, as shown in fig. 13 and 14, the orthographic projection of the active layer M20-a of the second data writing transistor on the substrate 100 may be made the same shape as the orthographic projection of the active layer M2-a of the first data writing transistor on the substrate 100. And making the orthographic projection of the active layer M20-a of the second data writing transistor on the substrate 100 the same as the orthographic projection of the active layer M2-a of the first data writing transistor on the substrate 100 in area. This allows the structural design of the second data writing transistor and the first data writing transistor to be substantially the same, and thus allows the second pixel circuit 411 to compensate the first data line 210 more uniformly.

In an actual process, the same or different features may not be completely the same due to limitations of process conditions or other factors, and therefore, the same relationship between the features may be satisfied only by approximately satisfying the above conditions, and all of the features fall within the scope of the present invention. For example, the same may be the same or equal as allowed within an error allowable range.

Another display panel according to an embodiment of the present invention is shown in fig. 15 and 16, which is a modification of the above embodiment. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In practical implementation, when the second pixel circuit 411 includes only the second data writing transistor, in the embodiment of the present invention, as shown in fig. 15 and 16, the orthographic projection of the second sub-data line 212 on the substrate 100 may be made to cover the orthographic projection of the active layer M20-a of the second data writing transistor electrically connected to the second sub-data line 212 on the substrate 100. This not only compensates for the RC loading of the first data line 210, but also reduces the occupied area of the second pixel circuit 411 to the maximum. Moreover, since the area of the first non-display area B1 is small, the pitch between the second sub data lines 212 is small, and the front projection of the second sub data lines 212 covers the front projection of the active layer M20-a of the second data writing transistor, so that the occupied area of the second pixel circuit 411 can be reduced to the greatest extent, the occupied space of the second pixel circuit 411 can be saved to the greatest extent, and the occupied area of the first non-display area B1 can be reduced to the greatest extent.

In addition, the RC loading compensation of the first data line can be realized without increasing the distance between two adjacent second sub data lines.

In practical application, when the array substrate is prepared, the original composition pattern is changed only when the pattern of the active layer is formed, the patterns of the active layer in the first pixel circuit and the active layer in the second display circuit are simultaneously formed through one-time composition process, and the process for independently preparing the active layer is not needed to be added, so that the preparation process flow can be simplified, the production cost is saved, and the production efficiency is improved.

Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The principle of the display device to solve the problem is similar to the display panel, so the implementation of the display device can be referred to the implementation of the display panel, and repeated details are not repeated herein.

In particular implementation, in the embodiment of the present invention, as shown in fig. 17, the display device may include a display panel 01. The structure of the display panel 01 can be seen in the embodiments described above, and is not described herein.

In specific implementation, in an embodiment of the present invention, the display device may include: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. The display panel is characterized by comprising an array substrate with at least one notch;

the display area also comprises display sub-pixels arranged in an array; one of the second data lines is electrically connected with one column of the display sub-pixels, and the first sub-data line of the same first data line is electrically connected with one column of the display sub-pixels;

the first non-display area further comprises at least one auxiliary sub-pixel; the second sub data line at least close to the second display area is electrically connected with at least one auxiliary sub pixel;

the array substrate further comprises a second grid line; each second grid line is electrically connected with the display sub-pixel;

the auxiliary sub-pixel electrically connected with the second sub-data line is also electrically connected with the second grid line.

2. The display panel according to claim 1, wherein the display sub-pixel includes an electroluminescent diode and a first pixel circuit electrically connected to the electroluminescent diode; the first pixel circuit includes a first data writing transistor; the second data line is electrically connected with the first data writing transistor in the corresponding display sub-pixel;

the auxiliary sub-pixel includes only a second pixel circuit; the second pixel circuit includes a second data write transistor; the second sub data line is electrically connected with the second data writing transistor in the corresponding auxiliary sub pixel.

3. The display panel of claim 2, wherein the array substrate further comprises: a plurality of gate lines extending in the first direction,

the gate electrode of the second data writing transistor is electrically connected to the gate line.

4. The display panel according to claim 3, wherein the number of transistors in the first pixel circuit and the second pixel circuit is the same;

the orthographic projection of the first functional transistor in the first pixel circuit on the array substrate is the same as the orthographic projection of the first functional transistor in the second pixel circuit on the array substrate in shape;

the area of the orthographic projection of the first functional transistor in the second pixel circuit on the array substrate is smaller than or equal to the area of the orthographic projection of the first functional transistor in the first pixel circuit on the array substrate.

5. The display panel according to claim 4, wherein active layers of the transistors in the first pixel circuit and the second pixel circuit are of a unitary structure;

the orthographic projection of the active layer in the second pixel circuit on the array substrate is the same as the orthographic projection of the active layer in the first pixel circuit on the array substrate in shape;

the area of the orthographic projection of the active layer in the second pixel circuit on the array substrate is smaller than or equal to the area of the orthographic projection of the active layer in the first pixel circuit on the array substrate.

6. The display panel according to claim 3, wherein the second pixel circuit includes only the second data writing transistor.

7. The display panel according to claim 6, wherein an area and a shape of an orthogonal projection of the second data writing transistor on the array substrate are respectively the same as an area and a shape of an orthogonal projection of the first data writing transistor on the array substrate.

8. The display panel of claim 6, wherein an orthographic projection of the second sub data line on the array substrate covers an orthographic projection of an active layer of a second data writing transistor electrically connected with the second sub data line on the array substrate.

9. The display panel according to any one of claims 1 to 8, wherein at least a part of the second sub data lines are electrically connected to a plurality of the auxiliary sub pixels.

10. The display panel according to claim 9, wherein the number of the auxiliary sub-pixels to which the second sub-data lines are electrically connected is sequentially decreased or increased in a direction in which the second display area is directed to the first display area.

11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.