WO2021233318A1 - 一种基于超级电容无源cms均衡电路与方法 - Google Patents

一种基于超级电容无源cms均衡电路与方法 Download PDF

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WO2021233318A1
WO2021233318A1 PCT/CN2021/094473 CN2021094473W WO2021233318A1 WO 2021233318 A1 WO2021233318 A1 WO 2021233318A1 CN 2021094473 W CN2021094473 W CN 2021094473W WO 2021233318 A1 WO2021233318 A1 WO 2021233318A1
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pin
equalization
capacitor
twenty
module
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PCT/CN2021/094473
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English (en)
French (fr)
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马新甜
阮殿波
陈胜军
何啸月
万二平
何灵
刘芳芳
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宁波中车新能源科技有限公司
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Publication of WO2021233318A1 publication Critical patent/WO2021233318A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0014—Circuits for equalisation of charge between batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices

Definitions

  • the invention relates to the field of super capacitors, in particular to a passive CMS equalization circuit and method based on super capacitors.
  • Supercapacitors are known for their high power density, long charge-discharge cycle life, appropriate energy density, high reliability, wide operating temperature range, and low environmental requirements. Compared with other existing energy storage technologies, supercapacitor energy storage technology has obvious advantages of pollution-free and high efficiency, which is in line with the current mainstream trend of developing green energy. It is mainly used in consumer electronics, smart watches, smart grids, electric vehicles, and petroleum. Military-related fields such as machinery, UPS and aerospace.
  • the rated voltage of supercapacitors is very low, and the rated voltage of organic electrolyte double-layer supercapacitors is only about 2.5V/2.7V. Therefore, in practical applications, multiple supercapacitors are generally combined in series and parallel to form supercapacitors. Module to meet the needs of energy storage capacity and voltage level. However, limited by factors such as manufacturing equipment and technological level, the capacity dispersion of electric double layer capacitors on the market is -10% to 20%. The voltage across the electric double layer capacitor increases with the accumulation of charge and decreases with the discharge. Unbalanced capacity and difference in leakage will lead to unbalanced cell voltages during charging and discharging, which will lead to inconsistent output power of each capacitor in the system.
  • each capacitor unit in the system will have inconsistent parameter attenuation, which will inevitably lead to more and more unbalanced voltages at the terminals of each unit, and individual units will fail prematurely and cause a series of continuous When the failure occurs, the system will eventually fail as a whole. Therefore, the voltage balance control between capacitors is directly related to the service life of the capacitors and the reliability of the system.
  • the super capacitor system adopts external power supply.
  • the control power DC12V, DC24V, AC220V
  • the control power DC12V, DC24V, AC220V
  • the control power DC12V, DC24V, AC220V
  • it takes a certain time to power on again It depends on the off-work time) to perform equalization before it can be put into work normally, which requires a certain amount of resources; at the same time, it is necessary to consider issues such as the power supply line of the equalization board, communication line layout, fixation, EMC, and communication interference.
  • the invention provides a passive CMS equalization circuit based on super capacitors.
  • the power of the super capacitor is used to maintain the balance circuit work to ensure that the super capacitor can achieve voltage equalization; at the same time, it eliminates the problems of power line layout, fixation and interference with communication lines.
  • the present invention proposes a super capacitor passive CMS equalization circuit, which includes a super capacitor group and a self Power supply module, sampling module, equalization control module, main control module and equalization module, including:
  • Super capacitor group including multiple capacitor monomers, used to provide DC power for the equalization circuit when the external control power is cut off;
  • Self-powered module used to convert DC power into DC working power under preset safety threshold, and provide working power for other modules
  • Sampling module used to collect the real-time voltage of each capacitor unit
  • Balance control module used to convert real-time voltage into real-time sampling signal
  • the main control module is configured to generate a first control signal according to the real-time sampling signal and send it to the equalization control module to generate a second control signal;
  • the equalization module is used to adjust the voltage balance of each capacitor unit through a resistor according to the second control signal.
  • the self-powered module includes:
  • the first switch (S1) one end of the first switch is connected to the positive output terminal of the super capacitor group, the other end is connected to the first fuse (FA1), and the other end of the first fuse is connected to the first thermistor (RTA1) ;
  • the other end of the first thermistor is simultaneously connected to the twentieth resistor (R20), the first transient suppression diode (D1), and the twenty-first capacitor (C21).
  • the twentieth resistor, the first transient The other end of the state suppression diode and the twenty-first capacitor are connected in parallel to the negative output end of the super capacitor group;
  • the first inductor (L1) includes first to fourth pins.
  • the first pin of the first inductor is connected to the negative output terminal of the supercapacitor group; the second pin of the first inductor passes through the first heat
  • the sensitive resistor is connected to the first fuse; the third pin of the first inductor is simultaneously connected to one end of the twenty-second to twenty-fourth capacitors (C22-C24), the twenty-second to twenty-fourth capacitors The other end of is connected in parallel to the fourth pin of the first inductor; the fourth pin of the first inductor is grounded;
  • the ninth power chip (U9) includes first to third pins, the first pin of the ninth power chip is connected to the third pin of the first inductor; the second pin of the ninth power chip is simultaneously Connect the fourth pin of the first inductor and one end of the twenty-second resistor (R22); the third pin of the ninth power chip is connected to one end of the twenty-first resistor (R21);
  • the first triode (Q1), the other ends of the twenty-first and twenty-second resistors are connected in parallel to the anode of the second diode (D2), and the cathode of the second diode is simultaneously connected to the second One end of the thirteen resistor (R23) and the base of the first triode; the other end of the twenty-third resistor and the emitter of the first triode are connected in parallel to the fourth pin of the first inductor;
  • the collector of the first transistor is simultaneously connected to the third pin of the ninth power chip and the source of the second transistor (K2) through the twenty-fifth resistor (R25).
  • the original question of the second transistor is also passed in order
  • the twenty-seventh resistor (R27) and the twenty-sixth capacitor (C26) are connected to the drain of the second transistor;
  • the gate of the second transistor is simultaneously connected to the cathode of the fourth diode (D4) and the twenty-eighth One end of the resistor (R28), the other end of the fourth diode and the twenty-eighth resistor are connected in parallel to the source of the second transistor;
  • the drain of the second transistor is used as the output terminal of the DC working power supply of the self-powered module ;
  • the second triode (Q2), the base of the second triode is simultaneously connected to one end of the twenty-sixth resistor (R26) and the cathode of the third diode, and the anode of the third diode is connected
  • the collector of the first diode, the other end of the twenty-sixth resistor and the emitter of the second triode are connected in parallel to the fourth pin of the first inductor, and the collector of the second triode is connected to the The gate of the second transistor.
  • the plurality of capacitor cells includes six capacitor cells from the forty-seventh to fifty-second capacitors (C47-C52);
  • the balance control module includes a thirteenth control chip (U13), including a first To the forty-eighth pins;
  • the main control module includes a first control chip (U1), including the first to the sixty-fourth pins.
  • sampling module includes:
  • the eighth to fourteenth inductors (L8-L14), and the forty-eighth resistor to the fifty-fourth resistor (R48-R54) are connected in series to form the first to seventh RL series circuit; the first The resistance end of the RL series circuit is connected to the fourteenth pin of the thirteenth control chip, the second RL series circuit resistance end is connected to the sixteenth pin of the thirteenth control chip, and the third RL series circuit resistance end is connected to the thirteenth control chip.
  • the eighteenth pin of the chip, the resistance end of the fourth RL series circuit is connected to the twentieth pin of the thirteenth control chip, and the resistance end of the fifth RL series circuit is connected to the twenty-second pin of the thirteenth control chip.
  • the resistance end of the six RL series circuit is connected to the twenty-fourth pin of the thirteenth control chip, and the seventh RL series circuit resistance end is connected to the twenty-sixth pin of the thirteenth control chip; the inductance of the first RL series circuit
  • the second, fourth, sixth, eighth, tenth and twelfth pins of the thirteenth control chip are respectively connected to the second, fourth, sixth, eighth, tenth and twelfth pins through the seventy-ninth resistor (R79);
  • the inductive end of the seventh RL series circuit passes The fifty-fifth resistor (R55) is grounded and one end of the seventy-third capacitor (C73) respectively, and the other end of the seventy-third capacitor is connected to the twenty-sixth pin of the thirteenth control chip;
  • the fourteenth pin of the thirteenth control chip is connected to the anode of the seventh diode (D7) and one end of the forty-seventh capacitor at the same time.
  • the other end is connected in parallel to the sixteenth pin; the sixteenth pin is simultaneously connected to the anode of the eighth diode (D8) and one end of the 48
  • the other end of the capacitor is connected to the eighteenth pin in parallel; the eighteenth pin is simultaneously connected to the anode of the ninth diode (D9) and one end of the forty-ninth capacitor.
  • the cathode of the ninth diode and the fourth The other end of the nineteenth capacitor is connected in parallel to the twentieth pin; the twentieth pin is simultaneously connected to the anode of the tenth diode (D10) and one end of the fiftieth capacitor.
  • the other end of the fifty capacitor is connected in parallel to the twenty-second pin; the twenty-second pin is simultaneously connected to the anode of the eleventh diode (D11) and one end of the fifty-first capacitor.
  • the negative pole and the other end of the fifty-first capacitor are connected in parallel to the twenty-fourth pin; the twenty-fourth pin is simultaneously connected to the positive pole of the twelfth diode (D12) and one end of the fifty-second capacitor.
  • the cathode of the twelve diode and the other end of the fifty-second capacitor are connected in parallel to the twenty-sixth pin.
  • the equalization module includes first to sixth equalization units, wherein each equalization unit includes:
  • the first field effect transistor (Q1A), the grid of the first field effect transistor uses the ninety-fourth resistor (R94) as the second control signal input terminal, and at the same time is connected to one end of the ninety-fifth resistor (R95) and The cathode of the first Zener diode (ZA1), the other end of the 95th resistor and the anode of the first Zener diode are connected in parallel to the source of the first FET; the source of the first FET As the second port; the drain of the field effect transistor is sequentially connected to the first equalization resistor (R1A) and the second equalization resistor (R2A) as the first port.
  • the first port of the first equalization unit is connected to the inductance end of the seventh RL series circuit, and the second port is connected to the inductance end of the sixth RL series circuit; the first port of the second equalization unit is connected to the inductance end of the sixth RL series circuit.
  • the two ports are connected to the inductance end of the fifth RL series circuit; the first port of the third equalization unit is connected to the inductance end of the fifth RL series circuit, and the second port is connected to the inductance end of the fourth RL series circuit; the first port of the fourth equalization unit The port is connected to the inductance end of the fourth RL series circuit, the second port is connected to the inductance end of the third RL series circuit; the first port of the fifth equalizing unit is connected to the inductance end of the third RL series circuit, and the second port is connected to the second RL series circuit The inductance end of the circuit; the first port of the sixth equalization unit is connected to the inductance end of the second RL series circuit, and the second port is connected to the inductance end of the first RL series circuit.
  • SPI module and a CAN communication module, among which:
  • SPI module used to balance the signal communication between the control module and the main control module
  • CAN communication module used for signal communication between the main control module and external equipment.
  • the present invention also provides a super capacitor passive CMS equalization method, which is characterized in that it includes a super capacitor bank, a self-powered module, a sampling module, an equalization control module, a main control module, and an equalization module, and includes the steps:
  • S2 Use the self-powered module to convert the DC power supply to the DC working power supply under the preset safety threshold to supply power to other modules;
  • S3 Collect the real-time voltage of each capacitor unit through the sampling module
  • S5 Use the main control module to generate the first control signal according to the real-time sampling signal
  • the second control signal is generated by the equalization control module to control the equalization module to adjust the voltage balance of each capacitor unit.
  • the present invention has at least the following beneficial effects:
  • a super capacitor passive CMS equalization circuit and method according to the present invention adopts when the external power supply of the super capacitor group is stopped, the electric energy stored in the super capacitor group is used as the power supply of the equalization circuit to ensure that the super capacitor is powered off Under the circumstance, it can still maintain the voltage equalization state to avoid the loss of capacitance caused by the destruction of the voltage equalization state due to power failure;
  • the self-powered module adopts the cooperation of the transistor K2 and the capacitors, resistors and diodes to ensure that the output voltage of the self-powered module does not exceed the preset safety threshold, ensuring the safety and reliability of circuit operation;
  • each module can be arranged relatively independently on the circuit board, which can eliminate or suppress most of the interference and enhance the stability of the circuit.
  • Figure 1 is a schematic block diagram of a super capacitor passive CMS equalization circuit and method
  • Figure 2 is a schematic diagram of a self-powered module circuit
  • Figure 3 is a schematic diagram of the circuit of the sampling module and the equalization control module
  • FIG. 4 is a schematic diagram of the circuit of the first voltage conversion module
  • FIG. 5 is a schematic diagram of the SPI module circuit
  • Figure 6 is a schematic diagram of the main control module circuit
  • Figure 7 is a schematic diagram of the CAN communication module circuit
  • Figure 8 is a schematic diagram of a second voltage conversion module circuit
  • Figure 9 is a schematic diagram of the equalizing unit circuit.
  • the present invention proposes a super capacitor passive CMS equalization circuit, as shown in Figure 1, including the super capacitor group , Self-powered module, sampling module, equalization control module, main control module and equalization module, including:
  • the super capacitor group includes a plurality of capacitor cells (a super capacitor group composed of 6 capacitor cells used in this embodiment), which is used to provide DC power for the equalization circuit when the external control power is cut off (or there is no power supply) (Voltage of capacitor bank is 5.5V ⁇ 36V);
  • the self-powered module is used to convert the DC power supply into a DC working power supply (5V forward DC power supply) under a preset safety threshold to provide working power for other modules;
  • Sampling module used to collect the real-time voltage of each capacitor unit
  • Balance control module used to convert real-time voltage into real-time sampling signal
  • the main control module is configured to generate a first control signal according to the real-time sampling signal and send it to the equalization control module to generate a second control signal;
  • the equalization module is used to adjust the voltage balance of each capacitor unit through a resistor according to the second control signal.
  • each module can be arranged relatively independently on the circuit board, which can eliminate or suppress most of the interference and enhance the stability of the circuit.
  • connection mode of the self-powered module includes:
  • the first switch (S1) one end of the first switch is connected to the positive output terminal of the super capacitor group, the other end is connected to the first fuse (FA1), and the other end of the first fuse is connected to the first thermistor (RTA1) ;
  • the other end of the first thermistor is simultaneously connected to the twentieth resistor (R20), the first transient suppression diode (D1), and the twenty-first capacitor (C21).
  • the twentieth resistor, the first transient The other end of the state suppression diode and the twenty-first capacitor are connected in parallel to the negative output end of the super capacitor group;
  • the first inductor (L1) includes first to fourth pins.
  • the first pin of the first inductor is connected to the negative output terminal of the supercapacitor group; the second pin of the first inductor passes through the first heat
  • the sensitive resistor is connected to the first fuse; the third pin of the first inductor is simultaneously connected to one end of the twenty-second to twenty-fourth capacitors (C22-C24), the twenty-second to twenty-fourth capacitors The other end of is connected in parallel to the fourth pin of the first inductor; the fourth pin of the first inductor is grounded;
  • the ninth power chip (U9) includes first to third pins, the first pin of the ninth power chip is connected to the third pin of the first inductor; the second pin of the ninth power chip is simultaneously Connect the fourth pin of the first inductor and one end of the twenty-second resistor (R22); the third pin of the ninth power chip is connected to one end of the twenty-first resistor (R21);
  • the first triode (Q1), the other ends of the twenty-first and twenty-second resistors are connected in parallel to the anode of the second diode (D2), and the cathode of the second diode is simultaneously connected to the second One end of the thirteen resistor (R23) and the base of the first triode; the other end of the twenty-third resistor and the emitter of the first triode are connected in parallel to the fourth pin of the first inductor;
  • the collector of the first transistor is simultaneously connected to the third pin of the ninth power chip and the source of the second transistor (K2) through the twenty-fifth resistor (R25).
  • the original question of the second transistor is also passed in order
  • the twenty-seventh resistor (R27) and the twenty-sixth capacitor (C26) are connected to the drain of the second transistor;
  • the gate of the second transistor is simultaneously connected to the cathode of the fourth diode (D4) and the twenty-eighth One end of the resistor (R28), the other end of the fourth diode and the twenty-eighth resistor are connected in parallel to the source of the second transistor;
  • the drain of the second transistor is used as the output terminal of the DC working power supply of the self-powered module ;
  • the second triode (Q2), the base of the second triode is simultaneously connected to one end of the twenty-sixth resistor (R26) and the cathode of the third diode, and the anode of the third diode is connected
  • the collector of the first diode, the other end of the twenty-sixth resistor and the emitter of the second triode are connected in parallel to the fourth pin of the first inductor, and the collector of the second triode is connected to the The gate of the second transistor.
  • the current passes through the first fuse (FA1) to judge the current flowing through, and when the current exceeds the preset current level (according to the actual When the current of the fuse model is required to be selected), the circuit is protected by fuse in time to avoid damage to the components due to the flow of large currents, and the characteristics of the transient secondary suppression tube and the inductance L1 are used to filter out the direct current. Then the voltage is reduced by the ninth power chip (U9, model K7805-1000R3), and the output voltage of 5V is output. At the same time, the input voltage is processed by the second transistor (K2, MOS tube) Judging to ensure that the output voltage does not exceed the preset safety threshold (5.5V), thereby ensuring the safety and reliability of the circuit as a whole.
  • the ninth power chip U9, model K7805-1000R3
  • the plurality of capacitor units includes six capacitor units from the forty-seventh to fifty-second capacitors (C47-C52);
  • the balance control module includes a thirteenth control chip (U13, chip The model number is LTC6804-2), including the first to forty-eighth pins;
  • the main control module includes the first control chip (U1, the chip model is STM32F107RCT6), which includes the first to the sixty-fourth pins.
  • the sampling module is combined with the equalization control module to collect the real-time voltage data of each capacitor unit, and the real-time voltage data is converted into The real-time sampling signal is transmitted to the main control module.
  • the main control module generates the first control signal according to the real-time sampling signal
  • the equalization control module generates the second control signal according to the first control signal
  • the equalization module balances each capacitor unit according to the second control signal The electric potential.
  • Figure 3 the circuit connection mode of the sampling circuit and the equalization control module is shown in Figure 3, including:
  • the eighth to fourteenth inductors (L8-L14), and the forty-eighth resistor to the fifty-fourth resistor (R48-R54) are connected in series to form the first to seventh RL series circuit; the first The resistance end of the RL series circuit is connected to the fourteenth pin of the thirteenth control chip, the second RL series circuit resistance end is connected to the sixteenth pin of the thirteenth control chip, and the third RL series circuit resistance end is connected to the thirteenth control chip.
  • the eighteenth pin of the chip, the resistance end of the fourth RL series circuit is connected to the twentieth pin of the thirteenth control chip, and the resistance end of the fifth RL series circuit is connected to the twenty-second pin of the thirteenth control chip.
  • the resistance end of the six RL series circuit is connected to the twenty-fourth pin of the thirteenth control chip, and the seventh RL series circuit resistance end is connected to the twenty-sixth pin of the thirteenth control chip; the inductance of the first RL series circuit
  • the second, fourth, sixth, eighth, tenth and twelfth pins of the thirteenth control chip are respectively connected to the second, fourth, sixth, eighth, tenth and twelfth pins through the seventy-ninth resistor (R79);
  • the inductive end of the seventh RL series circuit passes The fifty-fifth resistor (R55) is grounded and one end of the seventy-third capacitor (C73) respectively, and the other end of the seventy-third capacitor is connected to the twenty-sixth pin of the thirteenth control chip;
  • the fourteenth pin of the thirteenth control chip is connected to the anode of the seventh diode (D7) and one end of the forty-seventh capacitor at the same time.
  • the other end is connected in parallel to the sixteenth pin; the sixteenth pin is simultaneously connected to the anode of the eighth diode (D8) and one end of the 48
  • the other end of the capacitor is connected to the eighteenth pin in parallel; the eighteenth pin is simultaneously connected to the anode of the ninth diode (D9) and one end of the forty-ninth capacitor.
  • the cathode of the ninth diode and the fourth The other end of the nineteenth capacitor is connected in parallel to the twentieth pin; the twentieth pin is simultaneously connected to the anode of the tenth diode (D10) and one end of the fiftieth capacitor.
  • the other end of the fifty capacitor is connected in parallel to the twenty-second pin; the twenty-second pin is simultaneously connected to the anode of the eleventh diode (D11) and one end of the fifty-first capacitor.
  • the negative pole and the other end of the fifty-first capacitor are connected in parallel to the twenty-fourth pin; the twenty-fourth pin is simultaneously connected to the positive pole of the twelfth diode (D12) and one end of the fifty-second capacitor.
  • the cathode of the twelve diode and the other end of the fifty-second capacitor are connected in parallel to the twenty-sixth pin.
  • the uniform and constant control module further includes a first voltage conversion module for converting the 5V DC working power output from the self-powered module into a 24V working power supply to provide a suitable working power supply for the balancing control module, and its input end is connected The output terminal of the DC working power supply of the self-powered module is connected to the first pin of the thirteenth control chip. Since the power conversion module belongs to a conventional technology, the specific connection method will not be described in detail in this embodiment. If in doubt, refer to FIG. 4.
  • this embodiment adopts SPI communication, including the twelfth control chip (U12, the chip model is ADUM2401), which contains The first to sixteenth pins, of which the eleventh to fourteenth pins are respectively connected to the forty-fourth, forty-first, forty-third and forty-second pins of the thirteenth control chip (U13) Pins, the third to sixth pins are respectively connected to the 21st, 23rd, 20th and 22nd pins of the first control chip (U1). Refer to Figure 5 and Figure 6 for the specific connection .
  • this embodiment also includes a CAN communication module, which is used to transmit the operating data of the main control module (potential data of each capacitor unit, alarm signal, etc.) to the external device, and at the same time It can also receive control signals sent by external devices.
  • It includes the fifth chip (U5, the chip model is TD301DCAN), including the first to eighth pins, and its fourth pin (ie input) is connected to the first control chip (U1) through the thirty-first resistor (R31)
  • the forty-first pin, the three pins (that is, the output end) are connected to the 46th pin of the first control chip (U1) through the thirty-second resistor (R32).
  • the circuit connection mode of the other pins of the first control chip in the main control module is a conventional circuit connection mode, which is not described in detail in this embodiment. For details, refer to FIG. 6.
  • a second voltage conversion module which is used to convert the 5V DC working power output from the self-powered module into a 3.3V working power source to provide working power for the main control module and the CAN communication module, and its input terminal is connected to the self-powered module
  • the output terminal of the DC working power supply, the output terminal outputs a working voltage of 3.3V, causing it to belong to the conventional circuit connection mode, so this embodiment will not describe its connection mode in detail.
  • connection mode please refer to Figure 6, Figure 7 and Figure 8.
  • the equalization module in this embodiment includes first to sixth equalization units, and the connection mode of each equalization unit is shown in FIG. 9 and includes:
  • the first field effect transistor (Q1A), the grid of the first field effect transistor uses the ninety-fourth resistor (R94) as the second control signal input terminal, and at the same time is connected to one end of the ninety-fifth resistor (R95) and The cathode of the first Zener diode (ZA1), the other end of the 95th resistor and the anode of the first Zener diode are connected in parallel to the source of the first FET; the source of the first FET As the second port; the drain of the field effect transistor is sequentially connected to the first equalization resistor (R1A) and the second equalization resistor (R2A) as the first port.
  • connection mode of each equalization unit is as follows:
  • the first port of the first equalization unit is connected to the inductance end of the seventh RL series circuit, and the second port is connected to the inductance end of the sixth RL series circuit; the first port of the second equalization unit is connected to the inductance end of the sixth RL series circuit.
  • the two ports are connected to the inductance end of the fifth RL series circuit; the first port of the third equalization unit is connected to the inductance end of the fifth RL series circuit, and the second port is connected to the inductance end of the fourth RL series circuit; the first port of the fourth equalization unit The port is connected to the inductance end of the fourth RL series circuit, the second port is connected to the inductance end of the third RL series circuit; the first port of the fifth equalizing unit is connected to the inductance end of the third RL series circuit, and the second port is connected to the second RL series circuit The inductance end of the circuit; the first port of the sixth equalization unit is connected to the inductance end of the second RL series circuit, and the second port is connected to the inductance end of the first RL series circuit.
  • the equalization module When the equalization module receives the second control signal sent by the equalization control module through the second control signal input terminal, it adjusts the conduction state of the first field effect transistor according to the control signal, and uses the first and second equalization resistors to consume the capacitor unit The electric energy above the equalization line of each capacitor unit (the lowest potential of the capacitor unit is used as the equalization line), so as to achieve the potential balance of each capacitor unit in the power-off state.
  • the passive CMS equalization circuit of a super capacitor in this embodiment adopts when the external power supply of the super capacitor group is stopped, the electric energy stored in the super capacitor group itself is used as the power supply of the equalization circuit to ensure that the super capacitor is still in the event of a power failure. It can self-power to maintain the operation of the equalization circuit, avoiding the loss of capacitance caused by the destruction of the voltage equalization state due to power failure; at the same time, after the super capacitor group is powered on again, there is no need to spend extra time to wait for each capacitor unit to achieve voltage equalization. , Which greatly improves the operating efficiency of the machine relying on the work with the super capacitor group.
  • S2 Use the self-powered module to convert the DC power supply to the DC working power supply under the preset safety threshold to supply power to other modules;
  • S3 Collect the real-time voltage of each capacitor unit through the sampling module
  • S5 Use the main control module to generate the first control signal according to the real-time sampling signal
  • the second control signal is generated by the equalization control module to control the equalization module to adjust the voltage balance of each capacitor unit.
  • the passive CMS equalization circuit and method for supercapacitors of the present invention adopts that when the external power supply of the supercapacitor group is stopped, the electric energy stored in the supercapacitor group is used as the power supply of the equalization circuit to ensure that the supercapacitor is in In the case of power failure, the voltage equalization state can still be maintained, and the loss of capacitance caused by the destruction of the voltage equalization state caused by the power failure can be avoided. Therefore, after the super capacitor bank is powered on again, there is no need to spend extra time waiting for each capacitor unit to realize the voltage equalization work, which greatly improves the operating efficiency of the machine relying on the super capacitor bank.
  • the self-powered module adopts the cooperation of the transistor K2 and the capacitors, resistors and diodes to ensure that the output voltage of the self-powered module does not exceed the preset safety threshold, ensuring the safety and reliability of the circuit operation; at the same time, the modular design is adopted.
  • the relatively independent arrangement of each module on the circuit board can eliminate or suppress most of the interference and enhance the stability of the circuit.

Abstract

提供了一种基于超级电容无源CMS均衡电路与方法，包括超级电容组、自供电模块、采样模块、均衡控制模块、主控模块和均衡模块，通过自供电模块将断电状态下的超级电容组作为转换为均衡电路的电源，采集各电容单体的实时电压，并由均衡控制模块和主控模块控制，由均衡模块通过电阻消耗的形式维持各超级电容单体之间的电势平衡。实现了当超级电容组外部供电停止时，利用超级电容组自身存储的电能作为均衡电路的电源，使超级电容组再次上电后，无需花费额外的时间去等待各电容单体实现均压工作，大大提高了依托于超级电容组工作的机器的运行效率。

Description

一种基于超级电容无源CMS均衡电路与方法 技术领域
本发明涉及超级电容领域，具体涉及一种基于超级电容无源CMS均衡电路与方法。
背景技术
超级电容器以功率密度高、充放电循环寿命长、能量密度适当、可靠性高、工作温度范围宽、对环境要求低的优点著称。与其他现有储能技术相对比，超级电容储能技术具有无污染、效率高的明显优势，符合当下发展绿色能源的主流趋势，主要应用于消费电子、智能手表、智能电网、电动汽车、石油机械、UPS及航空航天等军事相关领域。
超级电容单体额定电压很低，有机电解液双电层超级电容器额定电压只有2.5V/2.7V左右，因此在实际应用中一般由多个超级电容通过串联和并联的方式组合构成超级电容储能模块，以满足储能容量和电压等级需要。然而，受制造装备、工艺水平等因素限制，市场上的双电层电容器的容量分散度为-10％～20％。双电层电容器两端电压随充电电荷的积累而上升，随放电而下降，容量不均衡及漏电差异会导致充放电过程中的单体电压不均衡，进而导致系统中各个电容器的输出功率不一致。随着充放电次数的不断增加，系统内的各个电容器单体会发生不一致的参数衰减现象，这必然导致各个单体端电压越来越不均衡，个别单体会提前失效，并引发一系列连续失效现象的发生，最终系统整体失效。因此，电容器间的电压平衡控制直接关系到电容器的使用寿命与系统的可靠性。
目前，大多数应用场景下，超级电容系统采用外部供电，在超级电容系统使用完成后将控制电(DC12V、DC24V、AC220V)全部断开，导致均衡电路无法工作，再次上电工作需要一定时间(取决于停止工作时间)进行均衡才能正常投入工作，需要耗费一定资源；同时需要考虑均衡板的供电线路、通信线路布置、固定及EMC、通信干扰等问题。本发明给出了一种基于超级电容无源CMS均衡电路。在超级电容系统控制电断开或无外部供电情况下利用超级电容自身电量维持均衡电路工作可保证超级电容实现均压工作；同时，省去电源线路布置、固定及与通信线路干扰等问题。
发明内容
为解决上述问题，使超级电容组在外部控制电断开之后均衡电路能够保持各电容单体之间的电势平衡，本发明提出了一种超级电容无源CMS均衡电路，包括超级电容组、自供电模块、采样模块、均衡控制模块、主控模块和均衡模块，其中：
超级电容组，包括多个电容单体，用于在外部控制电断电时，为均衡电路提供直流电源；
自供电模块，用于将直流电源转换为预设安全阀值下的直流工作电源，为其他模块提供工作电源；
采样模块，用于采集各电容单体的实时电压；
均衡控制模块，用于将实时电压转换为实时采样信号；
主控模块，用于根据实时采样信号，生成第一控制信号并发送至均衡控制模块生成第二控制信号；
均衡模块，用于根据第二控制信号通过电阻调节各电容单体的电压平衡。
进一步地，所述自供电模块，包括：
第一开关(S1)，所述第一开关一端接超级电容组正极输出端，另一端连接第一熔断器(FA1)，所述第一熔断器的另一端连接第一热敏电阻(RTA1)；所述第一热敏电阻的另一端同时连接第二十电阻(R20)、第一瞬态抑制二极管(D1)、第二十一电容(C21)，所述第二十电阻、第一瞬态抑制二极管和第二十一电容的另一端并联连接超级电容组的负极输出端；
第一电感(L1)，包括第一至第四引脚，所述第一电感的第一引脚连接超级电容组的负极输出端；所述中第一电感的第二引脚通过第一热敏电阻连接第一熔断器；所述第一电感的第三引脚同时连接第二十二至第二十四电容(C22-C24)的一端，所述第二十二至第二十四电容的另一端并联连接第一电感的第四引脚；所述第一电感的第四引脚接地；
第九电源芯片(U9),包括第一至第三引脚，所述第九电源芯片的第一引脚连接第一电感的第三引脚；所述第九电源芯片的第二引脚同时连接第一电感的第四引脚和第二十二电阻(R22)的一端；所述第九电源芯片的第三引脚连接第二十一电阻(R21)的一端；
第一三极管(Q1)，所述第二十一和第二十二电阻的另一端并联连接第二二极管(D2)的正极，所述第二二极管的负极同时连接第二十三电阻(R23)的一端和第一三极管的基极；所述第二十三电阻的另一端和第一三极管的发射极并联连接第一电感的第四引脚；所述第一三极管的集电极通过第二十五电阻(R25)同时连接第九电源芯片的第三引脚和第二晶体管(K2)的源极，所述第二晶体管的原题还顺序通过第二十七电阻(R27)和第二十六电容(C26)连接第二晶体管的漏极；所述第二晶体管的栅极同时连接第四二极管(D4)的负极和第二十八电阻(R28)的一端，所述第四二极管和第二十八电阻的另一端并联接连第二晶体管的源极；所述第二晶体管的漏极作为自供电模块的直流工作电源输出端；
第二三极管(Q2)，所述第二三极管的基极同时连接第二十六电阻(R26)的一端和第三二级管的负极，所述第三二极管的正极连接第一二极管的集电极，所述第二十六电阻的另一端和第二三管的发射极并联连接第一电感的第四引脚，所述第二三极管的集电极连接第二晶体管的栅极。
进一步地，所述多个电容单体包括第四十七至第五十二电容(C47-C52)六个电容单体；所述均衡控制模块包括第十三控制芯片(U13)，包含第一至第四十八引脚；所述主控模块包括第一控制芯片(U1)，包含第一至第六十四引脚。
进一步地，所述采样模块，包括：
第八至第十四电感(L8-L14)，和第四十八电阻至第五十四电阻(R48-R54)，并顺序两两串联组成第一至第七RL串联电路；所述第一RL串联电路电阻端连接第十三控制芯片的第十四引脚，第二RL串联电路电阻端连接第十三控制芯片的第十六引脚，第三RL串联电路电阻端连接第十三控制芯片的第十八引脚，第四RL串联电路电阻端连接第十三控制芯片的的二十引脚，第五RL串联电路电阻端连接第十三控制芯片的第二十二引脚，第六RL串联电路电阻端连接第十三控制芯片的第二十四引脚，第七RL串联电路电阻端连接第十三控制芯片的第二十六引脚；所述第一RL串联电路的电感端通过第七十九电阻(R79)分别连接第十三控制芯片的第二、第四、第六、第八、第十和第十二引脚；所述第七RL串联电路的电感端通过第五十五电阻(R55)分别接地和第七十三电容(C73)的一端，第七十三电容的另一端接第十三控制芯片的第二十六引脚；
所述第十三控制芯片的第十四引脚同时连接第七二极管(D7)的正极和第四十七电容的一端，所述第七二极管的负极和第四十七电容的另一端并联连接第十六引脚；第十六引脚同时连接第八二极管(D8)的正极和第四十八电容的一端，所述第八二极管的负极和第四十八电容的另一端并联连接第十八引脚；第十八引脚同时连接第九二极管(D9)的正极和第四十九电容的一端，所述第九二极管的负极和第四十九电容的另一端并联连接第二十引脚；第二十引脚同时连接第十二极管(D10)的正极和第五十电容的一端，所述第十二极管的负极和第五十电容的另一端并联连接第二十二引脚；第二十二引脚同时连接第十一二极管(D11)的正极和第五十一电容的一端，所述第十一电容的负极和第五十一电容的另一端并联连接第二十四引脚；第二十四引脚同时连接第十二二极管(D12)的正极和第五十二电容的一端，所述第十二二极管的负极和第五十二电容的另一端并联连接第二十六引脚。
进一步地，所述均衡模块包括第一至第六均衡单元，其中各均衡单元包括：
第一场效应管(Q1A)，所述第一场效应管的栅极通过第九十四电阻(R94)作为第二控制信号输入端，并同时连接第九十五电阻(R95)的一端和第一稳压二极管(ZA1)的负极，所述第九十五电阻的另一端和第一稳压二极管的正极并联连接第一场效应管的源极；所述第一场效应管的源极作为第二端口；所述场效应管的漏极顺序连接第一均衡电阻(R1A)和第二均衡电阻(R2A)作为第一端口。
进一步地，所述：
第一均衡单元的第一端口连接第七RL串联电路的电感端，第二端口连接第六RL串联电路的电感端；第二均衡单元的第一端口连接第六RL串联电路的电感端，第二端口连接第五RL串联电路的电感端；第三均衡单元的第一端口连接第五RL串联电路的电感端，第二端口连接第四RL串联电路的电感端；第四均衡单元的第一端口连接第四RL串联电路的电感端，第二端口连接第三RL串联电路的电感端；第五均衡单元的第一端口连接第三RL串联电路的电感端，第二端口连接第二RL串联电路的电感端；第六均衡单元的第一端口连接第二RL串联电路电感端，第二端口连接第一RL串联电路的电感端。
进一步地，还包括SPI模块和CAN通讯模块，其中：
SPI模块，用于均衡控制模块和主控模块之间的信号通讯；
CAN通讯模块，用于主控模块与外部设备的信号通讯。
本发明还提出了一种超级电容无源CMS均衡方法，其特征在于，包括超级电容组、自供电模块、采样模块、均衡控制模块、主控模块和均衡模块，包括步骤：
S1：外部控制电断电，将超级电容组的输出电压作为直流电源；
S2：利用自供电模块将直流电源转换为预设安全阀值下的直流工作电源，为其它模块供电；
S3：通过采样模块采集各电容单体的实时电压；
S4：将实时电压通过均衡控制模块转换为实时采样信号；
S5：根据实时采样信号利用主控模块生成第一控制信号；
S6：根据第一控制信号，通过均衡控制模块生成第二控制信号控制均衡模块调节各电容单体的电压平衡。
与现有技术相比，本发明至少含有以下有益效果：
(1)本发明所述的一种超级电容无源CMS均衡电路与方法，采取当超级电容组外部供电停止时，利用超级电容组自身存储的电能作为均衡电路的电源，保证超级电容在断电的情况下仍能够保持均压状态，避免因为断电，导致的均压状态破坏引起的电容损耗；
(2)超级电容组再次上电后，无需花费额外的时间去等待各电容单体实现均压工作，大大提高了依托于超级电容组工作的机器的运行效率；
(3)自供电模块中采用三极管K2与各电容、电阻与二极管的配合，保证自供电模块的输出电压不超过预设安全阀值，确保了电路运行的安全性和可靠性；
(4)采用模块化设计，可以在电路板上将各模块进行相对独立的布置，可以消除或抑制绝大部分的干扰，增强了电路的稳定性。
附图说明
图1为一种超级电容无源CMS均衡电路与方法的模块示意图；
图2为自供电模块电路示意图；
图3为采样模块与均衡控制模块电路示意图；
图4为第一电压转换模块电路示意图；
图5为SPI模块电路示意图；
图6为主控模块电路示意图；
图7为CAN通讯模块电路示意图；
图8为第二电压转换模块电路示意图；
图9为均衡单元电路示意图。
具体实施方式
以下是本发明的具体实施例并结合附图，对本发明的技术方案作进一步的描述，但本发明并不限于这些实施例。
为了使超级电容组在外部控制电断开之后均衡电路能够保持各电容单体之间的电势平衡，本发明提出了一种超级电容无源CMS均衡电路，如图1所示，包括超级电容组、自供电模块、采样模块、均衡控制模块、主控模块和均衡模块，其中：
超级电容组，包括多个电容单体(本实施例中采用的6个电容单体组成的超级电容组)，用于在外部控制电断电(或无供电)时，为均衡电路提供直流电源(电容组电压为5.5V～36V)；
自供电模块，用于将直流电源转换为预设安全阀值下的直流工作电源(5V正向直流电源)， 为其他模块提供工作电源；
采样模块，用于采集各电容单体的实时电压；
均衡控制模块，用于将实时电压转换为实时采样信号；
主控模块，用于根据实时采样信号，生成第一控制信号并发送至均衡控制模块生成第二控制信号；
均衡模块，用于根据第二控制信号通过电阻调节各电容单体的电压平衡。
采用模块化设计，可以在电路板上将各模块进行相对独立的布置，可以消除或抑制绝大部分的干扰，增强了电路的稳定性。
其中，所述自供电模块具体连接方式，如图2所示，包括：
第一开关(S1)，所述第一开关一端接超级电容组正极输出端，另一端连接第一熔断器(FA1)，所述第一熔断器的另一端连接第一热敏电阻(RTA1)；所述第一热敏电阻的另一端同时连接第二十电阻(R20)、第一瞬态抑制二极管(D1)、第二十一电容(C21)，所述第二十电阻、第一瞬态抑制二极管和第二十一电容的另一端并联连接超级电容组的负极输出端；
第一电感(L1)，包括第一至第四引脚，所述第一电感的第一引脚连接超级电容组的负极输出端；所述中第一电感的第二引脚通过第一热敏电阻连接第一熔断器；所述第一电感的第三引脚同时连接第二十二至第二十四电容(C22-C24)的一端，所述第二十二至第二十四电容的另一端并联连接第一电感的第四引脚；所述第一电感的第四引脚接地；
第九电源芯片(U9),包括第一至第三引脚，所述第九电源芯片的第一引脚连接第一电感的第三引脚；所述第九电源芯片的第二引脚同时连接第一电感的第四引脚和第二十二电阻(R22)的一端；所述第九电源芯片的第三引脚连接第二十一电阻(R21)的一端；
第一三极管(Q1)，所述第二十一和第二十二电阻的另一端并联连接第二二极管(D2)的正极，所述第二二极管的负极同时连接第二十三电阻(R23)的一端和第一三极管的基极；所述第二十三电阻的另一端和第一三极管的发射极并联连接第一电感的第四引脚；所述第一三极管的集电极通过第二十五电阻(R25)同时连接第九电源芯片的第三引脚和第二晶体管(K2)的源极，所述第二晶体管的原题还顺序通过第二十七电阻(R27)和第二十六电容(C26)连接第二晶体管的漏极；所述第二晶体管的栅极同时连接第四二极管(D4)的负极和第二十八电阻(R28)的一端，所述第四二极管和第二十八电阻的另一端并联接连第二晶体管的源极；所述第二晶体管的漏极作为自供电模块的直流工作电源输出端；
第二三极管(Q2)，所述第二三极管的基极同时连接第二十六电阻(R26)的一端和第三二级管的负极，所述第三二极管的正极连接第一二极管的集电极，所述第二十六电阻的另一端和第二三管的发射极并联连接第一电感的第四引脚，所述第二三极管的集电极连接第二晶体管的栅极。
当超级电容组输入直流电源至自供电模块，且第一开关(S1)导通时，电流先经过第一熔断器(FA1)对流经的电流进行判断，在超过预设电流大小(可根据实际需求对熔断器型号进行选定)的电流通过时，及时熔断对电路进行保护，避免大电流流过对元器件的损坏，并利用瞬态二级抑制管，以及电感L1的特性，滤除直流电中的杂波；然后通过第九电源芯片(U9，型号为K7805-1000R3)对电压大小进行降压处理，输出5V大小的输出电压，同时通过第二晶体管(K2，MOS管)对输入电压进行判断，保证输出的电压大小不会超过预设安全阀值(5.5V)，进而保证了电路整体的安全性和可靠性。
在本实施例中，所述多个电容单体包括第四十七至第五十二电容(C47-C52)六个电容单体；所述均衡控制模块包括第十三控制芯片(U13，芯片型号为LTC6804-2)，包含第一至第四十八引脚；所述主控模块包括第一控制芯片(U1，芯片型号为STM32F107RCT6)，包含第一至第六十四引脚。
而为了对超级电容各电容单体进行电势平衡，本实施例中采用采样模块结合均衡控制模块的方法，对各电容单体的实时电压数据进行采集，并通过均衡控制模块将实时电压数据转换为实时采样信号，并传递给主控模块，主控模块根据实时采样信号生成第一控制信号，均衡控制模块根据第一控制信号生成第二控制信号，均衡模块根据第二控制信号平衡各电容单体的电势。
其中，采样电路与均衡控制模块的电路连接方式如图3所示，包括：
第八至第十四电感(L8-L14)，和第四十八电阻至第五十四电阻(R48-R54)，并顺序两两串联组成第一至第七RL串联电路；所述第一RL串联电路电阻端连接第十三控制芯片的第十四引脚，第二RL串联电路电阻端连接第十三控制芯片的第十六引脚，第三RL串联电路电阻端连接第十三控制芯片的第十八引脚，第四RL串联电路电阻端连接第十三控制芯片的的二十引脚，第五RL串联电路电阻端连接第十三控制芯片的第二十二引脚，第六RL串联电路电阻端连接第十三控制芯片的第二十四引脚，第七RL串联电路电阻端连接第十三控制芯片的第二十六引脚；所述第一RL串联电路的电感端通过第七十九电阻(R79)分别连接第十三控制芯片的第二、第 四、第六、第八、第十和第十二引脚；所述第七RL串联电路的电感端通过第五十五电阻(R55)分别接地和第七十三电容(C73)的一端，第七十三电容的另一端接第十三控制芯片的第二十六引脚；
所述第十三控制芯片的第十四引脚同时连接第七二极管(D7)的正极和第四十七电容的一端，所述第七二极管的负极和第四十七电容的另一端并联连接第十六引脚；第十六引脚同时连接第八二极管(D8)的正极和第四十八电容的一端，所述第八二极管的负极和第四十八电容的另一端并联连接第十八引脚；第十八引脚同时连接第九二极管(D9)的正极和第四十九电容的一端，所述第九二极管的负极和第四十九电容的另一端并联连接第二十引脚；第二十引脚同时连接第十二极管(D10)的正极和第五十电容的一端，所述第十二极管的负极和第五十电容的另一端并联连接第二十二引脚；第二十二引脚同时连接第十一二极管(D11)的正极和第五十一电容的一端，所述第十一电容的负极和第五十一电容的另一端并联连接第二十四引脚；第二十四引脚同时连接第十二二极管(D12)的正极和第五十二电容的一端，所述第十二二极管的负极和第五十二电容的另一端并联连接第二十六引脚。
而诸如电源输入、晶振和程序下载口等控制芯片常用的配套电路，因其属于常规技术，因此不再添加额外的附图对其电路进行说明。
进一步地，所述均匀恒控制模块内还包括第一电压转换模块，用于将自供电模块输出的5V直流工作电源转换为24V的工作电源为均衡控制模块提供合适的工作电源，其输入端连接自供电模块的直流工作电源输出端，其输出端连接第十三控制芯片的第一引脚。因电源转换模块属于常规技术，因此，本实施例不再对其具体连接方式进行详细说明，如有疑问，参考图4。
继续上文所述的主控模块，为了实现均衡控制模块和主控模块之间的信号通讯，本实施例采用SPI通讯的方式，包括第十二控制芯片(U12，芯片型号为ADUM2401)，含有第一至第十六引脚，其中第十一至第十四引脚分别连接第十三控制芯片(U13)的第四十四、第四十一、第四十三和第四十二引脚，第三至第六引脚分别连接第一控制芯片(U1)的第二十一、第二十三、第二十和第二十二引脚，其具体连接方式参考图5和图6。
而为了实现主控模块与外部设备的数据传输，本实施例还包括CAN通讯模块，用于将主控模块的运行数据(各电容单体的电势数据、报警信号等)传输给外部设备，同时也可接收外部设备发送的控制信号。其包括第五芯片(U5，芯片型号为TD301DCAN)，包括第一至第八引脚，其第四引脚(即输入端)通过第三十一电阻(R31)连接第一控制芯片(U1)的第四十一引脚， 其三引脚(即输出端)通过第三十二电阻(R32)连接第一控制芯片(U1)的第四十六引脚，其具体电路参考图6和图7。而主控模块中第一控制芯片其它引脚的电路连接方式，因其属于常规电路连接方式，本实施例不再详细说明，具体参考附图6。
同时，还包括第二电压转换模块，用于将将自供电模块输出的5V直流工作电源转换为3.3V的工作电源，为主控模块和CAN通讯模块提供工作电源，其输入端接自供电模块的直流工作电源输出端，输出端输出3.3V的工作电压，引起属于常规电路连接方式，因此本实施例不再对其连接方式进行详细描述，其具体的连接方式可以参考图6、图7和图8。
进一步地，为了配合所配置的六个电容单体，本实施例中均衡模块含有第一至第六均衡单元，其中个均衡单元的连接方式如图9所示，包括：
第一场效应管(Q1A)，所述第一场效应管的栅极通过第九十四电阻(R94)作为第二控制信号输入端，并同时连接第九十五电阻(R95)的一端和第一稳压二极管(ZA1)的负极，所述第九十五电阻的另一端和第一稳压二极管的正极并联连接第一场效应管的源极；所述第一场效应管的源极作为第二端口；所述场效应管的漏极顺序连接第一均衡电阻(R1A)和第二均衡电阻(R2A)作为第一端口。
其中，各均衡单元的连接方式具体为：
第一均衡单元的第一端口连接第七RL串联电路的电感端，第二端口连接第六RL串联电路的电感端；第二均衡单元的第一端口连接第六RL串联电路的电感端，第二端口连接第五RL串联电路的电感端；第三均衡单元的第一端口连接第五RL串联电路的电感端，第二端口连接第四RL串联电路的电感端；第四均衡单元的第一端口连接第四RL串联电路的电感端，第二端口连接第三RL串联电路的电感端；第五均衡单元的第一端口连接第三RL串联电路的电感端，第二端口连接第二RL串联电路的电感端；第六均衡单元的第一端口连接第二RL串联电路电感端，第二端口连接第一RL串联电路的电感端。
当均衡模块通过第二控制信号输入端接收到均衡控制模块发送的第二控制信号时，根据控制信号调节第一场效应管的导通状态，利用第一和第二均衡电阻消耗掉电容单体中各电容单体均衡线(电容单体中电势最低的作为均衡线)以上的电能，从而达到断电状态下，各电容单体的电势平衡。
本实施例所述的一种超级电容无源CMS均衡电路，采取当超级电容组外部供电停止时，利用超级电容组自身存储的电能作为均衡电路的电源，保证超级电容在断电的情况下仍能够自供 电维持均衡电路的运转，避免因为断电，导致的均压状态破坏引起的电容损耗；同时，超级电容组再次上电后，无需花费额外的时间去等待各电容单体实现均压工作，大大提高了依托与超级电容组工作的机器的运行效率。
实时例二
为了更清楚的对本发明的核心内容进行理解，本实施例通过方法步骤的形式对发明点进行简单的描述，一种超级电容无源CMS均衡方法：
S1：外部控制电断电，将超级电容组的输出电压作为直流电源；
S2：利用自供电模块将直流电源转换为预设安全阀值下的直流工作电源，为其它模块供电；
S3：通过采样模块采集各电容单体的实时电压；
S4：将实时电压通过均衡控制模块转换为实时采样信号；
S5：根据实时采样信号利用主控模块生成第一控制信号；
S6：根据第一控制信号，通过均衡控制模块生成第二控制信号控制均衡模块调节各电容单体的电压平衡。
综合上述实施例，本发明所述的一种超级电容无源CMS均衡电路与方法，采取当超级电容组外部供电停止时，利用超级电容组自身存储的电能作为均衡电路的电源，保证超级电容在断电的情况下仍能够保持均压状态，避免因为断电，导致的均压状态破坏引起的电容损耗。因此，在超级电容组再次上电后，无需花费额外的时间去等待各电容单体实现均压工作，大大提高了依托于超级电容组工作的机器的运行效率。
自供电模块中采用三极管K2与各电容、电阻与二极管的配合，保证自供电模块的输出电压不超过预设安全阀值，确保了电路运行的安全性和可靠性；同时采用模块化设计，可以在电路板上将各模块进行相对独立的布置，可以消除或抑制绝大部分的干扰，增强了电路的稳定性。
本文中所描述的具体实施例仅是对本发明精神作举例说明。本发明所属技术领域的技术人员可以对所描述的具体实施例做各种各样的修改或补充或采用类似的方式替代，但并不会偏离本发明的精神或者超越所附权利要求书所定义的范围。

Claims (8)

  1. 一种基于超级电容无源CMS均衡电路，其特征在于，包括超级电容组、自供电模块、采样模块、均衡控制模块、主控模块和均衡模块，其中：
    超级电容组，包括多个电容单体，用于在外部控制电断电时，为均衡电路提供直流电源；
    自供电模块，用于将直流电源转换为预设安全阀值下的直流工作电源，为其他模块提供工作电源；
    采样模块，用于采集各电容单体的实时电压；
    均衡控制模块，用于将实时电压转换为实时采样信号；
    主控模块，用于根据实时采样信号，生成第一控制信号并发送至均衡控制模块生成第二控制信号；
    均衡模块，用于根据第二控制信号通过电阻调节各电容单体的电压平衡。
  2. 如权利要求1所述的一种超级电容无源CMS均衡电路，其特征在于，所述自供电模块，包括：
    第一开关(S1)，所述第一开关一端接超级电容组正极输出端，另一端连接第一熔断器(FA1)，所述第一熔断器的另一端连接第一热敏电阻(RTA1)；所述第一热敏电阻的另一端同时连接第二十电阻(R20)、第一瞬态抑制二极管(D1)、第二十一电容(C21)，所述第二十电阻、第一瞬态抑制二极管和第二十一电容的另一端并联连接超级电容组的负极输出端；
    第一电感(L1)，包括第一至第四引脚，所述第一电感的第一引脚连接超级电容组的负极输出端；所述中第一电感的第二引脚通过第一热敏电阻连接第一熔断器；所述第一电感的第三引脚同时连接第二十二至第二十四电容(C22-C24)的一端，所述第二十二至第二十四电容的另一端并联连接第一电感的第四引脚；所述第一电感的第四引脚接地；
    第九电源芯片(U9),包括第一至第三引脚，所述第九电源芯片的第一引脚连接第一电感的第三引脚；所述第九电源芯片的第二引脚同时连接第一电感的第四引脚和第二十二电阻(R22)的一端；所述第九电源芯片的第三引脚连接第二十一电阻(R21)的一端；
    第一三极管(Q1)，所述第二十一和第二十二电阻的另一端并联连接第二二极管(D2)的正极，所述第二二极管的负极同时连接第二十三电阻(R23)的一端和第一三极管的基极；所述第二十三电阻的另一端和第一三极管的发射极并联连接第一电感的第四引脚；所述第一三极管的集电极通过第二十五电阻(R25)同时连接第九电源芯片的第三引脚和第二晶体管(K2)的源极，所述第二晶体管的原题还顺序通过第二十七电阻(R27)和第二十六电容(C26)连接第二晶体管的漏极；所述第二晶体管的栅极同时连接第四二极管(D4)的负极和第二十八电阻(R28)的一端，所述第四二极管和第二十八电阻的另一端并联接连第二晶体管的源极；所述第二晶体管的漏极作为自供电模块的直流工作电源输出端；
    第二三极管(Q2)，所述第二三极管的基极同时连接第二十六电阻(R26)的一端和第三二级管的负极，所述第三二极管的正极连接第一二极管的集电极，所述第二十六电阻的另一端和第二三管的发射极并联连接第一电感的第四引脚，所述第二三极管的集电极连接第二晶体管的栅极。
  3. 如权利要求1所述的一种超级电容无源CMS均衡电路，其特征在于，所述多个电容单体包括第四十七至第五十二电容(C47-C52)六个电容单体；所述均衡控制模块包括第十三控制芯片(U13)，包含第一至第四十八引脚；所述主控模块包括第一控制芯片(U1)，包含第一至第六十四引脚。
  4. 如权利要求3所述的一种超级电容无源CMS均衡电路，其特征在于，所述采样模块，包括：
    第八至第十四电感(L8-L14)，和第四十八电阻至第五十四电阻(R48-R54)，并顺序两两串联组成第一至第七RL串联电路；所述第一RL串联电路电阻端连接第十三控制芯片的第十四引脚，第二RL串联电路电阻端连接第十三控制芯片的第十六引脚，第三RL串联电路电阻端连接第十三控制芯片的第十八引脚，第四RL串联电路电阻端连接第十三控制芯片的的二十引脚，第五RL串联电路电阻端连接第十三控制芯片的第二十二引脚，第六RL串联电路电阻端连接第十三控制芯片的第二十四引脚，第七RL串联电路电阻端连接第十三控制芯片的第二十六 引脚；所述第一RL串联电路的电感端通过第七十九电阻(R79)分别连接第十三控制芯片的第二、第四、第六、第八、第十和第十二引脚；所述第七RL串联电路的电感端通过第五十五电阻(R55)分别接地和第七十三电容(C73)的一端，第七十三电容的另一端接第十三控制芯片的第二十六引脚；
    所述第十三控制芯片的第十四引脚同时连接第七二极管(D7)的正极和第四十七电容的一端，所述第七二极管的负极和第四十七电容的另一端并联连接第十六引脚；第十六引脚同时连接第八二极管(D8)的正极和第四十八电容的一端，所述第八二极管的负极和第四十八电容的另一端并联连接第十八引脚；第十八引脚同时连接第九二极管(D9)的正极和第四十九电容的一端，所述第九二极管的负极和第四十九电容的另一端并联连接第二十引脚；第二十引脚同时连接第十二极管(D10)的正极和第五十电容的一端，所述第十二极管的负极和第五十电容的另一端并联连接第二十二引脚；第二十二引脚同时连接第十一二极管(D11)的正极和第五十一电容的一端，所述第十一电容的负极和第五十一电容的另一端并联连接第二十四引脚；第二十四引脚同时连接第十二二极管(D12)的正极和第五十二电容的一端，所述第十二二极管的负极和第五十二电容的另一端并联连接第二十六引脚。
  5. 如权力要求3或4所述的任意一种超级电容无源CMS均衡电路，其特征在于，所述均衡模块包括第一至第六均衡单元，其中各均衡单元包括：
    第一场效应管(Q1A)，所述第一场效应管的栅极通过第九十四电阻(R94)作为第二控制信号输入端，并同时连接第九十五电阻(R95)的一端和第一稳压二极管(ZA1)的负极，所述第九十五电阻的另一端和第一稳压二极管的正极并联连接第一场效应管的源极；所述第一场效应管的源极作为第二端口；所述场效应管的漏极顺序连接第一均衡电阻(R1A)和第二均衡电阻(R2A)作为第一端口。
  6. 如权利要求5所述的一种超级电容无源CMS均衡电路，其特征在于，所述：第一均衡单元的第一端口连接第七RL串联电路的电感端，第二端口连接第六RL串联电路的电感端；第二均衡单元的第一端口连接第六RL串联电路的电感 端，第二端口连接第五RL串联电路的电感端；第三均衡单元的第一端口连接第五RL串联电路的电感端，第二端口连接第四RL串联电路的电感端；第四均衡单元的第一端口连接第四RL串联电路的电感端，第二端口连接第三RL串联电路的电感端；第五均衡单元的第一端口连接第三RL串联电路的电感端，第二端口连接第二RL串联电路的电感端；第六均衡单元的第一端口连接第二RL串联电路电感端，第二端口连接第一RL串联电路的电感端。
  7. 如权利要求1所述的一种超级电容无源CMS均衡电路，其特征在于，还包括SPI模块和CAN通讯模块，其中：
    SPI模块，用于均衡控制模块和主控模块之间的信号通讯；
    CAN通讯模块，用于主控模块与外部设备的信号通讯。
  8. 一种超级电容无源CMS均衡方法，其特征在于，包括超级电容组、自供电模块、采样模块、均衡控制模块、主控模块和均衡模块，包括步骤：
    S1：外部控制电断电，将超级电容组的输出电压作为直流电源；
    S2：利用自供电模块将直流电源转换为预设安全阀值下的直流工作电源，为其它模块供电；
    S3：通过采样模块采集各电容单体的实时电压；
    S4：将实时电压通过均衡控制模块转换为实时采样信号；
    S5：根据实时采样信号利用主控模块生成第一控制信号；
    S6：根据第一控制信号，通过均衡控制模块生成第二控制信号控制均衡模块调节各电容单体的电压平衡。
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