WO2021227310A1

WO2021227310A1 - Novel distributed array and contact architecture for 4 stack 3d x-point memory

Info

Publication number: WO2021227310A1
Application number: PCT/CN2020/113459
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-05-12
Filing date: 2020-09-04
Publication date: 2021-11-18
Also published as: CN111758171B; WO2021226816A1; CN111758171A

Abstract

A three-dimensional memory includes a bottom cell layer of memory cells, a top cell layer of memory cells, and at least one middle cell layer of memory cells. The bottom cell layer is coupled to bottom cell bit lines, bottom cell bit line decoders, bottom cell word lines, and bottom cell word line decoders. The middle cell layers are coupled to middle cell bit lines, middle cell bit line decoders, either the bottom or middle cell word lines, and either the bottom or middle cell word line decoders. The top cell layer is coupled to top cell bit lines, bottom cell bit line decoders, middle cell word lines, and middle cell word line decoders. The bit line decoders may be arranged in subsections that are offset in a vertical direction. The word line decoders may be arranged in subsections that are offset in a horizontal direction.

Description

[Title established by the ISA under Rule 37.2] NOVEL DISTRIBUTED ARRAY AND CONTACT ARCHITECTURE FOR 4 STACK 3D X-POINT MEMORY

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the density of memory cells in three-dimensional crosspoint (X-point) memories.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. There is still a need for a three-dimensional (3D) memory architecture that can address the density limitation in planar memory cells.

SUMMARY

The presently disclosed three-dimensional memory and method solves the problems of current state of the art, and provides many more benefits. In accordance with an aspect, disclosed and shown is a distributed array and contact architecture for a 4 stack 3D crosspoint memory. Top cell bit line contacts are landing on bottom cell bit line contacts to be electrically in contact on pitch. Middle cell bit line contacts are in between bottom cell array blocks. Bottom cell word line contacts are located in the middle of bottom cell word lines, and in the middle of bit line arrays. Middle cell word line contacts are located in the middle of bottom cell word lines, and in the middle of bit line arrays, and between two adjacent bottom cell word line arrays. All bit line and word line decoder blocks are arranged in a checkboard distributed pattern to maximize bit density. As a result the array efficiency is greatly improved compared to the current state of the art systems.

In another aspect, a plurality of memory cell layers are stacked in a depth direction. A plurality of bit lines are coupled to the plurality of memory cell layers. A plurality of word lines are coupled to the plurality of memory cell layers. A plurality of bit line decoders are coupled to the plurality of bit lines and operable to selectively activate the plurality of bit lines. A plurality of word line decoders are coupled to the plurality of word lines and operable to selectively activate the plurality of word lines. The bit line decoders are arranged in bit line decoder subsections that are offset in a vertical direction. The word line decoders are arranged in word line decoder subsections that are offset in a horizontal direction.

In still another aspect, a method of forming a three-dimensional memory comprises providing a plurality of memory cell layers stacked in a depth direction; providing a plurality of bit lines coupled to the plurality of memory cell layers; providing a plurality of word lines coupled to the plurality of memory cell layers; providing a plurality of bit line decoders coupled to the plurality of bit lines and operable to selectively activate the plurality of bit lines; providing a plurality of word line decoders coupled to the plurality of word lines and operable to selectively activate the plurality of word lines; forming the bit line decoders in bit line decoder subsections that are offset in a vertical direction; and forming the word line decoders in word line decoder subsections that are offset in a horizontal direction.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

FIG. 1 is an isometric view of a section of three-dimensional crosspoint memory.

FIG. 2 is a plan view of section of a prior three-dimensional crosspoint memory.

FIGS. 3A and 3B are plan views of a section of prior three-dimensional crosspoint memory.

FIGS. 4A and 4B are cross-sectional views of a section of three-dimensional crosspoint memory according to an embodiment.

FIGS. 5A and 5B are plan views of a section of three-dimensional crosspoint memory according to the embodiment of FIGS. 4A and 4B.

FIGS. 6A and 6B are plan views of a section of three-dimensional crosspoint memory according to the embodiment of FIGS. 4A and 4B.

FIG. 7 is a plan view of a section of three-dimensional crosspoint memory according to the embodiment of FIGS. 4A and 4B.

FIG. 8 is a plan view of a section of three-dimensional crosspoint memory according to the embodiment of FIGS. 4A and 4B.

DETAILED DESCRIPTION

The present technology is applied in the field of three-dimensional memory. A generalized example of a three-dimensional (3D) memory is shown in FIG. 1. In particular, FIG. 1 is an isometric view of a section of three-dimensional crosspoint memory. The memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and the second layer of memory cells 10 is a number of word lines 15 extending in a horizontal (X) direction. Above the first layer of memory cells 5 in a depth (Z) direction is a number of first bit lines 20 extending along a vertical (Y) direction, and below the second layer of memory cells 10 is a number of second bit lines 25 extending along the Y direction.

Further as shown in FIG. 1, the sequential structure of bit line, memory cell, word line, memory cell may be repeated along the Z direction to create a stacked configuration. In the example of FIG. 1, a first layer of the stack may include the first layer of memory cells 5, bit lines 20, and word lines 15, while a second layer of the stack may include the second layer of memory cells 10, the bit lines 25, and word lines 15. Thus, while the first layer of memory cells 5 and the second layer of memory cells 10 each have its respective set of

bit lines

20 and 25, the first layer of memory cells 5 and the second layer of memory cells 10 may share a same set of word lines 15. Although the example of FIG. 1 shows a 4-layer stack configuration, in other examples, the stacked configuration may include any number of memory cell layers and other elements. In any event, an individual memory cell in the structure may be accessed by selectively activating the word line and bit line corresponding to the cell.

In order to selectively activate the word lines and bit lines, the memory includes word line decoders and bit line decoders (not shown) . The word line decoders are coupled to the word lines by word line contacts (not shown) and are used to decode word line addresses such that a particular word line is activated when it is addressed. Similarly, the bit line decoders are coupled to the bit lines by bit line contacts (not shown) and are used to decode bit line addresses such that a particular bit line is activated when it is addressed. Thus, the stack configuration of memory may further include bit line contacts and decoders, and word line contacts and decoders for selectively activating the bit lines and word lines in the stack. For instance, the stack configuration may be arranged as arrays of elements, where each array may include a set of memory cells, and corresponding sets of bit lines, word lines, bit line and word line contacts, and bit line and word line decoders. The positioning of the word line decoders and contacts, and the bit line decoders and contacts of a prior configuration are shown and discussed further in reference to FIG. 2.

FIG. 2 is a plan view of section of three-dimensional crosspoint memory of a prior configuration. The figure depicts the section as viewed along the Z (depth) direction. In this example, the stacked configuration is a 2-layer stack. The stacked configuration includes multiple arrays of memory cells, including two

top cell arrays

60 and 61 and two

bottom cell array

65 and 66. Although individual memory cells are not shown in FIG. 2, they are illustrated by FIG. 1, for example in the top arrays the memory cells may be arranged as the first layer of memory cells 5 shown in FIG. 1 and in the bottom arrays the memory cells may be arranged as the second layer of memory cells 10 shown in FIG. 1.

The section includes word lines and bit lines, word line and bit line contacts, and word line and bit line decoders corresponding to the top cells and bottom cells. As shown, a number of word lines, e.g. word lines 30, extend in the X (horizontal) direction and corresponding to both the top cells and bottom cells. The section further includes a number of top cell bit lines, e.g., bit lines 35, extending along the Y (vertical) direction and corresponding to the top cell array of memory cells 60, and a number of bottom cell bit lines, e.g., bit lines 40, extending along the vertical direction and corresponding to the bottom cell array of memory cells 65. The word lines, top cell bit lines, and bottom cell bit lines are typically formed of a 20 nm /20 nm Line /Space (L/S) pattern and are formed on a silicon substrate. Moreover, the memory may employ complementary metal-oxide semiconductor (CMOS) technology.

The word lines in FIG. 2 are horizontally aligned for a given cell array. For instance as shown, word lines for

cell arrays

60, 61, 65, and 66 are all horizontally aligned with one another along the X direction. Each of these word lines are shown extending across an entire width of the respective cell arrays. Top cell bit lines for a given top cell array and bottom cell bit lines for a given bottom cell array are vertically aligned. For instance, top cell bit lines 35 are vertically aligned along the Y direction, and bottom cell bit lines 40 are vertically aligned along the Y direction. The top cell bit lines of a top cell array and bottom cell bit lines of an overlapping bottom cell array, such as top cell bit lines 35 and bottom cell bit lines 40, are also horizontally aligned with one another, although they are shown in FIG. 2 as slightly offset in order to clearly show both layers. Each of these bit lines are shown extending across an entire length of the respective cell arrays.

The memory section of FIG. 2 includes a word line contact area 45, a top cell bit line contact area 50, and a bottom cell bit line contact area 55. The word line contact area 45 is elongated along the vertical direction, while the top cell bit line contact area 50 and bottom cell contact area 55 are elongated along the horizontal direction. The word line contact area 45 includes a multiple of word line contacts, e.g., contact 45a, shown as dots enclosed by the word line contact area 45. The top cell bit line contact area 50 includes a multiple of word line contacts, e.g., contact 50a, shown as dots enclosed by top cell bit line contact area 50. The bottom cell bit line contact area 55 includes a multiple of bottom cell bit line contacts, e.g., contact 55a, shown as dots enclosed by bottom cell bit line contact area 55.

The word line contacts and bit line contacts are connected to the middle of the respective word lines and bit lines. Thus as shown, word line contact area 45 is positioned in the horizontal middle of word lines 40, bottom cell bit line contact area 55 is positioned in the vertical middle of the bottom cell bit lines 40, and top cell bit line contact area 50 is positioned in the vertical middle of the top cell bit lines 35. Since the word lines for a given cell array are horizontally aligned, the word line contacts for a given cell array are also substantially aligned in the horizontal direction. Likewise, since the bit lines for a given cell array are vertically aligned, the bit line contacts for a given cell array are also substantially aligned in the vertical direction.

The word line contact area 45 also includes a multiple of word line decoders (not shown) . The word line decoders generally conform to the word line contact area and generally extend along the vertical direction. The word line decoders couple to the word lines through the word line contacts. For instance, the word line contacts may extend from a plane of the word lines to a plane below in the depth direction where the word line decoders are provided. The top cell bit line contact area 50 also includes a multiple of top cell bit line decoders (not shown) . The top cell bit line decoders generally conform to the top cell bit line contact area 50 and generally extend along the horizontal direction. The top cell bit line decoders couple to the top cell bit lines through the top cell bit line contacts. For instance, the top cell bit line contacts may extend from a plane of the top cell bit lines to a plane below in the depth direction where the top cell bit line decoders are provided. The bottom cell bit line contact area 55 also includes a multiple of bottom cell bit line decoders (not shown) . The bottom cell bit line decoders generally conform to the bottom cell bit line contact area 55 and generally extend along the horizontal direction. The bottom cell bit line decoders couple to the bottom cell bit lines through the bottom cell bit line contacts. For instance, the bottom cell bit line contacts may extend from a plane of the bottom cell bit lines to a plane below in the depth direction where the bottom cell bit line decoders are provided. The word line decoders, and top and bottom cell bit line decoders may be provided in a plane below the stacks of memory cells, bit lines, and word lines, in the depth direction.

It has been recognized by the developers of the present technology that the prior configuration as exemplified in FIG. 2 is inefficient in its use of memory real estate, and that other configurations can provide improved memory cell density and bit line density. One drawback of the prior configuration is related to the number of stacks in the architecture, which includes only two layers of memory cells. Another drawback of the prior configuration are related to the arrangement of the word line decoders. As can be seen from FIG. 2, the word line contact area 45, and accordingly the word line contacts and word line decoders, are arranged along the horizontal middle of the memory structure. For instance as shown, the word line contacts 45 and word line decoders are arranged along the horizontal middle of the top and bottom arrays of memory cells 60 and 65 (but may extend to a different depth in Z direction) . This is also true for other arrays in the memory, such as top cell array 61 and bottom cell array 66, where a word line contact area also occupies the horizontal middle of these arrays. The decoders are arranged as such because, as described above, within a given array, the word lines are horizontally aligned, and the bit lines are vertically aligned. Thus, if the 2-layer stack shown in FIG. 2 is simply duplicated into a 4-layer stack, such a configuration would introduce the same inefficiencies to the additional layers. Such configuration and its drawbacks are shown and discussed further in reference to FIGS. 3A and 3B.

FIG. 3A is a plan view of a section of a prior three-dimensional crosspoint memory. The figure depicts the section as viewed along the depth or Z direction. This example is a 2-layer stack configuration. The figure shows a multiple of bottom cell arrays including bottom cell array 60 extending from a first edge or top edge 75 to a second edge or bottom edge 80, and a multiple of top cell arrays, including a top cell array 65 extending from a first edge or top edge 76 to a second edge or bottom edge 81. FIG. 3B is the same plan view as FIG. 3A with the exception that the markings denoting the bottom cell array 60 and the top cell array 65 have been removed. For purposes of clarity of presentation FIGS. 3A and 3B will be discussed only with respect to the portions pertaining to the bottom cell array 60 and the top cell array 65, with the understanding that such discussion can be readily applied to the other parts of the figures. Also, it should be noted the figures show only the word line decoders, top cell bit line decoders, and bottom cell bit line decoders, and does not show the other parts of the memory.

Referring to FIGS. 3A and 3B, it can be seen that the memory section includes a set of word line decoders 70 that is arranged in a contiguous vertical stripe of area extending along the Y direction from the top edge 75 of the bottom cell array 60 to the bottom edge 80 of the bottom cell array 60. The memory section also includes a set of top cell bit line decoders 85 of the top cell array 65 that is split into two

portions

85a and 85b along the horizontal or X direction and which are vertically aligned, and a set of bottom cell bit line decoders 90 of the bottom cell array 60 that are split into two

portions

90a and 90b along the horizontal or X direction which are vertically aligned. Therefore as shown in FIG. 3A and 3B, the bit line and word line decoders are arranged symmetrically in the memory structure. This is because, as describe in relation to FIG. 2, the word lines are horizontally aligned within a given array, and the bit lines are vertically aligned within a given array. This prior configuration shown in FIGS. 3A and 3B thus dedicates a vertical stripe of the memory area to word line contacts and word line decoders, which does not include any bit lines or memory cells for data storage, thereby limiting the efficiency of the memory. Further as mentioned above, this dedicated stripe may extend along the depth direction to multiple layers, thereby introducing more inefficiencies.

The developers of the present technology have recognized the drawbacks arising from the prior configuration and provide the present technology in light of such drawbacks. The present technology is a memory structure including more than two layers of memory cells, with various elements provided at offset positions to optimize use of memory real estate.

FIGS. 4A and 4B are cross-sectional views of a section of three-dimensional crosspoint memory according to an embodiment. It should be noted that, for clarity of presentation, FIGS. 4A and 4B illustrate only some elements of the memory. Other elements are further described with reference to other figures. The architecture includes more than two layers of memory cells arranged in a stack configuration along the depth (Z) direction. Although in the example shown, the architecture includes four layers of memory cells, in other examples the architecture may include fewer or more layers of memory cells, including multiples of the architecture stacked on top of one another. As shown, a bottom cell layer 100 of memory cells are positioned at the bottom (in depth direction) of this four-layer stack. A first middle cell layer 200 of memory cells are positioned above the bottom cell layer 100 in the stack. Then, a second middle cell layer 300 of memory cells are positioned above the first middle cell layer 200 in the stack. Finally a top cell layer 400 of memory cells are positioned above the second middle cell layer 300 in the stack.

To access any individual cell within the four cell layers, bit lines and word lines are provided. In the architecture, at least some of the bit lines and word lines are arranged in portions that are offset from one another. Such offsets may allow dedicated areas for decoders to be avoided, which increases efficiency.

FIG. 4A illustrates an example arrangement of bit lines in the architecture. As shown, bottom cell bit lines, such as bottom cell bit lines 110, are provided below the bottom cell layer 100 in the depth direction. Top cell bit lines, such as top cell bit lines 410, are provided above the top cell layer 400. Middle cell bit lines, such as middle cell bit lines 210, are provided between the first middle cell layer 200 and the second middle cell layer 300. Because the middle cell bit lines 210 may be in contact with both the memory cells in the first middle cell layer 200 and the memory cells in the second middle cell layer 300, the middle cell bit lines 210 may be shared by the first middle cell layer 200 and the second middle cell layer 300. Further as shown, the bottom cell bit lines 110 and the top cell bit lines 410 are aligned along a vertical or Y direction. However, the bottom cell bit lines 110 and the top cell bit lines 410 are offset from the middle cell bit line 210 along the vertical or Y direction. The vertical offset may be a predetermined distance, such as a fraction of a length of the bit lines. In this particular example, the offset is about half of the length of the bit lines.

Bit line contacts in the architecture are also illustrated in FIG. 4A. For instance, bottom cell bit line contacts, such as bottom cell bit line contacts 120, are operable to connect the bottom cell bit lines to bit line decoders (not shown) . For instance, bottom cell bit line contacts 120 may connect to a vertical middle of respective bottom cell bit lines 110. Middle cell bit line contacts, such as middle cell bit line contacts 220, are operable to connect the middle cell bit lines to bit line decoders (not shown) . For instance, middle cell bit line contacts 220 may connect to a vertical middle of respective middle cell bit lines 210. Top cell bit line contacts, such as top cell bit line contacts 420, are operable to connect the top cell bit lines to bit line decoders (not shown) . For instance, top cell bit line contacts 420 may connect to a vertical middle of the respective top cell bit lines 410.

Due to the vertical offsets between the bit lines, the bit line contacts may be positioned in the spacing between the offset bit lines. For instance, middle cell bit line contacts 220 may be positioned between the bottom cell bit lines 110 and the adjacent bottom cell bit lines along the vertical or Y direction. This allows the bit line decoders for the middle cell bit lines to be arranged in different areas as the bit line decoders for the bottom and/or top cell bit lines. For instance, where the middle cell bit line decoders are provided in a plane below the bottom cell bit lines in the depth direction, the middle cell bit line contacts 220 may extend in the depth direction from the plane of the middle cell bit lines 210, through the spacing between the bottom cell bit lines 110 and the vertically adjacent bottom cell bit lines, to reach the middle cell bit line decoders below the bottom cell bit lines 110. Further, because the bottom cell bit lines 110 and the top cell bit lines 410 are aligned with one another, and because the top cell bit lines 110 and the middle cell bit lines 220 are offset from one another, the top cell bit line contacts 420 may connect to the bottom cell bit line contacts 110. For instance, the top cell bit line contacts 420 may extend in a depth direction from a plane of the top cell bit lines 410, through spacing between the middle cell bit lines 210 and the vertically adjacent middle cell bit lines, to connect with the bottom cell bit line contacts 220. As such, the bottom cell bit lines 110 and the top cell bit lines 410 may share a same set of bit line decoders (not shown) .

FIG. 4B illustrates an example arrangement of word lines in the architecture. As shown, bottom cell word lines, such as bottom cell word lines 150, are provided between the bottom cell layer 100 and the first middle cell layer 200. Middle cell word lines, such as middle cell word lines 250, are provided between the second middle cell layer 300 and the top cell layer 400. Because the bottom cell word lines 210 may be in contact with both memory cells in the bottom cell layer 100 and memory cells in the first middle cell layer 200, the middle cell word lines 250 may be shared by the bottom cell layer 100 and the first middle cell layer 200. Likewise, because the middle cell word lines 250 may be in contact with both memory cells in the first middle cell layer 200 and memory cells in the second middle cell layer 300, the middle cell word lines 250 may be shared by the first middle cell layer 200 and the second middle cell layer 300. Further as shown, the bottom cell word lines 150 and the middle cell word lines 250 are offset along a horizontal or X direction. The horizontal offset may be a predetermined distance, such as a fraction of a length of the word lines. In this particular example, the offset is about half of the length of the word lines.

Word line contacts in the architecture are also illustrated in FIG. 4B. For instance, bottom cell word line contacts, such as bottom cell word line contacts 160, are operable to connect the bottom cell word lines 150 to word line decoders (not shown) . For instance, bottom cell word line contacts 160 may connect to a horizontal middle of respective bottom cell word lines 150. Middle cell word line contacts, such as middle cell word line contacts 250, are operable to connect the middle cell word lines 250 to word line decoders (not shown) . For instance, middle cell word line contacts 260 may connect to a horizontal middle of respective middle cell word lines 250.

Due to the horizontal offsets between the word lines, word line contacts may be positioned in the spacing between the offset word lines. As shown, because the bottom cell word lines 150 and the middle cell word lines 250 are offset from one another, the middle cell word line contacts 260 may be positioned in the spacing between bottom cell word lines 150 and the adjacent word lines along the horizontal or X direction. This allows the word line decoders for the middle cell word lines to be arranged in different sections as the word line decoders for the bottom cell word lines. For instance, where the middle cell word line decoders are provided in a plane below the bottom cell word lines in the depth direction, the middle cell word line contacts 260 may extend in the depth direction from the plane of the middle cell word lines 250, through the spacing between the bottom cell word lines 150 and the horizontally adjacent bottom cell word lines, to reach the middle cell word line decoders below the bottom cell word lines 110. Further, because the bottom cell layer 100 and the first middle cell layer 200 share the same set of word lines, they may share the same set of word line contacts and/or word line decoders. Likewise, because the first middle cell layer 300 and the top cell layer 400 share the same set of word lines, they may share the same set of word line contacts and/or word line decoders.

FIGS. 5A and 5B are plan views of a section of three-dimensional crosspoint memory according to the embodiment of FIGS. 4A and 4B. It should be noted that, for clarity of presentation, FIGS. 5A and 5B illustrate only some elements of the memory. Other elements are further described with reference to other figures. FIGS. 5A and 5B are provided to further illustrate the arrangement of bit lines and bit line decoders for the architecture. In particular, FIGS. 5A and 5B show the same plan view, with the exception that the markings highlight different elements.

FIG. 5A illustrates an example arrangement of bottom cell bit lines and bottom cell bit line decoders. As described above with reference to FIG. 4A, the bottom cell bit lines are vertically offset from the middle cell bit lines. FIG. 5A further shows that, the bottom cell bit lines may be arranged also with offsets among themselves. Thus as shown, the bottom cell bit lines are arranged in portions that are offset from each other along the vertical or Y direction. For example, a first portion of bottom cell bit lines 110a are vertically offset from a second portion of bottom cell bit lines 110b. Further as shown, the first portion of bottom cell bit lines 110a are vertically aligned with a third portion of bottom cell bit lines 110c. The vertical offset may be a predetermined distance, such as a fraction of a length of the bit lines. In this particular example, the offset is less than half of the length of the bit lines. Although the example shows every other portion of bit lines as having the same vertical offset, resulting in a zig-zagging pattern, in other examples the offsets may form another pattern, such as every third portion having the same offset, every fourth portion having the same offset, or some random pattern.

Bottom cell bit line decoders are shown provided for each portion of bottom cell bit lines. For instance, a first set of bottom cell bit line decoders may be provided in a first bottom cell bit line decoder subsection 140a for activating the first portion of bottom cell bit lines 110a, a second set of bottom cell bit line decoders may be provided in a second bottom cell bit line decoder subsection 140b for activating the second portion of bottom cell bit lines 110b, a third set of bottom cell bit line decoders may be provided in a third bottom cell bit line decoder subsection 140c for activating the third portion of bottom cell bit lines 110c. Since the bottom cell bit lines are arranged in portions that are offset, bottom cell bit line decoders may also be arranged in subsections that are offset. For instance as shown, the first bottom cell bit line decoder subsection 140a is vertically offset from the second bottom cell bit line decoder subsection 140b. However, the first bottom cell bit line decoder subsection 140a is vertically aligned with the third bottom cell bit line decoder subsection 140c. The vertical offset may be a predetermined distance, such as a fraction of a length of the bit lines. In this particular example, the offset is less than half of the length of the bit lines. Although the example shows every other portion of bit lines as having the same vertical offset, resulting in a checker-board like pattern, in other examples the offsets may form another pattern, such as every third portion having the same offset, every fourth portion having the same offset, or some random pattern.

As described above with respect to FIG. 4A, top cell bit lines may be arranged in the same manner as the bottom cell bit lines, with exception that the top cell bit lines are positioned along a different depth plane in Z direction. Further as described above, top cell bit lines may share the same bit line decoders as the bottom cell bit lines. Thus, the top cell bit lines may be arranged in the same manner with respect to the bottom cell bit line decoders as the bottom cell bit lines shown in FIG. 5A.

FIG. 5B illustrates an example arrangement of middle cell bit lines and middle cell bit line decoders. As described above with reference to FIG. 4A, the middle cell bit lines are vertically offset from the bottom and/or top cell bit lines. FIG. 5B further shows that, the middle cell bit lines are also offset among themselves. Thus as shown, the middle cell bit lines are arranged in portions that are offset from each other along the vertical or Y direction. For example, a first portion of middle cell bit lines 210a are vertically offset from a second portion of middle cell bit lines 210b. Further as shown, the first portion of middle cell bit lines 210a are vertically aligned with a third portion of middle cell bit lines 210c. The vertical offset may be a predetermined distance, such as a fraction of a length of the bit lines. In this particular example, the offset is less than half of the length of the bit lines. Although the example shows every other portion of bit lines as having the same vertical offset, resulting in a zig-zagging pattern, in other examples the offsets may form another pattern, such as every third portion having the same offset, every fourth portion having the same offset, or some random pattern.

Middle cell bit line decoders are shown provided for each portion of middle cell bit lines. For instance, a first set of middle cell bit line decoders may be provided in a first middle cell bit line decoder subsection 240a for activating the first portion of middle cell bit lines 210a, a second set of middle cell bit line decoders may be provided in a second middle cell bit line decoder subsection 140b for activating the second portion of middle cell bit lines 210b, a third set of middle cell bit line decoders may be provided in a third middle cell bit line decoder subsection 240c for activating the third portion of middle cell bit lines 210c. Since the middle cell bit lines are arranged in portions that are offset, middle cell bit line decoders may also be arranged in subsections that are offset. For instance as shown, the first middle cell bit line decoder subsection 240a is vertically offset from the second middle cell bit line decoder subsection 240b. Further as shown, the first middle cell bit line decoder subsection 240a is vertically aligned with the third middle cell bit line decoder subsection 240c. The vertical offset may be a predetermined distance, such as a fraction of a length of the bit lines. In this particular example, the offset is less than half of the length of the bit lines. Although the example shows every other portion of bit lines as having the same vertical offset, resulting in a checker-board like pattern, in other examples the offsets may form another pattern, such as every third portion having the same offset, every fourth portion having the same offset, or some random pattern.

FIGS. 5A and 5B further illustrate that the vertical offsets between the portions of bottom cell bit lines, the vertical offsets between the portions of top cell bit lines, the vertical offsets between the portions of middle cell bit lines, as well as the vertical offsets between the portions of the middle cell bit lines with the top and/or bottom cell bit lines allow bit line decoders to be arranged in subsections that are offset. For example, where the bit lines corresponding to a given cell layer are arranged with a vertical offset of about a quarter of the length of the bit lines, and the bit lines corresponding to different cell layers are arranged with a vertical offset of about a half of the length of the bit lines, this in turn allows the bit line decoders to be arranged in adjacent subsections that are offset by a quarter of the length of the bit lines. This allows the bit line decoder subsections to be in an area along the vertical middle of the corresponding bit lines. Such an arrangement allows a bit line contact and decoder to be positioned equidistance from both ends of a corresponding bit line, and thus increase data speed and energy efficiency. Such an arrangement also allows bit line contacts to directly connect bit lines to corresponding bit line decoders by extending straight in a depth direction without further routing, which may result in further increase in data speed and energy efficiency. Alternatively, the bit line decoder subsections may be provided offset from the vertical middle of the respective bit lines, in such instances routing between the bit line contacts and the bit line decoders may be provided.

FIGS. 6A and 6B are plan views of a section of three-dimensional crosspoint memory according to the embodiment of FIGS. 4A and 4B. It should be noted that, for clarity of presentation, FIGS. 6A and 6B illustrate only some elements of the memory. Other elements are further described with reference to other figures. FIGS. 6A and 6B are provided to further illustrate the arrangement of word lines and word line decoders for the architecture. In particular, FIGS. 6A and 6B show the same plan view, with the exception that the markings highlight different elements.

FIG. 6A illustrates an example arrangement of bottom cell word lines and bottom cell word line decoders. As described above with reference to FIG. 4B, the bottom cell word lines are horizontally offset from the middle cell word lines. FIG. 6A further shows that, the bottom cell word lines are also offset among themselves. Thus as shown, the bottom cell word lines are arranged in portions that are offset from each other along the horizontal or X direction. For example, a first portion of bottom cell word lines 150a are horizontally offset from a second portion of bottom cell word lines 150b. Further as shown, the first portion of bottom cell word lines 150a are horizontally aligned with a third portion of bottom cell word lines 150c. The horizontal offset may be a predetermined distance, such as a fraction of a width of the word lines. In this particular example, the offset is less than half of the width of the word lines. Although the example shows every other portion of word lines as having the same horizontal offset, resulting in a zig-zagging pattern, in other examples the offsets may form another pattern, such as every third portion having the same offset, every fourth portion having the same offset, or some random pattern.

Bottom cell word line decoders are shown provided for each portion of bottom cell word lines. For instance, a first set of bottom cell word line decoders may be provided in a first bottom cell word line decoder subsection 160a for activating the first portion of bottom cell word lines 150a, a second set of bottom cell word line decoders may be provided in a second bottom cell word line decoder subsection 160b for activating the second portion of bottom cell word lines 160b, a third set of bottom cell word line decoders may be provided in a third bottom cell word line decoder subsection 160c for activating the third portion of bottom cell word lines 150c. Since the bottom cell word lines are arranged in portions that are offset, bottom cell word line decoders may also be arranged in subsections that are offset. For instance as shown, the first bottom cell word line decoder subsection 160a is horizontally offset from the second bottom cell word line decoder subsection 160b. Further as shown, bottom cell word line decoder subsection 160a is horizontally aligned with bottom cell word line decoder subsection 160c. The horizontal offset may be a predetermined distance, such as a fraction of a width of the word lines. In this particular example, the offset is less than half of the width of the word lines. Although the example shows every other portion of word lines as having the same horizontal offset, resulting in a zig-zagging pattern, in other examples the offsets may form another pattern, such as every third portion having the same offset, every fourth portion having the same offset, or some random pattern.

FIG. 6B illustrates an example arrangement of middle cell word lines and middle cell word line decoders. As described above with reference to FIG. 4B, the middle cell word lines are horizontally offset from the bottom cell word lines. FIG. 6B further shows that, the middle cell word lines are also offset among themselves. Thus as shown, the middle cell word lines are arranged in portions that are offset from each other along the horizontal or X direction. For example, a first portion of middle cell word lines 250a are horizontally offset from a second portion of middle cell word lines 250b. Further as shown, the first portion of middle cell word lines 250a are horizontally aligned with a third portion of middle cell word lines 250c. The horizontal offset may be a predetermined distance, such as a fraction of a width of the word lines. In this particular example, the offset is less than half of the width of the word lines. Although the example shows every other portion of word lines as having the same horizontal offset, resulting in a zig-zagging pattern, in other examples the offsets may form another pattern, such as every third portion having the same offset, every fourth portion having the same offset, or some random pattern.

Middle cell word line decoders are shown provided for each middle cell word line portion. For instance, a first set of middle cell word line decoders may be provided in a first middle cell word line decoder subsection 260a for activating the first portion of middle cell word lines 250a, a second set of middle cell word line decoders may be provided in a second middle cell word line decoder subsection 260b for activating the second portion of middle cell word lines 250b, a third set of middle cell word line decoders may be provided in a third middle cell word line decoder subsection 260c for activating the third portion of middle cell word lines 250c. Since the middle cell word lines are arranged in portions that are offset, middle cell word line decoders may also be arranged in subsections that are offset. For instance as shown, the first middle cell word line decoder subsection 260a is horizontally offset from the second middle cell word line decoder subsection 260b. Further as shown, the first middle cell word line decoder subsection 260a is horizontally aligned with the third middle cell word line decoder subsection 260c. The horizontal offset may be a predetermined distance, such as a fraction of a width of the word lines. In this particular example, the offset is less than half of the width of the word lines. Although the example shows every other portion of word lines as having the same horizontal offset, resulting in a checker-board like pattern, in other examples the offsets may form another pattern, such as every third portion having the same offset, every fourth portion having the same offset, or some random pattern.

FIGS. 6A and 6B further illustrate that the horizontal offsets between the portions of bottom cell word lines, the horizontal offsets between the portions of middle cell word lines, as well as the horizontal offsets between the portions of middle cell word lines and the bottom cell word lines allow word line decoders to be arranged in subsections that are offset. For example, where the word lines corresponding to a given cell layer are arranged with a horizontal offset of about a quarter of the width of the word lines, and the word lines corresponding to different cell layers are arranged with a horizontal offset of about a half of the width of the word lines, this in turn allows the word line decoders to be arranged in adjacent subsections that are offset by a quarter of the width of the word lines. This allows the word line decoder subsections to be in an area along the horizontal middle of the corresponding word lines. The arrangement allows a word line contact and decoder to be positioned equidistance from both ends of a corresponding word line, and thus increase data speed and energy efficiency. Such an arrangement also allows word line contacts to directly connect word lines to word line decoders by extending straight in a depth direction without further routing, which may result in further increase in data speed and energy efficiency. Alternatively, the word line decoder subsections may be provided offset from the horizontal middle of the respective word lines, in such instances routing between the word line contacts and the word line decoders may be provided.

FIG. 7 is a plan view of a section of three-dimensional crosspoint memory according to the embodiment of FIGS. 4A and 4B. It should be noted that, for clarity of presentation, FIG. 7 illustrates only some elements of the memory. Other elements are further described with reference to other figures. FIG. 7 is provided to show arrangement of decoders, including various bit line decoders and word line decoders. As shown, the bottom cell bit line decoder subsections, including bottom cell bit line decoder subsection 140a, form a zig-zag row that extend in a horizontal or X direction, likewise the middle cell bit line decoder subsections, including middle cell bit line decoder subsection 240a, form a zig-zag row that extend in the horizontal direction. Further as described above, because the bottom cell bit lines (and top cell bit lines) are offset from the middle cell bit lines by half the length of the bit lines, this in turn creates space between the zig-zagged row of the bottom cell bit line decoders and the zig-zagged row of the middle cell bit line decoders. Word line decoders can be provided in this space between the two adjacent rows of bit line decoders. Thus as shown, the bottom cell word line decoder subsections, including bottom cell word line decoder subsection 170a, form a zig-zag column that extend in a vertical or Y direction, likewise the middle cell word line decoder subsections, including middle cell word line decoder subsection 270a, form a zig-zag column that extend in the vertical direction. The various decoder subsections form a checker-board like pattern, and may be provided in a same plane, such as a plane below the stacked structure of FIGS. 4A and 4B in the depth or Z direction. FIG. 7 thus shows a decoder arrangement that efficiently uses limited space in a memory structure.

FIG. 8 is a plan view of a section of three-dimensional crosspoint memory according to the embodiment of FIGS. 4A and 4B. It should be noted that, for clarity of presentation, FIG. 8 illustrates only some elements of the memory. Other elements are further described with reference to other figures. FIG. 8 is provided to show arrangement of bit line and word line contacts relative to the bit lines and word lines. FIG. 8 does not show bit line or word line decoders, but it may be assumed that the bit line or word line decoders are generally provided in the same area as the corresponding bit line and/or word line contacts. The architecture of FIG. 8 allows for bit lines to be introduced in the areas provided for the word line decoders. As shown, bottom cell bit lines 110 (and top cell bit lines) overlap areas where bottom and middle cell word line contacts (and bottom and middle cell word line decoders) are provided. Likewise, middle cell bit lines 210 overlap areas where bottom and middle cell word line contacts (and bottom and middle cell word line decoders) . For instance, the bit lines may be provided above or below the word line contacts and decoders with respect to the depth or Z direction. Moreover, the architecture of FIG. 8 allows for memory cells to be included in the areas provided for the word line decoders. For instance, the memory cells may be provided above or below the word line contacts and decoders with respect to the depth or Z direction. Accordingly, the architecture of FIG. 8 does not require an area dedicated to word line contacts and decoders, and thus allows for an architecture having a higher memory density and greater efficiency relative to the prior architectures. FIG. 8 further shows that, because the decoder subsections are arranged with offsets, such as the checker-board like pattern of FIG. 7, the corresponding contacts may also be arranged with offsets, such as bottom cell bit line contacts 120, middle cell bit line contacts 220, bottom cell word line contacts 160, and middle cell word line contacts 260. Since the contacts may extend through different depths along the Z direction, in depth planes where the contacts do not extend to, word lines, bit lines, and memory cells may continue to run, thus maximizing use of space in the memory structure.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the precise order described above. Rather, various steps can be handled in a different order, such as reversed, or simultaneously. Steps can also be omitted unless otherwise stated. In addition, the provision of the examples described herein, as well as clauses phrased as "such as, " "including" and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A three-dimensional memory comprising:

a plurality of memory cell layers of memory cells stacked in a depth direction;

a plurality of bit lines coupled to the plurality of memory cell layers;

a plurality of word lines coupled to the plurality of memory cell layers;

a plurality of bit line decoders coupled to the plurality of bit lines and operable to selectively activate the plurality of bit lines; and

a plurality of word line decoders coupled to the plurality of word lines and operable to selectively activate the plurality of word lines;

wherein the bit line decoders are arranged in bit line decoder subsections that are offset in a vertical direction; and

wherein the word line decoders are arranged in word line decoder subsections that are offset in a horizontal direction.
The three-dimensional memory according to claim 1, wherein the plurality of bit line decoders include bottom cell bit line decoders operable to selectively activate bottom cell bit lines that are coupled to a bottom cell layer and to selectively activate top cell bit lines that are coupled to a top cell layer, and middle cell bit line decoders operable to selectively activate middle cell bit lines that are coupled to at least one middle cell layer;

wherein the bottom cell bit line decoders are arranged in bottom cell bit line decoder subsections and the middle cell bit line decoders are arranged in middle cell bit line decoder subsections; and

wherein the bottom cell bit line decoder subsections are offset from the middle cell bit line decoder subsections in the vertical direction.
The three-dimensional memory according to claim 2, wherein horizontally adjacent bottom cell bit line decoder subsections are arranged with an offset in the vertical direction, horizontally adjacent top cell bit line decoder subsections are arranged with an offset in the vertical direction, and horizontally adjacent middle cell bit line decoder subsections are arranged with an offset in the vertical direction.
The three-dimensional memory according to claim 1, wherein the plurality of word line decoders include bottom cell word line decoders operable to selectively activate bottom cell word lines that are coupled to a bottom cell layer and coupled to at least one middle cell layer, and middle cell word line decoders operable to selectively activate middle cell word lines that are coupled to at least one middle cell layer and coupled to a top cell layer;

wherein the bottom cell word line decoders are arranged in bottom cell word line decoder subsections and the middle cell word line decoders are arranged in middle cell word line decoder subsections; and

wherein the bottom cell word line decoder subsections are offset from the middle cell word line decoder subsections in the horizontal direction.
The three-dimensional memory according to claim 4, wherein vertically adjacent bottom cell word line decoder subsections are arranged with an offset in the horizontal direction, and vertically adjacent middle cell word line decoder subsections are arranged with an offset in the horizontal direction.
The three-dimensional memory according to claim 2, wherein the bottom cell bit lines are arranged in portions such that horizontally adjacent portions of bottom cell bit lines are offset in the vertical direction, the middle cell bit lines are arranged in portions such that horizontally adjacent portions of middle cell bit lines are offset in the vertical direction, and the top cell bit lines are arranged in portions such that horizontally adjacent portions of top cell bit lines are offset in the vertical direction.
The three-dimensional memory according to claim 4, wherein the bottom cell word lines are arranged in portions such that vertically adjacent portions of bottom cell word lines are offset in the horizontal direction, and the middle cell word lines are arranged in portions such that vertically adjacent portions of middle cell word lines are offset in the horizontal direction.
The three-dimensional memory according to claim 2, further comprising:

bit line contacts including bottom cell bit line contacts each connecting a vertical middle of a respective one of the bottom cell bit lines to the bottom cell bit line decoders, top cell bit line contacts each connecting a vertical middle of a respective one of the top cell bit lines to the bottom cell bit line decoders, and middle cell bit line contacts each connecting a vertical middle of a respective one of the middle cell bit lines to the middle cell bit line decoders.
The three-dimensional memory according to claim 4, further comprising:

word line contacts including bottom cell word line contacts each connecting a horizontal middle of a respective one of the bottom cell word lines to the bottom cell word line decoders, and middle cell word line contacts each connecting a horizontal middle of a respective one of the middle cell word lines to the middle cell word line decoders.
The three-dimensional memory according to claim 2, wherein the at least one middle cell layer includes a first middle cell layer of memory cells and a second middle cell layer of memory cells; and wherein the bottom cell bit lines are coupled to the first middle cell layer of memory cells and the middle cell bit lines are coupled to the second middle cell layer of memory cells.
The three-dimensional memory according to claim 4, wherein the at least one middle cell layer includes a first middle cell layer of memory cells and a second middle cell layer of memory cells; and wherein the bottom cell word lines are coupled to the first middle cell layer of memory cells and the middle cell word lines are coupled to the second middle cell layer of memory cells.
A method of forming a three-dimensional memory comprising:

providing a plurality of memory cell layers of memory cells stacked in a depth direction;

providing a plurality of bit lines coupled to the plurality of memory cell layers;

providing a plurality of word lines coupled to the plurality of memory cell layers;

providing a plurality of bit line decoders coupled to the plurality of bit lines and operable to selectively activate the plurality of bit lines;

providing a plurality of word line decoders coupled to the plurality of word lines and operable to selectively activate the plurality of word lines;

forming the bit line decoders in bit line decoder subsections that are offset in a vertical direction; and

forming the word line decoders in word line decoder subsections that are offset in a horizontal direction.
The method according to claim 12, wherein the plurality of bit lines include bottom cell bit lines coupled to a bottom cell layer, middle cell bit lines coupled to at least one middle cell layer, and top cell bit lines coupled to at least one top cell layer, further comprising:

forming the bottom cell bit lines in portions such that horizontally adjacent portions of bottom cell bit lines are offset in the vertical direction;

forming the middle cell bit lines in portions such that horizontally adjacent portions of middle cell bit lines are offset in the vertical direction;

forming the top cell bit lines in portions such that horizontally adjacent portions of top cell bit lines are offset in the vertical direction.
The method according to claim 12, wherein the plurality of word lines include bottom cell word lines coupled to a bottom cell layer, and middle cell word lines coupled to at least one middle cell layer and coupled to a top cell layer, further comprising:

forming the bottom cell word lines in portions such that vertically adjacent portions of bottom cell word lines are offset in the horizontal direction; and

forming the middle cell word lines in portions such that vertically adjacent portions of middle cell word lines are offset in the horizontal direction.
The method according to claim 13, further comprising:

providing bit line contacts, including bottom cell bit line contacts each connecting a vertical middle of a respective one of the bottom cell bit lines to the bottom cell bit line decoders, top cell bit line contacts each connecting a vertical middle of a respective one of the top cell bit lines to the bottom cell bit line decoders, and middle cell bit line contacts each connecting a vertical middle of a respective one of the middle cell bit lines to the middle cell bit line decoders.
The method according to claim 14, further comprising:

providing word line contacts, including bottom cell word line contacts each connecting a horizontal middle of a respective one of the bottom cell word lines to the bottom cell word line decoders, and middle cell word line contacts each connecting a horizontal middle of a respective one of the middle cell word lines to the middle cell word line decoders.