WO2021223743A1 - 像素驱动电路、显示面板、驱动方法、显示装置 - Google Patents

像素驱动电路、显示面板、驱动方法、显示装置 Download PDF

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Publication number
WO2021223743A1
WO2021223743A1 PCT/CN2021/092180 CN2021092180W WO2021223743A1 WO 2021223743 A1 WO2021223743 A1 WO 2021223743A1 CN 2021092180 W CN2021092180 W CN 2021092180W WO 2021223743 A1 WO2021223743 A1 WO 2021223743A1
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Prior art keywords
terminal
sub
circuit
transistor
switch
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PCT/CN2021/092180
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English (en)
French (fr)
Inventor
王志冲
李付强
刘鹏
冯京
栾兴龙
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京东方科技集团股份有限公司
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Priority to US17/796,118 priority Critical patent/US11893936B2/en
Publication of WO2021223743A1 publication Critical patent/WO2021223743A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, a driving method, and a display device.
  • OLED display devices are one of the current research hotspots in the field of display technology. Compared with liquid crystal display devices (LCD), OLED display devices have low energy consumption and low production costs. , Self-luminous, wide viewing angle and fast response speed.
  • the OLED display device includes a plurality of sub-pixels, and each sub-pixel includes a pixel driving circuit and a light-emitting device, and the light-emitting device is driven to emit light by the pixel driving circuit, thereby realizing display.
  • a pixel driving circuit includes a driving sub-circuit, a signal writing sub-circuit, a compensation sub-circuit, a light emission control sub-circuit, and an initialization sub-circuit.
  • the signal writing sub-circuit is respectively coupled to the data signal terminal, the first control signal terminal, and the driving sub-circuit; the signal writing sub-circuit is configured to control the signal from the first control signal terminal Next, write the voltage of the data signal terminal as the data voltage to the driving sub-circuit.
  • the light-emitting control sub-circuit is respectively coupled to the light-emitting control terminal, the driving sub-circuit and the light-emitting device; the light-emitting control sub-circuit is configured to communicate with the light-emitting control terminal under the control of the signal from the light-emitting control terminal.
  • the driving sub-circuit cooperates to drive the light-emitting device to emit light.
  • the initialization sub-circuit is respectively coupled to the data signal terminal, the second control signal terminal, and the compensation sub-circuit, and the initialization sub-circuit is configured to: under the control of the signal from the second control signal terminal, The voltage of the data signal terminal is transmitted to the compensation sub-circuit as a reset voltage.
  • the compensation sub-circuit is also respectively coupled to the driving sub-circuit and the first control signal terminal; the compensation sub-circuit is configured to: under the control of the signal from the first control signal terminal, the The reset voltage of the initialization sub-circuit is transmitted to the driving sub-circuit to reset the driving sub-circuit.
  • the compensation sub-circuit is further coupled to the third control signal terminal, and the compensation sub-circuit is further configured to: Under the control of the signal, the threshold voltage of the driving transistor is compensated to the first end of the capacitor.
  • the driving sub-circuit is also coupled to the first voltage terminal.
  • the light-emitting control sub-circuit is also respectively coupled to the anode and the reference signal terminal of the light-emitting device, and the cathode of the light-emitting device is coupled to the second voltage terminal; the light-emitting control sub-circuit is configured to: Under the control of the signal of the light-emitting control terminal, the reference voltage of the reference signal terminal is transmitted to the second terminal of the capacitor to cooperate with the driving sub-circuit to drive the light-emitting device to emit light.
  • the first electrode of the driving transistor is coupled to the first voltage terminal, and the second electrode of the driving transistor is coupled to the light emission control sub-circuit.
  • the signal writing sub-circuit includes a first transistor.
  • the gate of the first transistor is coupled to the first control signal terminal, the first electrode of the first transistor is coupled to the data signal terminal, and the second electrode of the first transistor is connected to the capacitor The second end is coupled.
  • the compensation sub-circuit includes a second transistor and a third transistor.
  • the gate of the second transistor is coupled to the first control signal terminal, the first pole of the second transistor is coupled to the first terminal of the capacitor, and the second pole of the second transistor is coupled to the first terminal of the capacitor.
  • the initialization sub-circuit is coupled.
  • the gate of the third transistor is coupled to the third control signal terminal, the first electrode of the third transistor is coupled to the second electrode of the second transistor, and the second electrode of the third transistor is coupled to the The second pole of the driving transistor is coupled.
  • the light emission control sub-circuit includes a fourth transistor and a fifth transistor.
  • the gate of the fourth transistor is coupled to the light-emitting control terminal, the first electrode of the fourth transistor is coupled to the reference signal terminal, and the second electrode of the fourth transistor is connected to the first electrode of the capacitor. Two-terminal coupling.
  • the gate of the fifth transistor is coupled to the light-emitting control terminal, the first electrode of the fifth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the fifth transistor is coupled to the The anode of the light emitting device is coupled.
  • the initialization sub-circuit includes a sixth transistor.
  • the gate of the sixth transistor is coupled to the second control signal terminal, the first electrode of the sixth transistor is coupled to the data signal terminal, and the second electrode of the sixth transistor is coupled to the compensation signal terminal.
  • the sub-circuit is coupled.
  • the signal writing sub-circuit includes a first transistor
  • the compensation sub-circuit includes a second transistor and a third transistor
  • the light emission control sub-circuit includes a fourth transistor and a fifth transistor
  • the initialization The sub-circuit includes a sixth transistor.
  • the gate of the first transistor is coupled to the first control signal terminal
  • the first electrode of the first transistor is coupled to the data signal terminal
  • the second electrode of the first transistor is coupled to the capacitor
  • the second end is coupled.
  • the gate of the second transistor is coupled to the first control signal terminal
  • the first pole of the second transistor is coupled to the first terminal of the capacitor
  • the second pole of the second transistor is coupled to the first terminal of the capacitor.
  • the second electrode of the sixth transistor is coupled.
  • the gate of the third transistor is coupled to the third control signal terminal, the first electrode of the third transistor is coupled to the second electrode of the second transistor, and the second electrode of the third transistor is coupled to the The second pole of the driving transistor is coupled.
  • the gate of the fourth transistor is coupled to the light-emitting control terminal, the first electrode of the fourth transistor is coupled to the reference signal terminal, and the second electrode of the fourth transistor is connected to the second terminal of the capacitor. Coupling.
  • the gate of the fifth transistor is coupled to the light-emitting control terminal, the first electrode of the fifth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the fifth transistor is coupled to the The anode of the light emitting device is coupled.
  • the gate of the sixth transistor is coupled to the second control signal terminal, the first electrode of the sixth transistor is coupled to the data signal terminal, and the second electrode of the sixth transistor is coupled to the second control signal terminal. The second poles of the two transistors are coupled.
  • a display panel in another aspect, includes a plurality of sub-pixels, and each sub-pixel is provided with a pixel driving circuit as described in any of the above-mentioned embodiments.
  • the display panel further includes a plurality of switch controller groups, a source driver, a plurality of scan signal lines, a plurality of first data signal lines, and a plurality of second data signal lines.
  • the first control signal terminal of the pixel driving circuit in the same row of sub-pixels is coupled to the same scanning signal line.
  • the data signal terminal in each pixel driving circuit corresponding to odd rows in the same column of sub-pixels is coupled to the same first data signal line; the data signal terminal in each pixel driving circuit corresponding to even rows in the same column of sub-pixels is connected to the same The second data signal line is coupled.
  • Each switch controller group includes a first switch and a second switch, one end of the first switch is coupled to the first data signal line, and the other end of the first switch is coupled to the source driver; One end of the two switches is coupled to the second data signal line, and the other end of the second switch is coupled to the source driver.
  • a display device in another aspect, includes the display panel as described in any of the foregoing embodiments.
  • a driving method of a pixel driving circuit includes a plurality of frame periods, and each frame period includes an initialization phase, a scanning phase, and a light-emitting phase.
  • the initialization stage includes a plurality of row initialization periods
  • the scanning stage includes a plurality of row scanning periods
  • the light-emitting stage includes a plurality of row light-emitting periods.
  • Each row initialization period of the plurality of row initialization periods includes: the initialization sub-circuit transmits the voltage of the data signal terminal as a reset voltage to the compensation sub-circuit under the control of the turn-on signal transmitted from the second control signal terminal; the compensation sub-circuit Under the control of the turn-on signal transmitted from the first control signal terminal, the reset voltage transmitted to the compensation sub-circuit is transmitted to the gate of the driving transistor to reset the gate of the driving transistor.
  • Each of the plurality of horizontal scanning periods includes: under the control of the turn-on signal transmitted from the first control signal terminal and the third control signal terminal, the compensation sub-circuit adjusts the threshold voltage of the driving transistor and the first voltage terminal of the first voltage terminal.
  • a voltage is written into the first end of the capacitor; the signal writing sub-circuit, under the control of the turn-on signal transmitted from the first control signal end, writes the voltage of the data signal end into the second end of the capacitor as the data voltage.
  • Each of the plurality of row light-emitting periods includes: under the control of the turn-on signal transmitted by the light-emitting control terminal, the light-emitting control sub-circuit writes the reference voltage of the reference signal terminal into the second terminal of the capacitor, so as to write the The voltage difference between the data voltage and the reference voltage is coupled to the first terminal of the capacitor, and a current path is formed between the first voltage terminal and the second voltage terminal. When a current path is formed between the first voltage terminal and the second voltage terminal, a driving current is provided to the light emitting device through the current path to drive the light emitting device to emit light.
  • a method for driving a display panel wherein the display panel includes the display panel as described in any of the above embodiments, and the driving method for the display panel includes a driving method of multiple control periods, and each control The cycle includes the first phase, the second phase and the third phase.
  • the display panel further includes a switch controller group, a source driver, a plurality of scan signal lines, a plurality of first data signal lines and a plurality of second data signal lines
  • the display panel is controlled by one
  • the driving method in the cycle includes: in the first stage, the first control signal terminal and the second control signal terminal input the turn-on signal; in the first sub-stage of the first stage, the source driver controls the second When a switch is turned off, the second switch is turned on, and an initial voltage is provided to the second terminal of the first switch and the second terminal of the second switch; in the second sub-stage of the first stage, The source driver controls the first switch to be turned on and the second switch to turn off, and provides a data voltage to the second terminal of the first switch and the second terminal of the second switch.
  • the first control signal terminal and the third control signal terminal input turn-on signals; in the first sub-stage of the second stage, the source driver controls the first switch to turn off, and the The second switch is turned on, and provides a data voltage to the second terminal of the first switch and the second terminal of the second switch; in the second sub-stage of the second stage, the source driver controls all The first switch is turned on, the second switch is turned off, and an initial voltage is provided to the second terminal of the first switch and the second terminal of the second switch.
  • the third control signal terminal inputs an open signal; in the first sub-stage of the third stage, the source driver controls the first switch to turn off, the second switch to turn on, and to the The second terminal of the first switch and the second terminal of the second switch provide an initial voltage; in the second sub-stage of the third stage, the source driver controls the first switch to turn on, and the second switch Turn off and provide a data voltage to the second terminal of the first switch and the second terminal of the second switch.
  • another method for driving a display panel wherein the display panel includes the display panel as described in any of the above embodiments, and the driving method for the display panel includes a driving method of multiple control periods, each The control cycle includes the first phase, the second phase and the third phase.
  • the display panel further includes a switch controller group, a source driver, a plurality of scan signal lines, a plurality of first data signal lines and a plurality of second data signal lines
  • the display panel is controlled by one
  • the driving method in the cycle includes: in the first stage, the first control signal terminal and the second control signal terminal input the turn-on signal; in the first sub-stage of the first stage, the source driver controls the first switch Is turned off, the second switch is turned on, and an initial voltage is provided to the second terminal of the first switch and the second terminal of the second switch; in the second sub-stage of the first stage, the source The driver controls the first switch to be turned on, the second switch is turned off, and provides a data voltage to the second terminal of the first switch and the second terminal of the second switch.
  • the first control signal terminal and the third control signal terminal input turn-on signals; in the first sub-stage of the second stage, the source driver controls the first switch to turn on, and the second switch to turn off And provide an initial voltage to the second terminal of the first switch and the second terminal of the second switch; in the second sub-stage of the second stage, the source driver controls the first switch to turn off , The second switch is turned on, and provides a data voltage to the second terminal of the first switch and the second terminal of the second switch.
  • the third control signal terminal inputs an open signal; in the first sub-stage of the third stage, the source driver controls the first switch to turn off, the second switch to turn on, and to the The second terminal of the first switch and the second terminal of the second switch provide an initial voltage; in the second sub-stage of the third stage, the source driver controls the first switch to turn on and the second switch to turn off , And provide a data voltage to the second terminal of the first switch and the second terminal of the second switch.
  • FIG. 1A is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 1B is a structural diagram of another pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 1C is a structural diagram of still another pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 2 is a structural diagram of still another pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 3 is a flowchart of a driving method of a pixel driving circuit according to some embodiments of the present disclosure
  • FIG. 4 is a timing diagram of a pixel driving method according to some embodiments of the present disclosure.
  • FIG. 5 is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 7 is a structural diagram of still another pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 8A is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 8B is another structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 9 is a timing diagram of a driving method of a display panel according to some embodiments of the present disclosure.
  • FIG. 10 is another timing diagram of a driving method of a display panel according to some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • some embodiments of the present disclosure provide a pixel driving circuit 100, which includes a driving sub-circuit 10, a signal writing sub-circuit 20, a compensation sub-circuit 30, a light emission control sub-circuit 40, and an initialization sub-circuit 50.
  • the signal writing sub-circuit 20 is respectively coupled to the data signal terminal DATA, the first control signal terminal GATE_n and the driving sub-circuit 10.
  • the signal writing sub-circuit 20 is configured to write the voltage of the data signal terminal DATA as the data voltage V data to the driving sub-circuit 10 under the control of the signal from the first control signal terminal GATE_n.
  • the emission control sub-circuit 40 is respectively coupled to the emission control terminal EM_n, the driving sub-circuit 10 and the light-emitting device D.
  • the light-emitting control sub-circuit 40 is configured to cooperate with the driving sub-circuit 10 to drive the light-emitting device D to emit light under the control of the signal from the light-emitting control terminal EM_n.
  • the initialization sub-circuit 50 is respectively coupled to the data signal terminal DATA, the second control signal terminal GATE_(n-1) and the compensation sub-circuit 30.
  • the initialization sub-circuit 50 is configured to transmit the voltage of the data signal terminal DATA as the reset voltage V int to the compensation sub-circuit 30 under the control of the signal from the second control signal terminal GATE_(n-1).
  • the compensation sub-circuit 30 is also respectively coupled to the driving sub-circuit 10 and the first control signal terminal GATE_n.
  • the compensation sub-circuit 30 is configured to transmit the reset voltage transmitted to the compensation sub-circuit 30 to the driving sub-circuit 10 under the control of the signal from the first control signal terminal GATE_n, so as to reset the driving sub-circuit 10.
  • the signal writing sub-circuit 30 and the initialization sub-circuit 50 are both coupled to the data signal terminal DATA.
  • the data voltage V data can be written to the driving sub-circuit 10 by controlling the turn-on of the signal writing sub-circuit 30, so that the light-emitting device D can be driven to emit light in coordination with the turn-on of the light-emission control sub-circuit 40.
  • the reset voltage V int can be transmitted to the driving sub-circuit 10, so that the driving sub-circuit 10 can be reset.
  • the reset voltage V int and the data voltage V data can be input to the pixel driving circuit 100 at different time intervals through one signal terminal, thereby reducing the number of signal terminals in the pixel driving circuit 100, thereby simplifying the design of the pixel driving circuit 100 .
  • the driving sub-circuit 10 includes a driving transistor DT and a capacitor C; the first end of the capacitor C is coupled to the gate of the driving transistor DT.
  • the signal writing sub-circuit 20 is configured to write the voltage of the data signal terminal as the data voltage V data to the second terminal of the capacitor C under the control of the signal from the first control signal terminal GATE_n.
  • the compensation sub-circuit 30 is configured to transmit the reset voltage V int from the initialization sub-circuit 50 to the gate of the driving transistor DT under the control of the signal from the first control signal terminal GATE_n, so as to contact the gate of the driving transistor DT. Perform a reset.
  • the driving sub-circuit 10 is also coupled to the first voltage terminal ELVDD.
  • the light emission control sub-circuit 40 is also respectively coupled to the anode of the light emitting device D and the reference signal terminal VREF, and the cathode of the light emitting device D is coupled to the second voltage terminal ELVSS.
  • the light emission control sub-circuit 40 is configured to: under the control of the signal from the light emission control terminal EM_n, transmit the reference voltage V ref of the reference signal terminal VREF to the second terminal of the capacitor C to cooperate with the driving sub-circuit 10 to drive light emission Device D emits light.
  • the data voltage V data and the reference voltage V ref are respectively input to the second terminal of the capacitor C at different time periods.
  • the reference voltage V ref and the data voltage V data are different.
  • the pressure difference TP can be coupled to the first end of the capacitor C.
  • the electric potential of the first end of the capacitor C can be used to control the turn-on of the driving transistor DT, so that the light-emitting device D can be driven to emit light in cooperation with the turn-on of the light-emitting control sub-circuit 40.
  • the compensation sub-circuit 30 is also coupled to the third control signal terminal GATE_(n+1), and the compensation sub-circuit 30 is further configured to: Under the control of the signal of the control signal terminal GATE_(n+1), the threshold voltage V th of the driving transistor DT is compensated to the first terminal of the capacitor C.
  • the signals of the first control signal terminal GATE_n and the third control signal terminal GATE_(n+1) are used to control the conduction of the compensation sub-circuit 30 to compensate the threshold voltage V th to the first terminal of the capacitor C, thereby eliminating the threshold voltage V The influence of th on the light-emitting current of the light-emitting device D, thereby ensuring the stability of the light-emitting device D.
  • the “coupling” in some embodiments of the present disclosure may refer to a direct electrical connection between the two, or an indirect electrical connection through some devices (for example, thin film transistors).
  • the reset voltage V int and the data voltage V data can be input into the pixel driving circuit 100 in a time sharing manner through the data signal terminal DATA.
  • the reset voltage V int can be used to initialize the potential of the gate of the driving transistor DT in the driving sub-circuit 10 of the pixel driving circuit, so that the potential of the gate of the driving transistor DT becomes V int after the row initialization period.
  • the driving transistor DT start to work from the same gate voltage bias state during row initialization periods of different cycles; the data voltage V data can be used to make the second terminal potential of the capacitor C in the driving sub-circuit 10 of the pixel driving circuit become V data , which is beneficial for controlling the subsequent light-emitting device D to emit light.
  • the reset voltage V int and the data voltage V data can be input to the pixel driving circuit at different time intervals through one signal terminal, so that the number of signal terminals in the pixel driving circuit can be reduced, and the design of the pixel driving circuit 100 can be simplified.
  • the first pole of the driving transistor DT is coupled to the first voltage terminal ELVDD, and the second pole of the driving transistor DT is coupled to the light emission control sub-circuit 40.
  • the driving transistor DT can be controlled to turn on, so that the light-emitting device D can be driven to emit light in conjunction with the turn-on of the light-emitting control sub-circuit 40.
  • the signal writing sub-circuit 20 includes a first transistor T1.
  • the gate of the first transistor T1 is coupled to the first control signal terminal GATE_n, the first electrode of the first transistor T1 is coupled to the data signal terminal DATA, and the second electrode of the first transistor T1 is coupled to the second terminal of the capacitor C .
  • the compensation sub-circuit 30 includes a second transistor T2 and a third transistor T3.
  • the gate of the second transistor T2 is coupled to the first control signal terminal GATE_n
  • the first pole of the second transistor T2 is coupled to the first terminal of the capacitor C
  • the second pole of the second transistor T2 is coupled to the initializing sub
  • the circuit 50 is coupled.
  • the gate of the third transistor T3 is coupled to the third control signal terminal GATE_(n+1)
  • the first electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2
  • the second electrode of the third transistor T3 It is coupled to the second pole of the driving transistor DT.
  • the voltage signal written at the first end of the capacitor C can be effectively prevented from fluctuating due to the leakage of the second transistor T2 coupled to it, thereby effectively ensuring that the light-emitting device D emits light Stable drive.
  • the light emission control sub-circuit 40 includes a fourth transistor T4 and a fifth transistor T5.
  • the gate of the fourth transistor T4 is coupled to the emission control terminal EM_n, the first pole of the fourth transistor T4 is coupled to the reference signal terminal VREF, and the second pole of the fourth transistor T4 is coupled to the second terminal of the capacitor C Coupling.
  • the gate of the fifth transistor T5 is coupled to the emission control terminal EM_n, the first pole of the fifth transistor T5 is coupled to the second pole of the driving transistor DT, and the second pole of the fifth transistor T5 is coupled to the anode of the light emitting device D .
  • the initialization sub-circuit 50 includes a sixth transistor T6.
  • the gate of the sixth transistor T6 is coupled to the second control signal terminal GATE_(n-1), the first electrode of the sixth transistor T6 is coupled to the data signal terminal DATA, and the second electrode of the sixth transistor T6 is coupled to the compensation sub-circuit
  • the second pole of the second transistor T2 in 30 is coupled.
  • the voltage signal written at the first end of the capacitor C can be effectively prevented from fluctuating due to the leakage of the second transistor T2 coupled to it, thereby effectively ensuring that the light-emitting device D emits light Stable drive.
  • the transistors mentioned in some embodiments of the present disclosure can be the drain of the first pole and the source of the second pole; it can also be the source of the first pole and the drain of the second pole, which is not limited.
  • the transistor can be divided into an enhancement type transistor and a depletion type transistor; according to the different substrate required for the preparation of the transistor, the transistor can be divided into a thin film transistor (TFT) and a metal oxide Semi-Field-Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET); According to the different types of transistor conduction channels, transistors can be divided into P-type transistors and N-type transistors.
  • the first electrode of the thin film transistor may be the source and the second electrode may be the drain.
  • the first electrode of the thin film transistor may be the drain, and the second electrode may be the source.
  • the enhancement P-type thin film transistor is taken as an example for description.
  • the various embodiments of the present disclosure include but are not limited to this.
  • one or more thin film transistors in the pixel driving circuit 100 provided in some embodiments of the present disclosure may also be N-type transistors.
  • only the poles of the selected type of thin film transistors need to be referred to some embodiments of the present disclosure.
  • the poles of the corresponding thin film transistors are coupled correspondingly, and the corresponding voltage terminals provide corresponding high-level voltages or low-level voltages.
  • some embodiments of the present disclosure provide a driving method of the pixel driving circuit 100, which is configured to drive the pixel driving circuit 100 as described above.
  • the driving method includes multiple frame periods.
  • each frame period includes an initialization phase, a scanning phase, and a light-emitting phase.
  • the initialization phase includes a plurality of row initialization periods
  • the scanning phase includes a plurality of row scanning periods
  • the light-emitting phase includes a plurality of row light-emitting periods.
  • Each row initialization period in the multiple row initialization periods includes:
  • the initialization sub-circuit 50 transmits the voltage of the data signal terminal DATA as the reset voltage V int to the compensation sub-circuit 30 under the control of the turn-on signal transmitted from the second control signal terminal GATE_(n-1). Under the control of the turn-on signal transmitted from the first control signal terminal GATE_n, the compensation sub-circuit 30 transmits the reset voltage V int transmitted to the compensation sub-circuit 30 to the gate of the driving transistor DT to reset the gate of the driving transistor DT .
  • a low-level turn-on signal is input to the first control signal terminal GATE_n and the second control signal terminal GATE_(n-1), and the third control signal
  • the terminal GATE_(n+1) and the light-emitting control terminal EM_n input a high-level cutoff signal.
  • the first transistor T1, the second transistor T2, and the sixth transistor T6 can be controlled to be turned on, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 can be controlled to be turned off at the same time.
  • a reset voltage V int is input to the data signal terminal DATA, and the reset voltage V int is input to the gate of the driving transistor DT through the sixth transistor T6 and the second transistor T2, so that the potential of the gate of the driving transistor DT is V int .
  • Each line scanning period in the multiple line scanning stages includes:
  • the compensation sub-circuit 30 controls the threshold voltage of the driving transistor DT and the voltage ELvdd of the first voltage terminal ELVDD under the control of the turn-on signal respectively transmitted from the first control signal terminal GATE_n and the third control signal terminal GATE_(n+1). Write the first end of the capacitor C.
  • the signal writing sub-circuit 20 writes the voltage of the data signal terminal DATA as the data voltage V data to the second terminal of the capacitor C under the control of the turn-on signal transmitted from the first control signal terminal GATE_n.
  • the low-level turn-on signal is input to the first control signal terminal Gate_n and the third control signal terminal GATE_(n+1), and the second control signal terminal GATE_(n-1) ) And the light-emitting control terminal EM_n inputs a high-level cutoff signal.
  • the first transistor T1, the second transistor T2, and the third transistor T3 can be controlled to be turned on
  • the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be controlled to be turned off at the same time.
  • the data voltage V data is input to the data signal terminal DATA, the electric potential of the second terminal of the capacitor C is V data ; and the threshold voltage V th of the driving transistor DT and the voltage ELvdd of the first voltage terminal ELVDD are written into the first voltage terminal of the capacitor C.
  • the electric potential of the first end of the capacitor C is ELvdd+V th .
  • Each row light-emitting period of the multiple row light-emitting stages includes:
  • the light emission control sub-circuit 40 transmits the reference voltage Vref of the reference signal terminal VREF to the second terminal of the capacitor C under the control of the turn-on signal transmitted from the light emission control terminal EM_n, so as to combine the data voltage Vdata and the reference voltage Vref.
  • the difference TP is coupled to the first terminal of the capacitor C, and forms a current path between the first voltage terminal ELVDD and the second voltage terminal ELVSS.
  • a driving current is provided to the light emitting device D through the current path to drive the light emitting device D to emit light.
  • a high-level cut-off signal is input to the first control signal terminal Gate_n and the second control signal terminal GATE_(n-1), and a high-level cutoff signal is input to the third control signal terminal GATE_(n+1).
  • the light-emitting control terminal EM_n inputs a low-level turn-on signal.
  • the voltage of the gate of the driving transistor DT V g V th +ELvdd +V ref -V data . In this way, the current flowing through the driving transistor DT at this time is:
  • K is the coefficient
  • I the aspect ratio of the driving transistor DT
  • Cox is the gate insulating layer capacitance of the driving transistor DT
  • ⁇ is the carrier mobility of the driving transistor DT.
  • the pixel driving circuit 100 can input the reset voltage V int and the data voltage V data to the pixel driving circuit 100 through a signal terminal in a time-sharing manner, thereby reducing the number of signal terminals in the pixel driving circuit 100, thereby facilitating simplification.
  • the design of the pixel drive circuit 100 is a simple circuit that is used to input the reset voltage V int and the data voltage V data to the pixel driving circuit 100 through a signal terminal in a time-sharing manner, thereby reducing the number of signal terminals in the pixel driving circuit 100, thereby facilitating simplification.
  • the signals transmitted by the light-emitting control terminal EM_n and the first control signal terminal GATE_n are opposite to each other.
  • the light-emitting control terminal EM_n transmits a high-level signal
  • the first control signal terminal GATE_n transmits a low-level signal at this time. Therefore, the light-emitting control terminal EM_n and the first control signal terminal GATE_n
  • the same set of GOA circuits can be connected.
  • the two output terminals of the GOA circuit are respectively connected to the light-emitting control terminal EM_n and the first control signal terminal GATE_n, and at the same time, the two output terminals of the GOA circuit respectively output two signals with opposite phases.
  • one output terminal of the GOA circuit is connected to the light emission control terminal EM_n and the first control signal terminal GATE_n at the same time, and the transistor type and light emission control of the first transistor T1 and the second transistor T2 corresponding to the first control signal terminal GATE_n
  • the fourth transistor T4 and the fifth transistor T5 corresponding to the terminal EM_n have different transistor types.
  • the first transistor T1 and the second transistor T2 are both P-type thin film transistors
  • the fourth transistor T4 and the fifth transistor T5 are both N-type thin film transistors
  • the first transistor T1 and the second transistor T2 are both N-type thin film transistors
  • the fourth transistor T4 and the fifth transistor T5 are both P-type thin film transistors.
  • the setup of the GOA circuit can be simplified, and the frame occupation area of the GOA circuit can be reduced, thereby facilitating the realization of the narrow frame of the display panel.
  • some embodiments of the present disclosure also provide a display panel 200.
  • the display panel 200 includes a plurality of sub-pixels P, and each sub-pixel P is provided with a pixel driving circuit 100 as described above.
  • the beneficial effects that can be achieved by the display panel 200 provided by some embodiments of the present disclosure include at least the same beneficial effects that can be achieved by the pixel driving circuit 100 provided by some embodiments of the present disclosure, which will not be repeated here.
  • the display panel 200 has a display area (Active Area, AA for short) and a peripheral area BB located on at least one side of the display area AA.
  • the above-mentioned multiple sub-pixels P are all arranged in the display area AA.
  • the peripheral area BB surrounds the display area AA for illustration. It can be understood that the present disclosure is not limited to this.
  • the plurality of sub-pixels P includes at least a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel.
  • the first color, the second color, and the third color may be three primary colors (for example, red, green, and blue).
  • the sub-pixels P arranged in a row along the first direction are called the same row of sub-pixels, and are arranged in a row along the second direction (for example, the vertical direction Y in FIG. 8A).
  • the sub-pixels P in the row are called sub-pixels in the same column.
  • the display panel 200 further includes a plurality of scan signal lines G(n), a plurality of first data signal lines D1(n), and a plurality of second data signal lines D2(n).
  • the first control signal terminal GATE_n in each pixel driving circuit 100 corresponding to the same row of sub-pixels P is connected to the same scanning signal line G(n); the second control signal in each pixel driving circuit 100 corresponding to the same row of sub-pixels P
  • the terminal GATE_(n-1) is connected to the same scanning signal line G(n-1); and the third control signal terminal GATE_(n+1) in each pixel driving circuit 100 corresponding to the same row of sub-pixels P is connected to the same One scanning signal line G(n+1) is connected.
  • the data signal terminal DATA in each pixel driving circuit 100 corresponding to odd rows in the same column of sub-pixels P is coupled to the same first data signal line D1(n); in each pixel driving circuit corresponding to even rows in the same column of sub-pixels The data signal terminal DATA is coupled to the same second data signal line D2(n).
  • the data signal terminal DATA in each pixel driving circuit 100 corresponding to the odd row is coupled to the same first data signal line D1(1); then The data signal terminal DATA in each pixel driving circuit corresponding to the even and even rows is coupled to the same second data signal line D2(1).
  • calculation can be performed from any end of the first data signal line D1(n) on the display panel 200.
  • the first data signal line D1(n) is close to one end of the source driver SD to compare the "odd rows” And "even-numbered rows” for calculation.
  • the display panel 200 further includes a source driver SD and a plurality of groups of switch controller groups SW(n).
  • one switch controller group SW(n) corresponds to the same column of sub-pixels P
  • each switch controller group includes a first switch SW1 and a second switch SW2, one end of the first switch SW1 is connected to the first data signal line D1(n) is coupled, the other end of the first switch SW1 is coupled to the source driver SD, one end of the second switch SW2 is coupled to the second data signal line D2(n), and the other end of the first switch SW1 is coupled to the source
  • the pole driver SD is coupled.
  • the first switch SW1 and the second switch SW2 are turned on in time divisions.
  • the first data signal line D1(n) corresponding to odd rows and the second data signal line D2(n) corresponding to even rows in the same column of sub-pixels are connected to a switch controller group SW(n), and Make a switch controller group SW(n) include a first switch SW1 and a second switch SW2.
  • the signal output from the input source driver SD can be controlled to write Into the first data signal line D1(n) or into the second data signal line D2(n).
  • the signal input to the first data signal line D1(n) and the signal input to the second data signal line D2(n) can be controlled, so that one signal can be passed
  • the terminal inputs the reset voltage V int and the data voltage V data to the pixel driving circuit at different time periods, thereby simplifying the circuit design.
  • the signal output by the source driver SD is only written into the first data signal line D(1).
  • the signal output by the source driver SD is only written into the second data signal line D1 (2).
  • the signal output by the source driver may be the reset voltage V int or the data voltage V data .
  • reset voltage V int and the data voltage V data may be the same or different.
  • the specific settings of the two are subject to actual needs.
  • Some embodiments of the present disclosure provide a driving method of the display panel 200, which includes a control method of a plurality of control periods, and each control period includes a first phase P1, a second phase P2, and a third phase P3.
  • the display panel 200 includes the above-mentioned switch controller group SW(n), the source driver SD, a plurality of scanning signal lines G(n), a plurality of first data signal lines D1(n), and a plurality of second data signal lines D2. In the case of (n).
  • the driving method of the display panel 200 in one control period includes:
  • the first control signal terminal GATE_n and the second control signal terminal GATE_(n-1) input the turn-on signal;
  • the source driver controls the first switch SW1 to turn off ,
  • the second switch SW2 is turned on, and provides the initial voltage V int to the second end of the first switch SW1 and the second end of the second switch SW2;
  • the source driver controls the A switch SW1 is turned on, and the second switch SW2 is turned off, and provides the data voltage V data to the second terminal of the first switch SW1 and the second terminal of the second switch SW2.
  • the first control signal terminal GATE_n and the third control signal terminal GATE_(n+1) input the turn-on signal; in the first sub-stage P21 of the second stage P2, the source driver controls the first switch SW1 to turn off , The second switch SW2 is turned on, and provides the data voltage V data to the second end of the first switch SW1 and the second end of the second switch SW2; in the second sub-phase P22 of the second phase P2, the source driver controls the A switch SW1 is turned on, and the second switch SW2 is turned off, and an initial voltage V int is provided to the second terminal of the first switch SW1 and the second terminal of the second switch SW2.
  • the third control signal terminal GATE_(n+1) inputs the turn-on signal; in the first sub-stage P31 of the third stage P3, the source driver controls the first switch SW1 to turn off, and the second switch SW2 to turn on , Provide the initial voltage V int to the second end of the first switch SW1 and the second end of the second switch SW2; in the second sub-phase of the third phase P32, the source driver controls the first switch SW1 to turn on, and the second switch SW2 is turned off, and provides the data voltage V data to the second end of the first switch SW1 and the second end of the second switch SW2.
  • the driving method of the display panel 200 in one control period includes:
  • the first control signal terminal GATE_n and the second control signal terminal GATE_(n-1) input the turn-on signal;
  • the source driver controls the first switch SW1 to turn off ,
  • the second switch SW2 is turned on, and provides the initial voltage V int to the second end of the first switch SW1 and the second end of the second switch SW2;
  • the source driver controls the A switch SW1 is turned on, and the second switch SW2 is turned off, and provides the data voltage V data to the second terminal of the first switch SW1 and the second terminal of the second switch SW2.
  • the first control signal terminal GATE_n and the third control signal terminal GATE_(n+1) input the turn-on signal;
  • the source driver controls the first switch SW1 to be turned on ,
  • the second switch SW2 is turned off, and provides an initial voltage V int to the second end of the first switch SW1 and the second end of the second switch SW2;
  • the source driver controls the first A switch SW1 is turned off, and the second switch SW2 is turned on, and provides the data voltage V data to the second end of the first switch SW1 and the second end of the second switch SW2.
  • the third control signal terminal GATE_(n+1) inputs the turn-on signal; in the first sub-stage P31 of the third stage P3, the source driver controls the first switch SW1 to turn off, and the second switch SW2 to turn on , And provide an initial voltage V int to the second end of the first switch SW1 and the second end of the second switch SW2; in the second sub-phase P32 of the third phase P3, the source driver controls the first switch SW1 to be turned on, The second switch SW2 is turned off, and provides the data voltage V data to the second end of the first switch SW1 and the second end of the second switch SW2.
  • first switch SW1 and the second switch SW1 used in the display panel 200 may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. No restrictions.
  • some embodiments of the present disclosure provide a display device 300 that includes at least the display panel 200 described in any of the above-mentioned embodiments.
  • the display device 300 further includes a frame 101 disposed outside the display panel 200, and a circuit board 102, a display driver integrated circuit (integrated circuit, IC for short), and other components also disposed in the frame 101. Electronic accessories, etc.
  • the beneficial effects that can be achieved by the display device 300 provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display panel 200 provided by some embodiments of the present disclosure, and will not be repeated here.
  • the display device 300 may be any device that displays an image regardless of whether it is moving (for example, video) or fixed (for example, still image), and whether it is text or drawing.
  • the display device can be a mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver/navigator, camera, MP3 player, video camera, game console, watch, clock, calculator, TV Monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, camera-view displays (e.g., rear-view cameras in vehicles), electronic photos , Electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (for example, a display of the image of a piece of jewelry), etc.
  • PDA personal data assistant
  • GPS receiver/navigator GPS receiver/navigator
  • camera MP3 player
  • video camera game console
  • watch clock
  • calculator calculator
  • TV Monitors flat panel displays
  • computer monitors computer monitors
  • automotive displays e
  • the above-mentioned display panel 200 may be: a liquid crystal display substrate (Liquid Crystal Display, LCD for short), an Organic Light Emitting Diode (OLED) display substrate, Quantum Dot Light Emitting Diodes, Abbreviated as QLED) display substrate, etc., this disclosure does not specifically limit this.
  • a liquid crystal display substrate Liquid Crystal Display, LCD for short
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes

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Abstract

一种像素驱动电路（100）。像素驱动电路（100）包括驱动子电路（10）、信号写入子电路（20）、补偿子电路（30）、发光控制子电路（40）和初始化子电路（50）。信号写入子电路（20）分别与数据信号端（DATA）、第一控制信号端（GATE_n）以及驱动子电路（10）耦接。信号写入子电路（20）用于将数据信号端（DATA）的电压作为数据电压（Vdata）写入到驱动子电路（10）。发光控制子电路（40）分别与发光控制端（EM_n）、驱动子电路（10）以及发光器件（D）耦接；发光控制子电路（40）与驱动子电路（10）配合，驱动发光器件（D）发光。初始化子电路（50）用于将数据信号端（DATA）的电压作为复位电压（Vint）传输至补偿子电路（30）。补偿子电路（30）还分别与驱动子电路（10）、第一控制信号端（GATE_n）耦接；补偿子电路（30）用于将来自初始化子电路（50）的复位电压（Vint）传输至驱动子电路（10），以对驱动子电路（10）进行复位。

Description

像素驱动电路、显示面板、驱动方法、显示装置
本申请要求于2020年05月08日提交的、申请号为202010382816.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路、显示面板、驱动方法、显示装置。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)显示装置是目前显示技术领域研究的热点之一，与液晶显示装置(Liquid Crystal Display，LCD)相比，OLED显示装置具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。OLED显示装置包括多个亚像素，各亚像素包括像素驱动电路和发光器件，通过像素驱动电路驱动发光器件发光，从而实现显示。
发明内容
一方面，提供一种像素驱动电路。所述像素驱动电路包括驱动子电路、信号写入子电路、补偿子电路、发光控制子电路和初始化子电路。所述信号写入子电路分别与数据信号端、第一控制信号端以及所述驱动子电路耦接；所述信号写入子电路被配置为：在来自所述第一控制信号端的信号的控制下，将所述数据信号端的电压作为数据电压写入到所述驱动子电路。所述发光控制子电路分别与发光控制端、所述驱动子电路以及所述发光器件耦接；所述发光控制子电路被配置为：在来自所述发光控制端的信号的控制下，与所述驱动子电路配合，驱动所述发光器件发光。所述初始化子电路分别与数据信号端、第二控制信号端以及所述补偿子电路耦接，所述初始化子电路被配置为：在来自所述第二控制信号端的信号的控制下，将所述数据信号端的电压作为复位电压传输至所述补偿子电路。所述补偿子电路还分别与所述驱动子电路、所述第一控制信号端耦接；所述补偿子电路被配置为：在来自所述第一控制信号端的信号的控制下，将来自所述初始化子电路的复位电压传输至所述驱动子电路，以对所述驱动子电路的进行复位。
在一些实施例中，所述补偿子电路还与所述第三控制信号端耦接，所述补偿子电路还被配置为：在来自所述第一控制信号端以及所述第三控制信号端的信号的控制下，将所述驱动晶体管的阈值电压补偿至所述电容的第一端。
在一些实施例中，所述驱动子电路包括驱动晶体管和电容；所述电容的第一端与所述驱动晶体管的栅极耦接。所述信号写入子电路被配置为：在来 自所述第一控制信号端的信号的控制下，将所述数据信号端的电压作为数据电压写入到所述电容的第二端。所述补偿子电路被配置为：在来自第一控制信号端的信号控制下，将来自于所述初始化子电路的复位电压传输至所述驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位。
在一些实施例中，所述驱动子电路还与第一电压端耦接。所述发光控制子电路还分别与所述发光器件的阳极、参考信号端耦接，所述发光器件的阴极与第二电压端耦接；所述发光控制子电路被配置为：在来自所述发光控制端的信号的控制下，将所述参考信号端的参考电压传输至所述电容的第二端，以与所述驱动子电路配合，驱动所述发光器件发光。
在一些实施例中，所述驱动晶体管的第一极与所述第一电压端耦接，所述驱动晶体管的第二极与所述发光控制子电路耦接。
在一些实施例中，所述信号写入子电路包括第一晶体管。所述第一晶体管的栅极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述数据信号端耦接，所述第一晶体管的第二极与所述电容的第二端耦接。
在一些实施例中，所述补偿子电路包括第二晶体管和第三晶体管。所述第二晶体管的栅极与所述第一控制信号端耦接，所述第二晶体管的第一极与所述电容的第一端耦接，所述第二晶体管的第二极与所述初始化子电路耦接。所述第三晶体管的栅极与第三控制信号端耦接，所述第三晶体管的第一极与所述第二晶体管的第二极耦接，所述第三晶体管的第二极与所述驱动晶体管的第二极耦接。
在一些实施例中，所述发光控制子电路包括第四晶体管和第五晶体管。所述第四晶体管的栅极与所述发光控制端耦接，所述第四晶体管的第一极与所述参考信号端耦接，所述第四晶体管的第二极与所述电容的第二端耦接。所述第五晶体管的栅极与所述发光控制端耦接，所述第五晶体管的第一极与所述驱动晶体管的第二极耦接，所述第五晶体管的第二极与所述发光器件的阳极耦接。
在一些实施例中，所述初始化子电路包括第六晶体管。所述第六晶体管的栅极与所述第二控制信号端耦接，所述第六晶体管的第一极与所述数据信号端耦接，所述第六晶体管的第二极与所述补偿子电路耦接。
在一些实施例中，所述信号写入子电路包括第一晶体管，所述补偿子电路包括第二晶体管和第三晶体管，所述发光控制子电路包括第四晶体管和第五晶体管，所述初始化子电路包括第六晶体管。所述第一晶体管的栅极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述数据信号端耦接， 所述第一晶体管的第二极与所述电容的第二端耦接。所述第二晶体管的栅极与所述第一控制信号端耦接，所述第二晶体管的第一极与所述电容的第一端耦接，所述第二晶体管的第二极与所述第六晶体管的第二极耦接。所述第三晶体管的栅极与第三控制信号端耦接，所述第三晶体管的第一极与所述第二晶体管的第二极耦接，所述第三晶体管的第二极与所述驱动晶体管的第二极耦接。所述第四晶体管的栅极与所述发光控制端耦接，所述第四晶体管的第一极与所述参考信号端耦接，所述第四晶体管的第二极与电容的第二端耦接。所述第五晶体管的栅极与所述发光控制端耦接，所述第五晶体管的第一极与所述驱动晶体管的第二极耦接，所述第五晶体管的第二极与所述发光器件的阳极耦接。所述第六晶体管的栅极与所述第二控制信号端耦接，所述第六晶体管的第一极与所述数据信号端耦接，所述第六晶体管的第二极与所述第二晶体管的第二极耦接。
另一方面，提供一种显示面板，所述显示面板包括多个亚像素，每个亚像素对应设置一个如上述任一实施例所述像素驱动电路。
在一些实施例中，所述显示面板还包括多个开关控制器组、源极驱动器、多条扫描信号线、多条第一数据信号线和多条第二数据信号线。同一行亚像素中像素驱动电路的第一控制信号端与同一条扫描信号线耦接。同一列亚像素中奇数行对应的各像素驱动电路中的数据信号端与同一条第一数据信号线耦接；同一列亚像素中偶数行对应的各像素驱动电路中的数据信号端与同一条第二数据信号线耦接。每个开关控制器组均包括第一开关和第二开关，所述第一开关的一端与第一数据信号线耦接，所述第一开关的另一端与源极驱动器耦接；所述第二开关的一端与第二数据信号线耦接，所述第二开关的另一端与源极驱动器耦接。
再一方面，提供一种显示装置，所述显示装置包括如上述任一实施例所述显示面板。
又一方面，提供一种像素驱动电路的驱动方法，所述驱动方法包括多个帧周期，每个帧周期均包括初始化阶段、扫描阶段和发光阶段。所述初始化阶段包括多个行初始化时段，所述扫描阶段包括多个行扫描时段，所述发光阶段包括多个行发光时段。多个行初始化时段中的每个行初始化时段包括：初始化子电路在第二控制信号端传输的开启信号的控制下，将数据信号端的电压作为复位电压传输至补偿子电路；所述补偿子电路在第一控制信号端传输的开启信号的控制下，将传输至所述补偿子电路的所述复位电压传输至驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位。多个行扫描时段中 的每个行扫描时段包括：补偿子电路在第一控制信号端和第三控制信号端分别传输的开启信号的控制下，将驱动晶体管的阈值电压以及第一电压端的第一电压写入电容的第一端；信号写入子电路在所述第一控制信号端传输的开启信号的控制下，将数据信号端的电压作为数据电压写入电容的第二端。多个行发光时段中的每个行发光时段包括：发光控制子电路在发光控制端传输的开启信号的控制下，将参考信号端的参考电压写入所述电容的第二端，以将所述数据电压与参考电压的压差耦合至所述电容的第一端，且在所述第一电压端和所述第二电压端之间形成电流通路。当所述第一电压端和所述第二电压端之间形成电流通路时，通过所述电流通路向发光器件提供驱动电流，驱动发光器件发光。
又一方面，提供一种显示面板的驱动方法，其中，所述显示面板包括如上任一实施例所述的显示面板，所述显示面板的驱动方法包括多个控制周期的驱动方法，每个控制周期均包括第一阶段、第二阶段以及第三阶段。在所述显示面板还包括开关控制器组、源极驱动器、多条扫描信号线和多条第一数据信号线和多条第二数据信号线的情况下，所述显示面板在一个所述控制周期内的驱动方法包括：在所述第一阶段，第一控制信号端、第二控制信号端输入开启信号；在所述第一阶段的第一子阶段，所述源极驱动器控制所述第一开关断开，所述第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第一阶段的第二子阶段，所述源极驱动器控制所述第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压。在所述第二阶段，第一控制信号端、第三控制信号端输入开启信号；在所述第二阶段的第一子阶段，所述源极驱动器控制所述第一开关断开，所述第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压；在所述第二阶段的第二子阶段，所述源极驱动器控制所述第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压。在所述第三阶段，第三控制信号端输入开启信号；在所述第三阶段的第一子阶段，所述源极驱动器控制第一开关断开，第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第三阶段的第二子阶段，所述源极驱动器控制所述第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压。
又一方面，提供另一种显示面板的驱动方法，其中，所述显示面板包括如上任一实施例所述的显示面板，所述显示面板的驱动方法包括多个控制周 期的驱动方法，每个控制周期均包括第一阶段、第二阶段以及第三阶段。在所述显示面板还包括开关控制器组、源极驱动器、多条扫描信号线和多条第一数据信号线和多条第二数据信号线的情况下，所述显示面板在一个所述控制周期内的驱动方法包括：在所述第一阶段，第一控制信号端、第二控制信号端输入开启信号；在所述第一阶段的第一子阶段，所述源极驱动器控制第一开关断开，第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第一阶段的第二子阶段，所述源极驱动器控制第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压。在所述第二阶段，第一控制信号端、第三控制信号端输入开启信号；在所述第二阶段的第一子阶段，所述源极驱动器控制第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第二阶段的第二子阶段，所述源极驱动器控制第一开关断开，第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压。在所述第三阶段，第三控制信号端输入开启信号；在所述第三阶段的第一子阶段，所述源极驱动器控制第一开关断开，第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第三阶段的第二子阶段，所述源极驱动器控制第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据本公开一些实施例的一种像素驱动电路的结构图；
图1B为根据本公开一些实施例的另一种像素驱动电路的结构图；
图1C为根据本公开一些实施例的再一种像素驱动电路的结构图；
图2为根据本公开一些实施例的又一种像素驱动电路的结构图；
图3为根据本公开一些实施例的一种像素驱动电路的驱动方法的流程图；
图4为根据本公开的一些实施例的一种像素驱动方法的时序图；
图5为根据本公开的一些实施例的又一种像素驱动电路的结构图；
图6为根据本公开的一些实施例的又一种像素驱动电路的结构图；
图7为根据本公开的一些实施例的又一种像素驱动电路的结构图；
图8A为根据本公开的一些实施例的显示面板的一种结构图；
图8B为根据本公开的一些实施例的显示面板的另一种结构图；
图9为根据本公开的一些实施例的显示面板的驱动方法的一种时序图；
图10为根据本公开的一些实施例的显示面板的驱动方法的另一种时序图；
图11为根据本公开的一些实施例的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以 上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本文中“用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如图1A所示，本公开一些实施例提供一种像素驱动电路100,包括驱动子电路10、信号写入子电路20、补偿子电路30、发光控制子电路40和初始化子电路50。
信号写入子电路20分别与数据信号端DATA、第一控制信号端GATE_n以及驱动子电路10耦接。信号写入子电路20被配置为：在来自第一控制信号端GATE_n的信号的控制下，将数据信号端DATA的电压作为数据电压V data写入到驱动子电路10。
发光控制子电路40分别与发光控制端EM_n、驱动子电路10以及发光器件D耦接。发光控制子电路40被配置为：在来自发光控制端EM_n的信号的控制下，与驱动子电路10配合，驱动发光器件D发光。
初始化子电路50分别与数据信号端DATA、第二控制信号端GATE_(n-1)以及补偿子电路30耦接。初始化子电路50被配置为：在来自第二控制信号端GATE_(n-1)的信号的控制下，将数据信号端DATA的电压作为复位电压V int传输至补偿子电路30。
补偿子电路30还分别与驱动子电路10、第一控制信号端GATE_n耦接。补偿子电路30被配置为：在来自第一控制信号端GATE_n的信号的控制下，将传输至补偿子电路30的复位电压传输至驱动子电路10，以对驱动子电路10进行复位。
本公开一些实施例提供的像素驱动电路100，其信号写入子电路30和初始化子电路50均耦接至数据信号端DATA。一方面，通过控制信号写入子电路30的导通可以将数据电压V data写入到驱动子电路10，从而可以配合发光控制子电路40的导通来驱动发光器件D发光。另一方面，通过控制初始化子电路50以及补偿子电路30的导通可以将复位电压V int传输至驱动子电路10，从而可以对驱动子电路10进行复位。这样设置，便可以通过一个信号端在不同时段向像素驱动电路100中分别输入复位电压V int和数据电压V data，从而可以减少像素驱动电路100中信号端的数量，进而简化像素驱动电路100的设 计。
在一些示例中，如图1B所示，驱动子电路10包括驱动晶体管DT和电容C；电容C的第一端与驱动晶体管DT的栅极耦接。
信号写入子电路20被配置为：在来自第一控制信号端GATE_n的信号的控制下，将数据信号端的电压作为数据电压V data写入到电容C的第二端。
补偿子电路30被配置为：在来自第一控制信号端GATE_n的信号控制下，将来自于初始化子电路50的复位电压V int传输至驱动晶体管DT的栅极，以对驱动晶体管DT的栅极进行复位。
在一些示例中，继续参照图1B，驱动子电路10还与第一电压端ELVDD耦接。发光控制子电路40还分别与发光器件D的阳极、参考信号端VREF耦接，发光器件D的阴极与第二电压端ELVSS耦接。发光控制子电路40被配置为：在来自发光控制端EM_n的信号的控制下，将参考信号端VREF的参考电压V ref传输至电容C的第二端，以与驱动子电路10配合，驱动发光器件D发光。
可以理解的，电容C的第二端在不同时段分别输入了数据电压V data以及参考电压V ref，在数据电压V data与参考电压V ref不同的情况下，参考电压V ref与数据电压V data的压差TP可以耦合至电容C的第一端。而利用电容C的第一端的电位可以控制驱动晶体管DT的开启，这样便可以配合发光控制子电路40的导通来驱动发光器件D发光。
示例性的，如图1C所示，补偿子电路30还与第三控制信号端GATE_(n+1)耦接，补偿子电路30还被配置为：在来自第一控制信号端GATE_n以及第三控制信号端GATE_(n+1)的信号的控制下，将驱动晶体管DT的阈值电压V th补偿至电容C的第一端。
这样利用第一控制信号端GATE_n和第三控制信号端GATE_(n+1)的信号控制补偿子电路30导通，将阈值电压V th补偿至电容C的第一端，从而可以消除阈值电压V th对发光器件D发光电流的影响，进而保障发光器件D发光的稳定性。
需要说明的是，本公开一些实施例中的“耦接”可以指两者之间直接电连接，或者通过一些器件(例如薄膜晶体管)间接地电连接。
本公开一些实施例提供的像素驱动电路100，可以通过数据信号端DATA分时向像素驱动电路100中输入复位电压V int以及数据电压V data。其中，复位电压V int可用于将像素驱动电路的驱动子电路10中驱动晶体管DT的栅极的电位进行初始化，使该驱动晶体管DT的栅极的电位在行初始化时段之后变为 V int，这样可以使得驱动晶体管DT在不同周期的行初始化时段均从同一栅压偏置状态开始工作；数据电压V data可用于使像素驱动电路的驱动子电路10中电容C的第二端电位变为V data，有利于对后续发光器件D进行发光控制。这样设置，便可以通过一个信号端在不同时段向像素驱动电路分别输入复位电压V int和数据电压V data，从而可以减少像素驱动电路中信号端的数量，进而简化像素驱动电路100的设计。
在一些示例中，如图1C和图2所示，驱动晶体管DT的第一极与第一电压端ELVDD耦接，驱动晶体管DT的第二极与发光控制子电路40耦接。
这样设置，通过控制驱动晶体管DT的栅极以及第一极的电位差，可以控制驱动晶体管DT的开启，从而可以配合发光控制子电路40的导通来驱动发光器件D发光。
在一些示例中，如图2所示，信号写入子电路20包括第一晶体管T1。
第一晶体管T1的栅极与第一控制信号端GATE_n耦接，第一晶体管T1的第一极与数据信号端DATA耦接，第一晶体管T1的第二极与电容C的第二端耦接。
在一些示例中，如图2所示，补偿子电路30包括第二晶体管T2和第三晶体管T3。
示例性的，第二晶体管T2的栅极与第一控制信号端GATE_n耦接，第二晶体管T2的第一极与电容C的第一端耦接，第二晶体管T2的第二极与初始化子电路50耦接。第三晶体管T3的栅极与第三控制信号端GATE_(n+1)耦接，第三晶体管T3的第一极与第二晶体管T2的第二极耦接，第三晶体管T3的第二极与驱动晶体管DT的第二极耦接。
这样设置，通过第二晶体管T2和第三晶体管T3串联，能够有效防止电容C的第一端写入的电压信号因与其耦接的第二晶体管T2漏电而波动，从而可以有效确保发光器件D发光驱动稳定。
在一些示例中，如图2所示，发光控制子电路40包括第四晶体管T4和第五晶体管T5。
示例性的，第四晶体管T4的栅极与发光控制端EM_n耦接，第四晶体管T4的第一极与参考信号端VREF耦接，第四晶体管T4的第二极与电容C的第二端耦接。第五晶体管T5的栅极与发光控制端EM_n耦接，第五晶体管T5的第一极与驱动晶体管DT的第二极耦接，第五晶体管T5的第二极与发光器件D的阳极耦接。
在一些示例中，如图2所示，所述初始化子电路50包括第六晶体管T6。
第六晶体管T6的栅极与第二控制信号端GATE_(n-1)耦接，第六晶体管T6的第一极与数据信号端DATA耦接，第六晶体管T6的第二极与补偿子电路30中第二晶体管T2的第二极耦接。
这样设置，通过第二晶体管T2和第六晶体管T6串联，能够有效防止电容C的第一端写入的电压信号因与其耦接的第二晶体管T2漏电而波动，从而可以有效确保发光器件D发光驱动稳定。
需要说明的是，本公开一些实施例中提到的晶体管可以是第一极为漏极，第二极为源极；也可以是第一极为源极，第二极为漏极，对此不作限定。此外，根据晶体管导电方式的不同，可以将晶体管分为增强型晶体管和耗尽型晶体管；根据制备晶体管所需衬底的不同，可以将晶体管分为薄膜晶体管(Thin Film Transistor，TFT)和金氧半场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)；根据晶体管导电沟道类型的不同，可以将晶体管分为P型晶体管和N型晶体管。在薄膜晶体管为P型晶体管的情况下，薄膜晶体管的第一极可以为源极，第二极则为漏极。又示例性的，在薄膜晶体管为N型晶体管的情况下，薄膜晶体管的第一极可以为漏极，第二极则为源极。
为了便于解释，在本公开一些实施例所提供的像素驱动电路100中，均以增强型P型薄膜晶体管为例进行说明。需要说明的是，本公开的各个实施例包括但不限于此。例如，本公开一些实施例所提供的像素驱动电路100中的一个或多个薄膜晶体管也可以采用N型晶体管，此时，只需将选定类型的薄膜晶体管的各极参照本公开一些实施例中相应薄膜晶体管的各极相应耦接，并且使相应的电压端提供对应的高电平电压或低电平电压即可。
如图3所示，本公开一些实施例提供一种像素驱动电路100的驱动方法，被配置为驱动如前文所述的像素驱动电路100。该驱动方法包括多个帧周期。
如图4所示，每个帧周期均包括初始化阶段、扫描阶段和发光阶段。初始化阶段包括多个行初始化时段，扫描阶段包括多个行扫描时段，发光阶段包括多个行发光时段。
多个行初始化时段中的每个行初始化时段包括：
S1、初始化子电路50在第二控制信号端GATE_(n-1)传输的开启信号的控制下，将数据信号端DATA的电压作为复位电压V int传输至补偿子电路30。补偿子电路30在第一控制信号端GATE_n传输的开启信号的控制下，将传输至补偿子电路30的复位电压V int传输至驱动晶体管DT的栅极，以对驱 动晶体管DT的栅极进行复位。
示例性的，结合图4和图5所示，在行初始化时段，向第一控制信号端GATE_n和第二控制信号端GATE_(n-1)中输入低电平开启信号，向第三控制信号端GATE_(n+1)和发光控制端EM_n输入高电平截止信号。这样可以控制第一晶体管T1、第二晶体管T2以及第六晶体管T6打开，且同时控制第三晶体管T3、第四晶体管T4和第五晶体管T5关闭。与此同时，向数据信号端DATA输入复位电压V int，该复位电压V int通过第六晶体管T6和第二晶体管T2输入至驱动晶体管DT的栅极，使驱动晶体管DT的栅极的电位为V int。
多个行扫描阶段中的每个行扫描时段包括：
S2、补偿子电路30在第一控制信号端GATE_n和第三控制信号端GATE_(n+1)分别传输的开启信号的控制下，将驱动晶体管DT的阈值电压以及第一电压端ELVDD的电压ELvdd写入电容C的第一端。信号写入子电路20在第一控制信号端GATE_n传输的开启信号的控制下，将数据信号端DATA的电压作为数据电压V data写入到电容C的第二端。
示例性的，结合图4和图6所示，向第一控制信号端Gate_n以及第三控制信号端GATE_(n+1)输入低电平开启信号，向第二控制信号端GATE_(n-1)以及发光控制端EM_n输入高电平截止信号。这样可以控制第一晶体管T1、第二晶体管T2以及第三晶体管T3打开，且同时控制第四晶体管T4、第五晶体管T5以及控制第六晶体管T6关闭。与此同时，向数据信号端DATA输入数据电压V data，电容C第二端的电位为V data；且驱动晶体管DT的阈值电压V th以及第一电压端ELVDD的电压ELvdd一同写入电容C的第一端，电容C的第一端的电位为ELvdd+V th。
多个行发光阶段的每个行发光时段包括：
S3、发光控制子电路40在发光控制端EM_n传输的开启信号的控制下，将参考信号端VREF的参考电压V ref传输至电容C的第二端，以将数据电压Vdata与参考电压Vref的压差TP耦合至电容C的第一端，且在第一电压端ELVDD和第二电压端ELVSS之间形成电流通路。
当第一电压端ELVDD和第二电压端ELVSS之间形成电流通路时，通过电流通路向发光器件D提供驱动电流，驱动发光器件D发光。
示例性的，结合图4和图7所示，向第一控制信号端Gate_n和第二控制信号端GATE_(n-1)输入高电平截止信号，向第三控制信号端GATE_(n+1)以及发光控制端EM_n输入低电平开启信号。这样可以控制第一晶体管T1、第二晶体管T2以及第六晶体管T6关闭，且同时控制第三晶体管T3、第四晶 体管T4以及第五晶体管T5打开。与此同时，参考信号端VREF的参考电压V ref输入至电容C的第二端，电容C的第二端的电压由V data跳变至V ref，跳变量(即压差)TP＝V ref-V data，电容C的第一端的电压由于耦合作用，由V th+ELvdd变为V th+ELvdd+V ref-V data，此时，驱动晶体管DT栅极的电压V g＝V th+ELvdd+V ref-V data。这样，此时流经驱动晶体管DT的电流为：
Figure PCTCN2021092180-appb-000001
其中，K为系数，
Figure PCTCN2021092180-appb-000002
为驱动晶体管DT的宽长比，C ox为驱动晶体管DT的栅极绝缘层电容，μ为驱动晶体管DT的载流子迁移率。通过上述公式可知，对于同一像素驱动电路100，流经驱动晶体管DT的电流I(也即发光电流)只与参考电压V ref和数据电压V data有关，而与驱动晶体管DT的阈值电压V th无关，这样便可以实现对驱动晶体管DT的阈值电压V th的补偿，从而可以避免因为驱动晶体管DT的阈值电压V th的变化引起的显示不均的问题。例如，可以设置参考电压V ref小于数据电压V data，从而实现驱动发光器件D发光。
在此基础上，通过分时向数据信号端DATA输入复位电压V int和数据电压V data，不仅可以对像素驱动电路100进行初始化，从而有利于改善显示面板出现短期残像的问题，而且可以将数据信号V data写入电容C，从而方便对发光电流进行控制。本公开一些实施例提供的像素驱动电路100可以通过一个信号端分时向像素驱动电路100输入复位电压V int和数据电压V data，从而可以减少像素驱动电路100中信号端的数量，进而有利于简化像素驱动电路100的设计。
此外，参见图4，由于发光控制端EM_n和第一控制信号端GATE_n传输的信号互为相反信号。例如在图4中的初始化阶段和扫描阶段，发光控制端EM_n传输高电平信号，而第一控制信号端GATE_n此时传输低电平信号，因此，发光控制端EM_n和第一控制信号端GATE_n可以连接同一组GOA电路。示例性的，GOA电路的两个输出端分别连接发光控制端EM_n和第一控制信号端GATE_n，同时，GOA电路的两个输出端分别输出两个相位相反的信号。又示例性的，GOA电路的一个输出端同时连接发光控制端EM_n和第一控制信号端GATE_n，而第一控制信号端GATE_n所对应的第一晶体管T1和第二晶体管T2的晶体管类型与发光控制端EM_n所对应的第四晶体管T4和第五晶体管T5的晶体管类型不同。例如，第一晶体管T1和第二晶体管T2均为P型薄膜晶体管，而第四晶体管T4和第五晶体管T5均为N型薄膜晶体管。又例如，第一晶体管T1和第二晶体管T2均为N型薄膜晶体管，而第四晶体管T4和第五晶体管T5均为P型薄膜晶体管。
这样通过将发光控制端EM_n和第一控制信号端GATE_n耦接至同一组GOA电路中，可以简化GOA电路的设置，减少GOA电路的边框占用面积，从而有利于显示面板窄边框的实现。
如图8A所示，本公开一些实施例还提供一种显示面板200。显示面板200包括多个亚像素P，每个亚像素P中均设置一个如前文的像素驱动电路100。
本公开一些实施例所提供的显示面板200所能实现的有益效果，至少包含与本公开一些实施例所提供的像素驱动电路100所能达到的相同的有益效果，在此不做赘述。
示例性的，显示面板200具有显示区(Active Area，简称AA)和位于显示区AA的至少一侧的周边区BB。上述多个亚像素P均设置在显示区AA内。图8A中以周边区BB围绕显示区AA一圈进行示意，可以理解，本公开并不限于此。
在一些示例中，上述多个亚像素P至少包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素。示例性的，第一颜色、第二颜色和第三颜色可以为三基色(例如红色、绿色和蓝色)。
为了方便说明，本公开一些实施例中以上述多个亚像素P呈矩阵形式排列为例进行说明。在此情况下，沿第一方向(例如图8A中的横向方向X)排列成一排的亚像素P称为同一行亚像素，沿第二方向(例如图8A中的竖向方向Y)排列成一排的亚像素P称为同一列亚像素。
在一些示例中，如图8B所示，显示面板200还包括多条扫描信号线G(n)、多条第一数据信号线D1(n)和多条第二数据信号线D2(n)。
同一行亚像素P对应的各像素驱动电路100中的第一控制信号端GATE_n与同一条扫描信号线G(n)连接；同一行亚像素P对应的各像素驱动电路100中的第二控制信号端GATE_(n-1)与同一条扫描信号线G(n-1)连接；而同一行亚像素P对应的各像素驱动电路100中的第三控制信号端GATE_(n+1)则与同一条扫描信号线G(n+1)连接。
示例性的，对于某一行亚像素P，在该行亚像素P所对应的各像素驱动电路100中的第一控制信号端GATE_1与同一条扫描信号线G(1)连接的情况下；该行亚像素P对应的各像素驱动电路100中的第二控制信号端GATE_0与同一条扫描信号线G(0)连接；而同一行亚像素P对应的各像素驱动电路100中的第三控制信号端GATE_2与同一条扫描信号线G(2)连接。
同一列亚像素P中奇数行对应的各像素驱动电路100中的数据信号端DATA与同一条第一数据信号线D1(n)耦接；同一列亚像素中偶数行对应 的各像素驱动电路中的数据信号端DATA与同一条第二数据信号线D2(n)耦接。
示例性的，如图8B所示，对于某一列亚像素P，其奇数行对应的各像素驱动电路100中的数据信号端DATA与同一条第一数据信号线D1(1)耦接；则其偶数偶数行对应的各像素驱动电路中的数据信号端DATA与同一条第二数据信号线D2(1)耦接。
需要说明的是，对于上述“奇数行”和“偶数行”，可以从显示面板200上第一数据信号线D1(n)的任意一端进行计算。在显示面板200包括源极驱动器SD的情况下，如图8B所示，为了方便说明，本公开一些示例中以第一数据信号线D1(n)靠近源极驱动器SD一端来对“奇数行”和“偶数行”进行计算。
在一些示例中，继续参照图8B，显示面板200还包括源极驱动器SD和多组开关控制器组SW(n)。示例性的，一个开关控制器组SW(n)对应同一列亚像素P，每个开关控制器组均包括第一开关SW1和第二开关SW2，第一开关SW1的一端与第一数据信号线D1(n)耦接，第一开关SW1的另一端与源极驱动器SD耦接，第二开关SW2的一端与第二数据信号线D2(n)耦接，第一开关SW1的另一端与源极驱动器SD耦接。第一开关SW1和第二开关SW2分时开启。
这样设计，通过将同一列亚像素中奇数行对应的第一数据信号线D1(n)和偶数行对应的第二数据信号线D2(n)连接到一个开关控制器组SW(n)，并且使一个开关控制器组SW(n)包括第一开关SW1和第二开关SW2，通过控制第一开关SW1和第二开关SW2的开启和关断，即可控制输入源极驱动器SD输出的信号写入第一数据信号线D1(n)或者写入第二数据信号线D2(n)。这样一来，在不增加源极驱动器数量的情况下，可以实现对输入至第一数据信号线D1(n)和输入第二数据信号线D2(n)的信号的控制，从而可以通过一个信号端在不同时段向像素驱动电路分别输入复位电压V int和数据电压V data，进而可以简化电路设计。
示例性的，参照图8B和图9，当第一开关SW1打开，且第二开关SW2关闭时，源极驱动器SD输出的信号只写入第一数据信号线D(1)。当第一开关SW1关闭，且第二开关SW2打开时，源极驱动器SD输出的信号只写入第二数据信号线D1(2)。其中，源极驱动器输出的信号可以是复位电压V int，也可以是数据电压V data。
需要说明的是，复位电压V int与数据电压V data可以相同，也可以不同。 两者的具体设定以实际需要为准。
本公开一些实施例提供一种显示面板200的驱动方法，包括多个控制周期的控制方法，每个控制周期均包括第一阶段P1、第二阶段P2以及第三阶段P3。
在显示面板200包括上述开关控制器组SW(n)、源极驱动器SD、多条扫描信号线G(n)、多条第一数据信号线D1(n)和多条第二数据信号线D2(n)的情况下。
在一些示例中，如图9所示，显示面板200在一个控制周期内的驱动方法包括：
在第一阶段P1，第一控制信号端GATE_n、第二控制信号端GATE_(n-1)输入开启信号；在第一阶段P1的第一子阶段P11，源极驱动器控制第一开关SW1断开，第二开关SW2导通，并向第一开关SW1的第二端和第二开关SW2的第二端提供初始电压V int；在第一阶段P1的第二子阶段P12，源极驱动器控制第一开关SW1导通，第二开关SW2断开，并向第一开关SW1的第二端和第二开关SW2的第二端提供数据电压V data。
在第二阶段P2，第一控制信号端GATE_n、第三控制信号端GATE_(n+1)输入开启信号；在第二阶段P2的第一子阶段P21，源极驱动器控制第一开关SW1断开，第二开关SW2导通，并向第一开关SW1的第二端和第二开关SW2的第二端提供数据电压V data；在第二阶段P2的第二子阶段P22，源极驱动器控制第一开关SW1导通，第二开SW2关断开，并向第一开关SW1的第二端和第二开关SW2的第二端提供初始电压V int。
在第三阶段P3，第三控制信号端GATE_(n+1)输入开启信号；在第三阶段P3的第一子阶段P31，源极驱动器控制第一开关SW1断开，第二开关SW2导通，向第一开关SW1的第二端和第二开关SW2的第二端提供初始电压V int；在第三阶段P32的第二子阶段，源极驱动器控制第一开关SW1导通，第二开关SW2断开，并向第一开关SW1的第二端和第二开关SW2的第二端提供数据电压V data。
在另一些示例中，如图10所示，显示面板200在一个控制周期内的驱动方法包括：
在第一阶段P1，第一控制信号端GATE_n、第二控制信号端GATE_(n-1)输入开启信号；在第一阶段P1的第一子阶段P11，源极驱动器控制第一开关SW1断开，第二开关SW2导通，并向第一开关SW1的第二端和第二开关SW2的第二端提供初始电压V int；在第一阶段P1的第二子阶段P12，源极驱动器 控制第一开关SW1导通，第二开关SW2断开，并向第一开关SW1的第二端和第二开关SW2的第二端提供数据电压V data。
在第二阶段P2，第一控制信号端GATE_n、第三控制信号端GATE_(n+1)输入开启信号；在第二阶段P2的第一子阶段P21，源极驱动器控制第一开关SW1导通，第二开关SW2断开，并向第一开关SW1的第二端，第二开关SW2的第二端提供初始电压V int；在第二阶段P2的第二子阶段P22，源极驱动器控制第一开关SW1断开，第二开关SW2导通，并向第一开关SW1的第二端和第二开关SW2的第二端提供数据电压V data。
在第三阶段P3，第三控制信号端GATE_(n+1)输入开启信号；在第三阶段P3的第一子阶段P31，源极驱动器控制第一开关SW1断开，第二开关SW2导通，并向第一开关SW1的第二端，第二开关SW2的第二端提供初始电压V int；在第三阶段P3的第二子阶段P32，源极驱动器控制第一开关SW1导通，第二开关SW2断开，并向第一开关SW1的第二端和第二开关SW2的第二端提供数据电压V data。
需要说明的是，本公开的实施例提供的显示面板200中所采用第一开关SW1和第二开关SW1可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例对此不做限制。
在此基础上，通过控制第一开关SW1和第二开关SW2的开关，从而可以控制源极驱动器输出的信号输入至第一数据信号线D1(n)还是输入至第二数据信号线D2(n)，这样一来，在不增加源极驱动器输出的信号的数量的情况下，可以实现对输入至第一数据信号线D1(n)和输入第二数据信号线D2(n)的控制，简化了电路设计。
本领域普通技术人员可以理解：实现上述方法实施例(例如像素驱动电路100的驱动方法和显示面板200的驱动方法)的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
如图11所示，本公开一些实施例提供一种显示装置300，该显示装置300至少包括上述任一实施例所述的显示面板200。
在一些示例中，继续参照图11，显示装置300还包括设置于显示面板200外的框架101，以及同样设置于框架101内的电路板102、显示驱动集成电路(integrated circuit，简称IC)和其他电子配件等。
本公开一些实施例所提供的显示装置300所能实现的有益效果，与本公 开一些实施例所提供的显示面板200所能达到的有益效果相同，在此不做赘述。
该显示装置300可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图画的图像的任何装置。该显示装置可以移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP3播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
需要说明的是，上述显示面板200可以为：液晶显示基板(Liquid Crystal Display，简称LCD)、有机发光二极管(Organic Light Emitting Diode，简称OLED)显示基板、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示基板等，本公开对此不作具体限定。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种像素驱动电路，包括：驱动子电路、信号写入子电路、补偿子电路、发光控制子电路和初始化子电路；
    所述信号写入子电路分别与数据信号端、第一控制信号端以及所述驱动子电路耦接；所述信号写入子电路被配置为：在来自所述第一控制信号端的信号的控制下，将所述数据信号端的电压作为数据电压写入到所述驱动子电路；
    所述发光控制子电路分别与发光控制端、所述驱动子电路以及所述发光器件耦接；所述发光控制子电路被配置为：在来自所述发光控制端的信号的控制下，与所述驱动子电路配合，驱动所述发光器件发光；
    所述初始化子电路分别与数据信号端、第二控制信号端以及所述补偿子电路耦接，所述初始化子电路被配置为：在来自所述第二控制信号端的信号的控制下，将所述数据信号端的电压作为复位电压传输至所述补偿子电路；
    所述补偿子电路还分别与所述驱动子电路、所述第一控制信号端耦接；所述补偿子电路被配置为：在来自所述第一控制信号端的信号的控制下，将来自所述初始化子电路的复位电压传输至所述驱动子电路，以对所述驱动子电路的进行复位。
  2. 根据权利要求1所述的像素驱动电路，其中，所述驱动子电路包括驱动晶体管和电容；所述电容的第一端与所述驱动晶体管的栅极耦接；
    所述信号写入子电路被配置为：在来自所述第一控制信号端的信号的控制下，将所述数据信号端的电压作为数据电压写入到所述电容的第二端；
    所述补偿子电路被配置为：在来自第一控制信号端的信号控制下，将来自于所述初始化子电路的复位电压传输至所述驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位。
  3. 根据权利要求2所述的像素驱动电路，其中，所述驱动子电路还与第一电压端耦接；
    所述发光控制子电路还分别与所述发光器件的阳极、参考信号端耦接，所述发光器件的阴极与第二电压端耦接；所述发光控制子电路被配置为：在来自所述发光控制端的信号的控制下，将所述参考信号端的参考电压传输至所述电容的第二端，以与所述驱动子电路配合，驱动所述发光器件发光。
  4. 根据权利要求2或3所述的像素驱动电路，其中，所述补偿子电路还与所述第三控制信号端耦接，所述补偿子电路还被配置为：在来自所述第一控制信号端以及所述第三控制信号端的信号的控制下，将所述驱动晶体管的阈值电压补偿至所述电容的第一端。
  5. 根据权利要求4所述的像素驱动电路，其中，所述驱动晶体管的第一极与所述第一电压端耦接，所述驱动晶体管的第二极与所述发光控制子电路耦接。
  6. 根据权利要求2～4中任一项所述的像素驱动电路，其中，所述信号写入子电路包括第一晶体管；
    所述第一晶体管的栅极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述数据信号端耦接，所述第一晶体管的第二极与所述电容的第二端耦接。
  7. 根据权利要求2～4中任一项所述的像素驱动电路，其中，所述补偿子电路包括第二晶体管和第三晶体管；
    所述第二晶体管的栅极与所述第一控制信号端耦接，所述第二晶体管的第一极与所述电容的第一端耦接，所述第二晶体管的第二极与所述初始化子电路耦接；
    所述第三晶体管的栅极与第三控制信号端耦接，所述第三晶体管的第一极与所述第二晶体管的第二极耦接，所述第三晶体管的第二极与所述驱动晶体管的第二极耦接。
  8. 根据权利要求2～4中任一项所述的像素驱动电路，其中，所述发光控制子电路包括第四晶体管和第五晶体管；
    所述第四晶体管的栅极与所述发光控制端耦接，所述第四晶体管的第一极与所述参考信号端耦接，所述第四晶体管的第二极与所述电容的第二端耦接；
    所述第五晶体管的栅极与所述发光控制端耦接，所述第五晶体管的第一极与所述驱动晶体管的第二极耦接，所述第五晶体管的第二极与所述发光器件的阳极耦接。
  9. 根据权利要求1～4中任一项所述的像素驱动电路，其中，所述初始化子电路包括第六晶体管；
    所述第六晶体管的栅极与所述第二控制信号端耦接，所述第六晶体管的第一极与所述数据信号端耦接，所述第六晶体管的第二极与所述补偿子电路耦接。
  10. 根据权利要求4所述的像素驱动电路，其中，所述信号写入子电路包括第一晶体管，所述补偿子电路包括第二晶体管和第三晶体管，所述发光控制子电路包括第四晶体管和第五晶体管，所述初始化子电路包括第六晶体管；
    所述第一晶体管的栅极与所述第一控制信号端耦接，所述第一晶体管的第一极与所述数据信号端耦接，所述第一晶体管的第二极与所述电容的第二端耦接；
    所述第二晶体管的栅极与所述第一控制信号端耦接，所述第二晶体管的第一极与所述电容的第一端耦接，所述第二晶体管的第二极与所述第六晶体管的第二极耦接；
    所述第三晶体管的栅极与第三控制信号端耦接，所述第三晶体管的第一极与所述第二晶体管的第二极耦接，所述第三晶体管的第二极与所述驱动晶体管的第二极耦接；
    所述第四晶体管的栅极与所述发光控制端耦接，所述第四晶体管的第一极与所述参考信号端耦接，所述第四晶体管的第二极与电容的第二端耦接；
    所述第五晶体管的栅极与所述发光控制端耦接，所述第五晶体管的第一极与所述驱动晶体管的第二极耦接，所述第五晶体管的第二极与所述发光器件的阳极耦接；
    所述第六晶体管的栅极与所述第二控制信号端耦接，所述第六晶体管的第一极与所述数据信号端耦接，所述第六晶体管的第二极与所述第二晶体管的第二极耦接。
  11. 一种显示面板，包括：多个亚像素，每个亚像素对应设置一个如权利要求1～10中任一项所述像素驱动电路。
  12. 根据权利要求11所述的显示面板，还包括：多个开关控制器组、源极驱动器、多条扫描信号线、多条第一数据信号线和多条第二数据信号线；
    同一行亚像素中像素驱动电路的第一控制信号端与同一条扫描信号线耦接；
    同一列亚像素中奇数行对应的各像素驱动电路中的数据信号端与同一条第一数据信号线耦接；同一列亚像素中偶数行对应的各像素驱动电路中的数据信号端与同一条第二数据信号线耦接；
    每个开关控制器组均包括第一开关和第二开关，所述第一开关的一端与第一数据信号线耦接，所述第一开关的另一端与源极驱动器耦接；所述第二开关的一端与第二数据信号线耦接，所述第二开关的另一端与源极驱动器耦接。
  13. 一种显示装置，包括：
    如权利要求11或12所述显示面板。
  14. 一种像素驱动电路的驱动方法，包括：多个帧周期；
    每个帧周期均包括初始化阶段、扫描阶段和发光阶段；所述初始化阶段包括多个行初始化时段，所述扫描阶段包括多个行扫描时段，所述发光阶段包括多个行发光时段；
    多个行初始化时段中的每个行初始化时段包括：
    初始化子电路在第二控制信号端传输的开启信号的控制下，将数据信号端的电压作为复位电压传输至补偿子电路；所述补偿子电路在第一控制信号端传输的开启信号的控制下，将传输至所述补偿子电路的所述复位电压传输至驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位；
    多个行扫描时段中的每个行扫描时段包括：
    补偿子电路在第一控制信号端和第三控制信号端分别传输的开启信号的控制下，将驱动晶体管的阈值电压以及第一电压端的第一电压写入电容的第一端；信号写入子电路在所述第一控制信号端传输的开启信号的控制下，将数据信号端的电压作为数据电压写入电容的第二端；
    多个行发光时段中的每个行发光时段包括：
    发光控制子电路在发光控制端传输的开启信号的控制下，将参考信号端的参考电压写入所述电容的第二端，以将所述数据电压与参考电压的压差耦合至所述电容的第一端，且在所述第一电压端和所述第二电压端之间形成电流通路；
    当所述第一电压端和所述第二电压端之间形成电流通路时，通过所述电流通路向发光器件提供驱动电流，驱动发光器件发光。
  15. 一种显示面板的驱动方法，其中，所述显示面板包括如权利要求11所述的显示面板，所述显示面板的驱动方法包括多个控制周期的驱动方法，每个控制周期均包括第一阶段、第二阶段以及第三阶段；在所述显示面板还包括开关控制器组、源极驱动器、多条扫描信号线和多条第一数据信号线和多条第二数据信号线的情况下，所述显示面板在一个所述控制周期内的驱动方法包括：
    在所述第一阶段，第一控制信号端、第二控制信号端输入开启信号；在所述第一阶段的第一子阶段，所述源极驱动器控制所述第一开关断开，所述第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第一阶段的第二子阶段，所述源极驱动器控制所述第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压；
    在所述第二阶段，第一控制信号端、第三控制信号端输入开启信号；在 所述第二阶段的第一子阶段，所述源极驱动器控制所述第一开关断开，所述第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压；在所述第二阶段的第二子阶段，所述源极驱动器控制所述第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；
    在所述第三阶段，第三控制信号端输入开启信号；在所述第三阶段的第一子阶段，所述源极驱动器控制第一开关断开，第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第三阶段的第二子阶段，所述源极驱动器控制所述第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压。
  16. 一种显示面板的驱动方法，其中，所述显示面板包括如权利要求11所述的显示面板，所述显示面板的驱动方法包括多个控制周期的驱动方法，每个控制周期均包括第一阶段、第二阶段以及第三阶段；在所述显示面板还包括开关控制器组、源极驱动器、多条扫描信号线和多条第一数据信号线和多条第二数据信号线的情况下，所述显示面板在一个所述控制周期内的驱动方法包括：
    在所述第一阶段，第一控制信号端、第二控制信号端输入开启信号；在所述第一阶段的第一子阶段，所述源极驱动器控制第一开关断开，第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第一阶段的第二子阶段，所述源极驱动器控制第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压；
    在所述第二阶段，第一控制信号端、第三控制信号端输入开启信号；在所述第二阶段的第一子阶段，所述源极驱动器控制第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第二阶段的第二子阶段，所述源极驱动器控制第一开关断开，第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压；
    在所述第三阶段，第三控制信号端输入开启信号；在所述第三阶段的第一子阶段，所述源极驱动器控制第一开关断开，第二开关导通，并向所述第一开关的第二端和所述第二开关的第二端提供初始电压；在所述第三阶段的第二子阶段，所述源极驱动器控制第一开关导通，第二开关断开，并向所述第一开关的第二端和所述第二开关的第二端提供数据电压。
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