WO2021218125A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2021218125A1
WO2021218125A1 PCT/CN2020/130380 CN2020130380W WO2021218125A1 WO 2021218125 A1 WO2021218125 A1 WO 2021218125A1 CN 2020130380 W CN2020130380 W CN 2020130380W WO 2021218125 A1 WO2021218125 A1 WO 2021218125A1
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Prior art keywords
pattern
mask layer
forming
parallel
patterns
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PCT/CN2020/130380
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English (en)
French (fr)
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周震
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长鑫存储技术有限公司
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Priority to EP20933278.2A priority Critical patent/EP3971945A4/en
Priority to US17/396,695 priority patent/US11972953B2/en
Publication of WO2021218125A1 publication Critical patent/WO2021218125A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a semiconductor structure and a method of forming the same.
  • Dynamic random access memory is a kind of semiconductor memory widely used in modern intelligent systems. As the feature size of semiconductor integrated circuit devices continues to shrink, the critical size of dynamic random access memory is gradually approaching the physical limit of optical lithography. Therefore, more severe challenges are presented to semiconductor manufacturing technology.
  • the memory cells in the memory storage array are formed on the active area (AA).
  • the size of the active area array becomes smaller and smaller. Due to the limitations of photolithography, etching and other technologies, manufacturing The active area of the array arrangement is increasingly difficult. Therefore, how to use semiconductor technology to form small-sized discrete active regions arranged in an array to improve the memory yield is a technical problem that needs to be solved urgently.
  • the purpose of the present invention is to provide a semiconductor structure and a method of forming the same, which can improve the problems existing in the process of forming small-sized discrete active regions arranged in an array in the prior art.
  • an embodiment of the present invention provides a method for forming a semiconductor structure, including:
  • a substrate is provided, a first mask layer is formed on the substrate, and a plurality of parallel-arranged strip-shaped first patterns are formed in the first mask layer for forming a plurality of parallel-arranged strips in the substrate Continuous active area;
  • a second mask layer is formed on the first mask layer, and a plurality of parallel elongated second patterns are formed in the second mask layer;
  • a third mask layer is formed on the second mask layer, and a plurality of elongated third patterns arranged in parallel are formed in the third mask layer, wherein the second pattern crosses the third pattern Overlapping, the second graphic and the third graphic are used to divide the first graphic at a predetermined position;
  • the first mask layer, the second mask layer, and the third mask layer as masks, etch to the substrate layer by layer, and add the first pattern and the second pattern to the substrate. And the third pattern are transferred into the substrate to form a plurality of discrete active regions arranged in an array.
  • forming a second mask layer on the first mask layer, and forming a plurality of parallel elongated second patterns in the second mask layer includes: on the first mask layer A first sacrificial layer is formed, and a plurality of elongated fourth patterns arranged in parallel are formed in the first sacrificial layer; a mask material is formed on the sidewalls of the fourth pattern, and the first sacrificial layer is removed, leaving The sidewall mask material of the fourth pattern is used to form the second mask layer.
  • forming a third mask layer on the second mask layer, and forming a plurality of elongated third patterns arranged in parallel in the third mask layer includes: on the second mask layer A second sacrificial layer is formed, and a plurality of elongated fifth patterns arranged in parallel are formed in the second sacrificial layer; a mask material is formed on the sidewalls of the fifth pattern, and the second sacrificial layer is removed, leaving The sidewall mask material of the fifth pattern is used to form the third mask layer.
  • the angle between the second graphic and the first graphic is 65 degrees to 75 degrees.
  • the angle between the second graphic and the third graphic is 90 degrees.
  • the center distance between the plurality of fourth patterns arranged in parallel is 4 to 5 times the center distance between the plurality of first patterns arranged in parallel, and the plurality of fifth patterns arranged in parallel
  • the distance between the centers is 4 to 5 times the distance between the centers of the first patterns arranged in parallel.
  • the angle between the second graphic and the third graphic is 45 degrees to 55 degrees.
  • the center distance between the plurality of fourth patterns arranged in parallel is 4 to 5 times the center distance between the plurality of first patterns arranged in parallel, and the plurality of fifth patterns arranged in parallel
  • the distance between the centers is 3 to 4 times the distance between the centers of the first patterns arranged in parallel.
  • the use of the second graphic and the third graphic to divide the first graphic at a predetermined position includes: dividing the first graphic by using an overlapping area of the second graphic and the third graphic .
  • the use of the second pattern and the third pattern to divide the first pattern at a predetermined position further includes: forming a second complementary mask by using the second pattern on the second mask layer Layer, the second complementary mask layer is formed with a second complementary pattern including an area outside the second pattern; the second pattern on the third mask layer is used to form a third complementary mask layer, A third complementary pattern including an area other than the third pattern is formed in the third complementary mask layer; the first pattern is divided by the non-overlapping area of the second complementary pattern and the third complementary pattern.
  • the substrate includes an array area, and the first pattern, the second pattern, and the third pattern are all formed at least in the array area.
  • a fourth mask layer is formed on the third mask layer, a sixth pattern is formed in the fourth mask layer, and the sixth pattern covers at least part of the edge position of the array area The second graphic and the third graphic.
  • the sixth pattern also covers at least a secondary active region at the edge of the array region that is less than the length of the discrete active region at the end of the continuous active region; at the same time, the first mask layer, The second mask layer, the third mask layer, and the fourth mask layer are used as mask layers, and the first pattern, the second pattern, the third pattern, and the first pattern are used as mask layers.
  • the six patterns are transferred into the substrate to form discrete active regions arranged in an array, wherein the secondary active regions are not located at the edge of the array region.
  • the first pattern is formed by a self-aligned double patterning technique.
  • the array area is a storage array area of a dynamic random access memory.
  • the material of the mask layer includes: at least one of silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, single crystal silicon, and carbon.
  • An embodiment of the present invention also provides a semiconductor structure, including:
  • a semiconductor substrate which forms a plurality of discrete active regions arranged in an array
  • the discrete active region is formed based on any one of the above semiconductor structure forming methods.
  • an embodiment of the present invention is based on a larger-size photolithography pattern, forming a multilayer mask layer on the surface of the semiconductor substrate, and by rationally designing the multilayer mask
  • the patterns on the layers use these reasonably designed mask layers to obtain discrete active regions arranged in a smaller size array, which reduces the process difficulty and improves the yield of the semiconductor structure.
  • FIGS. 1 to 10 are schematic diagrams of structures obtained by sequentially implementing various steps in a method for forming a semiconductor structure according to an embodiment of the present invention
  • 11 to 18 are schematic top views of semiconductor structures formed in various embodiments of the present invention.
  • A-A1, B-B1 direction; 100: substrate; 110: first mask layer; 120: second mask layer; 130: third mask layer; 111: first pattern; 222: second pattern ; 333: the third figure;
  • 444 the fourth pattern; 555: the fifth pattern; 666: the sixth pattern; 222”: the second complementary pattern; 333”: the third complementary pattern; 210: the first sacrificial layer; 220: the second sacrificial layer; 112: Isolation layer;
  • FIG. 1 to FIG. 10 Please refer to FIG. 1 to FIG. 10 for a method for forming a semiconductor structure according to a first embodiment of the present invention.
  • Step 1 Referring to FIG. 1, a substrate 100 is provided. A first mask layer 110 is formed on the surface of the substrate 100, and a plurality of elongated first patterns arranged in parallel are formed in the first mask layer 110 111. Used to form a plurality of elongated continuous active regions arranged in parallel in the substrate. In this drawing, in order to show the structure more clearly, only three long strip-shaped first graphics 111 are schematically drawn.
  • FIG. 2 is a schematic top view of the elongated first pattern 111.
  • the first pattern 111 may be a rectangle or a curved irregular pattern.
  • the pitch between two adjacent first patterns 111 is a preset value ACT.
  • the first pattern 111 can be formed by a single photolithography, or can be formed by a self-aligned double patterning (SADP) technology.
  • SADP self-aligned double patterning
  • the material of the first pattern 111 in the first mask layer 110 may be at least one of silicon nitride, silicon oxynitride, silicon dioxide, polysilicon, silicon carbide, silicon nitride, and carbon.
  • another material different from the material of the first pattern 111 can be formed as the isolation layer 112, and the other material and the material of the first pattern 111 should be in At least one etching or etching condition has a sufficient etching selectivity ratio.
  • the substrate 100 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, a silicon-on-insulator substrate, or a sapphire substrate.
  • the substrate 100 is a single crystal substrate or a polycrystalline substrate. At the bottom, it may also be an intrinsic silicon substrate or a doped silicon substrate, and further, it may be an N-type single crystal silicon substrate or a P-type single crystal silicon substrate.
  • Step 2 A second mask layer 120 is formed on the first mask layer 110, and a plurality of parallel elongated second patterns 222 are formed in the second mask layer 120.
  • the method of forming the second mask layer 120 on the first mask layer 110 includes:
  • a first sacrificial layer 210 is deposited on the surface of the first mask layer 110 through a deposition process.
  • the specific deposition method of the first sacrificial layer may be various.
  • a chemical vapor deposition method is used to deposit a first sacrificial layer 210 with a predetermined thickness distribution on the surface of the first mask layer 110.
  • the material of the first sacrificial layer may include, but is not limited to, silicon dioxide, doped silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, single crystal silicon, carbon, and the like.
  • FIG. 14 is a top view of an embodiment of the semiconductor structure.
  • a plurality of elongated fourth patterns 444 arranged in parallel are formed in the first sacrificial layer 210.
  • the sidewalls of 444 form the mask material 300.
  • the mask material 300 may be directly formed on the sidewalls of the fourth pattern 444; or the mask material may be deposited entirely on the fourth pattern 444 first, and then etched to leave only the mask material on the fourth pattern 444.
  • the mask material 300 on the sidewall of the fourth pattern 444 Referring to FIG.
  • FIG. 5 is a schematic top view of the second graphics 222. (It should be noted that FIG. 14 is only to illustrate the positional relationship of the graphics in an embodiment of the present invention, and is not necessarily the actual top view presented in a certain step.)
  • the first sacrificial layer 210 may be removed by using a wet etching process or a dry etching process.
  • a suitable etchant or corrosive agent should be selected.
  • the second pattern 222 extends along the A-A1 direction, and the second pattern 222 may be rectangular. Due to the above process steps, the edge positions of every two adjacent second patterns 222 may be connected to At the same time, because the edge position will eventually be trimmed (trim), the connection of the edge position will not affect the formation of the discrete active regions distributed in the array. (It should be noted that the dimensions in the figure are only indicative, and do not represent the true ratio.)
  • the second mask layer 120 may include other materials other than the second pattern 222 as the isolation layer 223, and the isolation layer 223 may be formed after the second pattern 222 is formed.
  • the top surface of the isolation layer 223 may be flush with the top surface of the second pattern 222, and only fill other areas other than the second pattern 222; the top surface of the isolation layer 223 may also be higher than the top surface of the second pattern 222
  • the top surface of the 222 that is, the isolation layer 223 not only fills the area between the adjacent second patterns 222, but also covers the surface of the second pattern 222.
  • the material of the isolation layer 223 and the second pattern 222 has a sufficient etching selection ratio.
  • the isolation layer 223 may include, but is not limited to, photoresist, silicon dioxide, doped silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, single crystal silicon, carbon, and the like.
  • Step 3 A third mask layer 130 is formed on the second mask layer 120, and a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer 130, wherein the second pattern 222 overlaps the third graphic 333, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • the method of forming the third mask layer 130 on the second mask layer 120 includes: Please refer to FIGS. 6 and 14.
  • FIG. 14 is a top view of an embodiment of the semiconductor structure.
  • a second sacrificial layer 220 is deposited on the surface of the second mask layer 120.
  • a plurality of elongated fifth patterns 555 arranged in parallel are formed in the second sacrificial layer 220, and a mask material 300 is formed on the sidewalls of the fifth patterns 555.
  • FIGS. 6, 7 and 14, removed The second sacrificial layer 220 leaves the sidewall mask material of the fifth pattern 555 to form the third mask layer 130.
  • a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer. (It should be noted that the sidewall mask material in this step and the sidewall mask material in the previous step can be the same material or different materials, and there are no restrictions on this.)
  • the second graphic 222 overlaps the third graphic 333, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • A-A1 is the extending direction of the second pattern 222
  • B-B1 is the extending direction of the third pattern 333.
  • the present embodiment sets the angle between the second pattern 222 and the first pattern 111 to be 65 degrees to 75 degrees. It can also be between 68 degrees and 72 degrees, or 70.15 degrees. In this embodiment, the angle between the second graphic 222 and the third graphic 333 is set to 90 degrees.
  • the center distance between two adjacent fourth graphics 444 is between 4 and 5 times the center distance between two adjacent first graphics 111 (the preset value ACT), or it may be 4 Between 4.5 times and 4.35 times.
  • the center distance between two adjacent fifth graphics 555 is between 4 and 5 times the center distance between two adjacent first graphics 111 (the preset value ACT), or it may be 4 To 4.5 times, it can also be 4.35 times.
  • the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position including: using the second graphic 222 and the third graphic
  • the overlapping area of the graphic 333 divides the first graphic 111.
  • the dashed circle represents a predetermined position where the first graphic 111 is cut by the overlapping area of the second graphic 222 and the third graphic 333.
  • the preset positions shown in FIG. 10 and FIG. 15 are all represented by circles, the overlapping area of the second graphic 222 and the third graphic 333 is not limited to a circle, which is only for illustration. In the actual process, it may be circular or irregular, which is not limited in the embodiment of the present invention.
  • the substrate 100 includes an array area, and the first pattern 111, the second pattern 222, and the third pattern 333 are all formed at least in the array area.
  • FIG. 15 is only to illustrate how to use the second graphic 222 and the third graphic 333 to divide the first graphic 111 in an embodiment, so that the first graphic is a continuous strip. 111 does not show continuity at the predetermined position, it is only a schematic diagram.
  • Step 4 Using the first mask layer 110, the second mask layer 120, and the third mask layer 130 as masks, etch the substrate 100 layer by layer, and remove the first mask layer
  • the pattern 111, the second pattern 222, and the third pattern 333 are transferred into the substrate 100 to form a plurality of discrete active regions arranged in an array, as shown in FIG. 18.
  • a multi-layer mask layer is formed on the surface of the semiconductor substrate, and the patterns on the multi-layer mask layer are rationally designed, and these masks with rationally designed patterns are used. Layers to obtain discrete active regions arranged in a smaller size array, which reduces the process difficulty, increases the productivity, and improves the yield of the semiconductor structure.
  • the large-size lithography pattern here refers to a pattern with a larger pitch that is easier to manufacture, and a small-size pattern refers to a pattern with a smaller pitch that is relatively difficult to manufacture.
  • the second embodiment of the present invention also provides another method for forming a semiconductor structure.
  • Step 1 Referring to FIG. 1, a substrate 100 is provided. A first mask layer 110 is formed on the surface of the substrate 100, and a plurality of elongated first patterns arranged in parallel are formed in the first mask layer 110 111. Used to form a plurality of elongated continuous active regions arranged in parallel in the substrate.
  • FIG. 2 is a schematic top view of the elongated first pattern 111.
  • the first pattern 111 may be a rectangle or a curved irregular pattern.
  • the pitch between two adjacent first patterns 111 is a preset value ACT.
  • the first pattern 111 can be formed by a single photolithography, or can be formed by a self-aligned double patterning (SADP) technology.
  • SADP self-aligned double patterning
  • Step 2 A second mask layer 120 is formed on the first mask layer 110, and a plurality of parallel elongated second patterns 222 are formed in the second mask layer 120.
  • the method of forming the second mask layer 120 on the first mask layer 110 includes: referring to FIG. 3, depositing a first sacrificial layer 210 on the surface of the first mask layer 110 through a deposition process.
  • FIG. 11 is a top view of the second embodiment of the semiconductor structure.
  • a plurality of elongated fourth patterns 444 arranged in parallel are formed in the first sacrificial layer 210.
  • the sidewalls of 444 form the mask material 300.
  • the mask material 300 may be directly formed on the sidewalls of the fourth pattern 444; or the mask material may be deposited entirely on the fourth pattern 444 first, and then etched to leave only the mask material on the fourth pattern 444.
  • the mask material 300 on the sidewall of the fourth pattern 444 Referring to FIG.
  • FIG. 5 is a schematic top view of the second graphics 222. (It should be noted that FIG. 11 is only to illustrate the positional relationship of the graphics in an embodiment of the present invention, and is not necessarily the actual top view presented in a certain step.)
  • Step 3 A third mask layer 130 is formed on the second mask layer 120, and a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer 130, wherein the second pattern 222 overlaps the third graphic 333, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • the method of forming the third mask layer 130 on the second mask layer 120 includes: refer to FIGS. 6, 11, and 12, and FIGS. 11 and 12 are top views of embodiments of the semiconductor structure.
  • the second sacrificial layer 220 is deposited on the surface of the second mask layer 120 through a deposition process.
  • a plurality of elongated fifth patterns 555 arranged in parallel are formed in the second sacrificial layer 220; a mask material 300 is formed on the sidewalls of the fifth patterns 555.
  • the second sacrificial layer 220 is removed, leaving the sidewall mask material of the fifth pattern 555 to form the third mask layer 130.
  • a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer.
  • the sidewall mask material in this step and the sidewall mask material in the previous step can be the same material or different materials, and there are no restrictions on this.
  • the second graphic 222 overlaps the third graphic 333, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • A-A1 is the extending direction of the second pattern 222
  • B-B1 is the extending direction of the third pattern 333.
  • the present embodiment sets the angle between the second pattern 222 and the first pattern 111 to be 65 degrees to 75 degrees. It can also be between 68 degrees and 72 degrees, or 70.15 degrees. In this embodiment, the angle between the second graphic 222 and the third graphic 333 is set to be between 45 degrees and 55 degrees, may also be between 48 degrees and 52 degrees, or may be 49.1 degrees.
  • the center distance between the plurality of fourth patterns 444 arranged in parallel is between 4 and 5 times the center distance between two adjacent first patterns 111 (the preset value ACT), or it may be 4 To 4.5 times, it can also be 4.25 times.
  • the center distance between the plurality of the fifth patterns 555 arranged in parallel is between 3 to 4 times the center distance between the two adjacent first patterns 111 (the preset value ACT), and it may also be It is between 3 to 3.5 times, and can also be 3.21 times.
  • the use of the second graphic 222 and the third graphic 333 to divide the first graphic 111 at a predetermined position includes: using the overlapping area of the second graphic 222 and the third graphic 333 to divide the Mentioned first graphic 111.
  • a dotted circle represents a predetermined position where the first graphic 111 is cut by the overlapping area of the second graphic 222 and the third graphic 333.
  • the preset positions shown in FIG. 10 and FIG. 12 are all represented by circles, the overlapping area of the second graphic 222 and the third graphic 333 is not limited to a circle, which is only for illustration. In the actual process, it may be circular or irregular, which is not limited in the embodiment of the present invention.
  • the substrate 100 includes an array area, and the first pattern 111, the second pattern 222, and the third pattern 333 are all formed at least in the array area.
  • FIG. 12 is only to illustrate how to use the second graphic 222 and the third graphic 333 to divide the first graphic 111 in the embodiment, so the first graphic 111 is a continuous strip. It does not show continuity at the predetermined position, it is only a schematic diagram.
  • Step 4 Using the first mask layer 110, the second mask layer 120, and the third mask layer 130 as masks, etch the substrate 100 layer by layer, and remove the first mask layer
  • the pattern 111, the second pattern 222, and the third pattern 333 are transferred into the substrate 100 to form a plurality of discrete active regions arranged in an array, as shown in FIG. 18.
  • This embodiment is different from the first embodiment in that the number of angles between the second graphic 222 and the third graphic 333 is set to be different. Those skilled in the art can make settings according to actual conditions, and it is not limited to this embodiment.
  • a multi-layer mask layer is also formed on the surface of the semiconductor substrate based on a larger-size photolithography pattern.
  • these reasonably designed masks are used.
  • the film layer obtains discrete active regions arranged in a smaller size array, which reduces the process difficulty, improves the yield of the semiconductor structure, and increases the productivity. Among them, the meaning of large size and small size is the same as the previous text.
  • the third embodiment of the present invention also provides another method for forming a semiconductor structure.
  • Step 1 Referring to FIG. 1, a substrate 100 is provided. A first mask layer 110 is formed on the surface of the substrate 100, and a plurality of elongated first patterns arranged in parallel are formed in the first mask layer 110 111. Used to form a plurality of elongated continuous active regions arranged in parallel in the substrate.
  • FIG. 2 is a schematic top view of the elongated first pattern 111.
  • a plurality of elongated first patterns 111 are schematically drawn.
  • Step 2 A second mask layer 120 is formed on the first mask layer 110, and a plurality of parallel elongated second patterns 222 are formed in the second mask layer 120.
  • the method of forming the second mask layer 120 on the first mask layer 110 includes: referring to FIG. 3, depositing a first sacrificial layer 210 on the surface of the first mask layer 110 through a deposition process.
  • FIG. 14 is a top view of the embodiment of the semiconductor structure.
  • a plurality of elongated fourth patterns 444 arranged in parallel are formed in the first sacrificial layer 210.
  • a mask material 300 is formed on the sidewall of the fourth pattern 444. Wherein, the mask material 300 may be directly formed on the sidewalls of the fourth pattern 444; or the mask material may be deposited entirely on the fourth pattern 444 first, and then etched to leave only the mask material on the fourth pattern 444. The mask material 300 on the sidewall of the fourth pattern 444. Referring to FIG.
  • FIG. 5 is a schematic top view of the second graphics 222. (It should be noted that FIG. 14 is only to illustrate the positional relationship of the graphics in an embodiment of the present invention, and is not necessarily the actual top view presented in a certain step.)
  • Step 3 A third mask layer 130 is formed on the second mask layer 120, and a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer 130, wherein the second pattern 222 overlaps the third graphic 333, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • the method of forming the third mask layer 130 on the second mask layer 120 includes: Please refer to FIGS. 6 and 14.
  • FIG. 14 is a top view of the semiconductor structure embodiment.
  • a second sacrificial layer 220 is deposited on the surface of the second mask layer 120.
  • a plurality of elongated fifth patterns 555 arranged in parallel are formed in the second sacrificial layer 220; a mask material 300 is formed on the sidewalls of the fifth patterns 555.
  • the second sacrificial layer 220 is removed, leaving the sidewall mask material of the fifth pattern 555 to form the third mask layer 130.
  • a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer. (It should be noted that the sidewall mask material in this step and the sidewall mask material in the previous step can be the same material or different materials, and there are no restrictions on this.)
  • the second graphic 222 and the third graphic 333 overlap, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • A-A1 is the extending direction of the second pattern 222
  • B-B1 is the extending direction of the third pattern 333.
  • the present embodiment sets the angle between the second pattern 222 and the first pattern 111 to be 65 degrees to 75 degrees. It can also be between 68 degrees and 72 degrees, or 70.15 degrees. In this embodiment, the angle between the second graphic 222 and the third graphic 333 is set to 90 degrees.
  • the center distance between two adjacent fourth graphics 444 is between 4 and 5 times the center distance between two adjacent first graphics 111 (the preset value ACT), or it may be 4 To 4.5 times, it can also be 4.25 times.
  • the center distance between two adjacent fifth graphics 555 is between 4 and 5 times the center distance between two adjacent first graphics 111 (the preset value ACT), or it may be 4 To 4.5 times, it can also be 4.25 times.
  • the second pattern 222 and the third pattern 333 are used to divide the first pattern 111 at a predetermined position further includes: referring to FIG. 16, using the first pattern on the second mask layer 120
  • the two patterns 222 form a second complementary mask layer (not shown), and a second complementary pattern 222" including an area other than the second pattern 222 is formed in the second complementary mask layer; using the third mask
  • the third pattern 333 on the film layer 130 forms a third complementary mask layer (not shown), and a third complementary pattern 333 including an area other than the third pattern 333 is formed in the third complementary mask layer "; Use the non-overlapping area of the second complementary pattern 222" and the third complementary pattern 333" to divide the first pattern 111.
  • the dashed circle indicates the predetermined position where the first pattern 111 is cut by the overlapping area of the second complementary pattern 222" and the third complementary pattern 333". It should be noted that although the preset positions shown in FIG. 10 and FIG. 16 are all represented by circles, it does not limit the overlapping area of the second complementary pattern 222" and the third complementary pattern 333" to a circle, which is only used as For illustration, in the actual process, it may be circular or irregular, which is not limited in the embodiment of the present invention.
  • the substrate 100 includes an array area, and the first pattern 111, the second complementary pattern 222", and the third complementary pattern 333" are all formed at least in the array area.
  • FIG. 16 is only to illustrate how the second pattern 222 and the third pattern 333 are used to divide the first pattern 111 in the embodiment, so the first pattern 111 is a continuous strip. It does not show continuity at the predetermined position, it is only a schematic diagram.
  • Step 4 Using the first mask layer 110, the second mask layer 120, and the third mask layer 130 as masks, etch the substrate 100 layer by layer, and remove the first mask layer
  • the pattern 111, the second complementary pattern 222" and the third complementary pattern 333" are transferred into the substrate 100 to form a plurality of discrete active regions arranged in an array, as shown in FIG. 18.
  • This embodiment is different from the first embodiment in that the first pattern 111 is divided by the non-overlapping area of the second complementary pattern 222" and the third complementary pattern 333". Those skilled in the art can make settings according to actual conditions, and are not limited to this embodiment.
  • a multi-layer mask layer is formed on the surface of the semiconductor substrate, and the patterns on the multi-layer mask layer are rationally designed, and these masks with rationally designed patterns are used. Layers to obtain discrete active regions arranged in a smaller size array, which reduces the process difficulty, improves the yield of the semiconductor structure, and increases the productivity.
  • the fourth embodiment of the present invention also provides another method for forming a semiconductor structure.
  • Step 1 Referring to FIG. 1, a substrate 100 is provided. A first mask layer 110 is formed on the surface of the substrate 100, and a plurality of elongated first patterns arranged in parallel are formed in the first mask layer 110 111. Used to form a plurality of elongated continuous active regions arranged in parallel in the substrate.
  • FIG. 2 is a schematic top view of the elongated first pattern 111.
  • the first pattern 111 may be a rectangle or a curved irregular pattern.
  • the pitch between two adjacent first patterns 111 is a preset value ACT.
  • the first pattern 111 can be formed by a single photolithography, or can be formed by a self-aligned double patterning (SADP) technology.
  • SADP self-aligned double patterning
  • Step 2 A second mask layer 120 is formed on the first mask layer 110, and a plurality of parallel elongated second patterns 222 are formed in the second mask layer 120.
  • the method of forming the second mask layer 120 on the first mask layer 110 includes: referring to FIG. 3, depositing a first sacrificial layer 210 on the surface of the first mask layer 110 through a deposition process.
  • FIG. 11 is a top view of an embodiment of the semiconductor structure.
  • a plurality of elongated fourth patterns 444 arranged in parallel are formed in the first sacrificial layer 210.
  • a mask material 300 is formed on the sidewall of the fourth pattern 444. Wherein, the mask material 300 may be directly formed on the sidewalls of the fourth pattern 444; or the mask material may be deposited entirely on the fourth pattern 444 first, and then etched to leave only the mask material on the fourth pattern 444. The mask material 300 on the sidewall of the fourth pattern 444. Referring to FIG.
  • FIG. 5 is a schematic top view of the second graphics 222. (It should be noted that FIG. 11 is only to illustrate the positional relationship of the graphics in an embodiment of the present invention, and is not necessarily the actual top view presented in a certain step.)
  • Step 3 A third mask layer 130 is formed on the second mask layer 120, and a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer 130, wherein the second pattern 222 overlaps the third graphic 333, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • the method of forming the third mask layer 130 on the second mask layer 120 includes: refer to FIGS. 6, 11, and 12, and FIGS. 11 and 12 are top views of embodiments of the semiconductor structure.
  • the second sacrificial layer 220 is deposited on the surface of the second mask layer 120 through a deposition process.
  • a plurality of elongated fifth patterns 555 arranged in parallel are formed in the second sacrificial layer 220; a mask material 300 is formed on the sidewalls of the fifth patterns 555.
  • the second sacrificial layer 220 is removed, leaving the sidewall mask material of the fifth pattern 555 to form the third mask layer 130.
  • a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer.
  • the sidewall mask material in this step and the sidewall mask material in the previous step can be the same material or different materials, and there are no restrictions on this.
  • the second graphic 222 and the third graphic 333 overlap, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • A-A1 is the extending direction of the second pattern 222
  • B-B1 is the extending direction of the third pattern 333.
  • the present embodiment sets the angle between the second pattern 222 and the first pattern 111 to be 65 degrees to 75 degrees. It can also be between 68 degrees and 72 degrees, or 70.15 degrees. In this embodiment, the angle between the second graphic 222 and the third graphic 333 is set to be between 45 degrees and 55 degrees, may also be between 48 degrees and 52 degrees, or may be 49.1 degrees.
  • the center distance between the plurality of fourth patterns 444 arranged in parallel is between 4 and 5 times the center distance between two adjacent first patterns 111 (the preset value ACT), or it may be 4 To 4.5 times, it can also be 4.25 times.
  • the center distance between the plurality of the fifth patterns 555 arranged in parallel is between 3 to 4 times the center distance between the two adjacent first patterns 111 (the preset value ACT), and it may also be It is between 3 to 3.5 times, and can also be 3.21 times.
  • the second pattern 222 and the third pattern 333 are used to divide the first pattern 111 at a predetermined position further includes: referring to FIG. 13, using the first pattern on the second mask layer 120
  • the two patterns 222 form a second complementary mask layer (not shown), and a second complementary pattern 222" including an area other than the second pattern 222 is formed in the second complementary mask layer; using the third mask
  • the third pattern 333 on the film layer 130 forms a third complementary mask layer (not shown), and a third complementary pattern 333 including an area other than the third pattern 333 is formed in the third complementary mask layer "; Use the non-overlapping area of the second complementary pattern 222" and the third complementary pattern 333" to divide the first pattern 111.
  • the dotted circle indicates that the first pattern 111 is cut by the overlapping area of the second complementary pattern 222" and the third complementary pattern 333".
  • the preset positions shown in FIG. 10 and FIG. 13 are all represented by circles, it does not limit the overlapping area of the second complementary pattern 222" and the third complementary pattern 333" to a circle, which is only used as For illustration, in the actual process, it may be circular or irregular, which is not limited in the embodiment of the present invention.
  • the substrate 100 includes an array area, and the first pattern 111, the second complementary pattern 222", and the third complementary pattern 333" are all formed at least in the array area.
  • Step 4 Using the first mask layer 110, the second mask layer 120, and the third mask layer 130 as masks, etch the substrate 100 layer by layer, and remove the first mask layer
  • the pattern 111, the second complementary pattern 222" and the third complementary pattern 333" are transferred into the substrate 100 to form a plurality of discrete active regions arranged in an array, as shown in FIG. 18.
  • This embodiment is different from the first embodiment in that the number of angles between the second graphic 222 and the third graphic 333 is set to be different.
  • the first pattern 111 is divided by the non-overlapping area of the second complementary pattern 222" and the third complementary pattern 333". It can be set according to the actual situation and is not limited to this embodiment.
  • a multi-layer mask layer is formed on the surface of the semiconductor substrate, and the patterns on the multi-layer mask layer are rationally designed, and these masks with rationally designed patterns are used. Layers to obtain discrete active regions arranged in a smaller size array, which reduces the process difficulty, improves the yield of the semiconductor structure, and increases the productivity.
  • the fifth embodiment of the present invention also provides another method for forming a semiconductor structure.
  • Step 1 Referring to FIG. 1, a substrate 100 is provided. A first mask layer 110 is formed on the surface of the substrate 100, and a plurality of elongated first patterns arranged in parallel are formed in the first mask layer 110 111. Used to form a plurality of elongated continuous active regions arranged in parallel in the substrate.
  • FIG. 2 is a schematic top view of the elongated first pattern 111.
  • the first pattern 111 may be a rectangle or a curved irregular pattern.
  • the pitch between two adjacent first patterns 111 is a preset value ACT.
  • the first pattern 111 can be formed by a single photolithography, or can be formed by a self-aligned double patterning (SADP) technology.
  • SADP self-aligned double patterning
  • Step 2 A second mask layer 120 is formed on the first mask layer 110, and a plurality of parallel elongated second patterns 222 are formed in the second mask layer 120.
  • the method of forming the second mask layer 120 on the first mask layer 110 includes: referring to FIG. 3, depositing a first sacrificial layer 210 on the surface of the first mask layer 110 through a deposition process.
  • FIG. 11 is a top view of an embodiment of the semiconductor structure.
  • a plurality of elongated fourth patterns 444 arranged in parallel are formed in the first sacrificial layer 210.
  • a mask material 300 is formed on the sidewall of the fourth pattern 444. Wherein, the mask material 300 may be directly formed on the sidewalls of the fourth pattern 444; or the mask material may be deposited entirely on the fourth pattern 444 first, and then etched to leave only the mask material on the fourth pattern 444. The mask material 300 on the sidewall of the fourth pattern 444. Referring to FIG.
  • FIG. 5 is a schematic top view of the second graphics 222. (It should be noted that FIG. 11 is only to illustrate the positional relationship of the graphics in the embodiment of the present invention, and is not necessarily the actual top view presented in a certain step.)
  • Step 3 A third mask layer 130 is formed on the second mask layer 120, and a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer 130, wherein the second pattern 222 overlaps the third graphic 333, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • the method of forming the third mask layer 130 on the second mask layer 120 includes: please refer to FIG. 6, FIG. 11 and FIG. 12.
  • FIG. 11 and FIG. 12 are top views of the semiconductor structure embodiment.
  • the second sacrificial layer 220 is deposited on the surface of the second mask layer 120 through a deposition process.
  • a plurality of elongated fifth patterns 555 arranged in parallel are formed in the second sacrificial layer 220; a mask material 300 is formed on the sidewalls of the fifth patterns 555.
  • the second sacrificial layer 220 is removed, leaving the sidewall mask material of the fifth pattern 555 to form the third mask layer 130.
  • a plurality of elongated third patterns 333 arranged in parallel are formed in the third mask layer.
  • the sidewall mask material in this step and the sidewall mask material in the previous step can be the same material or different materials, and there are no restrictions on this.
  • the second graphic 222 and the third graphic 333 overlap, and the second graphic 222 and the third graphic 333 are used to divide the first graphic 111 at a predetermined position.
  • A-A1 is the extending direction of the second pattern 222
  • B-B1 is the extending direction of the third pattern 333.
  • the present embodiment sets the angle between the second pattern 222 and the first pattern 111 to be 65 degrees to 75 degrees. It can also be between 68 degrees and 72 degrees, or 70.15 degrees. In this embodiment, the angle between the second graphic 222 and the third graphic 333 is set to be between 45 degrees and 55 degrees, may also be between 48 degrees and 52 degrees, or may be 49.1 degrees.
  • the center distance between the plurality of fourth patterns 444 arranged in parallel is between 4 and 5 times the center distance between two adjacent first patterns 111 (the preset value ACT), or it may be 4 To 4.5 times, it can also be 4.25 times.
  • the center distance between the plurality of the fifth patterns 555 arranged in parallel is between 3 to 4 times the center distance between the two adjacent first patterns 111 (the preset value ACT), and it may also be It is between 3 to 3.5 times, and can also be 3.21 times.
  • the use of the second graphic 222 and the third graphic 333 to divide the first graphic 111 at a predetermined position includes: using the overlapping area of the second graphic 222 and the third graphic 333 to divide the Mentioned first graphic 111.
  • the dotted circle indicates that the first graphic 111 is cut by the overlapping area of the second graphic 222 and the third graphic 333.
  • the predetermined location It should be noted that although the preset positions shown in FIG. 10 and FIG. 12 are all represented by circles, the overlapping area of the second graphic 222 and the third graphic 333 is not limited to a circle, which is only for illustration. In the actual process, it may be circular or irregular, which is not limited in the embodiment of the present invention.
  • the substrate 100 includes an array area, and the first pattern 111, the second pattern 222, and the third pattern 333 are all formed at least in the array area.
  • FIG. 12 is only to illustrate how to use the second graphic 222 and the third graphic 333 to divide the first graphic 111 in the embodiment, so the first graphic 111 is a continuous strip. It does not show continuity at the predetermined position, it is only a schematic diagram.
  • Step 4 Referring to FIG. 17, a fourth mask layer is formed on the third mask layer, a sixth pattern 666 is formed in the fourth mask layer, and the sixth pattern 666 covers the array At least part of the second graphic 222 and the third graphic 333 at the edge of the area.
  • Step 5 The sixth pattern 666 also covers at least the secondary active area (not shown) at the end of the continuous active area at the edge of the array area, which is less than the length of the discrete active area;
  • a mask layer 110, the second mask layer 120, the third mask layer 130, and the fourth mask layer are used as mask layers, and the first pattern 111 and the second pattern 222
  • the third pattern 333 and the sixth pattern 666 are transferred into the substrate to form discrete active regions arranged in an array, wherein the secondary active region is not located at the edge of the array region, as shown in FIG. 18.
  • a fourth mask layer is added to trim the discrete active areas with incomplete edge positions of the array area, so as to improve the process problems that may be caused by defective active areas at the edge positions.
  • the first mask layer, the second mask layer, and the third mask layer of this embodiment are the same as those of the previous embodiment, those skilled in the art should understand that the addition of the first mask layer in this embodiment All four mask layers can be used in the aforementioned first embodiment, second embodiment, third embodiment, and fourth embodiment, which will not be repeated. Those skilled in the art can make settings according to actual conditions and choose whether it is necessary to trim the active area at the edge of the array area after forming the discrete active areas distributed in the array.
  • An embodiment of the present invention also provides a semiconductor structure.
  • the semiconductor structure includes: a substrate and discrete active regions.
  • a number of discrete active regions arranged in an array are formed in the substrate.
  • the discrete active region is formed by the foregoing semiconductor structure forming method embodiment.
  • the dashed circle represents a predetermined position where the first graphic is cut by the overlapping area of the second graphic and the third graphic.
  • the preset positions shown in FIG. 10 are all represented by circles, it does not limit the overlapping area of the second graphic and the third graphic to be circular. It is only for illustration, and it may be possible in the actual process. It is circular or irregular, which is not limited in the embodiment of the present invention.

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Abstract

该发明涉及半导体技术领域，公开了一种半导体结构及其形成方法。该方法包括：提供衬底，在所述衬底上形成第一掩膜层，所述第一掩膜层内形成若干平行排列的长条状第一图形；在所述第一掩膜层上形成第二掩膜层，所述第二掩膜层内形成若干平行排列的长条状第二图形；在所述第二掩膜层上形成第三掩膜层，所述第三掩膜层内形成若干平行排列的长条状第三图形，其中，所述第二图形与所述第三图形交叠，所述第二图形与所述第三图形用于在预定位置分割所述第一图形；以所述第一掩膜层、所述第二掩膜层和所述第三掩膜层作为掩膜，逐层刻蚀至所述衬底，将所述第一图形、所述第二图形和第三图形传递至所述衬底内，形成若干阵列排布的分立有源区。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2020年04月30日递交的中国专利申请号202010361178.4，申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及半导体技术领域，具体涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器是一种广泛应用于现代智能系统的半导体存储器。随着半导体集成电路器件特征尺寸的不断缩小，动态随机存储器的关键尺寸逐渐接近光学光刻的物理极限，因此，给半导体制造技术提出了更加严峻的挑战。
存储器存储阵列中的存储单元形成于有源区(AA，activearea)之上，随着存储密度的增大，有源区阵列尺寸越来越小，由于光刻、蚀刻等技术的限制，导致制造阵列排布的有源区难度愈发增大。因此，如何利用半导体技术形成阵列排布的小尺寸分立有源区，提升存储器良率，是目前亟待解决的技术问题。
发明内容
本发明的目的在于提供一种半导体结构及其形成方法，能够改善现有技术形成阵列排布的小尺寸分立有源区过程中存在的问题。
为解决上述技术问题，本发明的一实施例中提供了一种半导体结构形成方法，包括：
提供衬底，在所述衬底上形成第一掩膜层，所述第一掩膜层内形成若干平行排列的长条状第一图形，用于在衬底内形成若干平行排列的长条状的连续有源区；
在所述第一掩膜层上形成第二掩膜层，所述第二掩膜层内形成若干平行排列的长条状第二图形；
在所述第二掩膜层上形成第三掩膜层，所述第三掩膜层内形成若干平行排列的长条状第三图形，其中，所述第二图形与所述第三图形交叠，所述第二图形与所述第三图形用于在预定位置分割所述第一图形；
以所述第一掩膜层、所述第二掩膜层和所述第三掩膜层作为掩膜，逐层刻蚀至所述衬底，将所述第一图形、所述第二图形和第三图形传递至所述衬底内，形成若干阵列排布的分立有源区。
可选的，在所述第一掩膜层上形成第二掩膜层，所述第二掩膜层内形成若干平行排列的长条状第二图形包括：在所述第一掩膜层上形成第一牺牲层，所述第一牺牲层内形成有若干平行排列的长条状第四图形；在所述第四图形的侧壁形成掩膜材料，去除所述第一牺牲层，留下所述第四图形的侧壁掩膜材料，以形成所述第二掩膜层。
可选的，在所述第二掩膜层上形成第三掩膜层，所述第三掩膜层内形成若干平行排列的长条状第三图形包括：在所述第二掩膜层上形成第二牺牲层，所述第二牺牲层内形成有若干平行排列的长条状第五图形；在所述第五图形的侧壁形成掩膜材料，去除所述第二牺牲层，留下所述第五图形的侧壁掩膜材料，以形成所述第三掩膜层。
可选的，所述第二图形与所述第一图形夹角为65度至75度。
可选的，所述第二图形和所述第三图形夹角为90度。
可选的，若干平行排列的所述第四图形之间的中心距为若干平行排列的所述第一图形之间的中心距的4至5倍，若干所述平行排列的所述第五图形之间的中心距为若干平行排列的所述第一图形之间的中心距的4至5倍。
可选的，所述第二图形和所述第三图形夹角为45度至55度。
可选的，若干平行排列的所述第四图形之间的中心距为若干平行排列的所述第一图形之间的中心距的4至5倍，若干所述平行排列的所述第五图形之间的中心距为若干平行排列的所述第一图形之间的中心距的3至4倍。
可选的，所述第二图形与所述第三图形用于在预定位置分割所述第一图形包括：利用所述第二图形和所述第三图形的交叠区域分割所述第一图形。
可选的，所述第二图形与所述第三图形用于在预定位置分割所述第一图形还包括：利用所述第二掩膜层上的所述第二图形形成第二互补掩膜层，所述第二互补掩膜层内形成有包含所述第二图形以外区域的第二互补图形；利用所述第三掩膜层上的所述第二图形形成第三互补掩膜层，所述第三互补掩膜层内形成有包含所述第三图形以外区域的第三互补图形；利用所述第二互补图形和第三互补图形的非交叠区域分割所述第一图形。
可选的，所述衬底包括阵列区域，所述第一图形、所述第二图形、所述第三图形均至少形成在所述阵列区域内。
可选的，在所述第三掩膜层上形成第四掩膜层，所述第四掩膜层内形成有第六图形，所述第六图形盖住所述阵列区边缘位置的至少部分所述第二图形和所述第三图形。
可选的，所述第六图形还至少盖住所述阵列区边缘位置处的连续有源区端部的小于分立有源区长度的次有源区；同时以所述第一掩膜层、所述第二掩膜层、所述第三掩膜层和所述第四掩膜层作为掩膜层，将所述第一图形、所述第二图形、所述第三图形、所述第六图形传递至衬底内，以形成阵列排布的分立有源区，其中所述阵列区边缘位置无所述次有源区。
可选的，所述第一图形由自对准双重图形化技术形成。
可选的，所述阵列区域为动态随机存储器的存储阵列区域。
可选的，所述掩膜层的材料包括：二氧化硅、氮化硅、氮氧化硅、多晶硅、单晶硅、碳中的至少一种。
本发明的一实施例还提供一种半导体结构，包括：
半导体衬底，所述半导体衬底形成若干阵列排布的分立有源区；
分立有源区，基于任意一项上述半导体结构形成方法形成。
本发明的优点在于，相较于现有的半导体制造技术，本发明的一实施例基于较大尺寸的光刻图形，在半导体衬底表面形成多层掩膜层，通过合理设计多层掩膜层上的图形，利用这些合理设计过图形的掩膜层，获得较小尺寸阵列排布的分立有源区，降低了工艺难度，提升了半导体结构的良率。
附图说明
图1至图10为本发明的一实施例的半导体结构形成方法依次实施各步骤所得到结构示意图；
图11至图18为本发明的各实施例形成半导体结构的俯视示意图。
附图标记：
A-A1，B-B1：方向；100：衬底；110：第一掩膜层；120：第二掩膜层；130：第三掩膜层；111：第一图形；222：第二图形；333：第三图形；
444：第四图形；555：第五图形；666：第六图形；222”：第二互补图形；333”：第三互补图形；210：第一牺牲层；220：第二牺牲层；112：隔离层；
223：隔离层；300：掩膜材料。
具体实施方式
以下结合附图和具体实施方式对本发明提出的一种半导体结构及其形成方法作进一步详细说明。
请参阅图1至图10，本发明提供的第一实施例的半导体结构的形成方法。
步骤一：请参阅图1，提供衬底100，在所述衬底100表面形成有第一掩膜层110，所述第一掩膜层110内形成有若干平行排列的长条状第一图形111，用于在衬底内形成若干平行排列的长条状的连续有源区。在本附图中，为了能更清楚地显示结构，仅示意性地绘示三个长条状第一图形111。
请参阅图2，其为长条状的第一图形111的俯视示意图，在本附图中，为了能更清楚地显示结构，示意性地绘示多个长条状第一图形111。所述第一图形111可以是长方形，也可以是弯曲的不规则图形，相邻两条所述第一图形111之间的中心距(pitch)为一预设值ACT。可通过一次光刻形成所述第一图形111，也可以通过自对准双重图形化(SADP)技术形成。且本领域内技术人员应当知道，若采用SADP技术形成的所述第一图形111，可能是封闭图形，在图2所示的所述第一图形111的上下边缘位置每两条所述第一图形111可能会连接到一起，类似图5所示的左右边缘。
所述第一掩膜层110内的所述第一图形111的材料可以是氮化硅、氮氧化硅、二氧化硅、多晶硅、碳化硅、氮碳硅、碳中的至少一种，而第一掩膜层110内除所述第一图形111以外的空白位置可以形成与所述第一图形111材料不同的其他材料作为隔离层112，该其他材料和所述第一图形111的材料应在至少一种蚀刻或腐蚀条件下具有足够的蚀刻选择比。
所述衬底100可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底、绝缘体上硅衬底或蓝宝石衬底，另外，衬底100为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是掺杂硅衬底，进一步，可以为N型单晶硅衬底或P型单晶硅衬底。
步骤二：在所述第一掩膜层110上形成第二掩膜层120，所述第二掩膜层120内形成若干平行排列的长条状第二图形222。
具体地说，在所述第一掩膜层110上形成第二掩膜层120的方法包括：
请参阅图3，通过沉积工艺在第一掩膜层110表面沉积第一牺牲层210。本实施例中， 第一牺牲层的具体沉积方式可以是多样的。例如，采用化学气相沉积的方式，在所述第一掩膜层110的表面，沉积预设厚度分布的第一牺牲层210。进一步的，可以控制导入气流的流速、控制导入气流的流量、控制沉积时长或控制沉积温度等手段，通过提高对气流和温度的精度控制，最终在第一掩膜层110的表面得到一层厚度均匀的第一牺牲层210。在本实施例中，第一牺牲层的材料可以包括但不限于二氧化硅、掺杂二氧化硅、氮化硅、氮氧化硅、多晶硅、单晶硅、碳等。
请参阅图3和图14，图14为所述半导体结构一实施例的俯视图，在所述第一牺牲层210内形成有若干平行排列的长条状第四图形444，在所述第四图形444的侧壁形成掩膜材料300。其中，可以直接在所述第四图形444的侧壁形成该掩膜材料300；或者也可以先在所述第四图形444上整体沉积掩膜材料，再通过刻蚀以仅留下在所述第四图形444的侧壁的掩膜材料300。请参阅图4，去除所述第一牺牲层210，留下所述第四图形444的侧壁掩膜材料300，以在所述第二掩膜层120内形成若干平行排列的长条状第二图形222，图5为所述第二图形222的俯视示意图。(需要注意的是，图14仅为了示意本发明一实施例中各图形的位置关系，并不一定是某一步骤中呈现的实际俯视图。)
在本实施例中，可以采用湿法腐蚀工艺或干法蚀刻工艺去除所述第一牺牲层210。但为了在去除所述第一牺牲层210时避免引起对侧壁掩膜材料的过多损伤，应选择合适的刻蚀剂或腐蚀剂。
请参阅图5，所述第二图形222沿A-A1方向延伸，所述第二图形222可以是长方形，由于上述工艺步骤，每两条相邻所述第二图形222边缘位置可能会连接到一起，但由于边缘位置最终会被修整(trim)，因此该边缘位置的连接最终并不会影响阵列分布的分立有源区的形成。(需要注意的是，图中的尺寸仅为示意，并不代表真实的比例。)
需要注意的是，所述第二掩膜层120可以包含所述在第二图形222之外的其他材料作为隔离层223，该隔离层223可以再形成所述第二图形222之后形成。该隔离层223的顶表面可以与所述第二图形222的顶表面齐平，仅填充所述第二图形222以外的其他区域；该隔离层223的顶表面也可以高于所述第二图形222的顶表面，即该隔离层223既填充相邻第二图形222之间的区域，也覆盖所述第二图形222的表面。其中，在至少一种蚀刻或腐蚀条件下，该隔离层223与所述第二图形222的材料具有足够的蚀刻选择比。该隔离层223可以包括但不限于光刻胶、二氧化硅、掺杂二氧化硅、氮化硅、氮氧化硅、多晶硅、单晶硅、碳等。
步骤三：在所述第二掩膜层120上形成第三掩膜层130，所述第三掩膜层130内形成若干平行排列的长条状第三图形333，其中，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。
具体地说，在所述第二掩膜层120上形成第三掩膜层130的方法包括：请参阅图6和图14，图14为所述半导体结构一实施例的俯视图，通过沉积工艺在第二掩膜层120表面沉积第二牺牲层220。所述第二牺牲层220内形成有若干平行排列的长条状第五图形555，在所述第五图形555的侧壁形成掩膜材料300，请参阅图6、图7和图14，去除所述第二牺牲 层220，留下所述第五图形555的侧壁掩膜材料，以形成所述第三掩膜层130。在第三掩膜层内形成若干平行排列的长条状第三图形333。(需要注意的是，此步骤中的侧壁掩膜材料与上一步骤中的侧壁掩膜材料，可以是相同材料，也可以是不同的材料，对此不做任何限定。)
请参阅图8和图15，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。其中，A-A1为第二图形222的延伸方向，B-B1为第三图形333的延伸方向。
具体地说，为了使后续形成的分立有源区排布合理，提高动态随机存储器的存储密度，本实施例设置所述第二图形222与所述第一图形111夹角为65度至75度之间，也可以为68度至72度之间，还可以是70.15度。本实施例设置所述第二图形222和所述第三图形333夹角为90度。相邻两条所述第四图形444之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的4至5倍之间，也可以为其4至4.5倍之间还可以是其4.35倍。相邻两条所述第五图形555之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的4至5倍之间，也可以为其4至4.5倍之间，还可以是其4.35倍。
进一步的，请参阅图10和图15，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111包括：利用所述第二图形222和所述第三图形333的交叠区域分割所述第一图形111。其中，虚线圆圈表示所述第一图形111被所述第二图形222和所述第三图形333的交叠区域分割(cut)的预定位置。需要注意的是，虽然图10和图15中显示预设位置均用圆圈表示，但并不限制所述第二图形222和所述第三图形333的交叠区域为圆形，仅作为示意，在实际工艺中可能为圆形，也可能为不规则图形，本发明的实施例对此不做限定。
进一步的，所述衬底100包括阵列区域，所述第一图形111、所述第二图形222、所述第三图形333均至少形成在所述阵列区域内。需要再注意的是，图15仅是为了示意一实施例中如何利用所述第二图形222和所述第三图形333分割所述第一图形111，因此连续长条状的所述第一图形111在预定位置未显示出连续性，仅为示意图。
步骤四：以所述第一掩膜层110、所述第二掩膜层120和所述第三掩膜层130作为掩膜，逐层刻蚀至所述衬底100，将所述第一图形111、所述第二图形222和第三图形333传递至所述衬底100内，形成若干阵列排布的分立有源区，如图18。
因此，在本实施例中，基于较大尺寸的光刻图形，在半导体衬底表面形成多层掩膜层，通过合理设计多层掩膜层上的图形，利用这些合理设计过图形的掩膜层，获得较小尺寸阵列排布的分立有源区，降低了工艺难度，提高了产能，提升了半导体结构的良率。需要说明的是，此处的大尺寸光刻图形指的更容易制作的中心距(pitch)较大的图形，而小尺寸图形指的是相对难制作的中心距(pitch)较小的图形。
本发明的第二实施例还提供另一种半导体结构的形成方法。
步骤一：请参阅图1，提供衬底100，在所述衬底100表面形成有第一掩膜层110，所述第一掩膜层110内形成有若干平行排列的长条状第一图形111，用于在衬底内形成若干平 行排列的长条状的连续有源区。
请参阅图2，其为长条状的第一图形111的俯视示意图，在本附图中，为了能更清楚地显示结构，示意性地绘示多个长条状第一图形111。所述第一图形111可以是长方形，也可以是弯曲的不规则图形，相邻两条所述第一图形111之间的中心距(pitch)为一预设值ACT。可通过一次光刻形成所述第一图形111，也可以通过自对准双重图形化(SADP)技术形成。且本领域内技术人员应当知道，若采用SADP技术形成的所述第一图形111，可能是封闭图形，在图2所示的所述第一图形111的上下边缘位置每两条所述第一图形111可能会连接到一起，类似图5所示的左右边缘。
步骤二：在所述第一掩膜层110上形成第二掩膜层120，所述第二掩膜层120内形成若干平行排列的长条状第二图形222。
具体地说，在所述第一掩膜层110上形成第二掩膜层120的方法包括：请参阅图3，通过沉积工艺在第一掩膜层110表面沉积第一牺牲层210。
请参阅图3和图11，图11为所述半导体结构第二实施例的俯视图，所述第一牺牲层210内形成有若干平行排列的长条状第四图形444，在所述第四图形444的侧壁形成掩膜材料300。其中，可以直接在所述第四图形444的侧壁形成该掩膜材料300；或者也可以先在所述第四图形444上整体沉积掩膜材料，再通过刻蚀以仅留下在所述第四图形444的侧壁的掩膜材料300。请参阅图4，去除所述第一牺牲层210，留下所述第四图形444的侧壁掩膜材料300，以在所述第二掩膜层120内形成若干平行排列的长条状第二图形222，图5为所述第二图形222的俯视示意图。(需要注意的是，图11仅为了示意本发明一实施例中各图形的位置关系，并不一定是某一步骤中呈现的实际俯视图。)
步骤三：在所述第二掩膜层120上形成第三掩膜层130，所述第三掩膜层130内形成若干平行排列的长条状第三图形333，其中，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。
具体地说，在所述第二掩膜层120上形成第三掩膜层130的方法包括：请参阅图6、图11和图12，图11、图12为所述半导体结构实施例的俯视图，通过沉积工艺在第二掩膜层120表面沉积第二牺牲层220。所述第二牺牲层220内形成有若干平行排列的长条状第五图形555；在所述第五图形555的侧壁形成掩膜材料300。请参阅图6、图7和图12，去除所述第二牺牲层220，留下所述第五图形555的侧壁掩膜材料，以形成所述第三掩膜层130。在第三掩膜层内形成若干平行排列的长条状第三图形333。(需要注意的是，此步骤中的侧壁掩膜材料与上一步骤中的侧壁掩膜材料，可以是相同材料，也可以是不同的材料，对此不做任何限定。)
请参阅图9和图12，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。其中，A-A1为第二图形222的延伸方向，B-B1为第三图形333的延伸方向。
具体地说，为了使后续形成的分立有源区排布合理，提高动态随机存储器的存储密度，本实施例设置所述第二图形222与所述第一图形111夹角为65度至75度之间，也可以为 68度至72度之间，还可以是70.15度。本实施例设置所述第二图形222和所述第三图形333夹角为45度至55度之间，也可以为48度至52度之间，还可以是49.1度。若干平行排列的所述第四图形444之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的4至5倍之间，也可以为其4至4.5倍之间，还可以是其4.25倍。若干所述平行排列的所述第五图形555之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的3至4倍之间，也可以为其3至3.5倍之间，还可以是其3.21倍。
进一步的，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111包括：利用所述第二图形222和所述第三图形333的交叠区域分割所述第一图形111。请参阅图10和图12，其中，虚线圆圈表示所述第一图形111被所述第二图形222和所述第三图形333的交叠区域分割(cut)的预定位置。需要注意的是，虽然图10和图12中显示预设位置均用圆圈表示，但并不限制所述第二图形222和所述第三图形333的交叠区域为圆形，仅作为示意，在实际工艺中可能为圆形，也可能为不规则图形，本发明的实施例对此不做限定。
进一步的，所述衬底100包括阵列区域，所述第一图形111、所述第二图形222、所述第三图形333均至少形成在所述阵列区域内。需要再注意的是，图12仅是为了示意实施例中如何利用所述第二图形222和所述第三图形333分割所述第一图形111，因此连续长条状的所述第一图形111在预定位置未显示出连续性，仅为示意图。
上述步骤一至三与上述具体实施方式的步骤一至三工艺相同，根据前面的工艺操作，相同的步骤细节就不再赘述。
步骤四：以所述第一掩膜层110、所述第二掩膜层120和所述第三掩膜层130作为掩膜，逐层刻蚀至所述衬底100，将所述第一图形111、所述第二图形222和第三图形333传递至所述衬底100内，形成若干阵列排布的分立有源区，如图18。
本实施例与第一实施例不同在于设置所述第二图形222和所述第三图形333夹角度数不同。本领域技术人员可根据实际情况进行设置，也不仅限于本实施例。
因此，在本实施例中，同样基于较大尺寸的光刻图形，在半导体衬底表面形成多层掩膜层，通过合理设计多层掩膜层上的图形，利用这些合理设计过图形的掩膜层，获得较小尺寸阵列排布的分立有源区，降低了工艺难度，提升了半导体结构的良率，提高了产能。其中，大尺寸和小尺寸的含义同前文。
本发明的第三实施例还提供另一种半导体结构的形成方法。
步骤一：请参阅图1，提供衬底100，在所述衬底100表面形成有第一掩膜层110，所述第一掩膜层110内形成有若干平行排列的长条状第一图形111，用于在衬底内形成若干平行排列的长条状的连续有源区。
请参阅图2，其为长条状的第一图形111的俯视示意图，在本附图中，为了能更清楚地显示结构，示意性地绘示多个长条状第一图形111。步骤二：在所述第一掩膜层110上形成第二掩膜层120，所述第二掩膜层120内形成若干平行排列的长条状第二图形222。
具体地说，在所述第一掩膜层110上形成第二掩膜层120的方法包括：请参阅图3，通 过沉积工艺在第一掩膜层110表面沉积第一牺牲层210。
请参阅图3和图14，图14为所述半导体结构实施例的俯视图，所述第一牺牲层210内形成有若干平行排列的长条状第四图形444。在所述第四图形444的侧壁形成掩膜材料300。其中，可以直接在所述第四图形444的侧壁形成该掩膜材料300；或者也可以先在所述第四图形444上整体沉积掩膜材料，再通过刻蚀以仅留下在所述第四图形444的侧壁的掩膜材料300。请参阅图4，去除所述第一牺牲层210，留下所述第四图形444的侧壁掩膜材料300，以在所述第二掩膜层120内形成若干平行排列的长条状第二图形222，图5为所述第二图形222的俯视示意图。(需要注意的是，图14仅为了示意本发明一实施例中各图形的位置关系，并不一定是某一步骤中呈现的实际俯视图。)
步骤三：在所述第二掩膜层120上形成第三掩膜层130，所述第三掩膜层130内形成若干平行排列的长条状第三图形333，其中，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。
具体地说，在所述第二掩膜层120上形成第三掩膜层130的方法包括：请参阅图6和图14，图14为所述半导体结构实施例的俯视图，通过沉积工艺在第二掩膜层120表面沉积第二牺牲层220。所述第二牺牲层220内形成有若干平行排列的长条状第五图形555；在所述第五图形555的侧壁形成掩膜材料300。请参阅图6、图7和图14，去除所述第二牺牲层220，留下所述第五图形555的侧壁掩膜材料，以形成所述第三掩膜层130。在第三掩膜层内形成若干平行排列的长条状第三图形333。(需要注意的是，此步骤中的侧壁掩膜材料与上一步骤中的侧壁掩膜材料，可以是相同材料，也可以是不同的材料，对此不做任何限定。)
请参阅图8，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。其中，A-A1为第二图形222的延伸方向，B-B1为第三图形333的延伸方向。具体地说，为了使后续形成的分立有源区排布合理，提高动态随机存储器的存储密度，本实施例设置所述第二图形222与所述第一图形111夹角为65度至75度之间，也可以为68度至72度之间，还可以是70.15度。本实施例设置所述第二图形222和所述第三图形333夹角为90度。相邻两条所述第四图形444之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的4至5倍之间，也可以为其4至4.5倍之间，还可以是其4.25倍。相邻两条所述第五图形555之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的4至5倍之间，也可以为其4至4.5倍之间，还可以是其4.25倍。
进一步的，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111还包括：请参阅图16，利用所述第二掩膜层120上的所述第二图形222形成第二互补掩膜层(未示出)，所述第二互补掩膜层内形成有包含所述第二图形222以外区域的第二互补图形222”；利用所述第三掩膜层130上的所述第三图形333形成第三互补掩膜层(未示出)，所述第三互补掩膜层内形成有包含所述第三图形333以外区域的第三互补图形333”；利用所述第二互补图形222”和第三互补图形333”的非交叠区域分割所述第一图形111。其中，虚线圆圈表示所述第一图形111被所述第二互补图形222”和所述第三互补图形333”的 交叠区域分割(cut)的预定位置。需要注意的是，虽然图10和图16中显示预设位置均用圆圈表示，但并不限制所述第二互补图形222”和第三互补图形333”的交叠区域为圆形，仅作为示意，在实际工艺中可能为圆形，也可能为不规则图形，本发明的实施例对此不做限定。
进一步的，所述衬底100包括阵列区域，所述第一图形111、所述第二互补图形222”、所述第三互补图形333”均至少形成在所述阵列区域内。需要再注意的是，图16仅是为了示意实施例中如何利用所述第二图形222和所述第三图形333分割所述第一图形111，因此连续长条状的所述第一图形111在预定位置未显示出连续性，仅为示意图。
上述步骤一至三与上述具体实施例的步骤一至三工艺相同，根据前面的工艺操作，相同的步骤细节就不再赘述。
步骤四：以所述第一掩膜层110、所述第二掩膜层120和所述第三掩膜层130作为掩膜，逐层刻蚀至所述衬底100，将所述第一图形111、所述第二互补图形222”和所述第三互补图形333”传递至所述衬底100内，形成若干阵列排布的分立有源区，如图18。
本实施例与第一实施例不同在于利用所述第二互补图形222”和第三互补图形333”的非交叠区域分割所述第一图形111。本领域技术人员可根据实际情况进行设置，不限于本实施例。
因此，在本实施例中，基于较大尺寸的光刻图形，在半导体衬底表面形成多层掩膜层，通过合理设计多层掩膜层上的图形，利用这些合理设计过图形的掩膜层，获得较小尺寸阵列排布的分立有源区，降低了工艺难度，提升了半导体结构的良率，提高了产能。
本发明的第四实施例还提供另一种半导体结构的形成方法。
步骤一：请参阅图1，提供衬底100，在所述衬底100表面形成有第一掩膜层110，所述第一掩膜层110内形成有若干平行排列的长条状第一图形111，用于在衬底内形成若干平行排列的长条状的连续有源区。
请参阅图2，其为长条状的第一图形111的俯视示意图，在本附图中，为了能更清楚地显示结构，示意性地绘示多个长条状第一图形111。所述第一图形111可以是长方形，也可以是弯曲的不规则图形，相邻两条所述第一图形111之间的中心距(pitch)为一预设值ACT。可通过一次光刻形成所述第一图形111，也可以通过自对准双重图形化(SADP)技术形成。且本领域内技术人员应当知道，若采用SADP技术形成的所述第一图形111，可能是封闭图形，在图2所示的所述第一图形111的上下边缘位置每两条所述第一图形111可能会连接到一起，类似图5所示的左右边缘。
步骤二：在所述第一掩膜层110上形成第二掩膜层120，所述第二掩膜层120内形成若干平行排列的长条状第二图形222。
具体地说，在所述第一掩膜层110上形成第二掩膜层120的方法包括：请参阅图3，通过沉积工艺在第一掩膜层110表面沉积第一牺牲层210。
请参阅图3和图11，图11为所述半导体结构实施例的俯视图，所述第一牺牲层210内形成有若干平行排列的长条状第四图形444。在所述第四图形444的侧壁形成掩膜材料300。 其中，可以直接在所述第四图形444的侧壁形成该掩膜材料300；或者也可以先在所述第四图形444上整体沉积掩膜材料，再通过刻蚀以仅留下在所述第四图形444的侧壁的掩膜材料300。请参阅图4，去除所述第一牺牲层210，留下所述第四图形444的侧壁掩膜材料300，以在所述第二掩膜层120内形成若干平行排列的长条状第二图形222，图5为所述第二图形222的俯视示意图。(需要注意的是，图11仅为了示意本发明一实施例中各图形的位置关系，并不一定是某一步骤中呈现的实际俯视图。)
步骤三：在所述第二掩膜层120上形成第三掩膜层130，所述第三掩膜层130内形成若干平行排列的长条状第三图形333，其中，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。
具体地说，在所述第二掩膜层120上形成第三掩膜层130的方法包括：请参阅图6、图11和图12，图11、图12为所述半导体结构实施例的俯视图，通过沉积工艺在第二掩膜层120表面沉积第二牺牲层220。所述第二牺牲层220内形成有若干平行排列的长条状第五图形555；在所述第五图形555的侧壁形成掩膜材料300。请参阅图6、图7和图12，去除所述第二牺牲层220，留下所述第五图形555的侧壁掩膜材料，以形成所述第三掩膜层130。在第三掩膜层内形成若干平行排列的长条状第三图形333。(需要注意的是，此步骤中的侧壁掩膜材料与上一步骤中的侧壁掩膜材料，可以是相同材料，也可以是不同的材料，对此不做任何限定。)
请参阅图9，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。其中，A-A1为第二图形222的延伸方向，B-B1为第三图形333的延伸方向。
具体地说，为了使后续形成的分立有源区排布合理，提高动态随机存储器的存储密度，本实施例设置所述第二图形222与所述第一图形111夹角为65度至75度之间，也可以为68度至72度之间，还可以是70.15度。本实施例设置所述第二图形222和所述第三图形333夹角为45度至55度之间，也可以为48度至52度之间，还可以是49.1度。若干平行排列的所述第四图形444之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的4至5倍之间，也可以为其4至4.5倍之间，还可以是其4.25倍。若干所述平行排列的所述第五图形555之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的3至4倍之间，也可以为其3至3.5倍之间，还可以是其3.21倍。
进一步的，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111还包括：请参阅图13，利用所述第二掩膜层120上的所述第二图形222形成第二互补掩膜层(未示出)，所述第二互补掩膜层内形成有包含所述第二图形222以外区域的第二互补图形222”；利用所述第三掩膜层130上的所述第三图形333形成第三互补掩膜层(未示出)，所述第三互补掩膜层内形成有包含所述第三图形333以外区域的第三互补图形333”；利用所述第二互补图形222”和第三互补图形333”的非交叠区域分割所述第一图形111。其中，虚线圆圈表示所述第一图形111被所述第二互补图形222”和所述第三互补图形333”的交叠区域分割(cut)。需要注意的是，虽然图10和图13中显示预设位置均用圆圈表示，但 并不限制所述第二互补图形222”和第三互补图形333”的交叠区域为圆形，仅作为示意，在实际工艺中可能为圆形，也可能为不规则图形，本发明的实施例对此不做限定。进一步的，所述衬底100包括阵列区域，所述第一图形111、所述第二互补图形222”、所述第三互补图形333”均至少形成在所述阵列区域内。
上述步骤一至三与上述具体实施例的步骤一至三工艺相同，根据前面的工艺操作，相同的步骤细节就不再赘述。
步骤四：以所述第一掩膜层110、所述第二掩膜层120和所述第三掩膜层130作为掩膜，逐层刻蚀至所述衬底100，将所述第一图形111、所述第二互补图形222”和所述第三互补图形333”传递至所述衬底100内，形成若干阵列排布的分立有源区，如图18。
本实施例与第一实施例不同在于设置所述第二图形222和所述第三图形333夹角度数不同。同时，利用所述第二互补图形222”和第三互补图形333”的非交叠区域分割所述第一图形111。可根据实际情况进行设置，不限于本实施例。
因此，在本实施例中，基于较大尺寸的光刻图形，在半导体衬底表面形成多层掩膜层，通过合理设计多层掩膜层上的图形，利用这些合理设计过图形的掩膜层，获得较小尺寸阵列排布的分立有源区，降低了工艺难度，提升了半导体结构的良率，提高产能。
本发明的第五实施例还提供另一种半导体结构的形成方法。
步骤一：请参阅图1，提供衬底100，在所述衬底100表面形成有第一掩膜层110，所述第一掩膜层110内形成有若干平行排列的长条状第一图形111，用于在衬底内形成若干平行排列的长条状的连续有源区。
请参阅图2，其为长条状的第一图形111的俯视示意图，在本附图中，为了能更清楚地显示结构，示意性地绘示多个长条状第一图形111。所述第一图形111可以是长方形，也可以是弯曲的不规则图形，相邻两条所述第一图形111之间的中心距(pitch)为一预设值ACT。可通过一次光刻形成所述第一图形111，也可以通过自对准双重图形化(SADP)技术形成。且本领域内技术人员应当知道，若采用SADP技术形成的所述第一图形111，可能是封闭图形，在图2所示的所述第一图形111的上下边缘位置每两条所述第一图形111可能会连接到一起，类似图5所示的左右边缘。
步骤二：在所述第一掩膜层110上形成第二掩膜层120，所述第二掩膜层120内形成若干平行排列的长条状第二图形222。
具体地说，在所述第一掩膜层110上形成第二掩膜层120的方法包括：请参阅图3，通过沉积工艺在第一掩膜层110表面沉积第一牺牲层210。
请参阅图3和图11，图11为所述半导体结构实施例的俯视图，所述第一牺牲层210内形成有若干平行排列的长条状第四图形444。在所述第四图形444的侧壁形成掩膜材料300。其中，可以直接在所述第四图形444的侧壁形成该掩膜材料300；或者也可以先在所述第四图形444上整体沉积掩膜材料，再通过刻蚀以仅留下在所述第四图形444的侧壁的掩膜材料300。请参阅图4，去除所述第一牺牲层210，留下所述第四图形444的侧壁掩膜材料300，以在所述第二掩膜层120内形成若干平行排列的长条状第二图形222，图5为所述第二图形 222的俯视示意图。(需要注意的是，图11仅为了示意本发明实施例中各图形的位置关系，并不一定是某一步骤中呈现的实际俯视图。)
步骤三：在所述第二掩膜层120上形成第三掩膜层130，所述第三掩膜层130内形成若干平行排列的长条状第三图形333，其中，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。
具体地说，在所述第二掩膜层120上形成第三掩膜层130的方法包括：请参阅图6图11和图12，图11、图12为所述半导体结构实施例的俯视图，通过沉积工艺在第二掩膜层120表面沉积第二牺牲层220。所述第二牺牲层220内形成有若干平行排列的长条状第五图形555；在所述第五图形555的侧壁形成掩膜材料300。请参阅图6、图7和图12，去除所述第二牺牲层220，留下所述第五图形555的侧壁掩膜材料，以形成所述第三掩膜层130。在第三掩膜层内形成若干平行排列的长条状第三图形333。(需要注意的是，此步骤中的侧壁掩膜材料与上一步骤中的侧壁掩膜材料，可以是相同材料，也可以是不同的材料，对此不做任何限定。)
请参阅图9，所述第二图形222与所述第三图形333交叠，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111。其中，A-A1为第二图形222的延伸方向，B-B1为第三图形333的延伸方向。
具体地说，为了使后续形成的分立有源区排布合理，提高动态随机存储器的存储密度，本实施例设置所述第二图形222与所述第一图形111夹角为65度至75度之间，也可以为68度至72度之间，还可以是70.15度。本实施例设置所述第二图形222和所述第三图形333夹角为45度至55度之间，也可以为48度至52度之间，还可以是49.1度。若干平行排列的所述第四图形444之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的4至5倍之间，也可以为其4至4.5倍之间，还可以是其4.25倍。若干所述平行排列的所述第五图形555之间的中心距为相邻两条所述第一图形111之间的中心距(预设值ACT)的3至4倍之间，也可以为其3至3.5倍之间，还可以是其3.21倍。
进一步的，所述第二图形222与所述第三图形333用于在预定位置分割所述第一图形111包括：利用所述第二图形222和所述第三图形333的交叠区域分割所述第一图形111。请参阅图10和图12，其中，虚线圆圈表示所述第一图形111被所述第二图形222和所述第三图形333的交叠区域分割(cut)。的预定位置。需要注意的是，虽然图10和图12中显示预设位置均用圆圈表示，但并不限制所述第二图形222和所述第三图形333的交叠区域为圆形，仅作为示意，在实际工艺中可能为圆形，也可能为不规则图形，本发明的实施例对此不做限定。
进一步的，所述衬底100包括阵列区域，所述第一图形111、所述第二图形222、所述第三图形333均至少形成在所述阵列区域内。需要再注意的是，图12仅是为了示意实施例中如何利用所述第二图形222和所述第三图形333分割所述第一图形111，因此连续长条状的所述第一图形111在预定位置未显示出连续性，仅为示意图。
上述步骤一至三与上述具体实施方式的步骤一至三工艺相同，根据前面的工艺操作， 相同的步骤细节就不再赘述。
步骤四：请参阅图17，在所述第三掩膜层上形成第四掩膜层，所述第四掩膜层内形成有第六图形666，所述第六图形666盖住所述阵列区边缘位置的至少部分所述第二图形222和所述第三图形333。
步骤五：所述第六图形666还至少盖住所述阵列区边缘位置处的连续有源区端部的小于分立有源区长度的次有源区(未示出)；同时以所述第一掩膜层110、所述第二掩膜层120、所述第三掩膜层130和所述第四掩膜层作为掩膜层，将所述第一图形111、所述第二图形222、所述第三图形333、所述第六图形666传递至衬底内，以形成阵列排布的分立有源区，其中所述阵列区边缘位置无所述次有源区，如图18。
本实施例与前述实施例的不同在于增加第四掩膜层，对阵列区边缘位置不完整的分立有源区进行修整(trim)，以提高边缘位置瑕疵有源区可能导致的工艺问题。虽然在说明书描述上，本实施例的第一掩膜层、第二掩膜层和第三掩膜层与前述一种实施例相同，但本领域技术人员应当理解，本实施例所增加的第四掩膜层均可以运用在前述第一实施例、第二实施例、第三实施例、第四实施例中，对此不做重复赘述。本领域技术人员可根据实际情况进行设置，选择是否需要在形成阵列分布的分立有源区后，对阵列区边缘位置的有源区进行修整。
因此，在本实施例中，通过对阵列区瑕疵有源区的修整，进一步提高半导体结构的可靠性及性能，提高良率。
需要注意的是，本发明的第二实施例、第三实施例、第四实施例、第五实施例描述得相对简洁，有些其他的共通内容可参照第一实施例的描述。
本发明的一实施例还提供一种半导体结构。
请参阅图18，所述半导体结构包括：衬底、分立有源区。
所述衬底内形成若干阵列排布的分立有源区。
所述分立有源区通过前述半导体结构的形成方法实施例形成。
具体包括：在半导体衬底表面形成多层掩膜层，通过合理设计多层掩膜层上的图形，利用这些合理设计过图形的掩膜层，获得较小尺寸阵列排布的分立有源区。
请参阅图18，若干平行排列的长条状的有源区被切割打断成分立的有源区。其中，请参阅图10，虚线圆圈表示所述第一图形被所述第二图形和所述第三图形的交叠区域分割(cut)的预定位置。需要注意的是，虽然图10中显示预设位置均用圆圈表示，但并不限制所述第二图形和所述第三图形的交叠区域为圆形，仅作为示意，在实际工艺中可能为圆形，也可能为不规则图形，本发明的实施例对此不做限定。
以上所述仅是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (17)

  1. 一种半导体结构形成方法，其特征在于，包括：
    提供衬底，在所述衬底上形成第一掩膜层，所述第一掩膜层内形成若干平行排列的长条状第一图形，用于在衬底内形成若干平行排列的长条状的连续有源区；
    在所述第一掩膜层上形成第二掩膜层，所述第二掩膜层内形成若干平行排列的长条状第二图形；
    在所述第二掩膜层上形成第三掩膜层，所述第三掩膜层内形成若干平行排列的长条状第三图形，其中，所述第二图形与所述第三图形交叠，所述第二图形与所述第三图形用于在预定位置分割所述第一图形；
    以所述第一掩膜层、所述第二掩膜层和所述第三掩膜层作为掩膜，逐层刻蚀至所述衬底，将所述第一图形、所述第二图形和第三图形传递至所述衬底内，形成若干阵列排布的分立有源区。
  2. 根据权利要求1所述的半导体结构形成方法，其特征在于，在所述第一掩膜层上形成第二掩膜层，所述第二掩膜层内形成若干平行排列的长条状第二图形包括：
    在所述第一掩膜层上形成第一牺牲层，所述第一牺牲层内形成有若干平行排列的长条状第四图形；
    在所述第四图形的侧壁形成掩膜材料，去除所述第一牺牲层，留下所述第四图形的侧壁掩膜材料，以形成所述第二掩膜层。
  3. 根据权利要求2所述的半导体结构形成方法，其特征在于，在所述第二掩膜层上形成第三掩膜层，所述第三掩膜层内形成若干平行排列的长条状第三图形包括：
    在所述第二掩膜层上形成第二牺牲层，所述第二牺牲层内形成有若干平行排列的长条状第五图形；
    在所述第五图形的侧壁形成掩膜材料，去除所述第二牺牲层，留下所述第五图形的侧壁掩膜材料，以形成所述第三掩膜层。
  4. 根据权利要求3所述的半导体结构形成方法，其特征在于，所述第二图形与所述第一图形夹角为65度至75度。
  5. 根据权利要求4所述的半导体结构形成方法，其特征在于，所述第二图形和所述第三图形夹角为90度。
  6. 根据权利要求5所述的半导体结构形成方法，其特征在于，若干平行排列的所述第四图形之间的中心距为若干平行排列的所述第一图形之间的中心距的4至5倍，若干所述平行排列的所述第五图形之间的中心距为若干平行排列的所述第一图形之间的中心距的4至5倍。
  7. 根据权利要求4所述的半导体结构形成方法，其特征在于，所述第二图形和所述第三图形夹角为45度至55度。
  8. 根据权利要求7所述的半导体结构形成方法，其特征在于，若干平行排列的所述第四图形之间的中心距为若干平行排列的所述第一图形之间的中心距的4至5倍，若干所述平行排列的所述第五图形之间的中心距为若干平行排列的所述第一图形之间的中心距的3 至4倍。
  9. 根据权利要求1所述的半导体结构形成方法，其特征在于，所述第二图形与所述第三图形用于在预定位置分割所述第一图形包括：利用所述第二图形和所述第三图形的交叠区域分割所述第一图形。
  10. 根据权利要求1所述的半导体结构形成方法，其特征在于，所述第二图形与所述第三图形用于在预定位置分割所述第一图形还包括：
    利用所述第二掩膜层上的所述第二图形形成第二互补掩膜层，所述第二互补掩膜层内形成有包含所述第二图形以外区域的第二互补图形；
    利用所述第三掩膜层上的所述第二图形形成第三互补掩膜层，所述第三互补掩膜层内形成有包含所述第三图形以外区域的第三互补图形；
    利用所述第二互补图形和第三互补图形的非交叠区域分割所述第一图形。
  11. 根据权利要求1所述的半导体结构形成方法，其特征在于，所述衬底包括阵列区域，所述第一图形、所述第二图形、所述第三图形均至少形成在所述阵列区域内。
  12. 根据权利要求10所述的半导体结构形成方法，其特征在于，还包括：
    在所述第三掩膜层上形成第四掩膜层，所述第四掩膜层内形成有第六图形，所述第六图形盖住所述阵列区边缘位置的至少部分所述第二图形和所述第三图形。
  13. 根据权利要求10所述的半导体结构形成方法，其特征在于，所述第六图形还至少盖住所述阵列区边缘位置处的连续有源区端部的小于分立有源区长度的次有源区；同时以所述第一掩膜层、所述第二掩膜层、所述第三掩膜层和所述第四掩膜层作为掩膜层，将所述第一图形、所述第二图形、所述第三图形、所述第六图形传递至衬底内，以形成阵列排布的分立有源区，其中所述阵列区边缘位置无所述次有源区。
  14. 根据权利要求1所述的半导体结构形成方法，其特征在于，所述第一图形由自对准双重图形化技术形成。
  15. 根据权利要求10所述的半导体结构形成方法，其特征在于，所述阵列区域为动态随机存储器的存储阵列区域。
  16. 根据权利要求1所述的半导体结构形成方法，其特征在于，还包括：所述掩膜层的材料包括：二氧化硅、氮化硅、氮氧化硅、多晶硅、单晶硅、碳中的至少一种。
  17. 一种半导体结构，其特征在于，包括：
    衬底，所述衬底形成有若干阵列排布的分立有源区；
    其中，所述分立有源区基于权利要求1所述半导体结构形成方法形成。
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