WO2021217356A1 - 基于pcie接口的数据传输装置 - Google Patents

基于pcie接口的数据传输装置 Download PDF

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WO2021217356A1
WO2021217356A1 PCT/CN2020/087284 CN2020087284W WO2021217356A1 WO 2021217356 A1 WO2021217356 A1 WO 2021217356A1 CN 2020087284 W CN2020087284 W CN 2020087284W WO 2021217356 A1 WO2021217356 A1 WO 2021217356A1
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interface
module
data transmission
pcie interface
pcie
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PCT/CN2020/087284
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English (en)
French (fr)
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邓远峰
张冬灵
钟志军
刘争
金瑞
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深圳市特博赛科技有限公司
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Priority to PCT/CN2020/087284 priority Critical patent/WO2021217356A1/zh
Publication of WO2021217356A1 publication Critical patent/WO2021217356A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Definitions

  • This application belongs to the technical field of equipment integration, and in particular relates to a data transmission device based on a PCIE interface.
  • the signal comes down from the frequency modulation head and is transmitted through the coaxial cable, or through the signal branching device, and then connected to the TV or set-top box.
  • a data transmission device occupies a large space and is not convenient for users to use.
  • the purpose of this application is to provide a data transmission device based on a PCIE interface, which aims to solve the technical problem that the data transmission device in the prior art occupies a large space and is inconvenient for users to use.
  • a data transmission device based on PCIE interface including a motherboard, and an input interface, photoelectric conversion module, tuner and demodulator, FPGA module and A PCIE interface, where the PCIE interface is connected to the FPGA module, and an external host can connect to the PCIE interface.
  • the input interface is an optical fiber input port, and an external device can be connected to the input interface through an optical fiber.
  • it further includes an electro-optical conversion module, the electro-optical conversion module is connected with the input interface through an optical fiber, and an external device is connected with the electro-optical conversion device.
  • the tuning demodulator includes a tuning module and a demodulation module connected to each other, the tuning module is connected to the photoelectric conversion module, and the demodulation module is connected to the FPGA module.
  • the photoelectric conversion module includes a first interface for outputting a vertical low local oscillation signal, a second interface for outputting a vertical high local oscillation signal, a third interface for outputting a horizontal low local oscillation signal, and a In the fourth interface that outputs a high-level local oscillator signal, the first interface, the second interface, the third interface, and the fourth interface are respectively connected to the tuning module.
  • At least one PCIE interface is connected to the FPGA module. .
  • there are at least two PCIE interfaces a plurality of PCIE interfaces are respectively connected to the FPGA module, and an external host can be respectively connected to the plurality of PCIE interfaces.
  • the FPGA module is a data acquisition card or an FPGA accelerator card.
  • the PCIE interface-based data transmission device of this application includes a motherboard, and an input interface, photoelectric conversion module, tuner and demodulator, FPGA module, and PCIE interface integrated on the motherboard, which can be controlled by a high degree of integration
  • the volume of the data transmission device based on the PCIE interface reduces the occupied space and is convenient for users to use.
  • the input interface, the photoelectric conversion module, the tuner demodulator, the FPGA module and the PCIE interface are connected in sequence. Since the PCIE interface can be directly connected to an external host, the data transmission device based on the PCIE interface is more stable in connection with the external host.
  • FIG. 1 is a schematic structural diagram of a data transmission device based on a PCIE interface provided by an embodiment of the application.
  • 131 tunneling module
  • 132 demodulation module
  • 16 electro-optical conversion module
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • the terms “installed”, “connected”, “connected”, “fixed” and other terms should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , Or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components.
  • installed can be a fixed connection or a detachable connection , Or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components.
  • an embodiment of the present application provides a data transmission device based on a PCIE interface, including a motherboard 10, and an input interface 11, a photoelectric conversion module 12, a tuner and demodulator 13, and an FPGA module connected to the motherboard 10 in sequence.
  • 14 is connected to the PCIE interface
  • the PCIE interface 15 is connected to the FPGA module 14, and an external host can connect to the PCIE interface 15.
  • the full name of FPGA in English is Field-Programmable Gate Array, which means field programmable gate array in Chinese;
  • the full name of PCIE in English is Peripheral Component Interconnect Express, which means high-speed serial computer expansion bus standard in Chinese.
  • the PCIE interface 15 is the high-speed serial computer expansion bus standard interface.
  • the PCIE interface-based data transmission device in the embodiment of the present application includes a motherboard 10, and an input interface 11, an optoelectronic conversion module 12, a tuner and demodulator 13, an FPGA module 14 and a PCIE interface 15 integrated with the motherboard 10, which are highly integrated It can control the volume of the data transmission device based on the PCIE interface, reduce the occupied space, and the input interface 11, the photoelectric conversion module 12, the tuner and demodulator 13, the FPGA module 14 and the PCIE interface 15 are connected in sequence, because the PCIE interface 15 can directly
  • the connection with the external host makes the connection between the data transmission device based on the PCIE interface and the external host more stable.
  • the input interface 11 is an optical fiber input port, and an external device can be connected to the input interface 11 through an optical fiber 20.
  • the signal is often transmitted via coaxial cable or through signal branching devices.
  • the coaxial cable takes up a lot of space. If you want to receive multiple sets of satellite TV programs or data, you need more A set-top box or other receiving equipment, and there are many coaxial cables, which is not conducive to management and data center wiring.
  • the optical fiber 20 is directly connected to the data transmission device based on the PCIE interface, which can remove the complicated coaxial cable and save the occupied space; on the other hand, adopt The optical fiber input port reduces signal attenuation and improves signal transmission quality and signal transmission distance.
  • an electro-optical conversion module 16 is further included.
  • the electro-optical conversion module 16 is connected to the input interface 11 through an optical fiber 20, and an external device is connected to the electro-optical conversion device.
  • the external device is a satellite pan
  • the satellite pan outputs an electrical signal. Therefore, an electro-optical conversion device that converts the electrical signal into an optical signal is provided, and the electrical-optical conversion device is connected to the data transmission device based on the PCIE interface.
  • the input interface 11 is connected by an optical fiber 20.
  • the tuning demodulator 13 includes a tuning module 131 and a demodulation module 132 connected to each other, the tuning module 131 is connected to the photoelectric conversion module 12, and the demodulation module 132 is connected to the FPGA module 14.
  • the tuning module 131 and the demodulation module 132 By providing the tuning module 131 and the demodulation module 132, the signal output by the photoelectric conversion module 12 can be converted into a digital signal, and the digital signal can be transmitted to the FPGA module 14.
  • the photoelectric conversion module 12 includes a first interface 121 for outputting a vertical low local oscillation signal, a second interface 122 for outputting a vertical high local oscillation signal, and a second interface 122 for outputting a horizontal low local oscillation signal.
  • the signal third interface 123 and the fourth interface 124 for outputting high-level local oscillator signals.
  • the first interface 121, the second interface 122, the third interface 123 and the fourth interface 124 are respectively connected to the tuning module.
  • the PCIE interface 15 is connected to the FPGA module 14.
  • the PCIE interface 15 may be an interface provided on the FPGA module 14, or may be another connection method capable of data transmission with the FPGA module 14, for example, connection through a wire or connection through a motherboard, which is not the only one here. limited.
  • the PCIE interface 15 can be directly connected to an external host, and data can be sent to the host through direct memory access.
  • PCIE interfaces 15 there are at least two PCIE interfaces 15, multiple PCIE interfaces 15 are respectively connected to FPGA module 14, and an external host can be connected to multiple PCIE interfaces 15 respectively.
  • the FPGA module 14 can also be connected to multiple interfaces, at least one of which is the PCIE interface 15, which can meet the different interface requirements of different external hosts, and can connect to multiple external hosts at the same time.
  • the FPGA module 14 is a data acquisition card or an FPGA accelerator card.
  • the host is a computer, etc., through the PCIE interface 15 to realize the fast communication between the computer and the PCIE interface 15 to complete the read and write operations to the FPGA module 14 to ensure the speed and reliability of data transmission.
  • the tuner of the satellite pan receives the signal, the satellite pan transmits the electrical signal to the electro-optical conversion module and converts it into an optical signal.
  • the optical signal is transmitted to the data transmission device based on the PCIE interface through the optical fiber 20. Specifically, the optical signal is input to the photoelectric conversion module through the input interface 11. Differentiate into VL signal, VH signal, HL signal or HH signal.
  • the signal is sent to the tuner and demodulator 13 module.
  • the tuner and demodulator 13 module demodulates the electrical signal into a digital signal and sends it to the FPGA module 14.
  • the FPGA module 14 is programmed into the data collection function and passes the data through DMA (Direct Memory Access) is sent to the host.
  • DMA Direct Memory Access

Abstract

本申请属于设备集成化技术领域，尤其涉及基于PCIE接口的数据传输装置，本申请实施例的基于PCIE接口的数据传输装置，包括主板，和集成与主板上的输入接口、光电转换模块、调谐解调器、FPGA模块和PCIE接口，较高地集成度能够控制该基于PCIE接口的数据传输装置的体积，降低占用空间，便于用户使用。且输入接口、光电转换模块、调谐解调器、FPGA模块和PCIE接口依次连接，由于PCIE接口能够直接与外部的主机连接，使得该基于PCIE接口的数据传输装置与外部的主机连接更稳定。

Description

基于PCIE接口的数据传输装置 技术领域
本申请属于设备集成化技术领域，尤其涉及一种基于PCIE接口的数据传输装置。
背景技术
传统的卫星电视节目或卫星数据接收，信号从调频头下来，通过同轴电缆线传输，或经过信号分支器件，再连接到电视机或机顶盒。但是这样的数据传输装置占用空间大，不便于用户使用。
实用新型内容
本申请的目的在于提供一种基于PCIE接口的数据传输装置，旨在解决现有技术中的数据传输装置占用空间大，不便于用户使用的技术问题。
为实现上述目的，本申请采用的技术方案是：一种基于PCIE接口的数据传输装置，包括主板，以及依次连接于所述主板上的输入接口、光电转换模块、调谐解调器、FPGA模块和PCIE接口，所述PCIE接口与所述FPGA模块连接，外部的主机能够连接所述PCIE接口。
在一个实施例中，所述输入接口为光纤输入口，外部设备能够通过光纤与所述输入接口连接。
在一个实施例中，还包括电光转换模块，所述电光转换模块与所述输入接口通过光纤连接，外部设备与所述电光转换设备连接。
在一个实施例中，所述调谐解调器包括相互连接的调谐模块和解调模块，所述调谐模块与所述光电转换模块连接，所述解调模块与所述FPGA模块连接。
在一个实施例中，所述光电转换模块包括用于输出垂直低本振信号的第一 接口、用于输出垂直高本振信号的第二接口、用于输出水平低本振信号的第三接口以及用于输出水平高本振信号的第四接口，所述第一接口、所述第二接口、所述第三接口以及所述第四接口分别与所述调谐模块连接。
在一个实施例中，所述FPGA模块至少连接有一个所述PCIE接口。。
在一个实施例中，所述PCIE接口至少为两个，多个所述PCIE接口分别与所述FPGA模块连接，且外部的主机能够分别与多个所述PCIE接口连接。
在一个实施例中，所述FPGA模块为数据采集卡或FPGA加速卡。
本申请的有益效果：本申请的基于PCIE接口的数据传输装置，包括主板，和集成与主板上的输入接口、光电转换模块、调谐解调器、FPGA模块和PCIE接口，较高地集成度能够控制该基于PCIE接口的数据传输装置的体积，降低占用空间，便于用户使用。且输入接口、光电转换模块、调谐解调器、FPGA模块和PCIE接口依次连接，由于PCIE接口能够直接与外部的主机连接，使得该基于PCIE接口的数据传输装置与外部的主机连接更稳定。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的基于PCIE接口的数据传输装置结构示意图。
其中，图中各附图标记：
10—主板；11—输入接口；12—光电转换模块；
13—调谐解调器；14—FPGA模块；15—PCIE接口；
131—调谐模块；132—解调模块；16—电光转换模块；
121—第一接口；122—第二接口；123—第三接口；
124—第四接口；20—光纤。
具体实施方式
下面详细描述本申请的实施例，实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图1描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
如图1所示，本申请实施例提供一种基于PCIE接口的数据传输装置，包括主板10，以及依次连接于主板10上的输入接口11、光电转换模块12、调谐解调器13、FPGA模块14和PCIE接口15，PCIE接口15与FPGA模块14连接，外部的主机能够连接PCIE接口15。FPGA英文全称Field-Programmable Gate Array，中文含义为现场可编程门阵列；PCIE英文全称Peripheral Component Interconnect Express,中文含义为高速串行计算机扩展总线标准，该PCIE接口15即为高速串行计算机扩展总线标准接口。
本申请实施例的基于PCIE接口的数据传输装置，包括主板10，和集成与主板10上的输入接口11、光电转换模块12、调谐解调器13、FPGA模块14和PCIE接口15，较高地集成度能够控制该基于PCIE接口的数据传输装置的体积，降低 占用空间，且输入接口11、光电转换模块12、调谐解调器13、FPGA模块14和PCIE接口15依次连接，由于PCIE接口15能够直接与外部的主机连接，使得该基于PCIE接口的数据传输装置与外部的主机连接更稳定。
如图1所示，在一个实施例中，输入接口11为光纤输入口，外部设备能够通过光纤20与输入接口11连接。传统的卫星电视节目或卫星数据接收，信号常是同轴电缆线进行传输，或经过信号分支器件，但是同轴电缆线占用空间较大，如果想要接收多套卫星电视节目或数据，需要多个机顶盒或其他接收设备，并且还有很多同轴电缆线，不利于管理和数据中心的布线。因此，通过将输入接口11替换为光纤输入口，一方面，光纤20直接接入到该基于PCIE接口的数据传输装置中，能够去掉繁杂的同轴电缆线，节省占用空间；另一方面，采用光纤输入口，更降低信号衰减，可提高信号传输质量以及信号传输距离。
如图1所示，在一个实施例中，还包括电光转换模块16，电光转换模块16与输入接口11通过光纤20连接，外部设备与电光转换设备连接。具体地，当外部设备为卫星锅时，卫星锅输出的是电信号，因此，提供一个将电信号转换成光信号的电光转换设备，且该电光转换设备与该基于PCIE接口的数据传输装置的输入接口11通过光纤20连接。
如图1所示，在一个实施例中，调谐解调器13包括相互连接的调谐模块131和解调模块132，调谐模块131与光电转换模块12连接，解调模块132与FPGA模块14连接。通过设置调谐模块131和解调模块132，能够将光电转换模块12输出的信号转换能够数字信号，并将该数字信号输送至FPGA模块14。
如图1所示，在一个实施例中，光电转换模块12包括用于输出垂直低本振信号的第一接口121、用于输出垂直高本振信号的第二接口122、用于输出水平低本振信号的第三接口123以及用于输出水平高本振信号的第四接口124，第一接口121、第二接口122、第三接口123以及第四接口124分别与调谐模块连接。通过将光电转换模块12设置为能够输出多种电信号，使得能够根据具体需求调整输出信号。
如图1所示，在一个实施例中，FPGA模块14至少连接有一个PCIE接口15。具体地，PCIE接口15可为设置于FPGA模块14上的接口，也可为能够与FPGA模块14进行数据传输的其它连接方式，例如，通过导线连接或通过主板进行连接，此处并不做唯一限定。当PCIE接口15为一个时，该PCIE接口15直接与外部的主机连接即可，并能通过直接存储器访问的方式将数据送入至主机。
如图1所示，在一个实施例中，PCIE接口15至少为两个，多个PCIE接口15分别与FPGA模块14连接，且外部的主机能够分别与多个PCIE接口15连接。当然，FPGA模块14也可连接有多个接口，至少其中一个为PCIE接口15，便能满足不同外部的主机的不同接口需求，且能够同时连接多个外部的主机。
如图1所示，在一个实施例中，FPGA模块14为数据采集卡或FPGA加速卡。主机为电脑等，通过PCIE接口15实现了电脑与PCIE接口15的快速通信,完成对FPGA模块14的读写操作，保证数据传输的速度和可靠性。当卫星锅的高频头接收到信号，卫星锅将电信号传输到电光转化模块中，转化成光信号。通过光纤20将光信号传输至该基于PCIE接口的数据传输装置，具体地，是通过输入接口11将光信号输入至光电转化模块，光电转化模块将光信号重新转化成电信号，并将信号重新分化成VL信号、VH信号、HL信号或HH信号。信号送到调谐解调器13模块，调谐解调器13模块将电信号解调成数字信号，并将其送入FPGA模块14中，FPGA模块14中被编写入采集数据功能，并将数据通过DMA(直接存储器访问)的方式送入主机。
以上仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (8)

  1. 基于PCIE接口的数据传输装置，其特征在于：包括主板，以及依次连接于所述主板上的输入接口、光电转换模块、调谐解调器、FPGA模块和PCIE接口，所述PCIE接口与所述FPGA模块连接，外部的主机能够连接所述PCIE接口。
  2. 根据权利要求1所述的基于PCIE接口的数据传输装置，其特征在于：所述输入接口为光纤输入口，外部设备能够通过光纤与所述输入接口连接。
  3. 根据权利要求2所述的基于PCIE接口的数据传输装置，其特征在于：还包括电光转换模块，所述电光转换模块与所述输入接口通过光纤连接，外部设备与所述电光转换设备连接。
  4. 根据权利要求1所述的基于PCIE接口的数据传输装置，其特征在于：所述调谐解调器包括相互连接的调谐模块和解调模块，所述调谐模块与所述光电转换模块连接，所述解调模块与所述FPGA模块连接。
  5. 根据权利要求4所述的基于PCIE接口的数据传输装置，其特征在于：所述光电转换模块包括用于输出垂直低本振信号的第一接口、用于输出垂直高本振信号的第二接口、用于输出水平低本振信号的第三接口以及用于输出水平高本振信号的第四接口，所述第一接口、所述第二接口、所述第三接口以及所述第四接口分别与所述调谐模块连接。
  6. 根据权利要求1所述的基于PCIE接口的数据传输装置，其特征在于：所述FPGA模块至少连接有一个所述PCIE接口。
  7. 根据权利要求6所述的基于PCIE接口的数据传输装置，其特征在于：所述PCIE接口至少为两个，多个所述PCIE接口分别与所述FPGA模块连接，且外部的主机能够分别与多个所述PCIE接口连接。
  8. 根据权利要求1所述的基于PCIE接口的数据传输装置，其特征在于：所述FPGA模块为数据采集卡或FPGA加速卡。
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