Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/319—Tester hardware, i.e. output processing circuits
  • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
  • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Definitions

• Apparatus for detecting invalid configurations in bi directional multiplexing infrastructures The invention relates to an apparatus for detecting invalid configurations in bi-directional multiplexing infrastructures .
• a multiplexer is a circuitry which selectively drives an output signal Z from different sources A, B, C, ...depending on a control signal SZ.
• Figure 1 shows the symbol of a multiplexer and a simplified circuitry. The output Z is driven by input A as soon as the control signal SZ is 0; input B is forwarded as soon as SZ becomes 1, and so on.
• the number of N identifies the size of the multiplexer.
• the example multiplexer 1 of figure 1 has four inputs 2 and is there with a 4:1 multiplexer.
• the width of the data signals Z, A, B, C ... is always identical; here they have the width 1. But any data width is supported.
• the multiplexer 1 is realized by two parts, the data path as one part and the control part 5 as another part, as shown in figure 2.
• the output Z is created by OR'ing all sources, which are gated by an AND-gate. Just one of the AND-gates gets a high- level on its second input and therewith just one multiplexer input passes.
• the control part 5 generates the secondary AND-gate input signals.
• a one-hot decoder creates a high signal depending on the control signal SZ. The following formulas specify the exact logic conditions:
• the forward multiplexers 7 are steered by the control signals SW, SX, SY and SZ 9.
• the backward direction multiplexer control can be derived from SW, SX, SY and SZ 9. Due to the fact, that there are four sinks and four sources in the example of figure 3, the width of the control signals Sm n is two. It is good to present the forward control signals SW, SX, SY and SZ to the end-user, as they are easy to understand, if the basic principle of a multiplexer is understood .
• the object will be solved by an apparatus for detecting invalid configurations in a bi-directional multiplexing infrastructure, whereas the infrastructure comprising a multiplexer decoder logic configured to process control signals, multiple sources as inputs and multiple sinks as outputs, whereas the sources and sinks are connected via forward and backward multiplexers, wherein the multiplexer decoder logic is extended by a configuration error checker which monitors each source and all control signals of the backward multiplexers connected to the sources and creates error information which source is used more than once.
• the configuration error detector is configured to detect invalid configurations.
• the multiplexer decoder logic is configured to generate the backward multiplexer control signals Sm n , where m stands for the sink identifier and n stands for the source identifier.
• the configuration error detector can be applied on bi directional multiplexing infrastructures with any number of sources N and any number of sinks M and gives detailed information on the configuration error.
• M and N are positive natural number greater than 0. It eases debugging and configuration of complex bi-directional multiplexers with larger numbers of N and M.
• the configuration error detector evaluates all backward multiplexer control signals and creates error information which source is used more than once. The backward signals for instance might signal if the next data can be accepted or a pause needs to be inserted.
• the multiplexer configuration is invalid as soon as more than one multiplexer selects the corresponding source.
• the configuration error checker comprises an evaluation instance for each source n, whereas each evaluation instance outputs a logical equivalent E n to the control signals of the backward multiplexers for one source n.
• E n indicating the error condition for a given source n. If E n is equal to zero than the control signal configuration for said source is valid, otherwise it is invalid.
• the configuration error checker or an evaluation instance for a source is only needed, if a source has to handle backward signals. Sources without backward signals do not need any multiplexer configuration checking.
• the evaluation instance for each source n comprises standard- cells with AND- and OR-gates. Hence the implementation of the inventive apparatus is very easy in chip design.
• the logical equivalent E n for one source n is determined by connecting the control signals of two sinks for said source n by an AND- and by an OR-operation, the result of the OR- operation is combined with a control signal of a further sink for said source n by an AND- and by an OR-operation, whereas this is going on until the control signals of all sinks for said source n are processed such and finally all outputs of the processed AND-operations are connected by a final OR-operation.
• the determination of the logical equivalent E n is realized by standard-cells.
• the multiplexer decoder logic generates the internal control signals Sm n for the backward multiplexers, whereas each sink m contributes a control signal Sm n to a source n of the bi-directional multiplexing infrastructure if said source n can be reached by backward signals.
• These control signals are further processed by the evaluation instance for each source in order to determine the logical equivalent E n for each source n and to evaluate if said source n is only used once, otherwise the configuration would be invalid, as it is not allowed to select an already allocated source more than once.
• the bi-directional multiplexing infrastructure is invalid as soon as more than one multiplexer selects the corresponding source.
• the number N of sources is equal or greater than two and in another variant the number M of sinks is equal or greater than two.
• the inventive apparatus works for any bi-directional multiplexer complexity, hence of any number of sources N and sinks M.
• a width of the multiplexed data signals is independent to the configuration error checker and can be any positive number.
• the inventive apparatus works for any bi-directional multiplexer complexity. For any number of sources N and sinks M.
• FIG. 4 Bi-directional multiplexer infrastructure with configuration error checker according to the invention (for sources A and B).
• Figure 4 shows the inventive apparatus which can be seen as an extension to the multiplexer decoder logic 11 as the configuration error checker 14 uses the generated internal control signals Sm n for the backward multiplexers for evaluating if an error condition is fulfilled or not, hence if E n is equal to zero or one.
• Figure 4 does not show the whole bi-directional multiplexer infrastructure.
• the configuration error checker circuitry 14 based on standard-cells.
• the lower part in figure 4 contains the multiplexer decoder logic 11 which generates the multiplexer internal control signals Sm n .
• the upper part contains two evaluation instances 15 of the configuration error checker 14 for the sources A and B.
• the circuitry can be repeated for all other source (i. e. C and D).
• One application of the present invention is the multiplexing of bi-directional pads on a chip. Every pad (sink) has multiple control signals, like output, output-enable, pull- up control and so on and feeds back the pad input level to the digital logic inside the chip.
• the pad might be used for different purposes and therewith by different chip-internal blocks, i. e. UART, SPI, I2C.
• the chip-internal blocks (sources) can be muxed to multiple pads (sinks).
• the configuration error checker hence the evaluation instance per pad eases the handling of complex setups.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Time-Division Multiplex Systems (AREA)

Priority Applications (1)

Applications Claiming Priority (4)

Publications (1)

Family

ID=73543971

Family Applications (1)

Country Status (3)

Citations (4)

• 2020
  • 2020-11-20 EP EP20208980.1A patent/EP3893009B1/en active Active
• 2021
  • 2021-03-30 WO PCT/EP2021/058373 patent/WO2021204612A1/en active Application Filing
  • 2021-03-30 CN CN202180021518.1A patent/CN115398255A/zh active Pending

Patent Citations (4)

Also Published As

Similar Documents

Legal Events