WO2021203875A1 - 脉冲消除电路、电压检测电路以及检测方法 - Google Patents

脉冲消除电路、电压检测电路以及检测方法 Download PDF

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Publication number
WO2021203875A1
WO2021203875A1 PCT/CN2021/078953 CN2021078953W WO2021203875A1 WO 2021203875 A1 WO2021203875 A1 WO 2021203875A1 CN 2021078953 W CN2021078953 W CN 2021078953W WO 2021203875 A1 WO2021203875 A1 WO 2021203875A1
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signal
circuit
input
voltage
pulse
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PCT/CN2021/078953
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English (en)
French (fr)
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李金博
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北京集创北方科技股份有限公司
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Priority to US17/918,099 priority Critical patent/US20230412177A1/en
Priority to KR1020227038666A priority patent/KR20220162790A/ko
Priority to JP2022562132A priority patent/JP2023520946A/ja
Publication of WO2021203875A1 publication Critical patent/WO2021203875A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H03L7/1978—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider using a cycle or pulse removing circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/1803—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the counter or frequency divider being connected to a cycle or pulse swallowing circuit

Definitions

  • the present disclosure relates to the technical field of voltage detection, and in particular to a pulse cancellation circuit, a voltage detection circuit, a detection method, and electronic equipment.
  • Active-matrix organic light-emitting diode Active-matrix organic light-emitting diode, AMOLED
  • AMOLED Active-matrix organic light-emitting diode
  • the voltage detection module is mainly implemented by a hysteresis comparator.
  • the detection voltage When the detection voltage is lower than the lower threshold voltage, it outputs a high level and when the detection voltage is higher than the upper threshold voltage, it outputs a low level, thereby detecting undervoltage or abnormal power failure. But if there is a short-time pulse and there is no power failure or insufficient voltage, it will cause detection errors.
  • the purpose of the embodiments of the present disclosure is to provide a pulse elimination circuit that can eliminate glitch interference, for example, to improve the accuracy of voltage detection.
  • the embodiment of the present disclosure provides a short pulse elimination circuit, including:
  • a clock generating circuit configured to receive a logic signal and a first input signal, and generate a clock signal according to the logic signal and the first input signal
  • a counter connected to the clock generating circuit, configured to receive the clock signal, count the number of cycles of the clock signal, and generate the second input signal;
  • the signal output circuit is connected to the counter and is configured to provide a first input signal to the clock generating circuit and generate a pulse cancellation signal according to the second input signal.
  • the clock generating circuit includes:
  • a first AND circuit one input terminal of the first AND circuit is configured to receive a logic signal, and the other input terminal of the first AND circuit is configured to receive a first input signal;
  • the enable terminal is connected to the output terminal of the first AND circuit
  • the second AND circuit one input terminal of the second AND circuit is configured to receive the first input signal, and the other input terminal of the second AND circuit is connected to the clock pulse output terminal of the oscillator;
  • the output terminal is connected to the counter and is configured to output a clock signal to the counter.
  • the signal output circuit includes:
  • a multi-input AND gate circuit, and multiple input terminals of the multi-input AND gate circuit are configured to input a second input signal
  • the first flip-flop the signal input end of the first flip-flop is connected to the output end of the multi-input AND circuit
  • a second flip-flop the signal input terminal of the second flip-flop is connected to the signal output terminal of the first flip-flop
  • one input terminal of the NAND gate circuit is connected to the signal output terminal of the first flip-flop, and the other input terminal of the NAND gate circuit is connected to the signal output terminal of the second flip-flop; the output terminal of the NAND circuit is configured Outputting the first input signal to the direction clock generating circuit;
  • the input terminal of the first inverter is connected to the output terminal of the NAND circuit; the output terminal of the first inverter is configured to output a pulse cancellation signal.
  • the clock pulse input terminal of the first flip-flop is connected to the clock signal output terminal of the clock generating circuit.
  • the signal output circuit further includes: a second inverter; one end of the second inverter is connected to the clock signal output terminal of the clock generating circuit, and the other end of the second inverter is connected to the clock pulse input of the second flip-flop end.
  • the enable ends of the first flip-flop and the second flip-flop are configured to input logic signals.
  • the enable terminal of the counter is configured to input a logic signal.
  • the second input signal includes multiple output signals of the counter.
  • the generating the pulse cancellation signal according to the second input signal includes: generating the pulse cancellation signal when it is determined that the multiple output signals of the counter are all high levels.
  • the embodiment of the present disclosure also provides a voltage detection circuit, including:
  • a hysteresis comparator the output terminal of the hysteresis comparator is connected to the clock generation circuit, and is configured to provide the logic signal to the clock generation circuit;
  • the forward input terminal of the hysteresis comparator is configured to input a reference voltage, and the reverse input terminal is configured to input a second voltage signal;
  • the hysteresis comparator is configured to compare the second voltage signal with a reference voltage, and output the corresponding logic signal based on the comparison result.
  • the above-mentioned voltage detection circuit further includes:
  • a voltage regulating circuit the input terminal of the voltage regulating circuit is configured to input a first voltage signal, and the output terminal of the voltage regulating circuit is connected to the inverting input terminal of the hysteresis comparator;
  • the voltage regulating circuit is configured to step up or step down the first voltage signal to obtain the second voltage signal.
  • the step of stepping up or stepping down the first voltage signal includes: stepping up the first voltage signal by a fixed proportional value through a voltage regulator; or, The first voltage signal is stepped down by a fixed proportional value through a voltage divider resistor.
  • the embodiment of the present disclosure also provides a voltage detection method, including:
  • the pulse elimination circuit eliminates the sudden change of the pulse whose duration is less than the threshold contained in the logic signal to obtain the pulse elimination signal.
  • the embodiment of the present disclosure also provides an electronic device including the above-mentioned voltage detection circuit.
  • the electronic equipment includes an AMOLED driving device, an LCD driving device, a power management device, or a voltage detection device.
  • the electronic equipment is a smart mobile device, a display device, a power supply device, a direct current detection device or an alarm device.
  • a clock signal is generated by a clock generation circuit according to a logic signal and a first input signal, and a counter counts the number of cycles of the clock signal, and outputs a corresponding second input signal.
  • the signal output circuit can output a pulse cancellation signal according to the second input signal, so that when the number of cycles of the logic signal reaches a certain number, the pulse cancellation signal can output a high level, which can eliminate short pulses contained in the logic signal and eliminate The false trigger caused by the short pulse improves the stability and accuracy of the signal.
  • FIG. 1 is a schematic diagram of a pulse elimination circuit provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of waveforms of a clock signal and a second input signal
  • FIG. 3 is a schematic diagram of a pulse elimination circuit provided by another embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of signal waveforms at different positions in the pulse elimination circuit shown in FIG. 3;
  • FIG. 5 is a schematic diagram of a voltage detection circuit provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a voltage regulating circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of waveforms of a first voltage signal, a second voltage signal, a logic signal, and a pulse cancellation signal provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic flowchart of a voltage detection method provided by an embodiment of the present disclosure.
  • FIG. 9 is a detailed flowchart of step 830 in the embodiment corresponding to FIG. 8.
  • FIG. 1 is a schematic diagram of a pulse elimination circuit provided by an embodiment of the disclosure.
  • the pulse elimination circuit 100 may include: a clock generation circuit 11, a counter 12 and a signal output circuit 13.
  • the counter 12 can be connected to the signal output circuit 13 and the clock generation circuit 11 respectively.
  • the clock generating circuit 11 may be configured to receive the logic signal IN and the first input signal S_4, and may generate a clock signal according to the logic signal IN and the first input signal S_4.
  • the counter 12 can be connected to the clock generating circuit 11, and the counter 12 can be configured to receive a clock signal, and can count the number of cycles of the clock signal to generate the second input signal CK ⁇ N:0>.
  • N+1 represents the number of bits of the output signal of the counter 12. Assuming that the signal output by the counter 12 is 4-bit, then N is 3.
  • the second input signal may include multiple output signals of the counter 12.
  • the counter 12 is a 4-bit binary counter, it includes 4 output signals, that is, the second input signal may be 4 output signals of the counter 12.
  • the signal output circuit 13 can be connected to the counter 12, and the signal output circuit 13 can be configured to provide the first input signal S_4 to the clock generation circuit 11, and can generate the pulse elimination signal OUT according to the second input signal CK ⁇ N:0>.
  • the generating the pulse cancellation signal according to the second input signal includes: generating the pulse cancellation signal when it is determined that the multiple output signals of the counter are all high levels.
  • the 12-bit counter is a 4-bit binary counter
  • the pulse elimination signal OUT generated according to the second input signal CK ⁇ 3:0> can be the pulse elimination signal OUT generated when it is determined that the four signals of the second input signal are all high level.
  • the pulse elimination signal OUT may be high level, and the pulse elimination signal OUT may be low level in the rest of the time.
  • an AND gate circuit with 4 inputs can be used to realize the above-mentioned functions.
  • the time required to trigger the generation of the pulse elimination signal can be set by a counter, so as to achieve the purpose of eliminating short pulses in the circuit with a short duration.
  • the present disclosure does not limit how to set the counting period of the counter, and how the counter is connected to the subsequent logic circuit.
  • the counter can be a 3-bit binary counter or a 4-bit binary counter. The choice may depend on the interference that needs to be eliminated.
  • the length of the short pulse; in addition, the counter and the subsequent logic circuit such as the AND circuit can also be arbitrarily modified according to the counting requirements.
  • the clock generating circuit 11 when the logic signal IN and the first input signal S_4 are both at a high level, the clock generating circuit 11 outputs a clock signal.
  • the clock signal may have a fixed period.
  • the enable terminal of the counter 12 can also be input with a logic signal IN, so that the counter 12 is started when the logic signal IN is at a high level.
  • the counter 12 can receive the clock signal output by the clock generation circuit 11 and count the number of cycles of the received clock signal.
  • FIG. 2 is a schematic diagram of waveforms of the clock signal and the second input signal CK ⁇ N:0>.
  • the clock signal can be the input signal of the counter 12.
  • the counter 12 as a 4-bit binary counter as an example, CK ⁇ 3>, CK ⁇ 2>, CK ⁇ 1>, CK ⁇ 0> can be counters respectively.
  • the output signal of 12 (ie, the second input signal) is the first signal, the second signal, the third signal, and the fourth signal.
  • counter 12 Before receiving a complete clock cycle, counter 12 outputs 0000, corresponding to decimal 0; when receiving a complete clock cycle, counter 12 outputs 0001, corresponding to decimal 1; when receiving two complete clock cycles, counter 12 outputs 0002 , Corresponding to decimal number 2, and so on, when counter 12 receives 15 cycles of the clock signal, counter 12 outputs 1111, corresponding to decimal number 15.
  • the enable terminal of the signal output circuit 13 can also be input with a logic signal IN, so that when the logic signal IN is at a high level, the signal output circuit 13 is activated.
  • the signal output circuit 13 can receive the second input signal CK ⁇ N:0> output by the counter 12.
  • the pulse elimination signal OUT output by the signal output circuit 13 may be at a high level; when it is less than 15 cycles , The pulse elimination signal OUT output by the signal output circuit 13 may be low level.
  • the pulse elimination signal OUT output by the signal output circuit 13 can all be low level; when more than 15 cycles, the signal output circuit 13 can continue to output a high level, so that when When the logic signal IN is a short pulse with a short duration, since the period of the short pulse does not reach 15 cycles, the signal output circuit 13 will not output a high level, so that the interference of the short pulse can be eliminated.
  • the pulse period is less than 10 microseconds, which can be considered as a short pulse.
  • the first input signal S_4 transmitted by the signal output circuit 13 to the clock generation circuit 11 may be The signal output circuit 13 receives the second input signal CK ⁇ N:0> to be 1111, and the first input signal S_4 output by the signal output circuit 13 is low. Therefore, the clock generating circuit 11 stops working, thus reducing the power consumption of the clock generating circuit 11.
  • the counter 12 continues to output 1111, so the signal output circuit 13 continues to output a high level, until the logic signal IN at the enable end is low, both the signal output circuit 13 and the counter 12 stop working.
  • the number of trigger cycles during which the signal output circuit 13 outputs a high level can be set.
  • the signal output circuit 13 may output a high level when 0111 is received, that is, when the counter 12 receives a clock signal of 7 cycles. Therefore, even if the logic signal IN has a short pulse with a duration of less than 7 cycles, the signal output circuit 13 will not output a high level, so that the interference of the short pulse can be eliminated.
  • the clock generating circuit 11 generates a clock signal according to the logic signal IN and the first input signal S_4, and the counter 12 counts the number of cycles of the clock signal, and outputs the corresponding second input signal CK ⁇ N:0> .
  • the signal output circuit 13 can output the pulse cancellation signal OUT according to the second input signal CK ⁇ N:0>, so that when the number of cycles that the logic signal IN lasts reaches a certain number, the pulse cancellation signal OUT can output a high level. Eliminate the short pulse contained in the logic signal, thereby eliminating the false trigger caused by the short pulse, and improving the stability and accuracy of the signal.
  • the above-mentioned clock generating circuit 11 may include: a first AND circuit 112, an oscillator (OSC) 111, and a second AND circuit 113.
  • One input terminal of the first AND circuit 112 may be configured to receive the logic signal IN, and the other input terminal may be configured to receive the first input signal S_4, so that when the logic signal IN and the first input signal S_4 are both high, the first input signal S_4 An AND circuit 112 outputs a high level. When the logic signal IN and/or the first input signal S_4 is at a low level, the first AND circuit 112 outputs a low level. To distinguish it from other AND circuits below, the AND circuit here is referred to as the first AND circuit 112.
  • the enable terminal EN of the oscillator 111 can be connected to the output terminal of the first AND circuit 112.
  • the oscillator 111 can be regarded as a frequency source, which outputs a high level (that is, a clock pulse) according to a fixed frequency.
  • One input terminal of the second AND circuit 113 can be configured to receive the first input signal S_4, and the other input terminal can be connected to the clock pulse output terminal of the oscillator 111; the output terminal of the second AND circuit 113 can be connected to the counter 12, It is configured to output a clock signal to the counter (COUNTER) 12.
  • the clock signal output by the second AND circuit 113 is the same as the clock pulse output by the oscillator 111; when the first input signal S_4 is at a low level, the first AND circuit 112 outputs a low level. Level, which in turn may cause the oscillator 111 to stop working, so that the second AND circuit 113 also has no clock signal output.
  • the above-mentioned signal output circuit 13 may include: a multi-input AND circuit 131, a first flip-flop 132, a second flip-flop 133, a NAND circuit 134, and a first inverter 135.
  • the multiple input terminals of the multi-input AND circuit 131 may be configured to input the second input signal CK ⁇ N:0>.
  • the multi-input AND circuit 131 can output a high level. For example, for a 4-input AND circuit, when the second input signal CK ⁇ N:0> is 1111 (that is, four high levels), the multi-input AND circuit 131 outputs a high level.
  • the second input signal CK ⁇ N:0> can be 0111 (CK ⁇ 3> ,CK ⁇ 2>,CK ⁇ 1>,CK ⁇ 0>).
  • the first signal CK ⁇ 3> can be inverted by an inverter and then input to the multi-input AND circuit 131, so when the second input signal CK ⁇ N:0> is 0111, the multi-input AND circuit 131 Can output high level.
  • the signal input terminal D of the first flip-flop 132 can be connected to the output terminal of the multi-input AND circuit 131.
  • the first flip-flop 132 may be a D flip-flop.
  • the output terminal Q of the first flip-flop 132 follows the signal of the input terminal D at the rising edge of the clock signal, so that when the multi-input AND circuit 131 outputs a high level, the first flip-flop 132 outputs high level.
  • the signal input terminal D of the second flip-flop 133 can be connected to the signal output terminal Q of the first flip-flop 132.
  • the second flip-flop 133 may output a high level.
  • the second flip-flop 133 may be the same as the first flip-flop 132.
  • One input terminal of the NAND circuit 134 can be connected to the signal output terminal of the first flip-flop 132, and the other input terminal of the NAND circuit 134 can be connected to the signal output terminal Q of the second flip-flop 133;
  • the output terminal may be configured to output the first input signal S_4 to the clock generating circuit 11.
  • the multi-input AND circuit 131 outputs a low level
  • the first flip-flop 132 and the second flip-flop 133 output a low level
  • the gate circuit 134 outputs a high level, that is, the first input signal S_4 is a high level, thereby prompting the clock generating circuit to continue to work and output a clock signal.
  • the input terminal of the first inverter 135 may be connected to the output terminal of the NAND circuit 134; the output terminal of the first inverter 135 may be configured to output a pulse cancellation signal.
  • the NAND gate circuit When the NAND gate circuit outputs a low level, the first inverter 135 can output a high level, so that when the counter 12 counts that the number of cycles of the clock signal is greater than the preset value n, that is, the logic signal IN is at a high level
  • nT represents the period of the clock signal
  • the clock pulse input terminal CLK of the first flip-flop 132 can be connected to the clock signal output terminal A of the clock generating circuit 11. So as to keep the timing of the entire circuit synchronized.
  • the signal output circuit 13 may further include: a second inverter 136; one end of the second inverter 136 may be connected to the clock signal output terminal A of the clock generating circuit 11, and the other end of the second inverter 136 may be The clock pulse input terminal CLK of the second flip-flop 133 is connected.
  • the clock signal output by the clock generating circuit 11 and the clock pulse received by the second flip-flop 133 are exactly inverted.
  • the first flip-flop 132 is a rising-edge flip-flop
  • the second inverter 136 and the second flip-flop 133 constitute a falling-edge flip-flop, so that the second flip-flop 133 is half a period later than the first flip-flop 132, thereby ensuring the first flip-flop.
  • the second flip-flop 133 receives the signal output by the first flip-flop 132.
  • the enable terminals EN of the first flip-flop 132 and the second flip-flop 133 are configured to input a logic signal IN. Therefore, when the logic signal IN is at a high level, the first flip-flop 132 and the second flip-flop 133 can be started, and when the logic signal IN is at a low level, the first flip-flop 132 and the second flip-flop 133 can stop working.
  • FIG. 4 is a schematic diagram of signal waveforms at different positions in the pulse cancellation circuit 100 shown in FIG. 3.
  • IN represents the logic signal IN
  • IN is low at the beginning
  • ENOSC is also 0 at this time.
  • the circuit starts timing with the rising edge of IN.
  • the circuit starts to work, ENOSC goes high, OSC (oscillator 111) starts, and the circuit starts to calculate the cycle.
  • FIG. 5 is a schematic diagram of a voltage detection circuit provided by an embodiment of the disclosure. As shown in FIG. 5, the voltage detection circuit includes: the pulse elimination circuit 100 shown in FIG. 1 or 3, and may also include a hysteresis comparator 200.
  • the output terminal of the hysteresis comparator 200 is connected to the clock generation circuit 11 and is configured to provide a logic signal IN to the clock generation circuit 11; the forward input terminal of the hysteresis comparator 200 is configured to input the reference voltage VREF, and the reverse input terminal is configured to input the second The voltage signal Vdet_2.
  • the hysteresis comparator 200 is configured to compare the second voltage signal Vdet_2 with a reference voltage to obtain a logic signal IN.
  • the logic signal IN output by the hysteresis comparator 200 may be provided as an enable signal to the counter 12, the first flip-flop 132, and the second flip-flop 133.
  • the hysteresis comparator 200 may be a comparator with hysteresis loop transmission characteristics. It can also be understood as a single-limit comparator with positive feedback. On the basis of the inverting input single threshold voltage comparator, a positive feedback network is introduced to form an inverting input hysteresis comparator 200 with double thresholds.
  • the reference voltage VREF of the hysteresis comparator 200 is the internal reference voltage of the chip, and the voltage threshold of the logic signal IN can be adjusted by setting the VREF voltage.
  • the logic signal IN Before the second voltage signal Vdet_2 increases and approaches the upper threshold voltage, the logic signal IN can maintain the high level unchanged. When the second voltage signal Vdet_2 increases again, the logic signal IN can remain at a low level. If the second voltage signal Vdet_2 decreases, as long as it is greater than the lower threshold value, the logic signal IN will always remain at a low level. Only when the second voltage signal Vdet_2 is less than the lower threshold value, the logic signal IN will jump to a high level . Therefore, even if the second voltage signal Vdet_2 has noise and ripple, it does not affect the result of the logic signal IN, and the interference of noise and ripple is eliminated.
  • the voltage detection circuit further includes a voltage regulating circuit 300.
  • the input terminal of the voltage regulation circuit 300 may be configured to input the first voltage signal Vdet
  • the output terminal of the voltage regulation circuit 300 may be connected to the inverting input terminal of the hysteresis comparator 200
  • the voltage regulation circuit 300 may be configured to input the first voltage signal Vdet.
  • the voltage signal Vdet is boosted or stepped down, and the second voltage signal Vdet_2 is output.
  • the first voltage signal Vdet may be considered as the voltage signal to be measured.
  • the voltage regulating circuit 300 can boost or step down the first voltage signal Vdet. Since the voltage value of the voltage signal to be measured is usually higher or lower, it exceeds the input range of the subsequent hysteresis comparator 200. Therefore, the voltage to be detected needs to be adjusted to be within the input range of the hysteresis comparator 200 by stepping down or stepping up. If the voltage signal to be measured is high, it can be reduced in a fixed proportion through the resistor divider; if the voltage to be measured is low, it can be boosted in a fixed proportion through a voltage regulator. In this way, the second voltage signal Vdet_2 proportional to the voltage signal to be measured is obtained.
  • Vdet/Vdet_2 K
  • ⁇ Vdet/ ⁇ Vdet_2 K
  • the step of stepping up or stepping down the first voltage signal includes: stepping up the first voltage signal by a fixed proportional value through a voltage regulator; or, The first voltage signal is stepped down by a fixed proportional value through a voltage divider resistor.
  • FIG. 7 is a schematic diagram of the waveforms of the first voltage signal Vdet, the second voltage signal Vdet_2, the logic signal IN, and the pulse elimination signal provided by an embodiment of the present disclosure.
  • Vdet is the first voltage signal (that is, the voltage to be detected), and the voltage regulating circuit 300 can adjust Vdet to a second voltage signal Vdet_2 suitable for detection by the hysteresis comparator 200; the hysteresis comparator 200 can adjust the second voltage
  • the signal Vdet_2 is compared with the reference voltage to output a logic signal IN; then the pulse elimination circuit 100 can eliminate the false short pulse Tpulse. Finally, a correct pulse elimination signal OUT is output.
  • FIG. 8 is a schematic flowchart of a voltage detection method provided by an embodiment of the present disclosure.
  • the voltage detection method can be applied to the voltage detection circuit provided in the embodiment corresponding to FIG. 5.
  • the voltage detection method may include the following steps S810 to S830.
  • step S810 the first voltage signal to be detected is received by the voltage regulating circuit 300, and the first voltage signal is boosted or lowered to obtain a second voltage signal;
  • step S820 the second voltage signal is compared with the reference voltage by the hysteresis comparator 200 to obtain a logic signal
  • step S830 the pulse elimination circuit 100 eliminates the sudden change of the pulse whose duration is less than the threshold value included in the logic signal to obtain a pulse elimination signal.
  • Pulse sudden change refers to a short pulse whose signal change duration is less than a threshold.
  • a pulse whose duration is less than 10 microseconds can be regarded as a short pulse.
  • the above step 830 eliminates the sudden change of the pulse whose duration is less than the threshold contained in the logic signal through the pulse elimination circuit 100, and obtaining the pulse elimination signal may include the following steps.
  • Step 831 Receive the logic signal IN and the first input signal S_4 through the clock generating circuit 11, and output a clock signal.
  • the first input signal S_4 may be output by the signal output circuit 13.
  • the first input signal S_4 output by the signal output circuit 13 is at a high level, and the clock generating circuit 11 receives a high-level logic signal IN and a high-level first input Signal S_4, output clock signal.
  • Step 832 Receive the clock signal through the counter 12, and count the number of cycles of the clock signal to generate the second input signal CK ⁇ N:0>.
  • the counter 12 can count the number of cycles of the clock signal and output a multi-bit binary digital signal. For example, 0111 means 7 cycles, and 1111 means 15 cycles.
  • the second input signal CK ⁇ N:0> is the multi-bit binary digital signal generated by the counter 12.
  • the second input signal CK ⁇ N:0> can be input to the signal output circuit 13.
  • Step 833 The signal output circuit 13 generates a pulse cancellation signal according to the second input signal CK ⁇ N:0>.
  • the signal output circuit 13 receives the second input signal CK ⁇ N:0>, and generates a pulse cancellation signal after processing. For example, when the second input signal CK ⁇ N:0> is 1111, the pulse cancellation signal outputs a high level. When the second input signal CK ⁇ N:0> is less than 1111 (that is, when the number of cycles of the clock signal is less than 15), the pulse elimination signal outputs a low level. Thereby eliminating the interference caused by short-term pulses.
  • the voltage detection circuit and the voltage detection method provided by the embodiments of the present disclosure can be applied to the driver chip of AMOLED (active matrix organic light-emitting diode panel), can be used to detect the power supply voltage provided by the outside, and can also be used to detect Detection of voltage generated inside the chip. Real-time monitoring of the voltage situation, the output will be triggered when the voltage is too low or abnormal power failure.
  • AMOLED active matrix organic light-emitting diode panel
  • An embodiment of the present disclosure also provides an electronic device, which may include the voltage detection circuit described in the foregoing embodiment.
  • the electronic device may include an AMOLED driving device, an LCD (Liquid Crystal Display) driving device, a power management device, or a voltage detection device.
  • the electronic device may be a smart mobile device, and the smart mobile device may be a smart phone, smart wearable device, smart robot, etc., equipped with an AMOLED display screen or an LCD display screen.
  • the electronic device can also be a display device, such as a television, computer or monitor equipped with an AMOLED display screen or an LCD display screen.
  • a display device such as a television, computer or monitor equipped with an AMOLED display screen or an LCD display screen.
  • the electronic equipment can also be a power supply device (such as a supplementary box, an electric box, a power distribution cabinet, a UPS uninterruptible power supply), a direct current detection device or an alarm device.
  • a power supply device such as a supplementary box, an electric box, a power distribution cabinet, a UPS uninterruptible power supply
  • a direct current detection device or an alarm device.
  • the voltage detection circuit provided by the embodiment of the present disclosure may be installed in the electronic device provided above.
  • each block in the flowchart or block diagram can represent a module, program segment, or part of the code, and the module, program segment, or part of the code contains one or more executables for implementing the specified logical functions. instruction.
  • the functions marked in the block may also occur in a different order from the order marked in the drawings.
  • each block in the block diagram and/or flowchart, and the combination of the blocks in the block diagram and/or flowchart can be implemented by a dedicated hardware-based system that performs the specified functions or actions Or it can be realized by a combination of dedicated hardware and computer instructions.
  • the functional modules in the various embodiments of the present disclosure may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.
  • the function is realized in the form of a software function module and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present disclosure essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods of the various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .
  • the embodiment of the present disclosure provides a pulse elimination circuit, a voltage detection circuit, a detection method, and an electronic device. Since the pulse elimination circuit of the embodiment of the present disclosure includes a counter, a clock generation circuit, and a signal output circuit, it can determine the number of cycles that the logic signal lasts. When it reaches a certain number, the pulse elimination signal can output a high level, which can eliminate the short pulse contained in the logic signal, thereby eliminating the false trigger caused by the short pulse, and improving the signal stability and the accuracy of voltage detection.

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Abstract

本公开实施例提供一种脉冲消除电路、电压检测电路以及检测方法，属于电路技术领域，该脉冲消除电路包括：时钟产生电路，配置成接收逻辑信号以及第一输入信号，并根据逻辑信号和第一输入信号生成时钟信号；计数器，连接时钟产生电路，配置成接收时钟信号，并统计时钟信号的周期个数，生成第二输入信号；信号输出电路，连接计数器，配置成提供第一输入信号至时钟产生电路，并根据第二输入信号生成脉冲消除信号。由此该电路在电压检测过程中，可以消除短脉冲造成的误触发，提高电压检测的准确性。

Description

脉冲消除电路、电压检测电路以及检测方法
相关申请的交叉引用
本公开要求于2020年04月08日提交中国专利局的申请号为202010272031.8、名称为“脉冲消除电路、电压检测电路以及检测方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及电压检测技术领域，特别涉及一种脉冲消除电路、电压检测电路、检测方法以及电子设备。
背景技术
有源矩阵有机发光二极体(Active-matrix organic light-emitting diode，AMOLED)对应的驱动芯片需求越来越大，而驱动芯片需要有电压检测模块，来进行实时检测电压，防止出现电压不足或异常掉电现象。
目前电压检测模块主要通过迟滞比较器实现，在检测电压小于下门限电压输出高电平以及在检测电压高于上门限电压输出低电平，从而检测电压不足或异常掉电现象。但是如果存在短时脉冲并且实际并没有掉电或电压不足，则会引起检测误差。
发明内容
本公开实施例的目的在于提供一种可消除短时脉冲干扰的脉冲消除电路，例如用以提高电压检测准确性。
本公开实施例提供了一种短脉冲消除电路，包括：
时钟产生电路，配置成接收逻辑信号以及第一输入信号，并根据逻辑信号和所述第一输入信号生成时钟信号；
计数器，连接时钟产生电路，配置成接收时钟信号，并统计时钟信号的周期个数，生成第二输入信号；
信号输出电路，连接计数器，配置成提供第一输入信号至时钟产生电路，并根据第二输入信号生成脉冲消除信号。
可选地，时钟产生电路包括：
第一与门电路，第一与门电路的一个输入端配置成接收逻辑信号，所述第一与门电路的另一个输入端配置成接收第一输入信号；
振荡器，使能端连接第一与门电路的输出端；
第二与门电路，第二与门电路的一个输入端配置成接收第一输入信号，所述第二与门电路的另一个输入端连接振荡器的时钟脉冲输出端；第二与门电路的输出端连接计数器，配置成向计数器输出时钟信号。
可选地，信号输出电路包括：
多输入与门电路，多输入与门电路的多个输入端配置成输入第二输入信号；
第一触发器，第一触发器的信号输入端连接多输入与门电路的输出端；
第二触发器，第二触发器的信号输入端连接第一触发器的信号输出端；
与非门电路，与非门电路的一个输入端连接第一触发器的信号输出端，与非门电路的另一个输入端连接第二触发器的信号输出端；与非门电路的输出端配置成向时钟产生电路输出第一输入信号；
第一反相器，第一反相器的输入端连接与非门电路的输出端；第一反相器的输出端配置成输出脉冲消除信号。
可选地，第一触发器的时钟脉冲输入端连接时钟产生电路的时钟信号输出端。
可选地，信号输出电路还包括：第二反相器；第二反相器的一端连接时钟产生电路的时钟信号输出端，第二反相器的另一端连接第二触发器的时钟脉冲输入端。
可选地，第一触发器和第二触发器的使能端配置成输入逻辑信号。
可选地，计数器的使能端配置成输入逻辑信号。
可选地，所述计数器中，所述第二输入信号包括所述计数器的多路输出信号。
可选地，所述信号输出电路中，所述根据所述第二输入信号生成脉冲消除信号，包括：确定所述计数器的多路输出信号均为高电平时，生成所述脉冲消除信号。
本公开实施例还提供了一种电压检测电路，包括：
上述任意一种脉冲消除电路；
迟滞比较器，所述迟滞比较器的输出端连接所述时钟产生电路，配置成提供所述逻辑信号至所述时钟产生电路；
所述迟滞比较器的正向输入端配置成输入参考电压，反向输入端配置成输入第二电压信号；
所述迟滞比较器配置成比较所述第二电压信号和参考电压，并基于比较结果输出相应的所述逻辑信号。
可选地，上述电压检测电路还包括：
调压电路，所述调压电路的输入端配置成输入第一电压信号，所述调压电路的输出端连接所述迟滞比较器的反向输入端；
所述调压电路配置成对所述第一电压信号进行升压或降压，得到所述第二电压信号。
可选地，所述调压电路中，所述对所述第一电压信号进行升压或降压，包括：通过调压器将所述第一电压信号以固定比例值进行升压；或者，通过分压电阻将所述第一电压信号以固定比例值进行降压。
本公开实施例还提供了一种电压检测方法，包括：
通过调压电路接收待检测的第一电压信号，对所述第一电压信号进行升压或降压，得到第二电压信号；
通过迟滞比较器比较所述第二电压信号和参考电压，得到逻辑信号；
通过脉冲消除电路消除所述逻辑信号中包含的持续时间小于阈值的脉冲突变，得到脉冲消除信号。
本公开实施例还提供了一种电子设备，包括上述的电压检测电路。
可选地，所述电子设备包括AMOLED驱动装置、LCD驱动装置、电源管理装置或电压检测装置。
可选地，所述电子设备为智能移动装置、显示装置、供电装置、直流电检测装置或报警装置。
本公开上述实施例提供的技术方案，通过时钟产生电路根据逻辑信号和第一输入信号生成时钟信号，计数器统计时钟信号的周期个数，输出相应的第二输入信号。信号输出电路可以根据第二输入信号输出脉冲消除信号，从而在逻辑信号持续的周期个数达到一定数量时，脉冲消除信号可以输出高电平，由此可以消除逻辑信号中包含的短脉冲，消除短脉冲造成的误触发，提高了信号稳定性和准确性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例中所需要使用的附图作简单地介绍。
图1为本公开实施例提供的脉冲消除电路示意图；
图2是时钟信号与第二输入信号的波形示意图；
图3为本公开另一实施例提供的脉冲消除电路示意图；
图4是图3所示脉冲消除电路中不同位置的信号波形示意图；
图5为本公开一实施例提供的电压检测电路示意图；
图6是本公开实施例提供的一种调压电路示意图；
图7是本公开实施例提供的第一电压信号、第二电压信号、逻辑信号以及脉冲消除信号的波形示意图；
图8是本公开实施例提供的电压检测方法的流程示意图；
图9是图8对应实施例中步骤830的细节流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行描述。
相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。同时，在本公开的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
图1为本公开实施例提供的脉冲消除电路示意图。如图1所示，脉冲消除电路100可以包括：时钟产生电路11、计数器12以及信号输出电路13。计数器12可以分别连接信号输出电路13以及时钟产生电路11。
时钟产生电路11可以配置成接收逻辑信号IN以及第一输入信号S_4，并可以根据逻辑信号IN和第一输入信号S_4生成时钟信号。
计数器12可以连接时钟产生电路11，计数器12可以配置成接收时钟信号，并可以统计时钟信号的周期个数，生成第二输入信号CK<N:0>。其中，N+1表示计数器12输出信号的位数。假设计数器12输出的信号是4位的，则N为3。
可选地，第二输入信号可以包括计数器12的多路输出信号，例如计数器12为4位二进制计数器，则包含4路输出信号，即第二输入信号可以为计数器12的4路输出信号。
信号输出电路13可以连接计数器12，信号输出电路13可以配置成提供第一输入信号S_4至时钟产生电路11，并可以根据第二输入信号CK<N:0>生成脉冲消除信号OUT。
可选地，所述信号输出电路中，所述根据所述第二输入信号生成脉冲消除信号，包括：确定所述计数器的多路输出信号均为高电平时，生成所述脉冲消除信号。例如计数器12位为4位二进制计数器，则根据第二输入信号CK<3:0>生成脉冲消除信号OUT可以是确定第二输入信号的4路信号均为高电平时，生成的脉冲消除信号OUT，换句话说，确定第二输入信号的4路信号均为高电平时，脉冲消除信号OUT可以为高电平，其余时间脉冲消除信号OUT可以为低电平。具体地，可以利用如4输入端的与门电路来实现上述功能。
需要说明的是，在本公开实施例中，描述了可以通过计数器来设置触发生成所述脉冲消除信号的所需的时长，从而达到消除电路中持续时间较短的短脉冲的目的，但本公开实施例并不限制如何设置计数器的计数周期，以及计数器与其后续的逻辑电路如何连接，例 如，计数器可以采用3位二进制计数器，也可以采用4位二进制计数器，如何选取可以取决于实际需要消除的干扰短脉冲的长度；另外，计数器与后续的逻辑电路如与门电路也可以按计数需求进行任意修改。例如，在4位二进制计数器的第一路输出端与4输入与门电路之间增加一个反相器，从而实现在计数至0111时，生成脉冲消除信号，也即将4位二进制计数器改造成为3位二进制计数器。以上举例并不限制本公开的保护范围。
可选地，逻辑信号IN和第一输入信号S_4均是高电平时，时钟产生电路11输出时钟信号。时钟信号可以具有固定的周期。
计数器12的使能端也可以输入逻辑信号IN，从而在逻辑信号IN为高电平时，启动计数器12。计数器12可以接收时钟产生电路11输出的时钟信号，并统计接收的时钟信号的周期个数。
以一个4位计数器12为例，图2是时钟信号与第二输入信号CK<N:0>的波形示意图。在本实施例中，时钟信号可以是计数器12的输入信号，以计数器12是4位二进制计数器为例，CK<3>，CK<2>,CK<1>,CK<0>可以分别是计数器12的输出信号(即第二输入信号)的第一路信号、第二路信号、第三路信号以及第四路信号。在接收到一个完整时钟周期之前，计数器12输出0000，对应十进制0；当接收到一个完整时钟周期时，计数器12输出0001，对应十进制1；当接收到两个完整时钟周期时，计数器12输出0002，对应十进制2，依次类推，当计数器12接收到15个周期的时钟信号后，计数器12输出1111，对应十进制15。
信号输出电路13的使能端也可以输入逻辑信号IN，从而在逻辑信号IN为高电平时，启动信号输出电路13。信号输出电路13可以接收计数器12输出的第二输入信号CK<N:0>。可选地，信号输出电路13在接收到1111时，即计数器12接收到15个周期的时钟信号时，信号输出电路13输出的脉冲消除信号OUT可以为高电平；在少于15个周期时，信号输出电路13输出的脉冲消除信号OUT可以为低电平。
对于持续时间少于15个周期的逻辑信号IN，信号输出电路13输出的脉冲消除信号OUT可以均为低电平；在大于15个周期时，信号输出电路13可以持续输出高电平，从而当逻辑信号IN是持续时间较短的短脉冲时，因短脉冲的周期达不到15个周期，信号输出电路13也不会输出高电平，从而可以消除短脉冲的干扰。可选地，脉冲周期小于10微秒，可以认为是短脉冲。
在信号输出电路13接收到第二输入信号CK<N:0>是1111之前，即逻辑信号IN少于15个周期之前，信号输出电路13向时钟产生电路11传输的第一输入信号S_4可以是高电平，从而促使时钟产生电路11持续输出时钟信号，直到信号输出电路13接收到第二输入信号CK<N:0>是1111时，信号输出电路13输出的第一输入信号S_4为低电平，从而时钟产生电 路11停止工作，如此降低了时钟产生电路11的功耗。计数器12持续输出1111，从而信号输出电路13持续输出高电平，直到使能端的逻辑信号IN为低电平，信号输出电路13和计数器12均停止工作。
根据实际需要，可以设置信号输出电路13输出高电平的触发周期个数。可选地，信号输出电路13可以在接收到0111时，即计数器12接收到7个周期的时钟信号时，信号输出电路13输出高电平。从而即使逻辑信号IN存在持续时间少于7个周期的短脉冲，信号输出电路13也不会输出高电平，从而可以消除短脉冲的干扰。
上述实施例提供的技术方案，通过时钟产生电路11根据逻辑信号IN和第一输入信号S_4生成时钟信号，计数器12统计时钟信号的周期个数，输出相应的第二输入信号CK<N:0>。信号输出电路13可以根据第二输入信号CK<N:0>输出脉冲消除信号OUT，从而在逻辑信号IN持续的周期个数达到一定数量时，脉冲消除信号OUT可以输出高电平，由此可以消除逻辑信号中包含的短脉冲，进而消除了短脉冲造成的误触发，提高了信号稳定性和准确性。
如图3所示，上述时钟产生电路11可以包括：第一与门电路112、振荡器(OSC)111以及第二与门电路113。
第一与门电路112的一个输入端可以配置成接收逻辑信号IN，另一个输入端可以配置成接收第一输入信号S_4，从而在逻辑信号IN和第一输入信号S_4均是高电平时，第一与门电路112输出高电平。当逻辑信号IN和/或第一输入信号S_4是低电平时，第一与门电路112输出低电平。为与下文的其他与门电路进行区分，将此处的与门电路称为第一与门电路112。
振荡器111的使能端EN可以连接第一与门电路112的输出端。在第一与门电路112输出高电平时，振荡器111工作；在第一与门电路112输出低电平时，振荡器111停止工作。振荡器111可以被认为是频率源，其按照固定频率输出高电平(也就是时钟脉冲)。
第二与门电路113的一个输入端可以配置成接收第一输入信号S_4，另一个输入端可以连接振荡器111的时钟脉冲输出端；第二与门电路113的输出端可以连接计数器12，可以配置成向计数器(COUNTER)12输出时钟信号。在第一输入信号S_4是高电平时，第二与门电路113输出的时钟信号与振荡器111输出的时钟脉冲相同；在第一输入信号S_4是低电平时，第一与门电路112输出低电平，进而可以导致振荡器111停止工作，从而第二与门电路113也无时钟信号输出。
如图3所示，上述信号输出电路13可以包括：多输入与门电路131、第一触发器132、第二触发器133、与非门电路134以及第一反相器135。
多输入与门电路131的多个输入端可以配置成输入第二输入信号CK<N:0>。在多个输入端同时输入高电平时，多输入与门电路131可以输出高电平。例如，对于4输入与门电路 来说，第二输入信号CK<N:0>是1111(即四个高电平)时，多输入与门电路131输出高电平。
可选地，假设规定逻辑信号IN持续7个时钟周期以上均是高电平，最后输出(OUT)为高电平，则第二输入信号CK<N:0>可以是0111(CK<3>,CK<2>,CK<1>,CK<0>)。其中，第一路信号CK<3>可以先通过反相器反相后再输入多输入与门电路131，从而在第二输入信号CK<N:0>是0111时，多输入与门电路131可以输出高电平。
第一触发器132的信号输入端D可以连接多输入与门电路131的输出端。第一触发器132可以是D触发器，在时钟信号上升沿时第一触发器132的输出端Q跟随输入端D的信号，从而在多输入与门电路131输出高电平时，第一触发器132输出高电平。
第二触发器133的信号输入端D可以连接第一触发器132的信号输出端Q。在第一触发器132输出高电平时，第二触发器133可以输出高电平。第二触发器133可以与第一触发器132相同。
与非门电路134的一个输入端可以连接第一触发器132的信号输出端，与非门电路134的另一个输入端可以连接第二触发器133的信号输出端Q；与非门电路134的输出端可以配置成向时钟产生电路11输出第一输入信号S_4。在第一触发器132输出高电平并且第二触发器133输出高电平时，与非门电路134输出低电平。从而在时钟信号的周期个数少于预设值(例如15个周期)时，多输入与门电路131输出低电平，第一触发器132和第二触发器133输出低电平，与非门电路134输出高电平，即第一输入信号S_4是高电平，从而促使时钟产生电路继续工作输出时钟信号。
第一反相器135的输入端可以连接与非门电路134的输出端；第一反相器135的输出端可以配置成输出脉冲消除信号。在与非门电路输出低电平时，第一反相器135可以输出高电平，从而在计数器12统计出时钟信号的周期个数大于预设值n时，也即逻辑信号IN处于高电平的时间大于nT(T表示时钟信号的周期)时，第一反相器135输出的脉冲消除信号OUT是高电平。
如图3所示，第一触发器132的时钟脉冲输入端CLK可以连接时钟产生电路11的时钟信号输出端A。从而保持整个电路时序的同步。可选地，信号输出电路13还可以包括：第二反相器136；第二反相器136的一端可以连接时钟产生电路11的时钟信号输出端A，第二反相器136的另一端可以连接第二触发器133的时钟脉冲输入端CLK。
时钟产生电路11输出的时钟信号与第二触发器133接收到的时钟脉冲正好反相。第一触发器132为上升沿触发器，第二反相器136与第二触发器133构成下降沿触发器，从而第二触发器133比第一触发器132晚半个周期，由此保证第二触发器133接收到第一触发器132输出的信号。
可选地，第一触发器132和第二触发器133的使能端EN配置成输入逻辑信号IN。从而在逻辑信号IN为高电平时，第一触发器132和第二触发器133可以启动，在逻辑信号IN为低电平时，第一触发器132和第二触发器133可以停止工作。
图4是图3所示脉冲消除电路100中不同位置的信号波形示意图。如图4所示，IN表示逻辑信号IN，开始IN为低电平，此时ENOSC也为0。随后IN上升，电路以IN的上升沿开始计时，此时电路开始工作，ENOSC变为高电平，OSC(振荡器111)启动，电路开始计算周期，当IN为高电平的时间超过nT(n是预设的时钟周期个数)，即OSC输出时钟超过n个周期时多输入与门电路131输出变为1，随后第一触发器132和第二触发器133依次被触发，即S_2与S_3依次变为1；然后与非门电路134的输出S_4由1变为0；S_4经过第一反相器135产生OUT信号，由0变为1；S_4经过第一与门电路112又将EN_OSC变为0，此时OUT输出为高电平，ENOSC为低电平，OSC关闭。当IN为高电平的持续时间少于nT时间时，OUT信号不会被触发。当逻辑信号IN变为低电平时，整个电路停止工作。
图5为本公开一实施例提供的电压检测电路示意图。如图5所示，该电压检测电路包括：图1或3所示的脉冲消除电路100，还可以包括迟滞比较器200。
迟滞比较器200的输出端连接时钟产生电路11，配置成提供逻辑信号IN至时钟产生电路11；迟滞比较器200的正向输入端配置成输入参考电压VREF，反向输入端配置成输入第二电压信号Vdet_2。迟滞比较器200配置成比较第二电压信号Vdet_2和参考电压，得到逻辑信号IN。
迟滞比较器200输出的逻辑信号IN可以作为使能信号提供至计数器12、第一触发器132和第二触发器133。
可选地，迟滞比较器200可以是一个具有迟滞回环传输特性的比较器。又可理解为加正反馈的单限比较器。在反相输入单门限电压比较器的基础上引入正反馈网络，就组成了具有双门限值的反相输入迟滞比较器200。迟滞比较器200的参考电压VREF为芯片内部参考电压，可以通过设置VREF电压来调节逻辑信号IN的电压阈值。
第二电压信号Vdet_2在递增接近上门限电压前，逻辑信号IN可以维持高电平不变。在第二电压信号Vdet_2再增加，逻辑信号IN可以保持低电平不变。若第二电压信号Vdet_2递减，只要大于下门限值，逻辑信号IN始终保持低电平不变，只有当第二电压信号Vdet_2小于下门限值时，逻辑信号IN才跳变到高电平。从而即使第二电压信号Vdet_2存在噪声和纹波，也不影响逻辑信号IN的结果，消除了噪声和纹波的干扰。
可选地，如图5所示，该电压检测电路还包括调压电路300。
可选地，调压电路300的输入端可以配置成输入第一电压信号Vdet，调压电路300的输出端可以连接迟滞比较器200的反向输入端，调压电路300可以配置成对第一电压信号 Vdet进行升压或降压，输出第二电压信号Vdet_2。
可选地，第一电压信号Vdet可以认为是待测电压信号。调压电路300可以对第一电压信号Vdet进行升压或降压。由于待测电压信号的电压值通常较高或较低，超过了后级迟滞比较器200的输入范围。因此需要将待检测电压降压或升压，调到符合迟滞比较器200的输入范围内。若待测电压信号较高，可通过电阻分压将其成固定比例降低；若待检测电压较低，可将其通过调压器按固定比例升压。这样便得到与待测电压信号成正比的第二电压信号Vdet_2。假设调压比例为固定值K，则有Vdet/Vdet_2＝K，又有△Vdet/△Vdet_2＝K。因此当待检测电压Vdet改变时，第二电压信号Vdet_2也会成固定比例变化。
可选地，所述调压电路中，所述对所述第一电压信号进行升压或降压，包括：通过调压器将所述第一电压信号以固定比例值进行升压；或者，通过分压电阻将所述第一电压信号以固定比例值进行降压。图6是本公开实施例提供的一种调压电路300示意图。如图6所示，将第一电压信号Vdet用电阻R1和电阻R2分压产生第二电压信号Vdet_2。计算公式Vdet_2＝(Vdet*R2)/((R1+R2))。通过调压电路300提前对待测电压信号进行降压，可以扩大电压检测的范围。
图7是本公开实施例提供的第一电压信号Vdet、第二电压信号Vdet_2、逻辑信号IN以及脉冲消除信号的波形示意图。
如图7所示，Vdet为第一电压信号(即待检测电压)，调压电路300可以将Vdet调至适合迟滞比较器200检测的第二电压信号Vdet_2；迟滞比较器200可以将第二电压信号Vdet_2与参考电压作比，输出逻辑信号IN；之后脉冲消除电路100可以消除错误短脉冲Tpulse。最终输出一个正确的脉冲消除信号OUT。
图8是本公开实施例提供的电压检测方法的流程示意图。该电压检测方法可以应用于图5对应实施例提供的电压检测电路。该电压检测方法可以包括以下步骤S810-步骤S830。
在步骤S810中，通过调压电路300接收待检测的第一电压信号，对所述第一电压信号进行升压或降压，得到第二电压信号；
在步骤S820中，通过迟滞比较器200比较所述第二电压信号和参考电压，得到逻辑信号；
在步骤S830中，通过脉冲消除电路100消除所述逻辑信号中包含的持续时间小于阈值的脉冲突变，得到脉冲消除信号。
脉冲突变是指信号变化持续的时间小于阈值的短脉冲，例如，脉冲持续小于10微秒，可以认为是短脉冲。
其中，上述调压电路300、迟滞比较器200和脉冲消除电路100可以参照上文实施例实现。
可选地，如图9所示，上述步骤830通过脉冲消除电路100消除所述逻辑信号中包含的持续时间小于阈值的脉冲突变，得到脉冲消除信号可以包括以下步骤。
步骤831：通过时钟产生电路11接收逻辑信号IN和第一输入信号S_4，输出时钟信号。第一输入信号S_4可以由信号输出电路13输出。
在时钟信号的周期个数小于预设个数时，信号输出电路13输出的第一输入信号S_4为高电平，时钟产生电路11接收高电平的逻辑信号IN和高电平的第一输入信号S_4，输出时钟信号。
步骤832：通过计数器12接收时钟信号，并统计时钟信号的周期个数，生成第二输入信号CK<N:0>。
计数器12可以统计时钟信号的周期个数，并输出多位二进制数字信号。例如，0111表示7个周期，1111表示15个周期。第二输入信号CK<N:0>就是计数器12生成的多位二进制数字信号。第二输入信号CK<N:0>可以输入信号输出电路13。
步骤833：通过信号输出电路13根据第二输入信号CK<N:0>，生成脉冲消除信号。
信号输出电路13接收到第二输入信号CK<N:0>，处理后生成脉冲消除信号。例如第二输入信号CK<N:0>是1111时，脉冲消除信号输出高电平。在第二输入信号CK<N:0>小于1111时(即时钟信号的周期个数小于15个时)，脉冲消除信号输出低电平。从而消除短时脉冲造成的干扰。
本公开实施例提供的电压检测电路和电压检测方法，可以应用于AMOLED(有源矩阵有机发光二极体面板)的驱动芯片中，可用于对外部提供的电源电压的检测，也可以用于对芯片内部产生电压的检测。实时监测电压情况，电压过低及异常掉电时，输出会有触发。
本公开实施例还提供了一种电子设备，该电子设备可以包括上述实施例所述的电压检测电路。其中，该电子设备可以包括AMOLED驱动装置、LCD(Liquid Crystal Display)驱动装置、电源管理装置或电压检测装置。
可选地，该电子设备可以是智能移动装置，智能移动装置可以是设有AMOLED显示屏或LCD显示屏的智能手机、智能穿戴设备、智能机器人等。
该电子设备还可以是显示装置，例如设有AMOLED显示屏或LCD显示屏的电视机、电脑或显示器。
该电子设备还可以是供电装置(例如补电盒、电箱、配电柜、UPS不间断电源)、直流电检测装置或报警装置。本公开实施例提供的电压检测电路可以安装于上述提供的电子设备中。
在本公开所提供的几个实施例中，所展示的装置和方法，也可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，附图中的流程图和框图显示了根据本公 开的多个实施例的装置、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或代码的一部分，模块、程序段或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。在有些作为替换的实现方式中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或动作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
另外，在本公开各个实施例中的各功能模块可以集成在一起形成一个独立的部分，也可以是各个模块单独存在，也可以两个或两个以上模块集成形成一个独立的部分。
功能如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
工业实用性
本公开实施例提供了脉冲消除电路、电压检测电路、检测方法以及电子设备，由于本公开实施例的脉冲消除电路包含了计数器、时钟产生电路和信号输出电路，能够在逻辑信号持续的周期个数达到一定数量时，脉冲消除信号可以输出高电平，由此可以消除逻辑信号中包含的短脉冲，进而消除了短脉冲造成的误触发，提高了信号稳定性以及电压检测的准确性。

Claims (16)

  1. 一种脉冲消除电路，其特征在于，包括：
    时钟产生电路，配置成接收逻辑信号以及第一输入信号，并根据所述逻辑信号和所述第一输入信号生成时钟信号；
    计数器，连接所述时钟产生电路，配置成接收所述时钟信号，并统计所述时钟信号的周期个数，生成第二输入信号；
    信号输出电路，连接所述计数器，配置成提供所述第一输入信号至所述时钟产生电路，并根据所述第二输入信号生成脉冲消除信号。
  2. 根据权利要求1所述的脉冲消除电路，其特征在于，所述时钟产生电路包括：
    第一与门电路，所述第一与门电路的一个输入端配置成接收所述逻辑信号，所述第一与门电路的另一个输入端配置成接收所述第一输入信号；
    振荡器，使能端连接所述第一与门电路的输出端；
    第二与门电路，所述第二与门电路的一个输入端配置成接收所述第一输入信号，所述第二与门电路的另一个输入端连接所述振荡器的时钟脉冲输出端；所述第二与门电路的输出端连接所述计数器，配置成向所述计数器输出所述时钟信号。
  3. 根据权利要求1或2所述的脉冲消除电路，其特征在于，所述信号输出电路包括：
    多输入与门电路，所述多输入与门电路的多个输入端配置成输入所述第二输入信号；
    第一触发器，所述第一触发器的信号输入端连接所述多输入与门电路的输出端；
    第二触发器，所述第二触发器的信号输入端连接所述第一触发器的信号输出端；
    与非门电路，所述与非门电路的一个输入端连接所述第一触发器的信号输出端，所述与非门电路的另一个输入端连接所述第二触发器的信号输出端；所述与非门电路的输出端配置成向所述时钟产生电路输出所述第一输入信号；
    第一反相器，所述第一反相器的输入端连接所述与非门电路的输出端；所述第一反相器的输出端配置成输出所述脉冲消除信号。
  4. 根据权利要求3所述的脉冲消除电路，其特征在于，所述第一触发器的时钟脉冲输入端连接所述时钟产生电路的时钟信号输出端。
  5. 根据权利要求3或4所述的脉冲消除电路，其特征在于，所述信号输出电路还包括：第二反相器；所述第二反相器的一端连接所述时钟产生电路的时钟信号输出端，所述第二反相器的另一端连接所述第二触发器的时钟脉冲输入端。
  6. 根据权利要求3至5中任一项所述的脉冲消除电路，其特征在于，所述第一触发器和所述第二触发器的使能端配置成输入所述逻辑信号。
  7. 根据权利要求1至6中任一项所述的脉冲消除电路，其特征在于，所述计数器的使能端配置成输入所述逻辑信号。
  8. 根据权利要求1至7中任一项所述的脉冲消除电路，其特征在于，所述计数器中，所述第二输入信号包括所述计数器的多路输出信号。
  9. 根据权利要求8所述的脉冲消除电路，其特征在于，所述信号输出电路中，所述根据所述第二输入信号生成脉冲消除信号，包括：
    确定所述计数器的多路输出信号均为高电平时，生成所述脉冲消除信号。
  10. 一种电压检测电路，其特征在于，包括：
    权利要求1-9中任一项所述的脉冲消除电路；
    迟滞比较器，所述迟滞比较器的输出端连接所述时钟产生电路，配置成提供所述逻辑信号至所述时钟产生电路；
    所述迟滞比较器的正向输入端配置成输入参考电压，反向输入端配置成输入第二电压信号；
    所述迟滞比较器配置成比较所述第二电压信号和参考电压，并基于比较结果输出相应的所述逻辑信号。
  11. 根据权利要求10所述的电压检测电路，其特征在于，还包括：
    调压电路，所述调压电路的输入端配置成输入第一电压信号，所述调压电路的输出端连接所述迟滞比较器的反向输入端；
    所述调压电路配置成对所述第一电压信号进行升压或降压，得到所述第二电压信号。
  12. 根据权利要求11所述的电压检测电路，其特征在于，所述调压电路中，所述对所述第一电压信号进行升压或降压，包括：
    通过调压器将所述第一电压信号以固定比例值进行升压；或者，
    通过分压电阻将所述第一电压信号以固定比例值进行降压。
  13. 一种电压检测方法，其特征在于，包括：
    通过调压电路接收待检测的第一电压信号，对所述第一电压信号进行升压或降压，得到第二电压信号；
    通过迟滞比较器比较所述第二电压信号和参考电压，得到逻辑信号；
    通过脉冲消除电路消除所述逻辑信号中包含的持续时间小于阈值的脉冲突变，得到脉冲消除信号。
  14. 一种电子设备，其特征在于，包括权利要求10至12中任一项所述的电压检测电路。
  15. 根据权利要求14所述的电子设备，其特征在于，所述电子设备包括AMOLED驱动装置、LCD驱动装置、电源管理装置或电压检测装置。
  16. 根据权利要求14所述的电子设备，其特征在于，所述电子设备为智能移动装置、显示装置、供电装置、直流电检测装置或报警装置。
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Publication number Priority date Publication date Assignee Title
CN111404517B (zh) * 2020-04-08 2023-11-10 北京集创北方科技股份有限公司 脉冲消除电路、电压检测电路以及检测方法
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101267194A (zh) * 2008-04-18 2008-09-17 启攀微电子（上海）有限公司 一种毛刺的判断及消除电路
CN103222193A (zh) * 2011-08-03 2013-07-24 松下电器产业株式会社 指令检测装置
US20150317496A1 (en) * 2012-08-03 2015-11-05 Freescale Semiconductor, Inc. Method and apparatus for limiting access to an integrated circuit (ic)
CN110690822A (zh) * 2018-07-06 2020-01-14 立锜科技股份有限公司 有过电压保护的返驰式电源供应电路及其一次侧控制电路
CN111404517A (zh) * 2020-04-08 2020-07-10 北京集创北方科技股份有限公司 脉冲消除电路、电压检测电路以及检测方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0136619B1 (ko) * 1995-03-20 1998-06-01 김주용 노이즈 제거 회로
US5687202A (en) * 1995-04-24 1997-11-11 Cyrix Corporation Programmable phase shift clock generator
JPH09149288A (ja) * 1995-11-20 1997-06-06 Fujitsu General Ltd 等価パルス除去回路
US6094082A (en) * 1998-05-18 2000-07-25 National Semiconductor Corporation DLL calibrated switched current delay interpolator
JP2000065881A (ja) * 1998-08-25 2000-03-03 Hitachi Ltd 電力変換器の故障モニタ装置
CN102103679B (zh) * 2009-12-18 2014-10-15 上海华虹集成电路有限责任公司 自适应场强变化的a/b模式检测电路
EP3149848A1 (en) * 2014-06-02 2017-04-05 Telefonaktiebolaget LM Ericsson (publ) Oscillator circuit with bias current generator
CN105897220A (zh) * 2016-03-31 2016-08-24 珠海矽尚科技有限公司 一种针对逻辑端口的双边数字滤波电路
US10003328B1 (en) * 2017-08-17 2018-06-19 Qualcomm Incorporated Hybrid pulse-width control circuit with process and offset calibration
CN110581698A (zh) * 2018-06-08 2019-12-17 恩智浦美国有限公司 数字毛刺滤波器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101267194A (zh) * 2008-04-18 2008-09-17 启攀微电子（上海）有限公司 一种毛刺的判断及消除电路
CN103222193A (zh) * 2011-08-03 2013-07-24 松下电器产业株式会社 指令检测装置
US20150317496A1 (en) * 2012-08-03 2015-11-05 Freescale Semiconductor, Inc. Method and apparatus for limiting access to an integrated circuit (ic)
CN110690822A (zh) * 2018-07-06 2020-01-14 立锜科技股份有限公司 有过电压保护的返驰式电源供应电路及其一次侧控制电路
CN111404517A (zh) * 2020-04-08 2020-07-10 北京集创北方科技股份有限公司 脉冲消除电路、电压检测电路以及检测方法

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