WO2021195979A1

WO2021195979A1 - Data storage method and related device

Info

Publication number: WO2021195979A1
Application number: PCT/CN2020/082483
Authority: WO
Inventors: 冉宜; 孙亚萍; 王金伟
Original assignee: 华为技术有限公司
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2021-10-07
Also published as: CN115298654A

Abstract

Embodiments of the present application disclose a data storage method and a related device. The method is applicable to a storage class memory, and comprises: measuring a bit error rate when current data is being read; determining, according to the bit error rate, a mapping relationship used to store the data to a storage class memory, wherein the mapping relationship comprises an association between a physical block address and a memory address; and performing data storage according to the mapping relationship. A bit error rate is measured when current data is being read, so as to determine a mapping relationship for storing the data to a storage class memory, and to perform data storage according to the mapping relationship, thereby effectively avoiding the use of a mapping relationship associated with a centralized memory failure for data storage, and accordingly reducing the check bit length required for a physical block address in a mapping relationship, and increasing an available storage space.

Description

Data storage method and related device

Technical field

This application relates to the field of storage technology, and in particular to a data storage method and related devices.

Background technique

Storage class memory (SCM), as a new type of non-volatile storage technology, has the characteristics of high read and write speed and high storage density. In order to achieve the characteristics of high storage density, storage-level memory usually adopts a crossbar or crosspoint structure. As shown in FIG. 1, the crossbar array is a structure in which multiple sets of bitlines (BL) and wordlines (WL) are stacked alternately, and the memory cells are controlled by the bitlines and wordlines.

In practical applications, the user accesses the storage-level memory through the operating system, specifically by accessing a logical block address (logical block address, LBA), and each LBA is mapped to a corresponding physical block address (physical block address, PBA). The physical block address is the underlying physical address of the storage-level memory. Each physical block address corresponds to multiple storage units. Since each storage unit has an independent media address (memory address, MA), each physical block address corresponds to Multiple media addresses.

In order to correct the errors generated when storing data in storage-level memory, error checking and correcting (ECC) is usually used to correct the data. The length of the check bit used in the error correction and the erroneous data in each physical block address are used. The length is positively correlated. Due to manufacturing defects in the semiconductor process, adjacent memory cells may make errors at the same time. Such errors are called concentrated failures. Concentration failure will increase the length of erroneous data in a single physical block address. Therefore, the length of the parity bit needs to be increased to implement error correction of data errors caused by centralized failure. A longer parity bit increases data redundancy and reduces available storage space.

Summary of the invention

In view of this, the embodiments of the present application provide a data storage method and related devices, which detect the bit error rate of the current data to select the mapping relationship corresponding to the current data, and use the mapping relationship to store the data. Therefore, it is possible to effectively avoid the use of a centralized failure mapping relationship to store data, thereby reducing the length of the check bit required by the physical block address, and increasing the available storage space.

In the first aspect, an embodiment of the present application provides a data storage method, which is applied to storage-level memory, and may include: first, detecting a symbol error rate (SER) when reading current data. Secondly, according to the bit error rate, determine the mapping relationship used to store data to the storage-level memory, where the mapping relationship includes the association relationship between the physical block address and the media address, and the mapping relationship is, for example, (physical block address A- Media address B). Again, data storage is performed according to the mapping relationship.

In the embodiment of the present application, the storage device can detect the bit error rate of the data (current data) in real time, and then select the mapping relationship corresponding to the current data according to the bit error rate of the current data. Finally, the data is stored according to the selected mapping relationship. By detecting the bit error rate of the data corresponding to the mapping relationship, for example: the bit error rate of the data stored in the media address B, it is determined whether a centralized failure occurs in the mapping relationship (physical block address A-media address B). Specifically, according to the bit error rate, choose what mapping relationship to use to store the data. By detecting the bit error rate when the current data is read, the mapping relationship used to store the data to the storage-level memory is determined. This can effectively avoid the use of a centralized failure mapping relationship (the data in the mapping relationship has a larger bit error rate) to store data, thereby reducing the check bit length required by the physical block address in the mapping relationship, and increasing the available storage space .

With reference to the first aspect, in a possible implementation of the first aspect, determining the mapping relationship for storing data to the storage-level memory according to the bit error rate includes: when the bit error rate is greater than a preset threshold, The second mapping relationship is determined as the mapping relationship, where, under the second mapping relationship and the first mapping relationship, the association relationship between the physical block address and the media address is different, and the first mapping relationship is that the current data read When fetching, the storage-level memory performs data storage based on the first mapping relationship. In an optional implementation manner, the preset threshold may be 5 bits.

In the embodiment of the present application, the mapping relationship is determined by comparing the relationship between the bit error rate and the preset threshold. When the bit error rate is greater than the preset threshold, the second mapping relationship is determined as the mapping relationship. Due to the high bit error rate, it is necessary to select a mapping relationship (second mapping relationship) that is different from the existing mapping relationship (first mapping relationship), for example: the physical block address A in the first mapping relationship is mapped to media addresses 1-4 , The physical block address B is mapped to the media address 10-15, because when the data stored using the first mapping relationship is read, the bit error rate of the detected data is relatively high. Therefore, a second mapping relationship is used to store data, in which physical block address A is mapped to

media address

1, 3, 5, or 7, and physical block address B is mapped to media address 10-15. Therefore, it is avoided to use a mapping relationship that has a centralized failure (the centralized failure occurs at certain media addresses in the mapping relationship) to store data.

With reference to the first aspect, in a possible implementation of the first aspect, determining the mapping relationship for storing data to the storage-level memory according to the bit error rate includes: when the bit error rate is less than or equal to the When the threshold is preset, the first mapping relationship is determined as the mapping relationship. When the bit error rate is less than or equal to the preset threshold, the first mapping relationship is determined as the mapping relationship. Since the bit error rate is small, there is no need to change the mapping relationship, and the read and write resources of the storage device can be saved.

With reference to the first aspect, in a possible implementation of the first aspect, a first mapping relationship is obtained, where the first mapping relationship includes a first physical block address and a first medium address, and the first physical block address and the second A media address is associated, the first mapping relationship is for example (logical block address 1-physical block address 1-media address 1); a second mapping relationship is generated according to the first mapping relationship, and the second mapping relationship includes the first physical The block address and the second media address, the first physical block address is associated with the second media address, the second media address is inconsistent with the first media address, and the second mapping relationship is for example (logical block address 1-physical block Address 1-Media Address 2). The first media address and the second media address are on the same die, or the first media address and the second media address are on different die; if the error rate of the data in the second media address is less than the first media address If the bit error rate of the data in the middle, the second mapping relationship is used to store the data.

In the embodiment of the present application, a first mapping relationship is acquired, and the first mapping relationship includes a first physical block address and a first media address, and the first physical block address is associated with the first media address. Then, a second mapping relationship is generated according to the first mapping relationship, the second mapping relationship includes the first physical block address and the second media address, and the first physical block address is associated with the second media address. When storing data, if the error rate of the data in the second media address is less than the error rate of the data in the first media address, the second mapping relationship is used to store the data. By changing the mapping relationship between the physical block address and the media address, the media addresses with centralized failures are assigned to different mapping relationships, thereby reducing the amount of error data generated by the centralized failure in a single physical block address, thereby reducing the physical The length of the check bit required by the block address increases the available storage space.

With reference to the first aspect, in a possible implementation of the first aspect, it may further include: generating a third mapping relationship according to the first mapping relationship, the third mapping relationship including the second physical block address, the third medium Address, the second physical block address is associated with the third media address, the second physical block address is associated with the third media address, the second physical block address is inconsistent with the first physical block address, the third The media address is inconsistent with the second media address, and the third media address includes part of the first media address. For example, the first mapping relationship is: the first physical block address LBA=X0b, and the first medium address (MA: X000/MA: X001/MA: X010/MA: X011). The third mapping relationship is generated according to the first mapping relationship, including: the second physical block address LBA=X1b, the third medium address (MA: X000/MA: X101/MA: X110/MA: X111), and the third medium address is Including part of the first media address "MA: X000"; use the third mapping relationship to store data.

In the embodiment of the present application, the first medium address included in the first mapping relationship belongs to the management of the third mapping relationship. In the third mapping relationship, the third medium address is associated with the second physical block address, and the third medium The address includes part of the first media address. Distribute the centralized failures in the first media address to different mapping relationships, thereby reducing the amount of erroneous data generated due to centralized failures in a single physical block address, thereby reducing the length of the check bit required by the physical block address To increase the available storage space.

With reference to the first aspect, in a possible implementation of the first aspect, it may include: when the first data is read, a first symbol error rate (SER) is detected, where the value of the first data The storage area is the address of the first medium; when the first error rate is greater than or equal to the first threshold, the first data and the second data are backed up, where the storage area of the second data is the second medium Address, the first threshold value is, for example, 5% or 8%. The first error rate may also be the length of the error data. In this case, the first threshold may be 5 bits; clear the data stored in the first media address and the second media address; use the second The mapping relationship stores the first data, or the third mapping relationship is used to store the first data. The data storage method proposed in the embodiments of this application can store data using different mapping relationships according to the bit error rate of the data when reading the data, which ensures the reliability of the data during the user’s use, and improves the efficiency of the solution. Achieve flexibility.

With reference to the first aspect, in a possible implementation of the first aspect, it may include: detecting a second bit error rate, where the second bit error rate is the value of the second data stored in the second media address Error rate; when the first error rate is greater than the second error rate, according to the second mapping relationship, the first data in the backup is stored in the second media address and the second media address is detected and stored The bit error rate of the second data is called the second bit error rate. In an optional implementation manner, before generating the second mapping relationship, the second data stored in the second media address needs to be backed up, and the bit error rate of the second data is detected in the process of reading the second data , The bit error rate is also the bit error rate of the second media address. In another optional implementation manner, after backing up the second data, first, clear the data stored in the second media address. Secondly, the storage device uses preset data to perform bit error rate detection on the second media address (corresponding storage unit) to obtain the second bit error rate. When the first error rate is greater than the second error rate, the second mapping relationship is used to store the data. When the first error rate is less than or equal to the second error rate, the storage unit corresponding to the second medium address in the second mapping relationship also has a centralized failure. The storage device needs to use other mapping relationships to store data. In the embodiment of the present application, after the storage device generates the second mapping relationship according to the first mapping relationship, it can detect the bit error rate (second bit error rate) of the second medium address in the second mapping relationship. The mapping method used when storing data is determined according to the first error rate and the second error rate. It is ensured that the bit error rate in the mapping relationship used by the storage device is low, the check bit length required by the physical block address is reduced, and the available storage space is increased.

With reference to the first aspect, in a possible implementation of the first aspect, it may include: acquiring a first detection instruction, where the first detection instruction is used to trigger detection of the bit error rate of the current data, and the first detection instruction It is an instruction that is automatically triggered periodically in the idle state, or the first detection instruction is an instruction that is actively triggered by the user. The first detection instruction may be obtained in various ways, and the first detection instruction is used to trigger the bit error rate of the current data and perform subsequent steps such as selecting the mapping relationship. Improved the flexibility of the solution.

With reference to the first aspect, in a possible implementation of the first aspect, it may include: writing third data to the first medium address according to the first detection instruction and the first mapping relationship. In an optional implementation manner, before the storage device leaves the factory, the storage device obtains the first detection instruction. First, the storage device writes third data to the first medium address according to the first detection instruction and the first mapping relationship. The third data is the test data used when detecting the bit error rate. Then, the storage device writes the third data to the second medium address according to the first detection instruction and the second mapping relationship. In another optional implementation manner, when the user uses the storage device, the media address with a higher error rate may be disabled through the first detection instruction to ensure data security. Specifically, first, the storage device backs up the data in the first media address and the data in the second media address according to the first detection instruction. Then, the storage device writes third data into the first media address and the second media address, respectively. In another optional implementation manner, the first detection instruction may be an instruction automatically triggered when the storage device is in an idle state. It can also be an instruction that is automatically triggered by the storage device periodically, and there is no restriction here. According to the first detection instruction and the second mapping relationship, write the third data to the second media address; detect a third error rate, the third error rate is the third data in the first media address The fourth error rate is detected, and the fourth error rate is the error rate of the third data in the second media address; the stored data is determined according to the third error rate and the fourth error rate The mapping relationship used at the time. In an optional implementation manner, when the third error rate is greater than the fourth error rate, the first mapping relationship is used to store the data. When the third error rate is less than or equal to the fourth error rate, the second mapping relationship is used to store the data. In another optional implementation manner, when the third error rate is greater than the first threshold, the second mapping relationship is used to store the data; when the fourth error rate is greater than the first threshold, the first The mapping relationship stores data.

In the embodiment of the present application, the storage device can detect the bit error rate of the media address in each current mapping relationship according to the first detection instruction before leaving the factory or during use, and determine the mapping relationship used when storing data according to the bit error rate. To improve the storage security of data.

In a second aspect, an embodiment of the present application provides a storage device. The storage device may include: a processing module for detecting the bit error rate of the current data; and the processing module for determining the bit error rate for The mapping relationship between data storage to the storage-level memory, where the mapping relationship includes the association relationship between the physical block address and the media address; the storage module is used to store the data using the selected mapping relationship.

With reference to the second aspect, in a possible implementation of the second aspect, the processing module is specifically configured to select the changed mapping relationship corresponding to the current data when the bit error rate of the current data is greater than a preset threshold; The processing module is specifically used to select the original mapping relationship corresponding to the current data when the bit error rate of the current data is less than or equal to the preset threshold.

With reference to the second aspect, in a possible implementation of the second aspect, the acquiring module is configured to acquire a first mapping relationship, where the first mapping relationship includes the first physical block address and the first medium address, and the first physical block address Associated with the first media address; a processing module, configured to generate a second mapping relationship according to the first mapping relationship, the second mapping relationship including the first physical block address and the second media address, the first physical block address and the second media address Correlation, the second media address is inconsistent with the first media address.

With reference to the second aspect, in a possible implementation of the second aspect, the storage module is configured to use the second mapping if the error rate of the data in the second media address is less than the error rate of the data in the first media address Relational storage data.

With reference to the second aspect, in a possible implementation of the second aspect, the processing module is further configured to generate a third mapping relationship according to the first mapping relationship, and the third mapping relationship includes the second physical block address and the third media address , The second physical block address is associated with the third media address, the second physical block address is associated with the third media address, the second physical block address is inconsistent with the first physical block address, and the third media address is inconsistent with the second media address , The third media address includes part of the first media address; the storage module is also used to store data using the third mapping relationship.

With reference to the second aspect, in a possible implementation of the second aspect, the first media address and the second media address are located on the same die, or the first media address and the second media address are located on different die.

With reference to the second aspect, in a possible implementation of the second aspect, the storage device further includes: a processing module, which is also used to detect the first bit error rate when reading the first data, where the first data The storage area is the first media address; the storage module is also used to back up the first data and the second data when the first error rate is greater than or equal to the first threshold value, where the storage area of the second data is the second Media address; the storage module is also used to clear the data stored in the first media address and the second media address.

With reference to the second aspect, in a possible implementation of the second aspect, the storage device further includes: a storage module, further configured to store the first data using the second mapping relationship, or store the first data using the third mapping relationship .

With reference to the second aspect, in a possible implementation of the second aspect, the storage device further includes: a processing module, which is further configured to detect a second bit error rate, where the second bit error rate is stored in the second medium address The bit error rate of the second data; the processing module is also used to determine the mapping relationship used when storing the data according to the first bit error rate and the second bit error rate.

With reference to the second aspect, in a possible implementation of the second aspect, the storage module is specifically configured to store data using a second mapping relationship when the first error rate is greater than the second error rate; the storage module is specifically It is used to store data using the third mapping relationship when the first error rate is less than or equal to the second error rate.

With reference to the second aspect, in a possible implementation of the second aspect, the storage module is specifically configured to store the first data in the backup to the second media address according to the second mapping relationship.

With reference to the second aspect, in a possible implementation of the second aspect, the storage module is specifically configured to store the second data in the backup to the first media address and the third media address according to the third mapping relationship.

With reference to the second aspect, in a possible implementation of the second aspect, the storage device further includes: an acquisition module, which is further configured to acquire a first detection instruction, and the first detection instruction is used to trigger detection of the bit error rate of the current data, The first detection instruction is an instruction that is automatically triggered in the idle state, or the first detection instruction is an instruction that is actively triggered by the user.

With reference to the second aspect, in a possible implementation of the second aspect, the storage device further includes: a storage module, further configured to write third data to the first medium address according to the first detection instruction and the first mapping relationship The storage module is also used to write third data to the second media address according to the first detection instruction and the second mapping relationship; the processing module is also used to detect the third bit error rate, the third bit error rate is the first The bit error rate of the third data in the media address; the processing module is also used to detect the fourth bit error rate, and the fourth bit error rate is the bit error rate of the third data in the second media address; the processing module is also used to The third error rate and the fourth error rate determine the mapping relationship used when storing data.

With reference to the second aspect, in a possible implementation of the second aspect, the storage module is specifically configured to use the first mapping relationship to store data when the third error rate is greater than the fourth error rate; the storage module specifically It is used to store data using the second mapping relationship when the third error rate is less than or equal to the fourth error rate.

In the third aspect, the embodiments of the present application provide a computer device. The terminal device includes at least one processor, a memory, a communication port, a display, and computer-executable instructions stored in the memory and running on the processor. When the computer When the execution instruction is executed by the processor, the processor executes the foregoing first aspect or any one of the possible implementation manners of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor executes the first aspect or the first aspect described above. Any one of the possible implementation methods.

In the fifth aspect, the embodiments of the present application provide a computer program product (or computer program) that stores one or more computer-executable instructions. When the computer-executable instructions are executed by the processor, the processor executes the above-mentioned first aspect. Or any possible implementation of the first aspect.

In a sixth aspect, the present application provides a chip system including a processor for supporting computer equipment to implement the functions involved in the above aspects. In a possible design, the chip system further includes a memory for storing necessary program instructions and data for the computer equipment. The chip system can be composed of chips, and can also include chips and other discrete devices.

In a seventh aspect, an embodiment of the present application also provides a storage device, the storage device includes a processor, a buffer, and a memory, the memory includes one or more storage units, and the buffer stores program instructions; wherein the The processor executes the foregoing first aspect or any one of the possible implementation manners of the first aspect, and stores data in the memory according to the program instruction; the memory is used to store data according to the instruction.

Description of the drawings

Figure 1 is a schematic diagram of the structure of a crossbar array;

Figure 2 is a schematic diagram of a system framework proposed by an embodiment of the application;

FIG. 3 is a schematic diagram of an embodiment of a data storage method proposed in an embodiment of this application;

4 is a schematic diagram of another embodiment of the data storage method proposed in the embodiment of the application;

FIG. 5 is a schematic diagram of another embodiment of a data storage method proposed in an embodiment of this application;

FIG. 6 is a schematic diagram of another embodiment of a data storage method proposed in an embodiment of the application;

FIG. 7 is a schematic diagram of a mapping relationship proposed in an embodiment of this application;

FIG. 8 is a schematic diagram of another mapping relationship proposed by an embodiment of the application;

FIG. 9 is a schematic diagram of another mapping relationship proposed in an embodiment of this application;

FIG. 10 is a schematic diagram of an association relationship between check digits and data involved in an embodiment of this application;

FIG. 11 is a schematic diagram of an embodiment of a storage device in an embodiment of the application;

FIG. 12 is a schematic diagram of the hardware structure of the computer device 1200 in an embodiment of the application.

Detailed ways

The embodiments of the present application provide a data storage method and related devices. First, a first mapping relationship is obtained. The first mapping relationship includes a first physical block address and a first media address, and the first media address is the same as the first physical block address. Associated; secondly, a second mapping relationship is generated according to the first mapping relationship, the second mapping relationship includes a first physical block address and a second media address, the first physical block address is associated with the second media address, and the second The media address is inconsistent with the first media address; again, the second mapping relationship is used to store data. When the centralized failure occurs in the storage unit corresponding to the first media address, the check bit required by the first physical block address is longer, which leads to increased data redundancy and reduces the available storage space of the memory. The second mapping relationship is generated according to the first mapping relationship. In the second mapping relationship, the media address managed by the first physical block address is the second media address, which avoids the storage unit that has centralized failure (the first media address corresponds to the Media address). Therefore, when the second mapping relationship is used to store data, the length of the check bit required by the first physical block address can be effectively reduced, and the available storage space is increased.

For ease of understanding, please refer to FIG. 2, which is a schematic diagram of a system framework according to an embodiment of the application. The data storage method proposed in the embodiments of the present application can be applied to storage-level memory. When the storage memory is deployed in a computer device, the host (central processing unit, motherboard, etc.) of the computer device can establish a communication connection with the storage-level memory through a bus. . The data storage instructions and data read instructions from the host are transmitted to the storage-level memory through the bus. The processor in the storage-level memory processes these instructions, and then reads or writes data from die 1 to die N corresponding to these instructions, where N is a positive integer.

Specifically, the host sends a data read instruction (or data storage instruction) to the storage-level memory through the bus, and the instruction carries the logical block address. After the storage-level memory receives the instruction, it determines the physical block address corresponding to the logical block address according to the mapping relationship list, and the mapping relationship list is stored in the buffer in the storage-level memory. Each physical block address corresponds to one or more storage units (such as the storage unit shown in Figure 1), and each storage unit has an independent media address. These storage units can be on the same die. The storage unit can also be a storage unit on a different die. Therefore, each physical block address corresponds to one or more media addresses, and the mapping relationship between these physical block addresses and media addresses is also stored in the buffer in the form of a mapping relationship list. For ease of understanding, please refer to Table 1.

Table 1

It should be noted that the data storage method proposed in the embodiments of this application can be applied to other storage devices in addition to storage-level memory (SCM), and it is not limited here, such as read-only memory (read-only memory). , ROM), programmable read-only memory (programmable rom, PROM), erasable programmable read-only memory (erasable prom, EPROM), electrically erasable programmable read-only memory (electrically eprom, EEPROM) or flash memory.

Hereinafter, the embodiments of the present application will be introduced with reference to the accompanying drawings. Please refer to FIG. 3, which is a schematic diagram of an embodiment of a data storage method according to an embodiment of the application. Taking the application of the data storage method to storage-level memory as an example, a data storage method proposed in an embodiment of the present application includes:

301. Obtain a first mapping relationship.

In this embodiment, the storage device of the data storage method proposed in the embodiment of the present application is deployed. During the operation, first, the bit error rate when reading the current data is detected. Secondly, according to the bit error rate, determine the mapping relationship used to store data to the storage device (in this embodiment, the storage device is a storage-level memory), and the mapping relationship includes the association relationship between the physical block address and the media address .

When the bit error rate is greater than the preset threshold, the second mapping relationship is determined as the mapping relationship, wherein, under the second mapping relationship and the first mapping relationship, the media addresses corresponding to the same physical block address are different, and the first The mapping relationship is that when the current data is read, the storage-level memory performs data storage based on the first mapping relationship. When the bit error rate is less than or equal to the preset threshold, the first mapping relationship is determined as the mapping relationship. For example, the first mapping relationship is: the physical block address A is associated with the medium address B, and the mapping relationship is still used Storing data.

In the following, when the bit error rate is greater than the preset threshold, determining the second mapping relationship as the mapping relationship will be described in detail:

First, obtain the first mapping relationship. The first mapping relationship includes a first physical address and a first media address, and the first physical address is associated with the first media address. Refer to Table 2 for the first mapping relationship.

Table 2

Specifically, the first mapping relationship is cached in a buffer in the storage-level memory in the form of a mapping relationship list. The first mapping relationship may be configured by a computer device, or may be pre-configured before the storage-level memory leaves the factory. No restrictions.

It should be noted that in the first mapping relationship, the first media address may be multiple media addresses, which is not limited here. For example: the first mapping relationship includes the first physical block address (PBA1) and the first medium address (MA: X000/MA: X001/MA: X010/MA: X011), and the first physical block address is related to the first medium address . The first physical block address manages the first media address.

302. Generate a second mapping relationship according to the first mapping relationship.

In this embodiment, the storage device generates a second mapping relationship according to the first mapping relationship. The second mapping relationship includes the first physical block address and the second media address, the first physical block address is associated with the second media address, and the second The media address is inconsistent with the first media address. The first media address may be one or more media addresses, and the second media address may be one or more media addresses. The first media address and the second media address may be located on the same die, or may be located on different dies, which is not limited here. When the first media address includes multiple media addresses, the first media address may be located in the same die or in different die. The second media address may be located in the same die as the first media address, or may be located in a die different from the first media address, which is not limited here.

It should be noted that the method for determining the second media address in the second mapping relationship may be pre-configured. For example, when the storage device needs to generate the second mapping relationship, the storage device selects one of all media addresses according to the pre-configured rule. Or multiple media addresses, and a part of the media address (one or more media addresses) is selected from the first media address as the second media address in the second mapping relationship. It may also randomly select one or more media addresses from all the media addresses currently managed, and select part of the media addresses (one or more media addresses) from the first media addresses as the second media addresses in the second mapping relationship, There is no limitation here. The pre-configured rule can be to select a single-digit media address, or a dual-digit media address, or to select one of the media addresses at intervals of N media addresses, where N is a positive integer, and there is no restriction here.

Refer to Table 3 for the second mapping relationship.

table 3

It should be noted that in the second mapping relationship, the second media address may be one or more media addresses, which is not limited here. The second media address included in the second mapping relationship may be the same as the number of the first media address included in the first mapping relationship. For example, the first media address shown in Table 2 and Table 3 includes 4 media addresses, and the second The media address includes 4 media addresses; the first media address may also be inconsistent with the second media address. For example, the first media address includes: (MA:X0000/MA:X0100/MA:X0010/MA:X0110/MA: X1110), the second media address includes: (MA: X0000/MA: X0100/MA: X0010/MA: X0110), there is no restriction here.

In the prior art, as shown in FIG. 10, a code is set after each piece of data in the storage device. The code is called error checking and correcting (ECC), and the code is also called check digit. Used to check and correct data errors. Generally, an ECC check bit is set after each physical block address. If some storage units in the current storage device will have a centralized failure, it is necessary to consider that the data length of some physical block addresses with errors is relatively large. Correspondingly, a longer ECC check bit needs to be designed.

In an optional implementation manner, please refer to FIG. 7, which is a schematic diagram of a mapping relationship proposed in an embodiment of the application. The first mapping relationship shown in FIG. 7 is the first physical block address "PBA1", and the first media address corresponding to the first physical block address is "(1)/(2)/(3)/(4)" , The first media address is located in the same die "Die1". When the transmission concentration fails, the storage unit corresponding to the first media address fails, and the data stored in "(1)/(2)/(3)/(4)" has a higher error rate. Before changing the mapping relationship, the media address corresponding to the physical block address "PBA2" is "(5)/(6)/(7)/(8)". In order to realize failure dispersion, a second mapping relationship is generated according to the first mapping relationship. The second mapping relationship includes the first physical block address "PBA1" and the corresponding second media address "(1)/(6)/(3)/(8)". The media address corresponding to the physical block address "PBA2" is "(5)/(2)/(7)/(4)". Through the above method, the ECC check bit length required by the second mapping relationship is halved compared to the ECC check bit length required by the first mapping relationship. The above media address is located in the same die "Die1".

In another optional implementation manner, the first physical block address in the first mapping relationship is "PBA1", and the first media address corresponding to the first physical block address is "(1)/(2)/(3) )/(4)". In the second mapping relationship generated according to the first mapping relationship, the second medium address corresponding to the first physical block address is "(1)/(5)/(3)/(4)".

In another optional implementation manner, please refer to FIG. 8. FIG. 8 is a schematic diagram of another mapping relationship proposed in an embodiment of this application. The first mapping relationship shown in FIG. 8 is the first physical block address "PBA1", and the first media address corresponding to the first physical block address is "(1)/(2)/(3)/(4)" , The first media address is located in the same die "Die1". Before changing the mapping relationship, the media address corresponding to the physical block address "PBA2" is "(5)/(6)/(7)/(8)", which is located on the same die "Die2". After the second mapping relationship is generated according to the first mapping relationship, the second medium address corresponding to the first physical block address in the second mapping relationship is "(1)/(6)/(3)/(8)", where the medium The address "(1)/(3)" is located on the die "die1", and the media address "(6)/(8)" is located on the die "die2".

Specifically, the second mapping relationship is stored in the buffer of the storage-level memory in the form of a mapping relationship list.

303. Use the second mapping relationship to store data.

In this embodiment, after the storage device generates the second mapping relationship, the second mapping relationship is used to store data. Specifically, after the storage device receives the data storage instruction, when the logical block address carried by the data storage instruction is LBA:X0b, the storage device determines the first physical block address (PBA1) corresponding to the logical block address according to the second mapping relationship And the second medium address (MA: X000/MA: X100/MA: X010/MA: X110). The storage device stores relevant data in the storage unit corresponding to the second medium address.

In the embodiment of the present application, firstly, a first mapping relationship is obtained, and the first mapping relationship includes a first physical block address and a first medium address, and the first medium address is associated with the first physical block address; secondly, according to the first mapping The relationship generates a second mapping relationship, the second mapping relationship includes a first physical block address and a second media address, the first physical block address is associated with a second media address, and the second media address is inconsistent with the first media address; Again, the second mapping relationship is used to store data. When the centralized failure occurs in the storage unit corresponding to the first media address, the check bit required by the first physical block address is longer, which leads to increased data redundancy and reduces the available storage space of the memory. The second mapping relationship is generated according to the first mapping relationship. In the second mapping relationship, the media address managed by the first physical block address is the second media address, which avoids the storage unit that has centralized failure (the first media address corresponds to the Media address). Therefore, when the second mapping relationship is used to store data, the length of the check bit required by the first physical block address can be effectively reduced, and the available storage space is increased.

The data storage method proposed in the embodiments of this application can be applied to a variety of different scenarios, including: (1) During the data storage and reading process of the storage device, the data storage is triggered according to the symbol error rate (SER) Method; (2) Before the storage device leaves the factory, the data storage method is used to determine a better mapping relationship to store data. In the following, the above solution will be introduced in conjunction with the drawings.

(1) During the data storage and reading process of the storage device, the data storage method is triggered according to the symbol error rate (SER):

Please refer to FIG. 4, which is a schematic diagram of another embodiment of the data storage method proposed in the embodiment of the application. The data storage method proposed in the embodiment of the application includes:

401. Read the first data, and detect the first bit error rate.

In this embodiment, the storage device reads the first data according to the instruction of the host, and the data stored in the first medium address is called the first data. The storage device uses the ECC check bit to perform error correction on the first data and detects the bit error rate of the first data, and the bit error rate is called the first bit error rate. Specifically, the first error rate may be the ratio of the length of the error data to the total length of the first data. For example, if the length of the error data is 5 bits and the total length of the first data is 100 bits, then the first error The code rate is 5/100=5%. The first bit error rate may also be the length of the error data, which is not limited here.

In another optional implementation manner, in order to determine the failure of the current storage device, the user issues a first detection instruction to the storage device, and the storage device reads the first data according to the first detection instruction, and detects the first error. Bit rate. The storage device can detect whether a concentration failure occurs in the mapping relationship corresponding to the data by detecting the bit error rate of a certain data according to the first detection instruction. The storage device may also detect the entire disk data according to the first detection instruction. The storage device can also detect the blank medium address (including the mapping relationship of the medium address) according to the first detection instruction, specifically: write the first data to the medium address, and detect the first bit error rate.

402. When the first bit error rate is greater than or equal to the first threshold value, back up the first data and the second data.

In this embodiment, when the first bit error rate is greater than or equal to the first threshold, the first data and the second data are backed up, and the data stored in the second medium address is called the second data. For example, if the first threshold is 5%, when the storage device detects that the first bit error rate is 5%, step 402 is entered, and the storage device backs up the first data and the second data to a buffer (Data Buffer). Then, the storage device clears the data in the first medium address and the second medium address.

403. Acquire a first mapping relationship.

In this embodiment, after step 402, step 403 is entered. Specifically, the method for obtaining the first mapping relationship is similar to the foregoing step 301, and will not be repeated here.

404. Generate a second mapping relationship according to the first mapping relationship.

In this embodiment, specifically, the method of generating the second mapping relationship according to the first mapping relationship is similar to the foregoing step 302, and will not be repeated here.

405. Generate a third mapping relationship according to the first mapping relationship.

In this embodiment, the third mapping relationship is generated according to the first mapping relationship. The third mapping relationship includes a second physical block address, a first media address, and a third media address. The second physical block address is associated with the first media address. The second physical block address is associated with the third media address, the second physical block address is inconsistent with the first physical block address, and the third media address is inconsistent with the second media address. Refer to Table 4 for the third mapping relationship.

Table 4

For ease of understanding, please refer to FIG. 9, which is a schematic diagram of another mapping relationship proposed in an embodiment of this application. The first mapping relationship is: the first physical block address LBA=X0b, and the first medium address (MA: X000/MA: X001/MA: X010/MA: X011). In the buffer of the storage-level memory, the following mapping relationship is also stored: physical block address LBA=X1b, media address (MA: X000/MA: X101/MA: X110/MA: X111). In step 405, a third mapping relationship is generated according to the first mapping relationship, including: the second physical block address LBA=X1b, and the third medium address (MA: X000/MA: X101/MA: X110/MA: X111).

406. Use the second mapping relationship and/or the third mapping relationship to store data.

In this embodiment, after step 405, the second mapping relationship and the third mapping relationship are generated in the storage device according to the first mapping relationship. The storage device may use the second mapping relationship to store the first data (the first data is backed up in the buffer), and use the third mapping relationship to store the second data (the second data is backed up in the buffer); or, the storage device The second mapping relationship may also be used to store the second data, and the third mapping relationship may be used to store the first data; or, the storage device may also use the second mapping relationship to store the first data and the second data; or, the storage device may use the second mapping relationship to store the first data and the second data. The three mapping relationships store the first data and the second data. The storage device may also use the second mapping relationship and/or the third mapping relationship to store other data, which will not be repeated here.

In the embodiment of the present application, the first media address that has a centralized failure is distributed to the management of other physical block addresses, which reduces the proportion of the wrong media addresses in a certain physical block address to the total media addresses. It can effectively reduce the length of the check bit required by the physical block address and increase the available storage space.

Please refer to FIG. 5, which is a schematic diagram of another embodiment of the data storage method proposed in the embodiment of the application. The data storage method proposed in the embodiment of the application includes:

501. Read the first data, and detect the first bit error rate.

In this embodiment, it is similar to the aforementioned step 401, and will not be repeated here.

502. When the first bit error rate is greater than or equal to the first threshold value, back up the first data and the second data.

In this embodiment, it is similar to the aforementioned step 402, and will not be repeated here.

503. Acquire a first mapping relationship.

In this embodiment, it is similar to the aforementioned step 403, and will not be repeated here.

504. Generate a second mapping relationship according to the first mapping relationship.

In this embodiment, it is similar to the aforementioned step 404, and will not be repeated here.

505. Detect a second bit error rate.

In this embodiment, after the second mapping relationship is generated according to the first mapping relationship in step 504, because the storage unit corresponding to the second media address may also have a centralized failure, the mapping used when determining the storage data Before the relationship, it is necessary to check the data stored in the second media address.

Specifically, the bit error rate of the second data stored in the second media address is detected, and the bit error rate is called the second bit error rate. In an optional implementation manner, before generating the second mapping relationship, the second data stored in the second media address needs to be backed up, and the bit error rate of the second data is detected in the process of reading the second data , The bit error rate is also the bit error rate of the second media address.

In another optional implementation manner, after backing up the second data, first, clear the data stored in the second media address. Secondly, the storage device uses preset data to perform bit error rate detection on the second media address (corresponding storage unit) to obtain the second bit error rate.

506. Determine a mapping relationship used when storing data according to the first error rate and the second error rate.

In this embodiment, the mapping relationship used when storing data is determined according to the first error rate and the second error rate. Specifically, when the first error rate is greater than the second error rate, the second mapping relationship is used to store the data. When the first error rate is less than or equal to the second error rate, the storage unit corresponding to the second medium address in the second mapping relationship also has a centralized failure. The storage device needs to use other mapping relationships to store data, for example, using a third mapping relationship to store data. The method for generating the third mapping relationship is similar to the foregoing step 405, and will not be repeated here.

In the embodiment of the present application, after the storage device generates the second mapping relationship according to the first mapping relationship, it can detect the bit error rate (second bit error rate) of the second medium address in the second mapping relationship. The mapping method used when storing data is determined according to the first error rate and the second error rate. It is ensured that the bit error rate in the mapping relationship used by the storage device is low, the check bit length required by the physical block address is reduced, and the available storage space is increased.

(2) Before the storage device leaves the factory, use this data storage method to determine a better mapping relationship to store data:

Please refer to FIG. 6. FIG. 6 is a schematic diagram of another embodiment of the data storage method proposed in the embodiment of the application. The data storage method proposed in the embodiment of the application includes:

601. Acquire a first detection instruction.

In this embodiment, the storage device obtains the first detection instruction, and the storage device detects the bit error rate of the media address in each current mapping relationship according to the first detection instruction, and determines the mapping relationship used when storing data according to the bit error rate.

In an optional implementation manner, before the storage device leaves the factory, the storage device obtains the first detection instruction. First, the storage device writes third data to the first medium address according to the first detection instruction and the first mapping relationship. The third data is the test data used when detecting the bit error rate, such as "000···000" or "111···111". Then, the storage device writes the third data to the second medium address according to the first detection instruction and the second mapping relationship.

In another optional implementation manner, when the user uses the storage device, the media address with a higher error rate may be disabled through the first detection instruction to ensure data security. Specifically, first, the storage device backs up the data in the first media address and the data in the second media address according to the first detection instruction. Then, the storage device writes third data into the first media address and the second media address, respectively.

In another optional implementation manner, the first detection instruction may be an instruction automatically triggered when the storage device is in an idle state. It can also be an instruction that is automatically triggered by the storage device periodically, and there is no restriction here.

602. Detect a third bit error rate.

In this embodiment, the third bit error rate is the bit error rate of the third data in the first medium address.

603. Detect a fourth bit error rate.

In this embodiment, the fourth error rate is the error rate of the third data in the second medium address.

604. Determine a mapping relationship used when storing data according to the third error rate and the fourth error rate.

In this embodiment, according to the third error rate and the fourth error rate,

According to the third error rate and the fourth error rate, the mapping relationship used when storing the data is determined. In an optional implementation manner, when the third error rate is greater than the fourth error rate, the first mapping relationship is used to store the data. When the third error rate is less than or equal to the fourth error rate, the second mapping relationship is used to store the data. In another optional implementation manner, when the third error rate is greater than the first threshold, the second mapping relationship is used to store the data; when the fourth error rate is greater than the first threshold, the first The mapping relationship stores data.

The foregoing mainly introduces the solutions provided in the embodiments of the present application from the perspective of methods. It can be understood that, in order to implement the above-mentioned functions, the above-mentioned storage device includes hardware structures and/or software modules corresponding to each function. Those skilled in the art should easily realize that in combination with the modules and algorithm steps of the examples described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software-driven hardware depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

The embodiment of the present application may divide the storage device into functional modules according to the foregoing method examples. For example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one storage module. The above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical function division, and there may be other division methods in actual implementation.

The information retrieval device in this application will be described in detail below, please refer to FIG. 11, which is a schematic diagram of an embodiment of a storage device in an embodiment of this application. The storage device 1100 includes:

The processing module 1101 is used to detect the bit error rate when reading the current data;

The processing module 1101 is further configured to determine a mapping relationship for storing data to the storage-level memory according to the bit error rate, where the mapping relationship includes an association relationship between a physical block address and a media address;

The storage module 1102 is used to store data according to the mapping relationship.

In some embodiments of this application,

The processing module 1101 is specifically configured to determine the second mapping relationship as the mapping relationship when the bit error rate is greater than the preset threshold, wherein, under the second mapping relationship and the first mapping relationship, the physical block address and the medium The association relationship between addresses is different, and the first mapping relationship is that when the current data is read, the storage-level memory performs data storage based on the first mapping relationship.

In some embodiments of this application,

The processing module 1101 is further configured to determine the first mapping relationship as the mapping relationship when the bit error rate is less than or equal to the preset threshold.

The obtaining module 1103 is configured to obtain a first mapping relationship, where the first mapping relationship includes a first physical block address and a first media address, and the first physical block address is associated with the first media address;

The processing module 1101 is configured to generate a second mapping relationship according to the first mapping relationship, the second mapping relationship includes a first physical block address and a second media address, the first physical block address is associated with the second media address, and the second media address Inconsistent with the address of the first medium;

The processing module 1101 is also used to select the second mapping relationship.

In some embodiments of the present application, the storage module 1102 is configured to use the second mapping relationship to store the data if the error rate of the data in the second media address is less than the error rate of the data in the first media address.

In some embodiments of the present application, the processing module 1101 is further configured to generate a third mapping relationship according to the first mapping relationship. The third mapping relationship includes a second physical block address, a third media address, and the second physical block address and the first mapping relationship. The three media addresses are related, the second physical block address is related to the third media address, the second physical block address is inconsistent with the first physical block address, the third media address is inconsistent with the second media address, and the third media address includes part of the A media address.

In some embodiments of this application,

The first media address and the second media address are located on the same die, or the first media address and the second media address are located on different die.

In some embodiments of the present application, the storage device 1100 further includes:

The processing module 1101 is also configured to detect the first bit error rate when reading the first data, where the storage area of the first data is the first media address;

The storage module 1102 is further configured to back up the first data and the second data when the first error rate is greater than or equal to the first threshold value, where the storage area of the second data is the second media address;

The storage module 1102 is also used to clear data stored in the first media address and the second media address.

The storage module 1102 is further configured to use the second mapping relationship to store the first data, or use the third mapping relationship to store the first data.

The processing module 1101 is further configured to detect a second bit error rate, where the second bit error rate is the bit error rate of the second data stored in the second media address;

The processing module 1101 is further configured to determine the mapping relationship used when storing data according to the first error rate and the second error rate.

In some embodiments of this application,

The storage module 1102 is specifically configured to use the second mapping relationship to store data when the first error rate is greater than the second error rate;

The storage module 1102 is specifically configured to use the third mapping relationship to store data when the first error rate is less than or equal to the second error rate.

In some embodiments of this application,

The storage module 1102 is specifically configured to store the first data in the backup to the second media address according to the second mapping relationship.

In some embodiments of this application,

The storage module 1102 is specifically configured to store the second data in the backup to the first medium address and the third medium address according to the third mapping relationship.

In some embodiments of this application,

The acquiring module 1103 is also used to acquire the first detection instruction, the first detection instruction is used to trigger the detection of the error rate of the current data, the first detection instruction is automatically triggered when the first detection instruction is in the idle state, or the first detection instruction It is an instruction triggered by the user.

The storage module 1102 is further configured to write third data to the first media address according to the first detection instruction and the first mapping relationship;

The storage module 1102 is further configured to write third data to the second media address according to the first detection instruction and the second mapping relationship;

The processing module 1101 is also used to detect a third bit error rate, where the third bit error rate is the bit error rate of the third data in the first medium address;

The processing module 1101 is further configured to detect a fourth bit error rate, where the fourth bit error rate is the bit error rate of the third data in the second medium address;

The processing module 1101 is further configured to determine the mapping relationship used when storing data according to the third error rate and the fourth error rate.

In some embodiments of the present application, the storage module 1102 is specifically configured to use the first mapping relationship to store data when the third error rate is greater than the fourth error rate;

The storage module 1102 is specifically configured to use the second mapping relationship to store data when the third error rate is less than or equal to the fourth error rate.

The storage device in the embodiment of the present application is described above from the perspective of a modular functional entity, and the storage device in the embodiment of the present application is described below from the perspective of hardware processing. FIG. 12 is a schematic diagram of the hardware structure of the computer device 1200 in an embodiment of the application. As shown in FIG. 12, the computer device 1200 may include:

The computer device 1200 includes at least one processor 1201, a communication line 1207, a memory 1203, and at least one communication interface 1204.

The processor 1201 can be a general-purpose central processing unit (central processing unit, CPU), a microprocessor, an application-specific integrated circuit (server IC), or one or more programs for controlling the execution of the program of this application. Integrated circuits.

The communication line 1207 may include a path to transmit information between the aforementioned components.

The communication interface 1204 uses any device such as a transceiver to communicate with other devices or communication networks, such as Ethernet.

The memory 1203 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), or other types that can store information and instructions The dynamic storage device, the memory can exist independently, and is connected to the processor through the communication line 1207. The memory can also be integrated with the processor.

Among them, the memory 1203 is used to store computer execution instructions for executing the solution of the present application, and the processor 1201 controls the execution. The processor 1201 is configured to execute computer-executable instructions stored in the memory 1203, so as to implement the data storage method provided in the foregoing embodiment of the present application.

Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application program codes, which are not specifically limited in the embodiments of the present application.

In a specific implementation, as an embodiment, the computer device 1200 may include multiple processors, such as the processor 1201 and the processor 1202 in FIG. 12. Each of these processors can be a single-CPU (single-CPU) processor or a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, and/or processing cores for processing data (for example, computer program instructions).

In a specific implementation, as an embodiment, the computer device 1200 may further include an output device 1205 and an input device 1206. The output device 1205 communicates with the processor 1201, and can display information in a variety of ways. The input device 1206 communicates with the processor 1201, and can receive user input in a variety of ways. For example, the input device 1206 may be a mouse, a touch screen device, a sensor device, or the like.

When the computer device 1200 is a terminal device, in the computer device 1200, the processor 1202 may include one or more processing units, for example: the processor 1202 may include an application processor (AP), a modem processor , Graphics processing unit (GPU), image signal processor (image signal processor, ISP), controller, memory, video codec, digital signal processor (digital signal processor, DSP), baseband processor, And/or neural-network processing unit (NPU), etc. Among them, the different processing units may be independent devices or integrated in one or more processors.

The terminal device can be a mobile station (MS), subscriber unit (subscriber unit), cellular phone, smart phone, wireless data card, personal digital assistant (personal digital assistant, abbreviated as PDA) ) Computers, tablet computers, wireless modems, handheld devices, laptop computers, machine type communication (MTC) terminal equipment, etc.

Among them, the controller may be the nerve center and command center of the computer device 1200. The controller can generate operation control signals according to the instruction operation code and timing signals to complete the control of fetching instructions and executing instructions.

A memory may also be provided in the processor 1202 for storing instructions and data. In some embodiments, the memory in the processor 1202 is a cache memory. The memory can store instructions or data that have just been used or recycled by the processor 1202. If the processor 1202 needs to use the instruction or data again, it can be directly called from the memory. Repeated accesses are avoided, the waiting time of the processor 1202 is reduced, and the efficiency of the system is improved.

In some embodiments, the processor 1202 may include one or more interfaces. The interface may include an integrated circuit (inter-integrated circuit, I1C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I1S) interface, a pulse code modulation (pulse code modulation, PCM) interface, and a universal asynchronous transmitter (universal asynchronous transmitter) interface. receiver/transmitter, UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and / Or Universal Serial Bus (USB) interface, etc.

It can be understood that the interface connection relationship between the modules illustrated in the embodiment of the present application is merely a schematic description, and does not constitute a structural limitation of the computer device 1200. In other embodiments of the present application, the computer device 1200 may also adopt different interface connection modes in the foregoing embodiments, or a combination of multiple interface connection modes.

The embodiment of the present application also provides a storage device. The storage device includes a processor, a buffer, and a memory. The memory includes one or more storage units. The steps performed by the storage device in the method described in the embodiment are also used to generate instructions; the memory is used to store data according to the instructions. In this embodiment, the storage device may be a non-embedded storage device or an embedded storage device. It should be understood that the specific expression form of the storage device should be flexibly set according to actual conditions, and is not limited here.

The embodiment of the present application also provides a computer program product containing storage block management instructions, which when running on a computer, causes the computer to execute the method described in the foregoing embodiments shown in FIGS. 2 to 8 as executed by the storage device A step of.

The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores storage block processing instructions, and when it runs on a computer, the computer executes the instructions shown in FIGS. 2 to 8 above. The steps performed by the storage device in the method described in the embodiment.

The embodiments of the present application also provide a chip system, the chip system includes a processor, used to support network equipment to achieve the functions involved in the above aspects, for example, for example, send or process the data and/or information involved in the above methods . In a possible design, the chip system further includes a memory, and the memory is used to store necessary program instructions and data of the network device. The chip system can be composed of chips, and can also include chips and other discrete devices.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part.

The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from a website, computer, server, or data center through a cable (such as Coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL) or wireless (such as infrared, wireless, microwave, etc.) transmission to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server or a data center integrated with one or more available media. The usable medium may be a magnetic medium, (for example, a floppy disk, a hard disk, and a magnetic tape), an optical medium, or a semiconductor medium, such as a solid state disk (SSD).

Those skilled in the art can clearly understand that, for the convenience and conciseness of the description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of modules is only a logical function division, and there may be other divisions in actual implementation, for example, multiple modules or components can be combined or integrated. To another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or modules, and may be in electrical, mechanical or other forms.

The modules described as separate components may or may not be physically separate, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional modules in the various embodiments of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or software functional modules.

If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disks or optical disks and other media that can store program codes. .

Claims

A data storage method, characterized in that the method is applied to storage-level memory, and includes:

Detect the bit error rate when reading the current data;

Determining a mapping relationship for storing data to the storage-level memory according to the bit error rate, where the mapping relationship includes an association relationship between a physical block address and a media address;

Data storage is performed according to the mapping relationship.
The method according to claim 1, wherein the determining a mapping relationship for storing data to the storage-level memory according to the bit error rate comprises:

When the bit error rate is greater than the preset threshold, the second mapping relationship is determined as the mapping relationship, wherein, under the second mapping relationship and the first mapping relationship, the association between the physical block address and the medium address The relationship is different,

The first mapping relationship is that when the current data is read, the storage-level memory performs data storage based on the first mapping relationship.
The method according to claim 2, wherein determining a mapping relationship for storing data to the storage-level memory according to the bit error rate, further comprising:

When the bit error rate is less than or equal to the preset threshold, the first mapping relationship is determined to be the mapping relationship.
The method according to any one of claims 2 to 3, wherein when the bit error rate is greater than the preset threshold, determining the second mapping relationship as the mapping relationship comprises:

Acquiring the first mapping relationship, where the first mapping relationship includes a first physical block address and a first media address, and the first physical block address is associated with the first media address;

The second mapping relationship is generated according to the first mapping relationship, the second mapping relationship includes the first physical block address and a second media address, and the first physical block address is related to the second media address The second medium address is not consistent with the first medium address.
The method according to claim 4, wherein the method further comprises:

Generating a third mapping relationship according to the first mapping relationship, where the third mapping relationship includes a second physical block address and the third media address, and the second physical block address is associated with the third media address; The second physical block address is associated with the third media address, the second physical block address is inconsistent with the first physical block address, and the third media address is inconsistent with the second media address, so The third medium address includes part of the first medium address;

Use the third mapping relationship to store data.
The method according to any one of claims 4 to 5, wherein the first media address and the second media address are located on the same die, or the first media address and the second media address are located on the same die. The media address is located on a different die.
The method according to any one of claims 3 to 6, wherein detecting the bit error rate when the current data is read comprises:

When the first data is read, a first bit error rate is detected, wherein the storage area of the first data is the first medium address;

When the first error rate is greater than or equal to a first threshold, back up the first data and the second data, where the storage area of the second data is the second medium address;

Clear data stored in the first media address and the second media address.
8. The method according to claim 7, wherein after clearing the data stored in the first media address and the second media address, the method further comprises:

Use the second mapping relationship to store the first data, or,

The first data is stored using the third mapping relationship.
8. The method according to claim 7, wherein after backing up the first data and the second data, the method further comprises:

Detecting a second bit error rate, where the second bit error rate is the bit error rate of the second data stored in the second media address;

According to the first error rate and the second error rate, the mapping relationship used when storing data is determined.
The method according to claim 9, wherein determining the mapping relationship used when storing data according to the first error rate and the second error rate comprises:

When the first error rate is greater than the second error rate, use the second mapping relationship to store data;

When the first error rate is less than or equal to the second error rate, the third mapping relationship is used to store data.
The method according to any one of claims 1 to 10, wherein detecting the bit error rate when the current data is read, the method further comprising:

Acquiring a first detection instruction, the first detection instruction being used to trigger detection of the bit error rate of the current data,

The first detection instruction is an instruction that is automatically triggered when in an idle state,

Or, the first detection instruction is an instruction actively triggered by the user.
The method according to claim 11, wherein after generating the second mapping relationship according to the first mapping relationship, the method further comprises:

Write third data to the first media address according to the first detection instruction and the first mapping relationship;

Write the third data to the second media address according to the first detection instruction and the second mapping relationship;

Detecting a third bit error rate, where the third bit error rate is the bit error rate of the third data in the first medium address;

Detecting a fourth bit error rate, where the fourth bit error rate is the bit error rate of the third data in the second medium address;

According to the third error rate and the fourth error rate, the mapping relationship used when storing data is determined.
The method according to claim 12, wherein determining the mapping relationship used when storing data according to the fourth error rate and the fifth error rate comprises:

When the third error rate is greater than the fourth error rate, the first mapping relationship is used to store data;

When the third error rate is less than or equal to the fourth error rate, the second mapping relationship is used to store data.
A storage device, characterized in that it comprises:

The processor is used to detect the bit error rate when reading the current data;

The processor is further configured to determine a mapping relationship for storing data to the storage-level memory according to the bit error rate, where the mapping relationship includes an association relationship between a physical block address and a media address;

The storage array is used for data storage according to the mapping relationship.
The storage device according to claim 14, wherein:

The processor is specifically configured to determine a second mapping relationship as the mapping relationship when the bit error rate is greater than a preset threshold, wherein, under the second mapping relationship and the first mapping relationship, the physical block The association relationship between the address and the media address is different, and the first mapping relationship is that when the current data is read, the storage-level memory performs data storage based on the first mapping relationship.
The storage device according to claim 15, wherein:

The processor is further configured to determine the first mapping relationship as the mapping relationship when the bit error rate is less than or equal to the preset threshold.
The storage device according to claim 16, wherein:

The processor is further configured to obtain a first mapping relationship, where the first mapping relationship includes a first physical block address and a first media address, and the first physical block address is associated with the first media address;

The processor is further configured to generate a second mapping relationship according to the first mapping relationship, where the second mapping relationship includes the first physical block address and the second media address, and the first physical block address and the The second media address is associated, and the second media address is inconsistent with the first media address.
The storage device according to claim 17, wherein:

The processor is further configured to generate a third mapping relationship according to the first mapping relationship, where the third mapping relationship includes a second physical block address, the third medium address, and the second physical block address and the The third media address is associated, the second physical block address is associated with the third media address, the second physical block address is inconsistent with the first physical block address, and the third media address is inconsistent with the first physical block address. The second media addresses are inconsistent, and the third media addresses include part of the first media addresses;

The storage array is also used to store data using the third mapping relationship.
The storage device according to any one of claims 16 to 18, wherein the first medium address and the second medium address are located on the same die, or the first medium address and the first medium address are located on the same die. The two media addresses are located on different dies.
The storage device according to any one of claims 16 to 19, wherein:

The processor is further configured to detect a first bit error rate when reading first data, wherein the storage area of the first data is the first media address;

The storage array is further configured to back up the first data and the second data when the first error rate is greater than or equal to a first threshold, wherein the storage area of the second data is the The second medium address;

The storage array is also used to clear data stored in the first medium address and the second medium address.
The storage device according to claim 20, wherein:

The storage array is further configured to use the second mapping relationship to store the first data, or to use the third mapping relationship to store the first data.
The storage device according to claim 20, wherein:

The processor is further configured to detect a second bit error rate, where the second bit error rate is the bit error rate of the second data stored in the second media address;

The processor is further configured to determine the mapping relationship used when storing data according to the first error rate and the second error rate.
The storage device according to claim 22, wherein:

The storage array is specifically configured to use the second mapping relationship to store data when the first error rate is greater than the second error rate;

The storage array is specifically configured to use the third mapping relationship to store data when the first error rate is less than or equal to the second error rate.
The storage device according to any one of claims 14 to 23, wherein:

The processor is further configured to obtain a first detection instruction, the first detection instruction is used to trigger detection of the bit error rate of the current data, and the first detection instruction is an instruction that is automatically triggered when an idle state is used, Or, the first detection instruction is an instruction actively triggered by the user.
The storage device according to claim 24, wherein:

The storage array is further configured to write third data to the first media address according to the first detection instruction and the first mapping relationship;

The storage array is further configured to write the third data to the second media address according to the first detection instruction and the second mapping relationship;

The processor is further configured to detect a third bit error rate, where the third bit error rate is the bit error rate of the third data in the first medium address;

The processor is further configured to detect a fourth bit error rate, where the fourth bit error rate is the bit error rate of the third data in the second media address;

The processor is further configured to determine the mapping relationship used when storing data according to the third error rate and the fourth error rate.
The storage device according to claim 25, further comprising:

The storage array is specifically configured to use the first mapping relationship to store data when the third error rate is greater than the fourth error rate;

The storage array is specifically configured to use the second mapping relationship to store data when the third error rate is less than or equal to the fourth error rate.
A storage device, wherein the storage device includes a processor, a buffer, and a memory, the memory includes one or more storage units, and the buffer stores program instructions;

Wherein, the processor is configured to store data in the memory according to the program instructions, and execute the method according to any one of claims 1 to 13.