WO2023050927A1 - Memory detection method and apparatus - Google Patents

Abstract

The present application provides a memory detection method and apparatus. The method can be applied to a computing device; the computing device comprises a memory controller and a memory; and in the method, the memory controller determines the access frequency of a first memory unit within a historical period of time on the basis of a historical access record of the first memory unit; and when the access frequency satisfies a preset condition, the memory controller performs memory detection on the first memory unit to determine a detection result of the first memory unit. According to the method, whether to trigger memory detection or not can be determined in combination with the access frequency of the first memory unit during startup or operation of the computing device, and the memory detection is no longer limited to a specific time, such that the flexibility of the memory detection is provided, a memory failure can be found in time, the risk of system crash is reduced, and the stability and reliability of system operation are improved.

Description

A memory detection method and device

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 202111162543.X and the application name "A Memory Detection Method and Device" submitted to the China Patent Office on September 30, 2021, the entire contents of which are incorporated herein by reference Applying.

technical field

The present application relates to the field of computer technology, in particular to a memory detection method and device in computing equipment.

Background technique

Memory is one of the more error-prone components of server motherboards. With the doubling of memory capacity and memory speed, the probability of memory errors will also double. How to better reduce memory errors is an important issue facing the new generation of servers.

At present, the common memory detection scheme is to trigger memory detection when the server is powered on to detect the hard failure bits in the memory. However, this method can only be executed when the server is powered on. Errors cannot be identified, which leads to low reliability of data processing in the server.

Contents of the invention

The present application provides a memory detection method and device, which are used to provide the flexibility of memory detection, improve the timeliness of memory detection, and improve system stability.

In a first aspect, the present application provides a memory detection method, which can be applied to a computing device. The computing device includes a memory controller and a memory, and the memory includes a plurality of memory units. In the method, the memory controller is based on the first memory unit The historical access record determines the access frequency of the first memory unit within a historical time period of a preset duration; wherein, the historical access record can be used to record information such as access requests (such as read requests or write requests) of the first memory unit; The memory controller judges whether the access frequency satisfies a preset condition, and if the access frequency satisfies a preset condition, the memory controller can perform memory detection on the first memory unit to determine the detection result of the first memory unit.

Through the above design, when the access frequency of the first memory unit satisfies the preset condition, the memory controller performs memory detection on the first memory unit to determine the detection result of the first memory unit. The above method can determine whether to trigger memory detection based on the access frequency of the first memory unit when starting up or during operation, and is no longer limited to a specific timing. It provides flexibility in memory detection, can detect memory faults in time, and reduces system Risk of downtime, improve system stability and reliability.

In a possible implementation method, the preset condition includes that the access frequency of the first memory unit is not greater than a preset threshold.

Through the above design, when the access frequency of the first memory unit is not greater than the preset threshold, then the data access to the first memory unit may be less in the future, or there may be no new data access. Under certain circumstances, memory detection is triggered on the first memory unit, which can reduce the congestion of data access requests as much as possible, and improve the read and write performance of the system on the basis of memory detection.

In a possible implementation method, the memory controller performs memory detection on the first memory unit, and the memory detection may include data error detection, and the detection process includes such as:

The memory controller can first read the data stored in the first memory unit (that is, the first data), and store the read first data in the first memory of the memory controller, and store the first data in the first memory The storage space for one data is called the first storage unit; after that, the memory controller checks the first data to determine whether there is a data error in the first data; the first case: there is no data error in the first data; the second Two cases: if there is a correctable error in the first data, the memory controller can correct the correctable error in the first data to obtain the error-corrected data (denoted as the second data), and store the second data Writing into the first storage unit; the third case: if there is an uncorrectable error in the first data, the memory controller can send error information, which can be used to indicate that there is an uncorrectable error in the first data.

Through the above design, the error data in the first data can be detected through the data error detection process, thereby improving the reliability of the data.

In a possible implementation method, after the memory controller stores the first data in the first storage unit, when performing data error detection, it may also perform hardware detection on the first memory unit, and the detection process includes such as:

The memory controller detects whether there is a hard failure bit in the first memory unit, and the hard failure bit is a bit whose binary value is different from the binary value read; the first case: there are one or more hard failure bits in the first memory unit. failure bit, the memory controller sends failure information, and the failure information is used to indicate that there is a hard failure bit in the first memory unit, or one or more hard failure bits in the first memory unit are detected. The second case: the first memory unit does not have a hard fail bit, and after it is determined through the data error detection process that there is no erroneous data or correctable data in the first data, the first data or corrected data stored in the first storage unit The erroneous second data is written back to the first memory unit.

Through the above design, the hard failure bit in the first memory unit can be detected through the hardware detection process, so as to discover the hardware failure of the memory in time, reduce the probability of uncorrectable errors, reduce the risk of system downtime, and improve the stability and reliability of the system operation .

In a possible implementation method, after the memory controller stores the first data in the first storage unit, it may also receive a read request for accessing the first memory unit;

If a correctable error exists in the first data is detected through the data error detection process, then the error-corrected second data is sent to the processor. Or if no data error exists in the first data is detected through the data error detection process, the first data stored in the first storage unit may be returned in response to the read request. Or if there is an uncorrectable error in the first data, error information indicating that there is an uncorrectable error in the first data may be returned.

Through the above design, the flexibility of responding to the data read request in the memory detection method is provided, and the data reliability is improved.

In a possible implementation method, after the memory controller stores the first data in the first storage unit, it may also receive a write request for accessing the first memory unit;

If it is detected through the hardware detection process that the first memory unit does not have a hard fail bit, the data carried in the write request can be written into the first memory unit; or if it is detected that the first memory unit has a hard fail bit, the write The data carried in the request is written into the second memory unit, and the second memory unit is a memory unit other than the first memory unit among the plurality of memory units included in the aforementioned memory.

Through the above design, the flexibility of responding to the data write request in the memory detection method is provided, and the system stability and data reliability are improved.

In a possible implementation method, the memory controller performs memory detection on the first memory unit, where the memory detection may include hardware detection, and the detection process includes, for example:

The memory controller can first read the data stored in the first memory unit (that is, the first data), and store the read first data in the first memory of the memory controller, and store the first data in the first memory A data storage space is called the first storage unit; afterward, the memory controller detects whether there is a hard fail bit in the first memory unit, and the hard fail bit is a bit whose binary value is different from the binary value read; the first Case 1: There are one or more hard fail bits in the first memory unit, the memory controller sends a fault message indicating that there are hard fail bits in the first memory unit, or the detected One or more hard fail bits. The second case: the first memory unit does not have a hard fail bit, and after it is determined through the data error detection process that there is no erroneous data or correctable data in the first data, the first data or corrected data stored in the first storage unit The erroneous second data is written back to the first memory unit.

Through the above design, the hard failure bit in the first memory unit can be detected through the hardware detection process, so as to discover the hardware failure of the memory in time, reduce the probability of uncorrectable errors, reduce the risk of system downtime, and improve the stability and reliability of the system operation .

In a possible implementation method, the method for the memory controller to detect whether there is a hard fail bit in the first memory unit includes:

The memory controller writes the first detection data into the first memory unit, and reads back the fourth data stored in the first memory unit; for each bit position, the first detection data is the same as the fourth data Compare the bit values on the bits of the position, if they are the same, it is determined that there is no hard failure in the bit of the first memory unit, otherwise, it is determined that there is a hard failure in the bit of the first memory unit. The memory controller writes the second detection data into the first memory unit, and reads back the fifth data stored in the first memory unit; compares the second detection data with the bit values at the same position in the fifth data , to determine whether there is a hard fail bit in the first memory unit; wherein, the second detection data is different from the first detection data.

Through the above design, at least two hard fail bit detections are performed on the same memory unit to determine the hard fail bit in the first memory unit, reducing the probability of missed detection due to the fact that the read value and the output data of the hard fail bit are exactly the same .

In the second aspect, the present application also provides a memory detection device, which has the function of realizing the behavior of the memory controller in the method example of the first aspect above. For the beneficial effects, please refer to the description of the first aspect and will not repeat them here. . The functions described above may be implemented by hardware, or may be implemented by executing corresponding software on the hardware. The hardware or software includes one or more modules corresponding to the above functions. In a possible design, the structure of the memory detection device includes a determination module, a detection module, and optionally, a reading module and a communication module. These modules can execute the memory controller in the method example of the first aspect above. For the corresponding functions, please refer to the detailed description in the method example for details, and will not repeat them here.

In the third aspect, the present application also provides a memory detection device, which has the function of realizing the behavior of the memory controller in the method example of the first aspect above, and the beneficial effects can be found in the description of the first aspect, which will not be repeated here. . The structure of the device includes a processor and a memory, and optionally, may also include a communication interface. The processor is configured to support the memory detection device to execute the corresponding functions of the memory controller in the method of the first aspect above. The memory is coupled to the processor and holds computer program instructions and data necessary for the communication device (eg at least one lock). The structure of the memory detection device also includes a communication interface for communicating with other devices, such as receiving lock access requests.

In a fourth aspect, the present application further provides a processor, where the processor includes a memory controller, and the memory controller is configured to realize the functions of the operation steps of the method in the first aspect or any possible implementation manner of the first aspect.

In the fifth aspect, the present application also provides a computing device, the computing device includes a processor and a memory controller, and the memory controller has the function of realizing the behavior in the method example of the first aspect above, and the beneficial effects can be referred to in the first aspect The description will not be repeated here.

In the sixth aspect, the present application also provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, the computer can execute the above-mentioned first aspect and each possibility of the first aspect. The method described in the implementation of .

In a seventh aspect, the present application further provides a computer program product including instructions, which, when run on a computer, cause the computer to execute the method described in the above first aspect and each possible implementation manner of the first aspect.

In the eighth aspect, the present application also provides a computer chip, the chip is connected to the memory, and the chip is used to read and execute the software program stored in the memory, and implement the above first aspect and each possibility of the first aspect. The method described in the implementation of .

On the basis of the implementation manners provided in the foregoing aspects, the present application may further be combined to provide more implementation manners.

For the beneficial effects of the above second to seventh aspects and their implementations, reference may be made to the description of the beneficial effects of the method of the first aspect and its implementations.

Description of drawings

FIG. 1 is a schematic structural diagram of a server provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of the architecture of a memory system;

FIG. 3 is a schematic flowchart corresponding to a memory detection method provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of implementing a memory detection method provided in the embodiment of the present application in the time dimension;

FIG. 5 is a schematic flow diagram of a memory detection method provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a memory detection device provided in an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another memory detection device provided by an embodiment of the present application.

Detailed ways

The memory detection method provided by the embodiment of the present application can be applied to computing devices, such as servers, desktop computers, tablet computers, mobile phones, etc. The embodiment of the present application does not limit the type of computing devices, and any device with memory is applicable to this application. Application example. The following uses a server as an example to introduce the technical solution of the embodiment of the present application, and the server in the following text can be replaced by a computing device.

FIG. 1 is a schematic structural diagram of a server provided by an embodiment of the present application. As shown in FIG. 1 , the server 10 includes at least a processor 110 and a memory 120 . Wherein, the processor 110 and the memory 120 are connected through a bus.

Wherein, the processor 110 may be a central processing unit (central processing unit, CPU), or a specific integrated circuit (application specific integrated circuit, ASIC), or be configured as one or more integrated circuits. Only one processor 110 is shown in FIG. 1 . In practical applications, there are often multiple processors 110 . Wherein, when the processor 110 is a CPU, one CPU 110 may have one or more CPU cores. This embodiment does not limit the number of CPUs and the number of CPU cores.

The memory 120 can be used to temporarily store computer executable program codes and data. The memory 120 has the characteristics of reading and writing data at any time, with a high speed, and can be used as a temporary data storage space for running applications. Memory includes various types of memory, such as dynamic random access memory (dynamic random access memory, DRAM), double data rate synchronous dynamic random access memory (double data rate, DDR) and so on. In practical applications, multiple memories 120 and different types of memories 120 may be configured in the server 10 . This embodiment does not limit the quantity and type of the memory 120 .

In one embodiment, a memory controller 1101 may also be provided in the processor 110 . Wherein, the memory controller 1101 is used for managing the memory 120 and communicating with the processor 110 , and in the server, data exchange is performed between the processor 110 and the memory 120 through the memory controller 1101 . For example, when the memory controller 1101 receives the data write request sent by the processor 110 , it will store the data in the data write request in the memory 120 . For another example, the memory controller 1101 receives the data read request sent by the processor 110 , may read data from the memory 120 according to the memory address carried in the data read request, and return the read data to the processor 110 .

Referring to FIG. 2 , FIG. 2 shows a schematic structural diagram of a memory system composed of a memory controller 1101 and a memory 120 . In hardware, the memory controller 1101 connects physical ranks through memory channels. The granularity of data exchange between the memory controller 1101 and the memory 120 is called the minimum data unit, and several memory blocks that provide the minimum data unit are ranks. For example, when a rank includes 64 bits, if each storage unit (or memory particle) in the memory 120 ) includes 8 bits, then 8 storage units are required to form the 64 bits, that is, a rank includes 8 storage units, such as when the memory 120 includes 32 storage units, the memory 120 includes 4 ranks.

As a possible implementation manner, the memory controller 1101 may also be a device external to the processor 110 and connected to the processor 110 through a bus, and the memory controller 1101 may also implement the functions of the operation steps of the method described in this application. For ease of description, in the following embodiments, the memory controller 1101 shown in FIG. 2 is located in the processor 110 as an example for illustration.

In one embodiment, a cache 1102 can also be set in the memory controller 1101, and the cache 1102 can be used to temporarily store data read from the memory 120, and can also be used to store data write requests received by the memory controller 1101 data carried. The cache 1102 can be a random access memory, static random access memory (static random access memory, SRAM) or DRAM, and the cache 1102 can also include other types of memory. The embodiment of the present application does not limit the type and quantity of the cache 1102.

It should be noted that (1) the structure shown in FIG. 1 does not constitute a specific limitation on the server. In other embodiments of the present application, the terminal device may include more or fewer components than shown in the illustration, for example, the server may also include hard disks, bios components, etc., or some components may be combined, or some components may be split, or different layout of the components. (2) The memory controller 1101 may not be disposed in the processor 110, which is not limited in this embodiment of the present application.

The following describes the memory detection method provided by the embodiment of the present application with reference to FIG. 3 and taking the server architecture shown in FIGS. 1 to 2 as an example. Fig. 3 is a schematic flow chart corresponding to the memory detection method provided in the embodiment of the present application, as follows, the method is executed by the memory controller 1101 in Fig. 1 or Fig. 2 as an example, as shown in Fig. 3, the method includes:

Step 301, the memory controller 1101 monitors data access requests, and records the monitored data access requests to obtain historical access records;

Specifically, the data access request includes the aforementioned data write request and data read request. There are many ways for the memory controller 1101 to obtain data access requests. For example, the memory controller 1101 obtains data access requests from the processor 110, or obtains data access requests from other components such as bios components. This embodiment of the present application does not do this limited.

The memory controller 1101 generates or updates historical access records based on the monitored data access requests. Exemplarily, the records can be used to record the access frequency of each memory unit. The memory unit can be of a preset size, such as the memory unit can be the aforementioned rank, or each memory unit includes multiple ranks, etc., the embodiment of the present application does not limit the size of the memory unit, and the following uses rank as an example to introduce historical access records. Exemplarily, for any memory unit, the historical access record may include, but not limited to: a memory identifier (such as a memory address) for uniquely identifying the memory unit, and an access frequency of the memory unit. Referring to Table 1, Table 1 is an example of a historical access record provided by the embodiment of the present application.

Table 1 Historical access records

memory unit	Frequency of visits
rank_0	20
rank_1	8
rank_2	1
rank_3	n (n is a positive integer greater than or equal to 0)
…	…

The visit frequency here may refer to the total visit frequency in a historical time window, and the length of the historical time window may be a preset length (such as called the first preset length), or the visit frequency may also refer to the statistical The total accumulative access frequency received is not limited in this embodiment of the present application.

Optionally, the historical access record may also include one or more of the following: latest access time, type of data access request (such as data read request, data write request) and so on. It is worth noting that if the type of data access request is not recorded in the historical access records, as shown in Table 1, the access frequency in Table 1 refers to the total access frequency of the memory unit being read and written, that is, no distinction is made between the monitored Whether the data access request is a data read request or a data write request, as long as the memory unit is accessed, the access frequency is increased by 1. In another implementation manner, the access frequency of the memory unit being read and/or the access frequency of the memory space being written may be separately recorded. It can be understood that the read access frequency is based on the monitored data read requests to the memory unit, and similarly, the written access frequency is based on the monitored data write requests to the memory space. of. For the convenience of description, the following uses the total access frequency counted based on data read requests and data write requests as shown in Table 1 as an example without distinguishing between data read requests and data write requests.

In another optional manner, the historical access record may also be used to record the access time of each data access request of the memory unit, as shown in Table 2, which is another example of the historical access record.

Table 2. Historical access records

memory unit	interview time
rank_0	10:01
rank_0	10:02
rank_0	10:03
rank_0	10:08
…	…

It should be noted that the historical access records shown in Table 1 and Table 2 are only examples, which are not limited in this embodiment of the present application, as long as the access frequency of the memory unit within a period of time can be counted.

In step 302, the memory controller 1101 determines the access frequency of the first memory unit within a preset historical time period based on the historical access record.

The memory 120 includes a plurality of memory units, and the first memory unit is any one of the plurality of memory units. Here, a memory unit (ie, the first memory unit) is taken as an example for illustration.

The memory controller 1101 can determine the access frequency of the first memory unit in a historical time period according to the historical access records, where the length of a historical time period can be a preset length (such as called a second preset length), as shown in FIG. As shown in 4, the historical time period may be a time period of a second preset length before _T0 , and the access frequency of the first memory unit within the historical time period is determined according to the historical access records.

It is worth noting that (1) in order to facilitate the determination of the access frequency of the memory unit in the historical time period whose length is the second preset length, the first preset duration and the second preset length in the aforementioned historical access records can be equal , of course, may also be different. For example, the first preset duration is longer than the second preset length, which is not limited in this embodiment of the present application. (2) The embodiment of the present application does not limit the duration of a certain period of time in the future.

Step 303, judging whether the access frequency of the first memory unit satisfies a preset condition, if so, execute step 304, otherwise, exit the process.

Exemplarily, the preset condition includes but is not limited to: the access frequency is not greater than a preset threshold.

If the access frequency determined in step 302 is less than or equal to the preset threshold, it is determined that there will be no new data access request for the first memory unit for a period of time in the future. As in FIG. 4, if the access frequency of the first memory unit in the historical time period whose length is the second preset length is less than or equal to the preset threshold, it is determined that there is no access to the first memory unit in a period of time in the future after the current time _T0 . A new data access request of a memory unit may trigger memory detection on the first memory unit at time T ₀ or at a certain time within a preset time range after T ₀ (see step 304 ).

Specifically, the preset threshold may be a positive integer greater than or equal to 0. It can be understood that when the preset threshold is 0, the probability of memory detection and data access request collisions can be reduced as much as possible.

In step 304, the memory controller 1101 detects the first memory unit to determine the detection result of the first memory unit.

Specifically, the memory detection method includes data detection and hardware detection, and the data detection can be used to detect whether there is a data error in the data read from the first memory unit. Hardware detection can be used to detect whether there is a hard failure bit in the first memory unit. The hard failure bit refers to the hardware failure of the memory bit. Whether the binary value of the bit is 0 or 1, the output value of this bit is a fixed value, such as only 0 or only 1.

The three memory detection methods are introduced as follows:

Detection method 1: performing data detection and hardware detection on the first memory unit;

FIG. 5 is a schematic flowchart of a method corresponding to the first detection mode. FIG. 5 shows the flow of the data detection method (step 502-step 505) and the flow of the hardware detection method (step 506-step 514).

As shown in Figure 5, the process includes:

Step 501 , the memory controller 1101 reads the data in the first memory unit (denoted as first data), and stores the first data in the cache 1102 of the memory controller 1101 .

The first data consists of bit values stored in each bit of the first memory unit.

Those skilled in the art can determine that a cache line (cacheline) is the smallest unit of cached data in a Cache (such as the cache 1102), wherein the data size of a rank stored data can include one or more cachelines, as follows for convenience of description, assuming The data size of the data stored in the first memory unit is one cacheline. Correspondingly, the cache space used for storing the first data in the cache 1102 is called a first cacheline.

Step 502 , detect whether there is a data error in the first data, if yes, execute step 503 , otherwise, execute step 512 .

In one embodiment, the first data includes information bits and check bits, and the memory controller 1101 can use the check bits of the first data to check the information bits of the first data based on a check algorithm to detect whether There is a data error. Specifically, based on whether the data error can be corrected, the data error includes a correctable error (correctable error, CE) and an uncorrectable error (uncorrectable error, UCE).

Step 503 , the memory controller 1101 judges whether the data error is CE, if yes, execute step 504 , otherwise, execute step 505 .

Step 504 , correct the erroneous data in the first data to obtain the second data, and write the second data back to the cache 1102 .

As mentioned above, the first data is stored in the first cache line, and here the error-corrected second data can be written back into the first cache line.

Step 505, the memory controller 1101 reports the UCE information in the first data to an intelligent management unit (intelligent management unit, IMU).

The IMU is a physical core and is used to process information reported by the UCE.

The flow of the data detection method is described above, and the flow of the hardware detection method is introduced as follows.

In step 506, the memory controller 1101 writes test data (such as first test data) into the first memory unit.

In step 507, the memory controller 1101 reads the data stored in the first memory unit (such as third data).

Exemplarily, the third data can be read after the first test data is written at an interval of a preset time period (such as called a third preset time length), so as to verify the time capability of the first memory unit to correctly store data, or The time for reading back the third data may not be limited, for example, the third data may be read immediately after writing the first test data, which is not limited in this embodiment of the present application. The similarities below will not be repeated.

In step 508, the memory controller 1101 compares the first test data with the third data to determine whether there is a hard failure location in the first memory unit.

Exemplarily, the bit value on each bit of the same position in the first test data and the third data is compared, and if they are consistent, it is determined that the bit has no fault; otherwise, it is determined that the bit is a hard failure bit .

For example, compare the bit value of the first bit of the first test data with the bit value of the first bit of the third data, and if they are the same, determine the first bit of the first memory unit No glitches. Assuming that the bit value on the first bit of the first test data is 0, if the bit value on the first bit of the third data is also 0, then the two are the same, determine the first memory cell There is no fault in each bit. If the bit value on the first bit of the first test data is 0, and the bit value on the first bit of the third data is 1, then the two are different, and the first bit of the first memory unit is determined is the hard fail bit. Afterwards, compare the bit value of the second bit of the first test data with the bit value of the second bit of the third data, and so on, each bit is detected based on this method, to All hard fail bits in the first memory unit are determined, of course, there may be no hard fail bits in the first memory unit.

Step 509, the memory controller 1101 writes the second test data into the first memory unit.

It should be noted that the second test data is different from the first test data, and the difference here may refer to different bit values at the same position. For example, the first test data is 001101011010, and the second test data is 110010100101. It should be understood that this is only an example, and the number of test data is not limited. For example, when the size of the first memory unit is 8 bytes, for example, the first test data may be 0x5A5A5A, and the second test data may be x0A5A5A5.

It should be noted that the above example is only an example, and the embodiment of the present application does not limit the values of the first test data and the second test data.

In step 510, the memory controller 1101 reads data stored in the first memory unit (such as fourth data).

Step 511 , the memory controller 1101 compares the second test data with the fourth data to determine whether there is a hard failure location in the first memory unit.

For the specific comparison method, please refer to the introduction of the above step 508, which will not be repeated here.

It should be noted that FIG. 5 shows that two hard fail bit detections are performed on the first memory unit, but this is not limited in this embodiment of the present application. In this embodiment of the present application, at least two hard fail bit detections can be performed on the same memory unit to determine the hard fail bit in the first memory unit, thereby reducing the missed detection caused by the fact that the read value is exactly the same as the output data of the hard fail bit probability.

Step 512 , the memory controller 1101 judges whether there is a hard fail bit in the first memory unit, if not, execute step 513 , otherwise, execute step 514 .

In step 513, the memory controller 1101 writes the data stored in the first cache line back to the first memory unit.

Step 514, the memory controller 1101 sends the detection result of the hard fail bit in the first memory unit to the IMU.

It should be noted that data detection and hardware detection are two independent detection methods, so there is no strict timing limit between the data detection process (step 502-step 505) and the hardware detection process (step 506-step 514), such as data The detection process and the hardware detection process can be executed in parallel, or the data detection process can be executed first and then the hardware detection process can be executed, or the hardware detection process can be executed first and then the data detection process can be executed. This embodiment of the application does not limit this, and it can be understood What's more, when the data detection process and the hardware detection process are executed in parallel, the total time consumption of memory detection can be shortened.

The above takes the first memory unit as an example, and introduces the process of performing memory detection on the first memory unit. For the detection methods of the other memory units in the memory 120 except the first memory unit, you can refer to the foregoing introduction. Here No longer. Wherein, the remaining memory units may be all memory units in the memory 120 except the first memory unit, or may be specified part of memory units except the first memory unit, which is not limited in this embodiment of the present application.

In the detection process shown in FIG. 5 above, a data access request (including a data read request and a data write request) to the first memory unit may also be received. Take the data access request from the processor 110 as an example as follows, respectively for The processing flow of the data read request and data write request received during the memory detection process is introduced:

1. A data read request is received during the memory detection process;

The data read request may be received at any timing of the memory detection process shown in FIG. 5 , which is not limited in this embodiment of the present application. No matter at what time the data read request is received, there are the following response methods based on whether there is a data error in the first data:

1) If it is determined in step 502 that the first data has no data error, then in response to the data read request, the memory controller 1101 sends the first data stored in the first cache line of the cache 1102 to the processor 110 .

It is worth noting that the data read request may be received before step 502 or after step 502. If it is received before step 502, it may wait for step 502 to be executed, and determine The data read request is responded to after the first data has no data error, so as to ensure that correct data is returned to the processor 110 and improve data reliability. Similarities will not be repeated below.

2) If it is determined in step 503 that there is a correctable error in the first data, then in response to the data read request, after writing the error-corrected second data into the first cache line in step 504, the memory controller 1101 writes the first cache line The second data stored in the row is sent to the processor 110 .

3) If it is determined in step 503 that there is an uncorrectable error in the first data, then in response to the data read request, the memory controller 1101 sends an error response.

2. A data write request is received during the memory detection process;

Similarly, the data write request may be received at any timing of the memory detection process shown in FIG. 5 , which is not limited in this embodiment of the present application. Regardless of when the data write request is received, there are the following response methods based on whether the first memory unit has a hard fail bit:

1) If it is determined in step 512 that the first memory unit does not have a hard fail bit, the memory controller 1101 writes the data carried in the data write request (for example, fifth data) into the first memory unit.

If the data write request is received before step 512, the fifth data carried in the data write request may be stored in the cache 1102 first, and in an optional implementation manner, the fifth data may be stored in the first In this way, when step 513 is executed, the fifth data can be directly written into the first memory unit. In another optional manner, the fifth data may also be stored in other cache lines, such as the second cache line, and after step 512 determines that the first memory unit has no hard fail bit, the second The cache line acquires the fifth data and writes it into the first memory unit, and step 513 is not executed again. Alternatively, if the data write request is received after step 512, the fifth data carried in the data write request may be directly written into the first memory unit, and step 510b is not performed again.

2) If it is determined in step 512 that the first memory unit has a hard fail bit, then in response to the data write request, the memory controller 1101 writes the fifth data in the data write request into the memory 120 except the first memory unit A new free memory unit, the new memory unit may be a memory unit that does not have a hard fail bit as determined by memory detection, or it may be a spare memory unit corresponding to the first memory unit. No limit.

The first operation detection method can not only detect the data error in the data stored in the first memory unit, and correct the error in time when there is data, but also detect the hardware of the first memory unit, and find the hard failure bit in time, Reduce the risk of system downtime, improve the stability and reliability of system operation, and also provide a way to respond to data access requests during the memory detection process, reducing the delay of data access requests as much as possible.

Detection method two: only perform data detection on the first memory unit.

For the process of performing data error detection on the first memory unit, refer to the specific introduction of steps 501 to 505 in FIG. 5 above, which will not be repeated here.

Similarly, in the process of performing data error detection on the data stored in the first memory unit, a data access request to the first memory unit may also be received, wherein, for the data read request received during the memory detection process For the response method, please refer to the introduction of the response method to the data read request in the first detection method, which will not be repeated here.

When receiving a data write request during the memory detection process, in response to the data write request, the memory controller 1101 may directly write the fifth data carried in the data write request into the first memory unit, and may terminate the data detection process .

The second operation detection method can correct the data stored in the first memory unit, and provides a response method to the data access request during the data detection process, which can reduce the data access request during the memory detection process as much as possible. time delay and can improve data reliability.

Detection method three: only perform hardware detection on the first memory unit.

For the detection process of performing hardware detection on the first memory unit, refer to the specific introduction of step 501, step 506-step 514 in FIG. 5 above, and details will not be repeated here.

Similarly, in the process of performing hard fail bit detection on the first memory unit, a data access request to the first memory unit may be received, wherein, the response method of receiving a data write request during the memory detection process can be referred to the aforementioned The introduction of the response method to the data write request in the detection method 1 will not be repeated here.

For receiving a data read request during the memory detection process, in response to the data read request, the memory controller 1101 may send the first data stored in the first cache line to the processor 110 .

The third operation detection method can perform hardware detection on the first memory unit to detect the hard failure bit of the first memory unit, and provides a response method to data access requests during the hardware detection process, which can reduce memory usage as much as possible. The delay of data access requests in the detection process can improve data reliability.

In the above manner, when the access frequency of the first memory unit within a historical period is less than or equal to the preset threshold, memory detection of the first memory unit may be triggered to determine the detection result of the first memory unit. It is possible to determine whether to trigger memory detection based on the access frequency of the first memory unit during startup or operation, so as to reduce the delay of data access requests to the first memory unit as much as possible, and the memory detection is no longer limited to specific timing, providing It improves the flexibility of memory detection, can detect memory faults in time, reduces the risk of system downtime, and improves the stability and reliability of system operation.

Based on the same idea as the method embodiment, the embodiment of the present application further provides a memory detection device, which is used to execute the method performed by the memory controller in the method embodiment shown in FIG. 3 or FIG. 5 . As shown in FIG. 6, the memory detection device 600 includes a determination module 601 and a detection module 602. Optionally, it may also include a reading module 603 and a communication module 604. Specifically, in the memory detection device 600, each module directly passes The communication path establishes the connection.

A determination module 601, configured to determine the access frequency of the first memory unit within a historical time period of a preset duration based on the historical access records of the first memory unit; the first memory unit is one of the plurality of memory units Any one of the memory units; the historical access record is used to record the information of the access request for the first memory unit; it is also used to judge whether the access frequency satisfies the preset condition; for the specific implementation, please refer to the The description of step 302 will not be repeated here.

The detection module 602 is configured to perform memory detection on the first memory unit to determine a detection result of the first memory unit when the access frequency satisfies a preset condition. For a specific implementation manner, please refer to the description of step 303 in FIG. 3 , which will not be repeated here.

As a possible implementation manner, the preset condition includes that the access frequency of the first memory unit is not greater than a preset threshold.

As a possible implementation, the reading module 603 is configured to read the first data stored in the first memory unit, and store the first data in the first storage unit of the first memory; for the specific implementation, please refer to The description of step 501 in FIG. 5 will not be repeated here.

The detection module 602 is configured to check whether there is a data error in the first data; if there is no error in the first data, then keep the first data stored in the first storage unit; or if the first data exists, it can Correcting the error CE, the detection module is also used to correct the first data to obtain the second data, and write the second data into the first storage unit; or if the first data If there is an uncorrectable error UCE, send error information for indicating the UCE through the communication module. For a specific implementation manner, please refer to the description of steps 502 to 505 in FIG. 5 , which will not be repeated here.

As a possible implementation manner, the detection module 602 is also used to detect whether there is a hard fail bit in the first memory unit, and the hard fail bit is a bit whose binary value written is different from the binary value read; if it exists, then Sending fault information through the communication module, the fault information is used to indicate one or more detected hard failure bits in the first memory unit; or if not present, and the first data has a CE, then The detection module is further configured to write the second data stored in the first storage unit into the first memory unit; or, if it does not exist and there is no error in the first data, then the The detection module is further configured to write the first data stored in the first storage unit into the first memory unit. For the specific implementation manner, please refer to the description of steps 506 to 514 in FIG. 5 , which will not be repeated here.

As a possible implementation manner, the communication module 604 is configured to receive a read request for requesting to read the data stored in the first memory unit; if the first data has a CE, the determination module 601 also Obtaining the second data from the first storage unit in response to the read request, and sending the second data through the communication module 604; or if there is no error in the first data, the determining module 601 also uses The first data is acquired from the first storage unit in response to the read request, and the first data is sent through the communication module 604 .

As a possible implementation manner, the communication module 604 is configured to receive a write request, and the write request is used to request to write the third data carried in the write request into the first memory unit; if the first memory unit does not If there is a hard failure bit, the determination module 601 is also used to write the third data into the first memory unit; or if the first memory unit has a hard failure bit, the determination module 601 is also used to write the third data to The second memory unit is inserted into the second memory unit, and the second memory unit is a memory unit except the first memory unit among the plurality of memory units included in the memory.

Based on the above content and the same idea, the present application provides a computing device. FIG. 7 is a schematic diagram of a computing device 700 provided in an embodiment of the present application. As shown in FIG. 7, the computing device 700 includes a processor 701 (processor 701 is provided with a memory controller 2) a communication interface 704, a storage medium 705, and a bus 706. Wherein, the processor 701 , the communication interface 704 and the storage medium 705 communicate through the bus 706 , or communicate through other means such as wireless transmission. Wherein, the memory medium 702 may be used to store computer-executable instructions, and the memory controller 2 is used to execute the computer-executable instructions stored in the memory medium 702 .

The memory medium 702 stores computer-executable instructions, and the memory controller 2 can call the computer-executable instructions stored in the memory medium 702 to perform the following operations:

Based on the historical access records of the first memory unit, determine the access frequency of the first memory unit within a historical period of a preset duration; the first memory unit is any one of the plurality of memory units unit; the historical access record is used to record the information of the access request for the first memory unit;

When the access frequency satisfies a preset condition, memory detection is performed on the first memory unit to determine a detection result of the first memory unit.

In this embodiment of the present application, the processor 701 integrates a memory controller. Specifically, the processor 701 may be a CPU, for example, a processor of an X86 architecture or a processor of an ARM architecture. The processor 701 can also be other general-purpose processors, digital signal processors (digital signal processing, DSP), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistors Logic devices, discrete hardware components, system on chip (SoC), graphics processing unit (graphic processing unit, GPU), artificial intelligence (artificial intelligent, AI) chips, etc. A general purpose processor may be a microprocessor or any conventional processor or the like.

As a possible embodiment, the memory controller may also be a controller off-chip of the processor 701, configured to implement the same function as the above memory controller.

The memory medium 702 may include read-only memory and random-access memory, and provides instructions and data to the processor 701 . Memory medium 702 may also include non-volatile random access memory. Memory medium 702 can be volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory can be random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available such as static random access memory (static RAM, SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), Double data rate synchronous dynamic random access memory (double data date SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct Memory bus random access memory (direct rambus RAM, DR RAM). Optionally, the memory medium 702 can also be a storage class memory SCM, and the SCM includes at least one of phase change memory PCM, magnetic random access memory MRAM, resistive random access memory RRAM, ferroelectric memory FRAM, fast NAND or nano random access memory NRAM .

In addition to the data bus, the bus 706 may also include a power bus, a control bus, a status signal bus, and the like. However, for clarity of illustration, the various buses are labeled as bus 04 in the figure. The bus 706 can be a peripheral component interconnection standard (Peripheral Component Interconnect Express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, unified bus (unified bus, Ubus or UB), computer fast link ( compute express link (CXL), cache coherent interconnect for accelerators (CCIX), etc. The bus 706 can be divided into address bus, data bus, control bus and so on.

It should be noted that although one processor 701 is taken as an example in the computing device 700 shown in FIG. The number of cores is not limited.

It should be understood that the memory controller 2 in the computing device 700 according to the embodiment of the present application may correspond to the memory detection device 600 in the embodiment of the present application, and may correspond to the implementation of the method in the embodiment shown in FIG. 3 or FIG. 5 of the present application. The corresponding subjects of the memory medium 702, and the above and other operations and/or functions of each module in the memory medium 702 are respectively for realizing the corresponding processes of each method, and for the sake of brevity, details are not repeated here.

As a possible embodiment, the present application further provides a memory controller, which is used to implement the operation steps of the methods shown in FIG. 3 to FIG. 5 , and details are not described here for brevity.

Based on the above content and the same idea, the present application provides a computer-readable storage medium, in which computer programs or instructions are stored. When the computer programs or instructions are executed by the computer, the computer executes the memory control method described in the above-mentioned method embodiments. The method executed by the device.

Based on the above content and the same idea, the present application provides a computer program product, the computer program product includes a computer program or instruction, when the computer program or instruction is executed by a computing device, the method performed by the memory controller in the above method embodiment is implemented .

Based on the above content and the same idea, the present application provides a chip, including at least one processor and an interface; the interface is used to provide program instructions or data for the at least one processor; the at least one processor is used to execute the The above program line instructions are used to implement the method executed by the memory controller in the above method embodiment.

In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device including a server, a data center, and the like integrated with one or more available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (Solid State Disk, SSD)), etc.

The various illustrative logic units and circuits described in the embodiments of the present application can be implemented by a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, Discrete gate or transistor logic, discrete hardware components, or any combination of the above designed to implement or operate the described functions. The general-purpose processor may be a microprocessor, and optionally, the general-purpose processor may also be any conventional processor, controller, microcontroller or state machine. A processor may also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration to accomplish.

The steps of the method or algorithm described in the embodiments of the present application may be directly embedded in hardware, a software unit executed by a processor, or a combination of both. The software unit may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM or any other storage medium in the art. Exemplarily, the storage medium can be connected to the processor, so that the processor can read information from the storage medium, and can write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be provided in an ASIC.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

Although the application has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely illustrative of the application as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of this application. Obviously, those skilled in the art can make various changes and modifications to the application without departing from the scope of the application. In this way, if these modifications and variations of the application fall within the scope of the claims of the application and their equivalent technologies, the application also intends to include these modifications and variations.

Claims (19)

1. A memory detection method, characterized in that it is applied to a computing device, the computing device includes a memory controller and a memory, the memory includes a plurality of memory units, and the method includes:

   The memory controller determines, based on the historical access records of the first memory unit, the access frequency of the first memory unit within a historical time period of a preset duration; the first memory unit is the plurality of memory units Any one of the memory units; the historical access record is used to record the information of the access request for the first memory unit;

   When the access frequency satisfies a preset condition, the memory controller performs memory detection on the first memory unit to determine a detection result of the first memory unit.
2. The method according to claim 1, wherein the preset condition includes that the access frequency of the first memory unit is not greater than a preset threshold.
3. The method according to claim 1 or 2, wherein performing memory detection on the first memory unit to determine the detection result of the first memory unit comprises:

   The memory controller reads the first data stored in the first memory unit, and stores the first data in the first storage unit of the first memory of the memory controller;

   The memory controller checks whether there is a data error in the first data;

   If there is no error in the first data, maintaining the first data stored in the first storage unit; or

   If there is a correctable error CE in the first data, performing error correction on the first data to obtain second data, and writing the second data into the first storage unit; or

   If there is an uncorrectable error UCE in the first data, sending error information for indicating the UCE.
4. The method according to claim 3, wherein after the memory controller stores the first data in the first storage unit, further comprising:

   The memory controller detects whether there is a hard fail bit in the first memory unit, and the hard fail bit is a bit with a binary value written different from a read binary value;

   if present, sending fault information, the fault information being used to indicate one or more hard fail bits detected in the first memory unit; or

   If it does not exist, and the first data has a CE, write the second data stored in the first storage unit into the first memory unit; or, if it does not exist, and the first data If there is no error, write the first data stored in the first storage unit into the first memory unit.
5. The method according to claim 3 or 4, wherein after the memory controller stores the first data in the first storage unit, further comprising:

   receiving a read request, where the read request is used to request to read data stored in the first memory unit;

   If there is a CE for the first data, obtaining the second data from the first storage unit in response to the read request, and returning the second data; or

   If there is no error in the first data, acquiring the first data from the first storage unit in response to the read request, and returning the first data.
6. The method according to claim 3 or 4, wherein after the memory controller stores the first data in the first storage unit, further comprising:

   Detecting a write request of the first memory unit, where the write request is used to request writing third data into the first memory unit;

   If there is no hard fail bit in the first memory unit, writing the third data into the first memory unit; or

   If there is a hard failure bit in the first memory unit, then write the third data into the second memory unit, and the second memory unit is a plurality of memory units included in the memory except the first memory unit A memory unit other than
7. The method according to claim 1 or 2, wherein performing memory detection on the first memory unit to determine the detection result of the first memory unit comprises:

   The memory controller reads first data stored in the first memory unit, and stores the first data in a first storage unit of a first memory of the memory controller;

   The memory controller detects whether there is a hard fail bit in the first memory unit, and the hard fail bit is a bit with a binary value written different from a read binary value;

   If it exists, send fault information, and the fault information is used to indicate one or more hard failure bits detected in the first memory unit; or if it does not exist, the stored in the first memory unit The first data is written back to the first memory unit.
8. The method according to claim 4 or 7, wherein the memory controller detects whether a hard fail bit exists in the first memory unit, comprising:

   The memory controller writes the first detection data into the first memory unit, and reads back the fourth data stored in the first memory unit;

   Comparing the bit values of the bits at the same position in the first detection data and the fourth data to determine whether there is a hard fail bit in the first memory unit;

   The memory controller writes the second detection data into the first memory unit, and reads back the fifth data stored in the first memory unit; writes the second detection data and the fifth data in the same position Compare the bit values on the bits of the first memory unit to determine whether there is a hard fail bit in the first memory unit;

   Wherein, the second detection data is different from the first detection data.
9. A kind of memory detection device, it is characterized in that, described memory detection device comprises:

   The determination module is configured to determine the access frequency of the first memory unit within a historical time period of a preset duration based on the historical access records of the first memory unit; the first memory unit is the plurality of memory units Any one of the memory units; the historical access record is used to record the information of the access request for the first memory unit; it is also used to judge whether the access frequency meets a preset condition;

   When the access frequency satisfies a preset condition, the detection module is configured to perform a memory detection on the first memory unit to determine a detection result of the first memory unit.
10. The device according to claim 9, wherein the preset condition includes that the access frequency of the first memory unit is not greater than a preset threshold.
11. The device according to claim 9 or 10, wherein the device also includes a reading module and a communication module:

    The reading module is used to read the first data stored in the first memory unit, and store the first data in the first storage unit of the first memory;

    The detection module is used to check whether there is a data error in the first data;

    If there is no error in the first data, maintaining the first data stored in the first storage unit; or

    If the first data has a correctable error CE, the detection module is further configured to correct the first data to obtain second data, and write the second data into the first storage unit ;or

    If there is an uncorrectable error UCE in the first data, sending error information for indicating the UCE through the communication module.
12. The device according to claim 11, further comprising a detection module and a communication module:

    The detection module is used to detect whether there is a hard fail bit in the first memory unit, and the hard fail bit is a bit different from the binary value written and the binary value read;

    If there is, sending fault information through the communication module, the fault information is used to indicate one or more detected hard failure bits in the first memory unit; or

    If it does not exist, and the first data has a CE, the detection module is further configured to write the second data stored in the first storage unit into the first memory unit; or, if it does not exist , and there is no error in the first data, the detection module is further configured to write the first data stored in the first storage unit into the first memory unit.
13. The device according to claim 11 or 12, wherein the device further comprises a communication module:

    The communication module is configured to receive a read request, and the read request is used to request to read data stored in the first memory unit;

    If the first data has a CE, the determining module is further configured to obtain the second data from the first storage unit in response to the read request, and send the second data through the communication module; or

    If there is no error in the first data, the determination module is further configured to obtain the first data from the first storage unit in response to the read request, and send the first data through the communication module.
14. The device according to claim 11 or 12, wherein the device further comprises a communication module:

    The communication module is configured to receive a write request, and the write request is used to request to write the third data carried in the write request into the first memory unit;

    If the first memory unit does not have a hard fail bit, the determining module is further configured to write the third data into the first memory unit; or

    If there is a hard failure bit in the first memory unit, the determination module is also used to write the third data into a second memory unit, and the second memory unit is one of the plurality of memory units included in the memory A memory cell other than the first memory cell.
15. The device according to claim 9 or 10, wherein the device also includes a reading module and a communication module:

    The reading module is configured to read the first data stored in the first memory unit, and store the first data in the first storage unit of the first memory;

    The detection module is used to detect whether there is a hard fail bit in the first memory unit, and the hard fail bit is a bit different from the binary value written and the binary value read;

    If it exists, the detection module is further configured to send fault information through the communication module, and the fault information is used to indicate one or more detected hard failure bits in the first memory unit; or if it does not exist , the detection module is further configured to write back the first data stored in the first storage unit to the first memory unit.
16. The device according to claim 12 or 15, wherein the detection module is specifically configured to: write the first detection data into the first memory unit, and read back the first memory unit through the reading module. The fourth data stored in the memory unit; comparing the first detection data with the bit value at the same position in the fourth data to determine whether there is a hard failure bit in the first memory unit ;

    Writing the second detection data into the first memory unit, and reading back the fifth data stored in the first memory unit through the read module; writing the second detection data to be the same as the fifth data Compare the bit values on the bits of the position to determine whether there is a hard fail bit in the first memory unit;

    Wherein, the second detection data is different from the first detection data.
17. A memory detection device, characterized in that the computing device includes a processor and a memory;

    The memory is used to store computer program instructions;

    The processor executes and invokes computer program instructions in the memory to perform the method according to any one of claims 1 to 8.
18. A computer-readable storage medium, characterized by comprising a computer-readable storage medium storing program codes, the program codes including instructions for executing the method according to any one of claims 1-8.
19. A computing device, characterized in that the computing device includes a processor and a memory controller;

    The processor is configured to send a data access request of the first memory unit to the memory controller;

    The memory controller is configured to execute the method according to any one of claims 1-8.

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