CN115298654A

CN115298654A - Data storage method and related device

Info

Publication number: CN115298654A
Application number: CN202080098749.8A
Authority: CN
Inventors: 冉宜; 孙亚萍; 王金伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2022-11-04
Also published as: WO2021195979A1

Abstract

The embodiment of the application discloses a data storage method and a related device. Detecting the error rate when the current data is read; determining a mapping relation for storing data to a storage-level memory according to the error rate, wherein the mapping relation comprises an association relation between a physical block address and a medium address; and storing data according to the mapping relation. The method comprises the steps of determining a mapping relation for storing data into a storage-class memory by detecting the error rate of current data during reading, and storing the data according to the mapping relation. Therefore, the data can be effectively prevented from being stored by using the mapping relation which is subjected to centralized failure, the check bit length required by the physical block address in the mapping relation is further reduced, and the available storage space is increased.

Description

Data storage method and related device

Technical Field

The present application relates to the field of storage technologies, and in particular, to a data storage method and a related apparatus.

Background

Storage Class Memory (SCM), as a new type of nonvolatile memory technology, has the characteristics of high read-write speed, high storage density, and the like. In order to realize the feature of high storage density, the memory of the storage stage usually adopts a crossbar or crossbar structure. As shown in fig. 1, the crossbar array is a structure in which a plurality of Bit Lines (BL) and Word Lines (WL) are alternately stacked, and the memory cells are controlled by the bit lines and the word lines.

In practical applications, a user accesses the storage class memory through an operating system, specifically, accesses Logical Block Addresses (LBAs), and each LBA is mapped to a corresponding Physical Block Address (PBA). The physical block addresses are physical addresses of the bottom layer of the storage-level memory, each physical block address corresponds to a plurality of storage units, and each physical block address corresponds to a plurality of media addresses because each storage unit has an independent Media Address (MA).

In order to correct errors generated when the storage class memory stores data, error Checking and Correcting (ECC) is usually used to correct the data, and the length of a check bit used in error correction is positively correlated with the length of the error data in each physical block address. Due to manufacturing defects of the semiconductor process, adjacent memory cells may simultaneously fail, such an error being referred to as a catastrophic failure. A centralized failure may increase the length of erroneous data in a single physical block address. Therefore, the length of the check bits needs to be increased to correct data errors caused by a concentrated failure. Longer check bits result in increased data redundancy and reduced available storage space.

Disclosure of Invention

In view of this, an embodiment of the present application provides a data storage method and a related apparatus, which select a mapping relationship corresponding to current data by detecting an error rate of the current data, and store the data using the mapping relationship. Therefore, the data can be effectively prevented from being stored by using the mapping relation which is subjected to centralized failure, the length of the check bit required by the physical block address is reduced, and the available storage space is increased.

In a first aspect, an embodiment of the present application provides a data storage method, where the data storage method is applied to a storage-class memory, and may include: first, a Symbol Error Rate (SER) at the time of current data reading is detected. Secondly, according to the error rate, determining a mapping relation for storing data to a storage class memory, wherein the mapping relation comprises an association relation between a physical block address and a medium address, and the mapping relation is (for example, (the physical block address A-the medium address B)). And thirdly, storing the data according to the mapping relation.

In the embodiment of the application, the storage device may detect the error rate of data (current data) in real time, and then select the mapping relationship corresponding to the current data according to the error rate of the current data. And finally, storing the data according to the selected mapping relation. By detecting the error rate of the data corresponding to the mapping relationship, for example: and determining whether the mapping relation (physical block address A-medium address B) has centralized failure or not according to the error rate of the data stored in the medium address B. Specifically, what kind of mapping relation is used to store data is selected according to the error code rate. And determining the mapping relation for storing the data into the storage class memory by detecting the error rate when the current data is read. Therefore, the data can be effectively prevented from being stored by using a mapping relation with centralized failure (the error rate of the data in the mapping relation is high), the check bit length required by the physical block address in the mapping relation is further reduced, and the available storage space is increased.

With reference to the first aspect, in a possible implementation manner of the first aspect, determining, according to a bit error rate, a mapping relationship used for storing data in a storage class memory includes: and when the error rate is greater than a preset threshold, determining a second mapping relation as the mapping relation, wherein under the second mapping relation and a first mapping relation, the association relation between the physical block address and the medium address is different, and the first mapping relation is that when the current data is read, the storage-level memory stores data based on the first mapping relation. In an alternative implementation, the preset threshold may be 5 bits.

In the embodiment of the application, the mapping relation is determined by comparing the relation between the bit error rate and a preset threshold. And when the error rate is greater than a preset threshold, determining the second mapping relation as the mapping relation. Since the error rate is large, a mapping relationship (second mapping relationship) different from the existing mapping relationship (first mapping relationship) needs to be selected, for example: the physical block address a in the first mapping is mapped to media addresses 1-4 and the physical block address B is mapped to media addresses 10-15, since when reading data stored using the first mapping, it is detected that the error rate of the data is high. Thus, the data is stored using a second mapping in which physical block address A maps to

media address

1, 3, 5 or 7 and physical block address B maps to media addresses 10-15. Thereby avoiding storing data using mappings that suffer from a centralized failure that occurs at some media address in the mapping.

With reference to the first aspect, in a possible implementation manner of the first aspect, determining, according to the error rate, a mapping relationship used for storing data in the storage class memory includes: and when the error rate is less than or equal to the preset threshold, determining the first mapping relation as the mapping relation. And when the error rate is less than or equal to a preset threshold, determining the first mapping relation as the mapping relation. Because the error rate is smaller, the mapping relation does not need to be changed, and the read-write resource of the storage device can be saved.

With reference to the first aspect, in a possible implementation manner of the first aspect, a first mapping relationship is obtained, where the first mapping relationship includes a first physical block address and a first media address, the first physical block address is associated with the first media address, and the first mapping relationship is, for example, (logical block address 1-physical block address 1-media address 1); a second mapping is generated according to the first mapping, the second mapping including the first physical block address and a second media address, the first physical block address being associated with the second media address, the second media address being inconsistent with the first media address, the second mapping being, for example, (logical block address 1-physical block address 1-media address 2). The first media address and the second media address are located on the same die, or the first media address and the second media address are located on different dies; and if the error rate of the data in the second medium address is smaller than the error rate of the data in the first medium address, storing the data by using the second mapping relation.

In the embodiment of the application, a first mapping relation is obtained, where the first mapping relation includes a first physical block address and a first media address, and the first physical block address is associated with the first media address. Then, a second mapping relation is generated according to the first mapping relation, wherein the second mapping relation comprises the first physical block address and a second medium address, and the first physical block address is associated with the second medium address. And when the data are stored, if the error rate of the data in the second medium address is less than that of the data in the first medium address, storing the data by using a second mapping relation. By changing the mapping relation between the physical block address and the medium address, the medium address with centralized failure belongs to different mapping relations, so that the error data volume generated by centralized failure in a single physical block address is reduced, the check bit length required by the physical block address is further reduced, and the available storage space is increased.

With reference to the first aspect, in a possible implementation manner of the first aspect, the method may further include: and generating a third mapping relation according to the first mapping relation, wherein the third mapping relation comprises a second physical block address and the third medium address, the second physical block address is associated with the third medium address, the second physical block address is inconsistent with the first physical block address, the third medium address is inconsistent with the second medium address, and the third medium address comprises part of the first medium address. For example: the first mapping relationship is: first physical block address LBA = X0b, first media address (MA: X000/MA: X001/MA: X010/MA: X011). Generating a third mapping relation according to the first mapping relation, wherein the third mapping relation comprises the following steps: second physical block address LBA = X1b, third media address (MA: X000/MA: X101/MA: X110/MA: X111) including part of first media address "MA: x000"; the data is stored using the third mapping relationship.

In this embodiment, a first media address included in a first mapping relationship belongs to management of a third mapping relationship, where a third media address in the third mapping relationship is associated with a second physical block address, and the third media address includes a part of the first media address. The centralized failures in the first medium addresses are dispersed into different mapping relations, so that the error data volume caused by the centralized failures in a single physical block address is reduced, the check bit length required by the physical block address is reduced, and the available storage space is increased.

With reference to the first aspect, in a possible implementation manner of the first aspect, the method may include: detecting to obtain a first error rate (SER) when reading first data, wherein a storage area of the first data is the first medium address; when the first error rate is greater than or equal to a first threshold value, the first data and the second data are backed up, wherein the storage area of the second data is the second medium address, and the first threshold value is, for example, 5% or 8%. The first error rate may also be an error data length, and at this time, the first threshold may be 5 bits (bit); clearing the data stored in the first medium address and the second medium address; and storing the first data by using the second mapping relation or storing the first data by using the third mapping relation. The data storage method provided by the embodiment of the application can store data by using different mapping relations according to the error rate of the data when reading the data, so that the reliability of the data in the use process of a user is ensured, and the implementation flexibility of the scheme is improved.

With reference to the first aspect, in a possible implementation manner of the first aspect, the method may include: detecting a second error rate, wherein the second error rate is an error rate of the second data stored in the second medium address; and when the first error rate is greater than the second error rate, storing the first data in the backup to the second medium address according to the second mapping relation, and detecting the error rate of second data stored in the second medium address, wherein the error rate is called as a second error rate. In an optional implementation manner, before generating the second mapping relationship, second data stored in the second medium address needs to be backed up, and a bit error rate of the second data is detected in a process of reading the second data, where the bit error rate is also a bit error rate of the second medium address. In another alternative implementation, after the second data is backed up, the data stored in the second medium address is first emptied. Secondly, the storage device uses the preset data to carry out error rate detection on the second medium address (corresponding storage unit) to obtain a second error rate. And when the first error rate is greater than the second error rate, storing the data by using a second mapping relation. And when the first error rate is less than or equal to the second error rate, the storage unit corresponding to the second medium address in the second mapping relation also has concentrated failure. The storage device needs to store data using other mapping relationships. In this embodiment, after the storage device generates the second mapping relationship according to the first mapping relationship, a bit error rate (second bit error rate) of the second medium address in the second mapping relationship may be detected. And determining a mapping mode used when the data is stored according to the first error rate and the second error rate. The method ensures that the error rate in the mapping relation used by the storage device is lower, reduces the check bit length required by the physical block address, and increases the available storage space.

With reference to the first aspect, in a possible implementation manner of the first aspect, the method may include: and acquiring a first detection instruction, wherein the first detection instruction is used for triggering and detecting the error rate of the current data, and the first detection instruction is an instruction which is periodically and automatically triggered in an idle state, or the first detection instruction is an instruction which is actively triggered by a user. The first detection instruction can be obtained in various ways, and is used for triggering the error rate of the current data, and performing the subsequent steps of selecting the mapping relation and the like. The realization flexibility of this scheme has been promoted.

With reference to the first aspect, in a possible implementation manner of the first aspect, the method may include: and writing third data into the first medium address according to the first detection instruction and the first mapping relation. In an optional implementation manner, before the storage device leaves a factory, the storage device acquires the first detection instruction. First, the storage device writes third data to the first medium address according to the first detection command and the first mapping relationship. The third data is test data used in detecting the bit error rate. Then, the storage device writes third data to the second medium address according to the first detection instruction and the second mapping relation. In another alternative implementation manner, during the process of using the storage device by a user, the medium address with a higher error rate may be disabled through the first detection instruction, so as to ensure the security of data. Specifically, first, the storage device backs up data in a first media address and data in a second media address according to a first detection instruction. Then, the storage device writes third data to the first medium address and the second medium address, respectively. In another alternative implementation, the first detection instruction may be an instruction that is automatically triggered when the storage device is in an idle state. Or may be an instruction that is automatically triggered periodically by the storage device, which is not limited herein. Writing the third data to the second medium address according to the first detection instruction and the second mapping relation; detecting a third error rate, wherein the third error rate is the error rate of the third data in the first medium address; detecting a fourth error rate, wherein the fourth error rate is the error rate of the third data in the second medium address; and determining a mapping relation used when the data is stored according to the third error rate and the fourth error rate. In an optional implementation manner, when the third error rate is greater than the fourth error rate, the data is stored using the first mapping relationship. And when the third error rate is less than or equal to the fourth error rate, storing the data by using a second mapping relation. In another optional implementation manner, when the third bit error rate is greater than the first threshold value, storing the data by using a second mapping relationship; and when the fourth error rate is larger than the first threshold value, storing the data by using the first mapping relation.

In the embodiment of the application, before leaving a factory or in the using process of the storage device, the error rate of the medium address in each current mapping relation can be detected according to the first detection instruction, and the mapping relation used when the data is stored is determined according to the error rate. So as to improve the storage safety of the data.

In a second aspect, an embodiment of the present application provides a storage apparatus, which may include: the processing module is used for detecting the error rate of the current data; the processing module is further used for determining a mapping relation for storing data to the storage-level memory according to the error rate, wherein the mapping relation comprises an association relation between a physical block address and a medium address; and the storage module is used for storing the data by using the selected mapping relation.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing module is specifically configured to select a mapping relationship corresponding to the changed current data when the bit error rate of the current data is greater than a preset threshold; the processing module is specifically configured to select an original mapping relationship corresponding to the current data when the bit error rate of the current data is less than or equal to the preset threshold.

With reference to the second aspect, in a possible implementation manner of the second aspect, the obtaining module is configured to obtain a first mapping relationship, where the first mapping relationship includes a first physical block address and a first media address, and the first physical block address is associated with the first media address; and the processing module is used for generating a second mapping relation according to the first mapping relation, wherein the second mapping relation comprises a first physical block address and a second medium address, the first physical block address is associated with the second medium address, and the second medium address is inconsistent with the first medium address.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage module is configured to store the data using the second mapping relationship if the error rate of the data in the second medium address is smaller than the error rate of the data in the first medium address.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing module is further configured to generate a third mapping relationship according to the first mapping relationship, where the third mapping relationship includes a second physical block address and a third media address, the second physical block address is associated with the third media address, the second physical block address is inconsistent with the first physical block address, the third media address is inconsistent with the second media address, and the third media address includes a part of the first media address; and the storage module is also used for storing the data by using the third mapping relation.

With reference to the second aspect, in a possible implementation manner of the second aspect, the first media address and the second media address are located on a same die, or the first media address and the second media address are located on different dies.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage apparatus further includes: the processing module is further used for detecting and obtaining a first error rate when the first data is read, wherein the storage area of the first data is a first medium address; the storage module is further used for backing up the first data and the second data when the first error rate is larger than or equal to a first threshold value, wherein a storage area of the second data is a second medium address; and the storage module is also used for emptying the data stored in the first medium address and the second medium address.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage apparatus further includes: and the storage module is also used for storing the first data by using the second mapping relation or storing the first data by using the third mapping relation.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage apparatus further includes: the processing module is further configured to detect a second error rate, where the second error rate is an error rate of second data stored in the second medium address; and the processing module is also used for determining a mapping relation used when the data is stored according to the first error rate and the second error rate.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage module is specifically configured to store the data using a second mapping relationship when the first error rate is greater than the second error rate; and the storage module is specifically used for storing the data by using the third mapping relation when the first error rate is less than or equal to the second error rate.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage module is specifically configured to store the first data in the backup to the second medium address according to the second mapping relationship.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage module is specifically configured to store the second data in the backup to the first medium address and the third medium address according to the third mapping relationship.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage apparatus further includes: the obtaining module is further configured to obtain a first detection instruction, where the first detection instruction is used to trigger detection of an error rate of current data, and the first detection instruction is an instruction that is automatically triggered when the first detection instruction is in an idle state, or the first detection instruction is an instruction that is actively triggered by a user.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage apparatus further includes: the storage module is further used for writing third data into the first medium address according to the first detection instruction and the first mapping relation; the storage module is further used for writing third data into the second medium address according to the first detection instruction and the second mapping relation; the processing module is further used for detecting a third error rate, wherein the third error rate is an error rate of third data in the first medium address; the processing module is further used for detecting a fourth error rate, wherein the fourth error rate is the error rate of third data in the second medium address; and the processing module is further used for determining a mapping relation used when the data is stored according to the third error rate and the fourth error rate.

With reference to the second aspect, in a possible implementation manner of the second aspect, the storage module is specifically configured to store the data using the first mapping relationship when the third error rate is greater than the fourth error rate; and the storage module is specifically used for storing the data by using the second mapping relation when the third error rate is less than or equal to the fourth error rate.

In a third aspect, an embodiment of the present application provides a computer device, where the terminal device includes at least one processor, a memory, a communication port, a display, and computer-executable instructions stored in the memory and executable on the processor, and when the computer-executable instructions are executed by the processor, the processor performs any one of the possible implementations of the first aspect or the first aspect.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing one or more computer-executable instructions, which, when executed by a processor, perform any one of the possible implementations of the first aspect or the first aspect as described above.

In a fifth aspect, embodiments of the present application provide a computer program product (or computer program) storing one or more computer-executable instructions, where when the computer-executable instructions are executed by the processor, the processor executes any one of the possible implementations of the first aspect or the first aspect.

In a sixth aspect, the present application provides a chip system comprising a processor for enabling a computer device to implement the functions recited in the above aspects. In one possible design, the system-on-chip further includes a memory for storing program instructions and data necessary for the computer device. The chip system may be formed by a chip, or may include a chip and other discrete devices.

In a seventh aspect, an embodiment of the present application further provides a storage apparatus, where the storage apparatus includes a processor, a buffer, and a memory, where the memory includes one or more storage units, and program instructions are stored in the buffer; wherein the processor executes the first aspect or any one of the possible implementations of the first aspect, and stores data to the memory according to the program instructions; the memory is used for storing data according to the instruction.

Drawings

FIG. 1 is a schematic diagram of a crossbar array;

FIG. 2 is a system framework diagram according to an embodiment of the present application;

fig. 3 is a schematic diagram of an embodiment of a data storage method according to an embodiment of the present application;

fig. 4 is a schematic diagram of another embodiment of a data storage method according to an embodiment of the present application;

fig. 5 is a schematic diagram of another embodiment of a data storage method according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another embodiment of a data storage method according to an embodiment of the present application;

fig. 7 is a schematic diagram of a mapping relationship provided in an embodiment of the present application;

fig. 8 is a schematic diagram of another mapping relationship proposed in the embodiment of the present application;

fig. 9 is a schematic diagram of another mapping relationship proposed in the embodiment of the present application;

FIG. 10 is a diagram illustrating a relationship between parity bits and data according to an embodiment of the present application;

FIG. 11 is a schematic diagram of an embodiment of a memory device in the embodiment of the present application;

fig. 12 is a schematic diagram of a hardware structure of a computer device 1200 in the embodiment of the present application.

Detailed Description

The embodiment of the application provides a data storage method and a related device, and a first mapping relation is obtained firstly, wherein the first mapping relation comprises a first physical block address and a first medium address, and the first medium address is associated with the first physical block address; secondly, generating a second mapping relation according to the first mapping relation, wherein the second mapping relation comprises a first physical block address and a second medium address, the first physical block address is associated with the second medium address, and the second medium address is inconsistent with the first medium address; again, the data is stored using the second mapping relationship. When a centralized failure occurs in a storage unit corresponding to the first medium address, the check bit required by the first physical block address is longer, which results in increased data redundancy and reduced available storage space of the memory. And generating a second mapping relation according to the first mapping relation, wherein the medium address managed by the first physical block address in the second mapping relation is a second medium address, and the storage unit (the medium address corresponding to the first medium address) with concentrated failure is avoided. Therefore, when the second mapping relation is used for storing data, the length of the check bit required by the first physical block address can be effectively reduced, and the available storage space is increased.

For easy understanding, please refer to fig. 2, and fig. 2 is a schematic diagram of a system framework according to an embodiment of the present application. The data storage method provided by the embodiment of the application can be applied to a storage-class memory, and when the storage memory is deployed in a computer device, a host (a central processing unit, a mainboard and the like) of the computer device can establish communication connection with the storage-class memory through a bus. The data storage command and the data reading command from the host are transmitted to the storage-class memory through the bus. The processor in the storage class memory processes the instructions and then reads or writes data from or to a die (die) 1 to a die N corresponding to the instructions, where N is a positive integer.

Specifically, the host sends a data reading instruction (or a data storing instruction) to the storage class memory through the bus, and the instruction carries the logical block address. And after receiving the instruction, the storage-level memory determines the physical block address corresponding to the logical block address according to a mapping relation list, and the mapping relation list stores and stores the buffer in the storage-level memory. Each physical block address corresponds to one or more memory units (e.g., the memory unit shown in fig. 1), each memory unit has a separate medium address, and the memory units may be memory units on the same die (die) or memory units on different dies. Thus, each physical block address corresponds to one or more media addresses, and the mapping relationship between the physical block address and the media addresses is also stored and buffered in the form of a mapping relationship list. For ease of understanding, please refer to table 1.

TABLE 1

It should be noted that the data storage method provided in the embodiments of the present application may be applied to other storage devices besides a Storage Class Memory (SCM), and the method is not limited herein, for example: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically Erasable PROM (EEPROM), or flash memory.

Hereinafter, embodiments of the present application will be described with reference to the drawings. Referring to fig. 3, fig. 3 is a schematic diagram illustrating an embodiment of a data storage method according to an embodiment of the present application. Taking the application of the data storage method to a storage-class memory as an example, the data storage method provided by the embodiment of the application comprises the following steps:

301. and acquiring a first mapping relation.

In this embodiment, in the operation process of the storage device that is deployed with the data storage method provided in this embodiment, first, the bit error rate when the current data is read is detected. Next, according to the error rate, a mapping relationship for storing data to a storage device (in this embodiment, the storage device is a storage class memory) is determined, where the mapping relationship includes an association relationship between a physical block address and a media address.

And when the error rate is greater than a preset threshold, determining a second mapping relation as the mapping relation, wherein under the second mapping relation and a first mapping relation, medium addresses corresponding to the same physical block address are different, and the first mapping relation is that when the current data is read, the storage-level memory stores data based on the first mapping relation. When the ber is less than or equal to the predetermined threshold, determining the first mapping relationship as the mapping relationship, for example, the first mapping relationship is: the physical block address a is associated with the media address B, and the mapping is still used to store data.

Next, when the bit error rate is greater than the preset threshold, the second mapping relationship is determined as the mapping relationship, and the detailed description is given below:

first, a first mapping relationship is obtained. The first mapping relationship includes a first physical address and a first media address, the first physical address being associated with the first media address. This first mapping relationship can be seen in table 2.

TABLE 2

Specifically, the first mapping relationship is cached in a cache in the storage-level memory in a form of a mapping relationship list, and the first mapping relationship may be configured by the computer device, or may be pre-configured before the storage-level memory leaves the factory, which is not limited herein.

In the first mapping relationship, the first media address may be a plurality of media addresses, and is not limited herein. For example: the first mapping relationship includes a first physical block address (PBA 1) and a first media address (MA: X000/MA: X001/MA: X010/MA: X011), the first physical block address and the first media address being related. The first physical block address manages the first media address.

302. And generating a second mapping relation according to the first mapping relation.

In this embodiment, the storage device generates a second mapping relationship according to the first mapping relationship, where the second mapping relationship includes a first physical block address and a second media address, the first physical block address is associated with the second media address, and the second media address is inconsistent with the first media address. The first media address may be one or more media addresses and the second media address may be one or more media addresses. The first media address and the second media address may be located on the same die (die) or on different dies, which is not limited herein. When the first media address includes multiple media addresses, the first media addresses may be located in the same die or in different dies. The second medium address may be located in the same die as the first medium address or in a different die from the first medium address, which is not limited herein.

It should be noted that the determination manner of the second medium address in the second mapping relationship may be configured in advance, for example: when the storage device needs to generate the second mapping relationship, the storage device selects one or more medium addresses from all medium addresses according to a preset rule, and selects part of the medium addresses (one or more medium addresses) from the first medium addresses as the second medium addresses in the second mapping relationship. It is also possible to randomly select one or more media addresses from all currently managed media addresses, and select a part of the media addresses (one or more media addresses) from the first media addresses as the second media addresses in the second mapping relationship, which is not limited herein. The pre-configured rule may be to select a single-bit medium address, or a double-bit medium address, or to select one of the medium addresses every N medium addresses, where N is a positive integer, and is not limited herein.

This second mapping relationship can be seen in table 3.

TABLE 3

It should be noted that, in the second mapping relationship, the second media address may be one or more media addresses, which is not limited herein. The second media addresses included in the second mapping relationship may be consistent with the first media addresses included in the first mapping relationship, for example, the first media addresses shown in table 2 and table 3 include 4 media addresses, and the second media addresses include 4 media addresses; the first media address may also be inconsistent with the second media address number, for example: the first medium address includes: (MA: X0000/MA: X0100/MA: X0010/MA: X0110/MA: X1110), the second media address comprising: (MA: X0000/MA: X0100/MA: X0010/MA: X0110), which is not limited herein.

In the prior art, as shown in fig. 10, a code called Error Checking and Correcting (ECC) is set after each piece of data of the storage device, and the code is also called check bit. For checking and correcting data errors. Generally, one section of ECC check bit is set after each section of physical block address, and if some memory cells in the current storage device are subject to centralized failure, it needs to be considered that the length of data with some physical block addresses having errors is large. Accordingly, longer ECC check bits need to be designed.

In an alternative implementation manner, please refer to fig. 7, and fig. 7 is a schematic diagram of a mapping relationship provided in the embodiment of the present application. The first mapping relationship shown in fig. 7 is a first physical block address "PBA1", which corresponds to a first media address of "(1)/(2)/(3)/(4)", which is located in the same Die "Die 1". When the transmission concentration fails, the storage unit corresponding to the first medium address fails, and the error rate of the data stored in the "(1)/(2)/(3)/(4)" is high. Before the mapping relationship is changed, the media address corresponding to the physical block address "PBA2" is "(5)/(6)/(7)/(8)". To achieve failure dispersion, a second mapping relationship is generated from the first mapping relationship. The second mapping includes a first physical block address "PBA1", and a corresponding second media address "(1)/(6)/(3)/(8)". The media address corresponding to the physical block address "PBA2" is "(5)/(2)/(7)/(4)". By the method, the ECC check bit length required by the second mapping relation is halved compared with the ECC check bit length required by the first mapping relation. The media addresses are located in the same Die "Die 1".

In another optional implementation manner, the first physical block address in the first mapping relationship is "PBA1", and the first medium address corresponding to the first physical block address is "(1)/(2)/(3)/(4)". In the second mapping relationship generated according to the first mapping relationship, the second medium address corresponding to the first physical block address is "(1)/(5)/(3)/(4)".

In another alternative implementation, please refer to fig. 8, where fig. 8 is a schematic diagram of another mapping relationship provided in the embodiment of the present application. The first mapping relationship shown in fig. 8 is a first physical block address "PBA1" corresponding to a first media address of "(1)/(2)/(3)/(4)", the first media address being located in the same Die "Die 1". Before the mapping relationship is changed, the media address corresponding to the physical block address "PBA2" is "(5)/(6)/(7)/(8)", and the media address is located on the same Die "Die2". After a second mapping relation is generated according to the first mapping relation, a second media address corresponding to the first physical block address in the second mapping relation is "(1)/(6)/(3)/(8)", wherein the media address "(1)/(3)" is located on the die "die1", and the media address "(6)/(8)" is located on the die "die2".

Specifically, the second mapping relationship is stored in a buffer of the storage-level memory in a form of a mapping relationship list.

303. The data is stored using the second mapping relationship.

In this embodiment, after the storage device generates the second mapping relationship, the data is stored using the second mapping relationship. Specifically, after the storage device receives the data storage instruction, when the logical block address carried by the data storage instruction is LBA: X0b, the storage device determines, according to the second mapping relationship, a first physical block address (PBA 1) and a second medium address (MA: X000/MA: X100/MA: X010/MA: X110) corresponding to the logical block address. The storage device stores the related data in the storage unit corresponding to the second medium address.

In the embodiment of the application, a first mapping relationship is obtained first, where the first mapping relationship includes a first physical block address and a first media address, and the first media address is associated with the first physical block address; secondly, generating a second mapping relation according to the first mapping relation, wherein the second mapping relation comprises a first physical block address and a second medium address, the first physical block address is associated with the second medium address, and the second medium address is inconsistent with the first medium address; again, the data is stored using the second mapping relationship. When a centralized failure occurs in a storage unit corresponding to the first medium address, the check bit required by the first physical block address is longer, which results in increased data redundancy and reduced available storage space of the memory. And generating a second mapping relation according to the first mapping relation, wherein the medium address managed by the first physical block address in the second mapping relation is a second medium address, and the storage unit (the medium address corresponding to the first medium address) with concentrated failure is avoided. Therefore, when the second mapping relation is used for storing data, the length of the check bit required by the first physical block address can be effectively reduced, and the available storage space is increased.

The data storage method provided by the embodiment of the application can be applied to various different scenes, including: triggering the data storage method according to a Symbol Error Rate (SER) in the data storage and reading process of the storage device; and secondly, before the storage device leaves the factory, determining the optimal mapping relation storage data by the data storage method. The above-mentioned solution is described below with reference to the accompanying drawings.

In the process of storing and reading data of a storage device, triggering the data storage method according to a Symbol Error Rate (SER):

referring to fig. 4, fig. 4 is a schematic diagram of another embodiment of a data storage method according to an embodiment of the present application. The data storage method provided by the embodiment of the application comprises the following steps:

401. the first data is read and a first error rate is detected.

In this embodiment, the storage device reads first data according to an instruction of the host, and data stored at a first medium address is referred to as first data. The memory device corrects the first data using the ECC check bits and detects an error rate of the first data, which is referred to as a first error rate. Specifically, the first error rate may be a ratio of a length of the error data to a total length of the first data, for example: the error data length is 5 bits (bit), the total length of the first data is 100 bits, and the first error rate is 5/100=5%. The first error rate may also be an error data length, which is not limited herein.

In another optional implementation manner, in order to determine a failure condition of the current storage device, a user issues a first detection instruction to the storage device, and the storage device reads first data according to the first detection instruction and detects a first bit error rate. The storage device can detect whether the mapping relation corresponding to the data is in centralized failure or not by detecting the error rate of a certain data according to the first detection instruction. The storage device may also detect full disk data according to the first detection instruction. The storage device may further detect a blank medium address (including a mapping relationship of the medium addresses) according to the first detection instruction, specifically: first data is written to the medium address, and a first error rate is detected.

402. And when the first error rate is larger than or equal to a first threshold value, backing up the first data and the second data.

In this embodiment, when the first error rate is greater than or equal to the first threshold value, the first data and the second data are backed up, and the data stored in the second medium address is referred to as the second data. For example: the first threshold is 5%, and when the storage device detects that the first error rate is 5%, step 402 is entered, where the storage device backs up the first Data and the second Data in a Buffer (Data Buffer). Then, the storage device clears the data in the first medium address and the second medium address.

403. And acquiring a first mapping relation.

In this embodiment, after step 402, the process proceeds to step 403. Specifically, the method for obtaining the first mapping relationship is similar to the step 301, and is not described herein again.

404. And generating a second mapping relation according to the first mapping relation.

In this embodiment, a method for generating the second mapping relationship according to the first mapping relationship is similar to the foregoing step 302, and is not described herein again.

405. And generating a third mapping relation according to the first mapping relation.

In this embodiment, a third mapping relationship is generated according to the first mapping relationship, where the third mapping relationship includes a second physical block address, a first media address, and a third media address, the second physical block address is associated with the first media address, the second physical block address is associated with the third media address, the second physical block address is inconsistent with the first physical block address, and the third media address is inconsistent with the second media address. This third mapping relationship can be seen in table 4.

TABLE 4

For easy understanding, please refer to fig. 9, where fig. 9 is a schematic diagram of another mapping relationship provided in the embodiment of the present application. The first mapping relationship is: first physical block address LBA = X0b, first media address (MA: X000/MA: X001/MA: X010/MA: X011). In the buffer of the storage-level memory, the following mapping relationship is also stored: physical block address LBA = X1b, media address (MA: X000/MA: X101/MA: X110/MA: X111). In step 405, generating a third mapping relationship according to the first mapping relationship, including: second physical block address LBA = X1b, third media address (MA: X000/MA: X101/MA: X110/MA: X111).

406. And storing the data by using the second mapping relation and/or the third mapping relation.

In this embodiment, after step 405, the storage device generates the second mapping relationship and the third mapping relationship according to the first mapping relationship. The storage device can store first data (the first data is backed up in the buffer) by using a second mapping relation, and store second data (the second data is backed up in the buffer) by using a third mapping relation; alternatively, the storage device may store the second data using the second mapping relationship and store the first data using the third mapping relationship; or, the storage device may further store the first data and the second data using a second mapping relationship; alternatively, the storage device stores the first data and the second data using a third mapping relationship. The storage device may further store other data using the second mapping relationship and/or the third mapping relationship, which is not described herein again.

In the embodiment of the application, the first medium addresses with concentrated failure are distributed to the management of other physical block addresses, and the proportion of error medium addresses to total medium addresses in a certain physical block address is reduced. The check bit length required by the physical block address can be effectively reduced, and the available storage space is increased.

Referring to fig. 5, fig. 5 is a schematic diagram of another embodiment of a data storage method according to an embodiment of the present application. The data storage method provided by the embodiment of the application comprises the following steps:

501. the first data is read and a first error rate is detected.

In this embodiment, similar to the foregoing step 401, further description is omitted here.

502. And when the first error rate is larger than or equal to a first threshold value, backing up the first data and the second data.

In this embodiment, similar to the foregoing step 402, the description is omitted here.

503. And acquiring a first mapping relation.

In this embodiment, similar to the foregoing step 403, details are not repeated here.

504. And generating a second mapping relation according to the first mapping relation.

In this embodiment, similar to the step 404, the description is omitted here.

505. A second bit error rate is detected.

In this embodiment, after the second mapping relationship is generated according to the first mapping relationship in step 504, since there is a possibility that a centralized failure occurs in the storage unit corresponding to the second media address, before determining the mapping relationship used in storing data, it is necessary to detect the data stored in the second media address.

Specifically, the error rate of the second data stored in the second medium address is detected, and the error rate is referred to as a second error rate. In an optional implementation manner, before generating the second mapping relationship, second data stored in the second medium address needs to be backed up, and a bit error rate of the second data is detected in a process of reading the second data, where the bit error rate is also a bit error rate of the second medium address.

In another alternative implementation, after the second data is backed up, the data stored in the second medium address is first emptied. Secondly, the storage device uses the preset data to carry out error rate detection on the second medium address (corresponding storage unit) to obtain a second error rate.

506. And determining a mapping relation used when the data is stored according to the first error rate and the second error rate.

In this embodiment, the mapping relationship used when data is stored is determined according to the first error rate and the second error rate. Specifically, when the first error rate is greater than the second error rate, the data is stored by using the second mapping relation. And when the first error rate is less than or equal to the second error rate, the storage unit corresponding to the second medium address in the second mapping relation also has centralized failure. The storage device needs to store data using other mapping relationships, such as: the data is stored using a third mapping relationship, and the generation method of the third mapping relationship is similar to that in step 405, and is not described here again.

In this embodiment, after the storage device generates the second mapping relationship according to the first mapping relationship, a bit error rate (second bit error rate) of the second medium address in the second mapping relationship may be detected. And determining a mapping mode used when the data is stored according to the first error rate and the second error rate. The method ensures that the error rate in the mapping relation used by the storage device is lower, reduces the length of the check bit required by the physical block address, and increases the available storage space.

And (II) before the storage device leaves a factory, determining the better mapping relation storage data by the data storage method:

referring to fig. 6, fig. 6 is a schematic diagram illustrating another embodiment of a data storage method according to an embodiment of the present application. The data storage method provided by the embodiment of the application comprises the following steps:

601. and acquiring a first detection instruction.

In this embodiment, the storage device obtains the first detection instruction, and the storage device detects, according to the first detection instruction, bit error rates of medium addresses in the current mapping relationships, and determines, according to the bit error rates, a mapping relationship used when data is stored.

In an optional implementation manner, before the storage device leaves a factory, the storage device acquires the first detection instruction. First, the storage device writes third data to the first medium address according to the first detection command and the first mapping relationship. The third data is test data used for detecting the bit error rate, such as "000 · 000" or "111 · 111". Then, the storage device writes third data to the second medium address according to the first detection instruction and the second mapping relation.

In another alternative implementation manner, during the process of using the storage device by a user, the medium address with a higher error rate may be disabled through the first detection instruction, so as to ensure the security of data. Specifically, first, the storage device backs up data in a first media address and data in a second media address according to a first detection instruction. Then, the storage device writes third data to the first medium address and the second medium address, respectively.

In another alternative implementation, the first detection instruction may be an instruction that is automatically triggered when the storage device is in an idle state. Or may be an instruction that is automatically triggered periodically by the storage device, which is not limited herein.

602. And detecting a third error rate.

In this embodiment, the third error rate is an error rate of the third data in the first medium address.

603. And detecting the fourth bit error rate.

In this embodiment, the fourth error rate is an error rate of the third data in the second medium address.

604. And determining a mapping relation used when the data is stored according to the third error rate and the fourth error rate.

In this embodiment, according to the third error rate and the fourth error rate,

and determining a mapping relation used when the data is stored according to the third error rate and the fourth error rate. In an optional implementation manner, when the third error rate is greater than the fourth error rate, the data is stored using the first mapping relationship. And when the third error rate is less than or equal to the fourth error rate, storing the data by using a second mapping relation. In another optional implementation manner, when the third bit error rate is greater than the first threshold value, storing the data by using a second mapping relationship; and when the fourth error rate is greater than the first threshold value, storing the data by using the first mapping relation.

The scheme provided by the embodiment of the application is mainly introduced in the aspect of a method. It is understood that the storage device includes hardware structures and/or software modules for performing the functions in order to realize the functions. Those of skill in the art will readily appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed in hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the storage device may be divided into the functional modules according to the method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one storage module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and another division manner may be available in actual implementation.

Referring to fig. 11, please refer to fig. 11, wherein fig. 11 is a schematic diagram of an embodiment of a storage device according to an embodiment of the present application. The storage apparatus 1100 includes:

a processing module 1101, configured to detect an error rate when reading current data;

the processing module 1101 is further configured to determine, according to the error rate, a mapping relationship used for storing data to the storage class memory, where the mapping relationship includes an association relationship between a physical block address and a media address;

the storage module 1102 is configured to store data according to the mapping relationship.

In some embodiments of the present application,

the processing module 1101 is specifically configured to determine a second mapping relationship as the mapping relationship when the bit error rate is greater than a preset threshold, where in the second mapping relationship and a first mapping relationship, an association relationship between a physical block address and a medium address is different, and the first mapping relationship is that, when the current data is read, the storage class memory performs data storage based on the first mapping relationship.

In some embodiments of the present application,

the processing module 1101 is further configured to determine the first mapping relationship as the mapping relationship when the bit error rate is less than or equal to the preset threshold.

An obtaining module 1103, configured to obtain a first mapping relationship, where the first mapping relationship includes a first physical block address and a first media address, and the first physical block address is associated with the first media address;

the processing module 1101 is configured to generate a second mapping relationship according to the first mapping relationship, where the second mapping relationship includes a first physical block address and a second media address, the first physical block address is associated with the second media address, and the second media address is inconsistent with the first media address;

the processing module 1101 is further configured to select a second mapping relationship.

In some embodiments of the present application, the storage module 1102 is configured to store the data using the second mapping relationship if the error rate of the data in the second medium address is smaller than the error rate of the data in the first medium address.

In some embodiments of the application, the processing module 1101 is further configured to generate a third mapping relationship according to the first mapping relationship, where the third mapping relationship includes a second physical block address and a third media address, the second physical block address is associated with the third media address, the second physical block address is not consistent with the first physical block address, the third media address is not consistent with the second media address, and the third media address includes a portion of the first media address.

In some embodiments of the present application,

the first media address and the second media address are located on the same die, or the first media address and the second media address are located on different dies.

In some embodiments of the present application, the storage device 1100 further comprises:

the processing module 1101 is further configured to detect to obtain a first error rate when reading the first data, where a storage area of the first data is a first medium address;

the storage module 1102 is further configured to backup the first data and the second data when the first error rate is greater than or equal to a first threshold, where a storage area of the second data is a second medium address;

the storage module 1102 is further configured to clear data stored in the first medium address and the second medium address.

the storage module 1102 is further configured to store the first data using the second mapping relationship, or store the first data using the third mapping relationship.

the processing module 1101 is further configured to detect a second error rate, where the second error rate is an error rate of second data stored in the second medium address;

the processing module 1101 is further configured to determine a mapping relation used when the data is stored according to the first error rate and the second error rate.

In some embodiments of the present application,

the storage module 1102 is specifically configured to store data using a second mapping relationship when the first error rate is greater than the second error rate;

the storing module 1102 is specifically configured to store the data using the third mapping relationship when the first error rate is less than or equal to the second error rate.

In some embodiments of the present application,

the storage module 1102 is specifically configured to store the first data in the backup to the second media address according to the second mapping relationship.

In some embodiments of the present application,

the storage module 1102 is specifically configured to store the second data in the backup to the first media address and the third media address according to the third mapping relationship.

In some embodiments of the present application,

the obtaining module 1103 is further configured to obtain a first detection instruction, where the first detection instruction is used to trigger detection of the bit error rate of the current data, and the first detection instruction is an instruction that is automatically triggered when the first detection instruction is in an idle state, or the first detection instruction is an instruction that is actively triggered by a user.

the storage module 1102 is further configured to write third data to the first medium address according to the first detection instruction and the first mapping relationship;

the storage module 1102 is further configured to write third data to the second medium address according to the first detection instruction and the second mapping relationship;

the processing module 1101 is further configured to detect a third error rate, where the third error rate is an error rate of third data in the first medium address;

the processing module 1101 is further configured to detect a fourth error rate, where the fourth error rate is an error rate of third data in the second medium address;

the processing module 1101 is further configured to determine a mapping relationship used when the data is stored according to the third error rate and the fourth error rate.

In some embodiments of the present application, the storage module 1102 is specifically configured to store the data using a first mapping relationship when the third error rate is greater than the fourth error rate;

the storing module 1102 is specifically configured to store the data using the second mapping relationship when the third error rate is less than or equal to the fourth error rate.

The storage device in the embodiment of the present application is described above from the perspective of the modular functional entity, and the storage device in the embodiment of the present application is described below from the perspective of hardware processing. Fig. 12 is a schematic diagram of a hardware structure of a computer device 1200 in the embodiment of the present application. As shown in fig. 12, the computer device 1200 may include:

the computer device 1200 includes at least one processor 1201, communication lines 1207, memory 1203, and at least one communication interface 1204.

The processor 1201 may be a general processing unit (CPU), a microprocessor, an application-specific integrated circuit (server IC), or one or more ICs for controlling the execution of programs in accordance with the present invention.

The communication link 1207 may include a path for communicating information between the aforementioned components.

The communication interface 1204 may be any device, such as a transceiver, for communicating with other devices or a communication network, such as ethernet, etc.

The memory 1203 may be a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, and may be separate and coupled to the processor via a communication link 1207. The memory may also be integral to the processor.

The memory 1203 is used for storing computer-executable instructions for implementing the present invention, and is controlled by the processor 1201 to execute the instructions. The processor 1201 is configured to execute computer-executable instructions stored in the memory 1203, thereby implementing the data storage method provided in the above-described embodiment of the present application.

Optionally, the computer-executable instructions in this embodiment may also be referred to as application program codes, which is not specifically limited in this embodiment.

In particular implementations, computer device 1200 may include multiple processors, such as processor 1201 and processor 1202 in fig. 12, for one embodiment. Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, and/or processing cores that process data (e.g., computer program instructions).

In particular implementations, computer device 1200 may also include an output 1205 and an input 1206, as one embodiment. The output device 1205 is in communication with the processor 1201 and may display information in a variety of ways. The input device 1206 is in communication with the processor 1201 and may receive user input in a variety of ways. For example, the input device 1206 may be a mouse, a touch screen device, a sensing device, or the like.

When the computer device 1200 is a terminal device, in the computer device 1200, the processor 1202 may include one or more processing units, such as: the processor 1202 may include an Application Processor (AP), a modem processor, a Graphics Processor (GPU), an Image Signal Processor (ISP), a controller, a memory, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), among others. The different processing units may be separate devices or may be integrated into one or more processors.

The terminal device may be a Mobile Station (MS), a subscriber module (subscriber unit), a cellular phone (cellular phone), a smart phone (smart phone), a wireless data card, a Personal Digital Assistant (PDA) computer, a tablet computer, a wireless modem (modem), a handheld device (handset), a laptop computer (laptop computer), a Machine Type Communication (MTC) terminal device, and the like.

The controller can be, among other things, a neural center and a command center of the computer device 1200. The controller can generate an operation control signal according to the instruction operation code and the timing signal to complete the control of instruction fetching and instruction execution.

A memory may also be provided within the processor 1202 for storing instructions and data. In some embodiments, the memory in the processor 1202 is a cache memory. The memory may hold instructions or data that have just been used or recycled by the processor 1202. If the processor 1202 needs to use the instruction or data again, it can be called directly from the memory. Avoiding repeated accesses reduces the latency of the processor 1202, thereby increasing the efficiency of the system.

In some embodiments, the processor 1202 may include one or more interfaces. The interface may include an integrated circuit (I1C) interface, an integrated circuit built-in audio (I1S) interface, a Pulse Code Modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose-input/output (GPIO) interface, a Subscriber Identity Module (SIM) interface, and/or a Universal Serial Bus (USB) interface, etc.

It should be understood that the connection relationship between the modules illustrated in the embodiment of the present application is only an exemplary illustration, and does not limit the structure of the computer device 1200. In other embodiments of the present application, the computer device 1200 may also adopt different interface connection manners or a combination of multiple interface connection manners in the above embodiments.

The embodiment of the application also provides a storage device, which comprises a processor, a buffer and a memory, wherein the memory comprises one or more memory units; wherein the processor is configured to perform the steps performed by the storage device in the method as described in the embodiments of fig. 3 to 10, and to generate instructions; the memory is configured to store data according to the instructions. In this embodiment, the storage device may be a non-embedded storage device or an embedded storage device, and it should be understood that a specific expression form of the storage device should be flexibly set according to an actual situation, and is not limited herein.

Also provided in an embodiment of the present application is a computer program product containing storage block management instructions, which when run on a computer, causes the computer to perform the steps performed by the storage device in the method as described in the embodiments of fig. 2 to 8.

Also provided in the embodiments of the present application is a computer-readable storage medium, which stores instructions for processing a storage block, and when the instructions are executed on a computer, the computer is caused to execute the steps performed by the storage device in the method described in the embodiments shown in fig. 2 to 8.

Embodiments of the present application further provide a chip system, which includes a processor, and is configured to enable a network device to implement the functions involved in the foregoing aspects, for example, sending or processing data and/or information involved in the foregoing methods. In one possible design, the system-on-chip further includes a memory that stores program instructions and data necessary for the network device. The chip system may be formed by a chip, or may include a chip and other discrete devices.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the invention are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). A computer-readable storage medium may be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium, or a semiconductor medium such as a Solid State Disk (SSD), etc.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a logical division, and other divisions may be realized in practice, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.

Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

Claims

A data storage method is applied to a storage class memory and comprises the following steps:

detecting the error rate when the current data is read;

determining a mapping relation for storing data to the storage-level memory according to the error rate, wherein the mapping relation comprises an association relation between a physical block address and a medium address;

and storing data according to the mapping relation.
The method of claim 1, wherein determining a mapping for storing data to the storage class memory based on the bit error rate comprises:

when the error rate is larger than a preset threshold, determining a second mapping relation as the mapping relation, wherein under the second mapping relation and the first mapping relation, the association relation between the physical block address and the medium address is different,

the first mapping relationship is that when the current data is read, the storage-class memory stores data based on the first mapping relationship.
The method of claim 2, wherein determining a mapping for storing data to the storage class memory according to the bit error rate further comprises:

and when the error rate is less than or equal to the preset threshold, determining the first mapping relation as the mapping relation.
The method according to any one of claims 2 to 3, wherein when the bit error rate is greater than the preset threshold, determining the second mapping relationship as the mapping relationship comprises:

acquiring the first mapping relation, wherein the first mapping relation comprises a first physical block address and a first medium address, and the first physical block address is associated with the first medium address;

and generating the second mapping relation according to the first mapping relation, wherein the second mapping relation comprises the first physical block address and a second medium address, the first physical block address is associated with the second medium address, and the second medium address is inconsistent with the first medium address.
The method of claim 4, further comprising:

generating a third mapping relation according to the first mapping relation, wherein the third mapping relation comprises a second physical block address and a third medium address, the second physical block address is associated with the third medium address, the second physical block address is inconsistent with the first physical block address, the third medium address is inconsistent with the second medium address, and the third medium address comprises a part of the first medium address;

storing data using the third mapping relationship.
The method of any of claims 4 to 5, wherein the first media address is located on the same die as the second media address or the first media address is located on a different die than the second media address.
The method according to any one of claims 3 to 6, wherein detecting the bit error rate at the current data read comprises:

when first data is read, detecting to obtain a first error rate, wherein a storage area of the first data is the first medium address;

when the first error rate is greater than or equal to a first threshold value, backing up the first data and second data, wherein a storage area of the second data is the second medium address;

and emptying the data stored in the first medium address and the second medium address.
The method of claim 7, wherein after flushing the data stored in the first media address and the second media address, the method further comprises:

storing the first data using the second mapping relationship, or,

storing the first data using the third mapping relationship.
The method of claim 7, wherein after backing up the first data and the second data, the method further comprises:

detecting a second error rate, wherein the second error rate is an error rate of the second data stored in the second medium address;

and determining the mapping relation used when the data is stored according to the first error rate and the second error rate.
The method of claim 9, wherein determining the mapping relationship for use in storing data based on the first error rate and the second error rate comprises:

when the first error rate is larger than the second error rate, storing data by using the second mapping relation;

and when the first error rate is less than or equal to the second error rate, storing data by using the third mapping relation.
The method according to any one of claims 1 to 10, wherein the bit error rate at the current data read is detected, the method further comprising:

acquiring a first detection instruction, wherein the first detection instruction is used for triggering and detecting the error rate of the current data,

the first detection instruction is an instruction automatically triggered in an idle state,

or the first detection instruction is an instruction actively triggered by a user.
The method of claim 11, wherein after generating the second mapping relationship from the first mapping relationship, the method further comprises:

writing third data into the first medium address according to the first detection instruction and the first mapping relation;

writing the third data into the second medium address according to the first detection instruction and the second mapping relation;

detecting a third error rate, wherein the third error rate is the error rate of the third data in the first medium address;

detecting a fourth error rate, wherein the fourth error rate is the error rate of the third data in the second medium address;

and determining the mapping relation used when the data is stored according to the third error rate and the fourth error rate.
The method of claim 12, wherein determining the mapping relationship used when storing data according to the fourth error rate and the fifth error rate comprises:

when the third error rate is larger than the fourth error rate, storing data by using the first mapping relation;

and when the third error rate is less than or equal to the fourth error rate, storing data by using the second mapping relation.
A memory device, comprising:

the processor is used for detecting the error rate when the current data is read;

the processor is further configured to determine a mapping relationship for storing data to the storage class memory according to the bit error rate, where the mapping relationship includes an association relationship between a physical block address and a media address;

and the storage array is used for storing data according to the mapping relation.
The storage device of claim 14,

the processor is specifically configured to determine a second mapping relationship as the mapping relationship when the bit error rate is greater than a preset threshold, where, under the second mapping relationship and a first mapping relationship, an association relationship between a physical block address and a media address is different, and the first mapping relationship is that, when the current data is read, the storage-level memory stores data based on the first mapping relationship.
The storage device of claim 15,

the processor is further configured to determine the first mapping relationship as the mapping relationship when the bit error rate is less than or equal to the preset threshold.
The storage device of claim 16,

the processor is further configured to obtain a first mapping relationship, where the first mapping relationship includes a first physical block address and a first media address, and the first physical block address is associated with the first media address;

the processor is further configured to generate a second mapping relationship according to the first mapping relationship, where the second mapping relationship includes the first physical block address and a second media address, the first physical block address is associated with the second media address, and the second media address is inconsistent with the first media address.
The storage device of claim 17,

the processor is further configured to generate a third mapping relationship according to the first mapping relationship, where the third mapping relationship includes a second physical block address and the third media address, the second physical block address is associated with the third media address, the second physical block address is inconsistent with the first physical block address, the third media address is inconsistent with the second media address, and the third media address includes a part of the first media address;

the storage array is further configured to store data using the third mapping relationship.
The memory device according to any one of claims 16 to 18, wherein the first media address is located on the same die as the second media address or the first media address is located on a different die than the second media address.
The storage device of any one of claims 16 to 19,

the processor is further configured to detect to obtain a first error rate when reading first data, where a storage area of the first data is the first medium address;

the storage array is further configured to backup the first data and the second data when the first error rate is greater than or equal to a first threshold value, where a storage area of the second data is the second medium address;

the storage array is further used for emptying the data stored in the first medium address and the second medium address.
The storage device of claim 20,

the storage array is further configured to store the first data using the second mapping relationship, or store the first data using the third mapping relationship.
The storage device of claim 20,

the processor is further configured to detect a second error rate, where the second error rate is an error rate of the second data stored in the second medium address;

the processor is further configured to determine the mapping relationship used when data is stored according to the first error rate and the second error rate.
The storage device of claim 22,

the storage array is specifically configured to store data using the second mapping relationship when the first error rate is greater than the second error rate;

the storage array is specifically configured to store data using the third mapping relationship when the first error rate is less than or equal to the second error rate.
The storage device of any one of claims 14 to 23,

the processor is further configured to obtain a first detection instruction, where the first detection instruction is used to trigger detection of the bit error rate of the current data, and the first detection instruction is an instruction that is automatically triggered when the first detection instruction is in an idle state, or the first detection instruction is an instruction that is actively triggered by a user.
The storage device of claim 24,

the storage array is further configured to write third data to the first medium address according to the first detection instruction and the first mapping relationship;

the storage array is further configured to write the third data to the second medium address according to the first detection instruction and the second mapping relationship;

the processor is further configured to detect a third error rate, where the third error rate is an error rate of the third data in the first medium address;

the processor is further configured to detect a fourth bit error rate, where the fourth bit error rate is a bit error rate of the third data in the second medium address;

the processor is further configured to determine the mapping relationship used when data is stored according to the third error rate and the fourth error rate.
The storage device of claim 25, comprising:

the storage array is specifically configured to store data using the first mapping relationship when the third error rate is greater than the fourth error rate;

the storage array is specifically configured to store data using the second mapping relationship when the third error rate is less than or equal to the fourth error rate.
A memory device, comprising a processor, a buffer, and a memory, wherein the memory comprises one or more memory units, and wherein the buffer stores program instructions;

wherein the processor is configured to store data to the memory in accordance with the program instructions to perform the method of any one of claims 1 to 13.