WO2021190242A1 - 残影测试方法和残影测试装置 - Google Patents

残影测试方法和残影测试装置 Download PDF

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WO2021190242A1
WO2021190242A1 PCT/CN2021/078054 CN2021078054W WO2021190242A1 WO 2021190242 A1 WO2021190242 A1 WO 2021190242A1 CN 2021078054 W CN2021078054 W CN 2021078054W WO 2021190242 A1 WO2021190242 A1 WO 2021190242A1
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Prior art keywords
preset
voltage
driving transistor
correspondence
time
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PCT/CN2021/078054
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English (en)
French (fr)
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赵东方
杜哲
郭双
刘勋
郭子栋
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昆山国显光电有限公司
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Publication of WO2021190242A1 publication Critical patent/WO2021190242A1/zh
Priority to US17/692,052 priority Critical patent/US11893915B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/046—Dealing with screen burn-in prevention or compensation of the effects thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present disclosure relates to display technology, for example, to an afterimage test method and an afterimage test device.
  • the display panel needs to be subjected to an afterimage test before leaving the factory.
  • the display panel has the problems of long tape-out period and high cost during the afterimage test.
  • the present disclosure provides a residual image test method and a residual image test device, so as to reduce the tape-out period and reduce the cost.
  • a residual image test method comprising: obtaining the preset time within a preset time after the voltage of a preset driving transistor in an array substrate is switched from a first preset voltage to a second preset voltage The first corresponding relationship between the source and drain current of the driving transistor and time; the preset time is obtained after the voltage of the preset driving transistor is switched from the third preset voltage to the second preset voltage A second corresponding relationship between the source and drain current of the driving transistor and time; obtaining a first residual image test curve of the array substrate according to the first corresponding relationship, the second corresponding relationship, and the residual image evaluation formula, wherein the The first residual image test curve is the corresponding relationship between time and the residual image evaluation value.
  • An afterimage testing device which includes: a first acquisition module configured to switch the voltage of the preset driving transistor in the array substrate from the first preset voltage to the second preset voltage The first corresponding relationship between the source and drain current of the preset driving transistor and time is acquired within the preset time; the second acquiring module is configured to switch the voltage of the driving transistor from the third preset voltage to the first After the second preset voltage, the second corresponding relationship between the source and drain current of the preset driving transistor and the time is acquired within the preset time; the third acquiring module is configured to obtain the second corresponding relationship according to the first corresponding relationship and the second corresponding relationship.
  • the relationship and the afterimage evaluation formula are used to obtain a first image retention test curve of the array substrate, wherein the first image retention test curve is a corresponding relationship between time and an image retention evaluation value.
  • the afterimage test method adopted includes: obtaining the preset drive within a preset time after the voltage of the preset drive transistor in the array substrate is switched from the first preset voltage to the second preset voltage The first corresponding relationship between the source and drain current of the transistor and the time; in the preset time after the voltage of the preset drive transistor is switched from the third preset voltage to the second preset voltage, the source and drain current of the preset drive transistor and The second corresponding relationship of time; obtaining the first residual image test curve of the array substrate according to the first corresponding relationship, the second corresponding relationship and the residual image evaluation formula.
  • the first corresponding relationship, the second preset relationship, and the residual image evaluation formula can be combined to directly obtain the first residual image test curve corresponding to the array substrate, without the need to evaporate the array substrate with a luminescent material and then obtain it through an optical device Corresponding to the first residual image test curve of the display panel, the tape-out period is reduced, and the waste of evaporation and module materials is avoided, and the cost is reduced.
  • FIG. 1 is a flow chart of a method for image retention testing according to an embodiment.
  • FIG. 2 is a graph of the corresponding relationship between time and source/drain current according to an embodiment.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment.
  • FIG. 4 is a result diagram of a first image retention test curve provided by an embodiment.
  • FIG. 5 is another curve diagram of the corresponding relationship between time and source/drain current provided by an embodiment.
  • FIG. 6 is a schematic structural diagram of a residual image testing device provided by an embodiment.
  • the afterimage test has the problem of long tape-out period and high cost.
  • the reason for this problem is that the afterimage test needs to be tested at the module stage, that is, the luminescent material needs to be deposited on the array substrate and After packaging, the optical characteristics of the screen are tested by optical equipment to evaluate the residual image of the display panel. Therefore, there is a problem of a long tape-out period and a waste of evaporation and module materials.
  • Fig. 1 is a flow chart of an image retention test method provided by an embodiment. Referring to Fig. 1, the image retention test method includes:
  • Step S110 in a preset time after the voltage of the preset driving transistor in the array substrate is switched from the first preset voltage to the second preset voltage, a first corresponding relationship between the source and drain current of the preset driving transistor and the time is acquired .
  • the array substrate may be an array substrate corresponding to a display panel such as an Organic Light-Emitting Diode (OLED) display panel or a liquid crystal display panel.
  • the array substrate may include a plurality of driving transistors.
  • the array substrate includes a plurality of pixel driving circuits, and each pixel driving circuit includes a driving transistor.
  • the source and drain currents current between the source and the drain generated by the transistors are different, that is, the driving currents of the sub-pixels are different at this time, and the light emission of the sub-pixels corresponds to different gray levels, that is, the display panel
  • the gray scale of the light emission is related to the source and drain current of the driving transistor.
  • the preset driving transistor can be any driving transistor in the array substrate.
  • the first preset voltage can be set to the first gray scale condition, The voltage corresponding to the simulated light emission of the array substrate; the second preset voltage is set to the voltage corresponding to the simulated light emission of the array substrate under the second gray-scale condition; the third preset voltage is set to the third gray-scale condition, the array substrate The voltage corresponding to the simulated light emission; wherein, the second gray scale is between the first gray scale and the third gray scale, and the array substrate is tested when the first preset voltage and the third preset voltage are switched to the second preset voltage The corresponding relationship between the current and the time is substituted into the residual image evaluation formula to obtain the residual image test curve of the display panel made of the array substrate.
  • the first preset voltage, the second preset voltage and the third preset voltage may all include the gate voltage, the source voltage and the drain voltage of the driving transistor, and the voltage of the preset driving transistor is switched from the first preset voltage to the first preset voltage. 2.
  • the voltage is preset, only the gate voltage can be switched, while the corresponding source voltage and drain voltage remain unchanged.
  • FIG. 2 is a graph of the correspondence relationship between time and source-drain current provided by an embodiment.
  • the first correspondence relationship can be understood as when the voltage of the preset driving transistor is switched from the first preset voltage to the second preset voltage. Set the corresponding relationship between the voltage and the source and drain current within the preset time.
  • the first gray scale can be 255 gray scales
  • the second gray scale can be 48 gray scales
  • the third gray scale can be 0 gray scales.
  • the second gray level can also be 128 gray levels
  • the preset time can be determined according to the display panel corresponding to the array substrate. For example, it can correspond to the time from the display panel gray level switch to the disappearance of the display panel afterimage, as shown in Figure 2.
  • the first correspondence curve 101 indicates that the preset driving transistor first works at the first preset voltage, switches from the first preset voltage to the second preset voltage at time t0, and always works at the second preset voltage.
  • the curve in the first relationship curve 101 from time t0 to a preset time may correspond to the first corresponding relationship.
  • Step S120 Acquire a second correspondence between the source and drain current of the preset drive transistor and the time within the preset time when the voltage of the preset drive transistor is switched from the third preset voltage to the second preset voltage.
  • the second correspondence curve 102 indicates that the preset driving transistor first works at the third preset voltage, switches from the third preset voltage to the second preset voltage at time t0, and always works at the second preset voltage. Under preset voltage.
  • the curve in the second relationship curve 102 from time t0 to the preset time may correspond to the second corresponding relationship.
  • Step S130 Obtain a first image retention test curve of the array substrate according to the first correspondence relationship, the second correspondence relationship and the image retention evaluation formula.
  • the first image retention test curve corresponding to the array substrate can be directly obtained by combining the image retention evaluation formula, without the need to vaporize the array substrate with luminescent material before passing
  • the optical device obtains the first residual image test curve of the corresponding display panel, which reduces the tape-out period, avoids the waste of evaporation and module materials, and reduces the cost.
  • the afterimage test method adopted includes: obtaining the preset driving transistor within a preset time when the voltage of the preset driving transistor in the array substrate is switched from the first preset voltage to the second preset voltage
  • the first corresponding relationship between the source and drain current and the time; in the preset time when the voltage of the preset drive transistor is switched from the third preset voltage to the second preset voltage, the source and drain current of the preset drive transistor and the time are obtained
  • the second correspondence relationship obtaining the first image retention test curve of the array substrate according to the first correspondence relationship, the second correspondence relationship and the image retention evaluation formula.
  • the first corresponding relationship, the second preset relationship, and the residual image evaluation formula can be combined to directly obtain the first residual image test curve corresponding to the array substrate, without the need to evaporate the array substrate with a luminescent material and then obtain it through an optical device Corresponding to the first residual image test curve of the display panel, the tape-out period is reduced, and the waste of evaporation and module materials is avoided, and the cost is reduced.
  • the second correspondence relationship may be acquired first, and then the first correspondence relationship may be acquired, that is, step S120 is performed first, and then step S110 is performed, which is not limited in this embodiment.
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment.
  • the preset driving transistor is located in the test group (Test Group, TEG) of electrical thin film transistors in the non-active area (NAA) ⁇ drive transistor.
  • TEG Test Group
  • NAA non-active area
  • the array substrate may include a display area AA and a non-display area NAA.
  • a test group TEG can be set in the non-display area NAA.
  • the test group includes multiple transistors, and the multiple transistors in the test group correspond to multiple transistors in the display area. If the test group includes driving transistors corresponding to the driving transistors in the display area, the parameters of the two driving transistors are the same, that is, the characteristics of the driving transistors in the test group are the same as those of the driving transistors in the display area. Obtaining the first corresponding relationship and the second corresponding relationship of the driving transistors in the test group through the test is equivalent to obtaining the first corresponding relationship and the second corresponding relationship of the driving transistors in the display area.
  • the gate, drain, and source of the driving transistor in the test group all have leads, the first preset voltage, the second preset voltage, or the third preset voltage can be easily applied to the driving transistor, and the display area
  • the gate, source, and drain of the driving transistor do not have external leads, and it is more difficult to apply the first preset voltage, the second preset voltage, or the third preset voltage; that is, by setting the preset driving transistor to be located at
  • the driving transistors in the test group (TEG) of electrical thin film transistors in the non-display area NAA can greatly reduce the difficulty of implementing the afterimage test method.
  • the afterimage evaluation formula is:
  • I(t) JND is the evaluation value of the afterimage of the array substrate at time t after the voltage of the preset drive transistor is switched;
  • I(t) A is the voltage of the preset drive transistor switched from the first preset voltage to the second At time t after the preset voltage, the source and drain currents of the driving transistor are preset;
  • I(t) B is the time t after the voltage of the preset driving transistor is switched from the third preset voltage to the second preset voltage, preset
  • I0 A is the source and drain current of the preset driving transistor at a first preset voltage;
  • I0 B is the source and drain current of the preset driving transistor at a third preset voltage.
  • FIG. 4 is a result diagram of a first image retention test curve provided by an embodiment.
  • the actual curve 202 represents the image retention evaluation value calculated by the preset driving transistor according to the measured source and drain current and the above image retention evaluation formula.
  • Fitting curve 201 represents the curve obtained after fitting the actual curve 202. As can be seen from Figure 4, the fitted curve is close to the actual afterimage curve of the display panel, but is more in form than the actual afterimage curve.
  • the first image retention test curve obtained by this embodiment has a linear relationship with the first image retention test curve obtained by testing the display panel with an optical device, so it only needs to pass through the array substrate
  • the test group TEG in the non-display area NAA performs the simulation afterimage test to obtain the afterimage test curve reflecting the display panel made of the array substrate. There is no need to evaporate the luminescent material on the array substrate, which reduces the test cycle while avoiding The waste of materials.
  • the afterimage test method further includes: obtaining the source/drain current and time of the preset driving transistor within a preset time after the voltage of the preset driving transistor in the array substrate is switched from the first preset voltage to the fourth preset voltage A third correspondence relationship; obtaining a fourth correspondence relationship between the source and drain current of the preset drive transistor and time within a preset time after the voltage of the preset drive transistor is switched from the third preset voltage to the fourth preset voltage; according to The third correspondence, the fourth correspondence and the afterimage evaluation formula are used to obtain the second afterimage test curve of the array substrate.
  • the second afterimage test curve is the corresponding relationship between time and the afterimage evaluation value; according to the first afterimage test curve and the second image retention test curve
  • the second residual image test curve acquires the fitted residual image test curve of the array substrate.
  • the fourth preset voltage is the voltage corresponding to the simulated light emission of the array substrate under the condition of the fourth gray scale, the fourth gray scale is between the first gray scale and the third gray scale, and the fourth gray scale is between the second gray scale and the second gray scale.
  • the fourth gray scale may be 128 gray scales.
  • I(t) A can represent the source and drain current of the preset driving transistor at the t time after the voltage of the preset driving transistor is switched from the first preset voltage to the fourth preset voltage
  • I(t) B can represent the source and drain current of the preset drive transistor at time t after the voltage of the preset drive transistor is switched from the third preset voltage to the fourth preset voltage; due to the first residual image test curve and the first The shapes of the two residual image test curves are similar.
  • the third residual image test curve of the array substrate can be fitted, for example, at any time t, the third residual image test
  • the afterimage evaluation value corresponding to the curve is the average of the afterimage evaluation value corresponding to the first afterimage test curve at the time t and the average afterimage evaluation value corresponding to the second afterimage test curve at the time t; the third afterimage test The curve is used as the residual image test curve of the array substrate, which can reduce the error in the test process, that is, the accuracy of the third residual image test curve is higher.
  • the method further includes: performing a stability test on the preset driving transistor, and/or performing a T-Aging process on the preset driving transistor.
  • the stability test (Id-Vg sweep) of the preset drive transistor can be performed first to determine the stability of the preset drive transistor. If the stability is good, it indicates that the performance of the preset drive transistor is better. A residual image test curve is more accurate. If the change of I(t) JND with time is smaller, it indicates that the residual image of the display panel corresponding to the array substrate is lighter. A T-Aging process can also be performed on the preset drive transistor to improve the stability of the drive transistor.
  • the first preset voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage are obtained through circuit simulation.
  • the voltage of the preset driving transistor at the first gray level, the second gray level, the third gray level, and the fourth gray level corresponding to the display panel made of the array substrate can be obtained through circuit simulation, that is, the first preset Set the voltage, the second preset voltage, the third preset voltage, and the fourth preset voltage to facilitate subsequent application of the first preset voltage, the second preset voltage, the third preset voltage, and the preset driving transistor to the preset driving transistors.
  • the fourth preset voltage is used to obtain the first correspondence, the second correspondence, the third correspondence, and the fourth correspondence.
  • the method further includes: adjusting the first preset voltage so that the source-drain current of the preset driving transistor is constant at the first preset voltage Is the first current value; the third preset voltage is adjusted so that the source-drain current of the preset driving transistor under the third preset voltage is constant at the second current value.
  • the first current value may be the actual current value of the driving transistor when the display panel made of the array substrate corresponding to the array substrate emits light in the first gray scale.
  • the first current Corresponds to 40 nanoamperes.
  • the third gray scale is 0 gray scale
  • the second current corresponds to 0 amperes.
  • the first current and the second current respectively correspond to the array substrate. Source and drain current in grayscale. This configuration can make the working state of the preset driving transistor during the test closer to the actual working state, and the obtained first afterimage test curve is closer to the actual afterimage curve of the display panel corresponding to the array substrate.
  • the preset time can be greater than or equal to 60 seconds.
  • the preset time is too short, after the voltage of the preset drive transistor is switched, the current of the preset drive transistor does not work at a constant value, and the obtained first residual image test curve is not complete enough to fully evaluate the corresponding array substrate
  • the afterimage performance of the display panel By setting the preset time to be greater than or equal to 60 seconds, a complete first image retention test curve can be obtained, and the image retention performance of the display panel corresponding to the array substrate can be effectively evaluated.
  • FIG. 5 is another graph of the corresponding relationship between time and source and drain current provided by an embodiment.
  • the driving transistors in the array substrate test group can be T- Aging process to improve the stability of the drive transistor; then the voltage of the drive transistor is applied as a second preset voltage, that is, warm-up (Warm-up), for example, the second preset voltage is applied for 50 seconds to test the drive transistor’s
  • the value of the source-drain current at multiple moments (the tA-tB segment of the first correspondence curve 101 in FIG.
  • the voltage of the driving transistor is switched from the second preset voltage to the first preset voltage for a period of time Time (such as 5 minutes (minutes, min)-10min), that is, the stress process, and test the value of the source and drain current of the driving transistor at multiple moments.
  • the stable value of the source and drain current is I0 A ( Figure 5)
  • the voltage of the driving transistor is switched from the first preset voltage to the second preset voltage, and for a preset time, to obtain the complete correspondence between source and drain current and time ,
  • the corresponding relationship between time and source-drain current is the first corresponding relationship (the first corresponding relationship curve 101 in FIG. 5 shows the curve at time t0 and thereafter).
  • the driving transistors in the array substrate test group may be subjected to a T-Aging process to improve the stability of the driving transistor; then the voltage of the driving transistor is applied as the second preset voltage, that is, Warm-up, for example, apply the second preset voltage for 50 seconds to test the value of the source and drain current of the driving transistor at multiple times (the tA-tB section of the second correspondence curve 102 in FIG.
  • the voltage is switched from the second preset voltage to the third preset voltage and lasts for a period of time (such as 5min-10min), that is, the stress process, and the value of the source and drain current of the driving transistor at multiple times is tested, and the source and drain current is stable
  • the value is I0 B (the tB-t0 segment of the second correspondence curve 102 in FIG. 5); then the voltage of the driving transistor is switched from the third preset voltage to the second preset voltage, and continues for a preset time to obtain
  • the complete correspondence between the source-drain current and the time, where the correspondence between the time and the source-drain current within the preset time is the second correspondence (the second correspondence curve 102 in FIG. 5 shows the time t0 and subsequent curves ).
  • the first residual image test curve of the array substrate is obtained according to the first correspondence relationship, the second correspondence relationship and the residual image evaluation formula obtained by the test.
  • the second image retention test curve of the array substrate can be obtained according to the third correspondence relationship, the fourth correspondence relationship and the image retention evaluation formula obtained by the above method.
  • FIG. 6 is a schematic structural diagram of a residual image testing device provided by an embodiment.
  • the residual image testing device includes: a first acquisition module 301, configured so that the voltage of the preset driving transistor in the array substrate is changed from the first The preset voltage is switched to the second preset voltage within the preset time, and the first corresponding relationship between the source and drain current of the preset driving transistor and the time is acquired; It is assumed that the voltage is switched to the second preset voltage within the preset time, and the second corresponding relationship between the source and drain current of the preset driving transistor and the time is obtained; wherein, the first preset voltage is that the array substrate is under the first gray scale condition The voltage corresponding to the simulated light emission, the second preset voltage is the voltage corresponding to the simulated light emission of the array substrate under the second gray-scale condition, and the third preset voltage is the voltage corresponding to the simulated light emission of the array substrate under the third gray-scale condition, The second gray scale is between the first gray scale and the third gray scale; the first residual
  • the afterimage evaluation formula is:
  • I(t) JND is the evaluation value of the afterimage of the array substrate at time t after the voltage of the preset drive transistor is switched;
  • I(t) A is the voltage of the preset drive transistor switched from the first preset voltage to the second At time t after the preset voltage, the source and drain currents of the driving transistor are preset;
  • I(t) B is the time t after the voltage of the preset driving transistor is switched from the third preset voltage to the second preset voltage, preset
  • I0 A is the source and drain current of the preset driving transistor at a first preset voltage;
  • I0 B is the source and drain current of the preset driving transistor at a third preset voltage.
  • the image retention testing device of this embodiment corresponds to the image retention testing method of the foregoing embodiment.
  • the afterimage test method has the same working principle and working method, so it also has the same effect, so I will not repeat it here.

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Abstract

本文公开了一种残影测试方法和残影测试装置。所述残影测试方法包括：在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第二预设电压后的预设时间内，获取预设驱动晶体管的源漏电流与时间的第一对应关系；在预设驱动晶体管的电压由第三预设电压切换至第二预设电压后的预设时间内，获取预设驱动晶体管的源漏电流与时间的第二对应关系；根据第一对应关系、第二对应关系及残影评价公式获取阵列基板的第一残影测试曲线，其中，第一残影测试曲线为时间与残影评价值的对应关系。

Description

残影测试方法和残影测试装置
本申请要求在2020年03月24日提交中国专利局、申请号为202010213705.7的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术，例如涉及一种残影测试方法和残影测试装置。
背景技术
随着显示技术的发展，显示面板所起到的作用也越来越大，相应地对显示面板的要求也越来越高。
显示面板出厂前都需要进行残影测试，然而，显示面板在进行残影测试时存在流片周期较长以及成本较高的问题。
发明内容
本公开提供一种残影测试方法和残影测试装置，以减少流片周期，降低成本。
提供了一种残影测试方法，所述方法包括：在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第二预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第一对应关系；在所述预设驱动晶体管的电压由第三预设电压切换至所述第二预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第二对应关系；根据所述第一对应关系、所述第二对应关系及残影评价公式获取所述阵列基板的第一残影测试曲线，其中，所述第一残影测试曲线为时间与残影评价值的对应关系。
还提供了一种残影测试装置，所述残影测试装置包括：第一获取模块，设置为在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第二预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第一对应关系；第二获取模块，设置为在所述驱动晶体管的电压由第三预设电压切换至所述第二预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第二对应关系；第三获取模块，设置为根据所述第一对应关系、所述第二对应关系及残影评价公式获取所述阵列基板的第一残影测试曲线，其中，所述第一残影测试曲线为时间与残影评价值的对应关系。
本实施例的技术方案，采用的残影测试方法包括：在阵列基板中的预设驱 动晶体管的电压由第一预设电压切换至第二预设电压后的预设时间内，获取预设驱动晶体管的源漏电流与时间的第一对应关系；在预设驱动晶体管的电压由第三预设电压切换至第二预设电压后的预设时间内，获取预设驱动晶体管的源漏电流与时间的第二对应关系；根据第一对应关系、第二对应关系及残影评价公式获取阵列基板的第一残影测试曲线。可结合第一对应关系、第二预设关系以及残影评价公式直接获取该阵列基板对应的第一残影测试曲线，而不需要再将该阵列基板蒸镀上发光材料之后再通过光学设备获取对应的显示面板的第一残影测试曲线，减少了流片周期，也避免了蒸镀和模组物料的浪费，降低了成本。
附图说明
图1为一实施例提供的一种残影测试方法的流程图。
图2为一实施例提供的一种时间与源漏电流的对应关系曲线图。
图3为一实施例提供的一种阵列基板的结构示意图。
图4为一实施例提供的一种第一残影测试曲线的结果图。
图5为一实施例提供的又一种时间与源漏电流的对应关系曲线图。
图6为一实施例提供的一种残影测试装置的结构示意图。
具体实施方式
下面结合附图和实施例对本公开作说明。此处所描述的具体实施例仅仅用于解释本公开，而非对本公开的限定。
残影测试时存在流片周期较长、成本较高的问题，产生此问题的原因在于：残影测试时，均需要在模组阶段进行测试，也即需要在阵列基板上蒸镀发光材料并进行封装后，通过光学设备测试屏体的光学特性来评价显示面板的残影，因此存在流片周期长且浪费蒸镀和模组物料的问题。
图1为一实施例提供的一种残影测试方法的流程图，参考图1，残影测试方法包括：
步骤S110，在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第二预设电压后的预设时间内，获取预设驱动晶体管的源漏电流与时间的第一对应关系。
阵列基板可为有机发光二极管(OrganicLight-Emitting Diode，OLED)显示面板或者液晶显示面板等显示面板对应的阵列基板。阵列基板可包括多个驱动 晶体管，例如在OLED显示面板中，阵列基板包括多个像素驱动电路，每个像素驱动电路中均包括驱动晶体管，驱动晶体管设置为向对应的子像素提供驱动电流，驱动晶体管的电压不同时，其产生的源漏电流(源极与漏极之间的电流)不同，也即此时子像素的驱动电流不同，子像素的发光对应不同的灰阶，也即显示面板发光的灰阶与驱动晶体管的源漏电流相关。预设驱动晶体管可为阵列基板中的任意一个驱动晶体管。
若显示面板需要测试由第一灰阶切换到第二灰阶、由第三灰阶切换到第二灰阶时的残影，可将第一预设电压设置为在第一灰阶条件下，阵列基板仿真发光对应的电压；将第二预设电压设置为在第二灰阶条件下，阵列基板仿真发光对应的电压；将第三预设电压设置为在第三灰阶条件下，阵列基板仿真发光对应的电压；其中，第二灰阶介于第一灰阶和第三灰阶之间，通过测试阵列基板由第一预设电压、第三预设电压切换到第二预设电压时的电流与时间的对应关系，将其代入残影评价公式从而得到由该阵列基板制成的显示面板的残影测试曲线。第一预设电压、第二预设电压和第三预设电压均可包括驱动晶体管的栅极电压、源极电压和漏极电压，预设驱动晶体管的电压由第一预设电压切换至第二预设电压时，可仅将栅极电压进行切换，而对应的源极电压和漏极电压不变。
图2为一实施例提供的一种时间与源漏电流的对应关系曲线图，参考图2，第一对应关系可理解为在预设驱动晶体管的电压由第一预设电压切换到第二预设电压的预设时间内，时间与源漏电流的对应关系，第一灰阶可为255灰阶，第二灰阶可为48灰阶，第三灰阶可为0灰阶，在其它实施例中，第二灰阶也可为128灰阶，预设时间可根据阵列基板对应的显示面板确定，如可对应显示面板灰阶切换后至显示面板残影消失的时间，如图2所示，第一对应关系曲线101表示预设驱动晶体管先工作于第一预设电压下，在t0时刻由第一预设电压切换至第二预设电压，并一直工作于第二预设电压下。第一关系曲线101中从t0时刻起，至预设时间(如t0至t1时间段内)内的曲线则可对应于第一对应关系。
步骤S120，在预设驱动晶体管的电压由第三预设电压切换至第二预设电压的预设时间内，获取预设驱动晶体管的源漏电流与时间的第二对应关系。
如图2所示，第二对应关系曲线102表示预设驱动晶体管先工作于第三预设电压下，在t0时刻由第三预设电压切换至第二预设电压，并一直工作于第二预设电压下。第二关系曲线102中从t0时刻起，至预设时间内的曲线则可对应于第二对应关系。
步骤S130，根据第一对应关系、第二对应关系及残影评价公式获取阵列基板的第一残影测试曲线。
获取第一对应关系，第二预设关系之后，则可结合残影评价公式直接获取该阵列基板对应的第一残影测试曲线，而不需要再将该阵列基板蒸镀上发光材料之后再通过光学设备获取对应的显示面板的第一残影测试曲线，减少了流片周期，也避免了蒸镀和模组物料的浪费，降低了成本。
本实施例的技术方案，采用的残影测试方法包括：在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第二预设电压的预设时间内，获取预设驱动晶体管的源漏电流与时间的第一对应关系；在预设驱动晶体管的电压由第三预设电压切换至第二预设电压的预设时间内，获取预设驱动晶体管的源漏电流与时间的第二对应关系；根据第一对应关系、第二对应关系及残影评价公式获取阵列基板的第一残影测试曲线。可结合第一对应关系、第二预设关系以及残影评价公式直接获取该阵列基板对应的第一残影测试曲线，而不需要再将该阵列基板蒸镀上发光材料之后再通过光学设备获取对应的显示面板的第一残影测试曲线，减少了流片周期，也避免了蒸镀和模组物料的浪费，降低了成本。
本实施例中也可先获取第二对应关系，再获取第一对应关系，也即先执行步骤S120，再执行步骤S110，本实施例对此不作限定。
图3为一实施例提供的一种阵列基板的结构示意图，参考图3，预设驱动晶体管为位于非显示区(Non Active Area，NAA)的电性薄膜晶体管测试组(Test Group，TEG)中的驱动晶体管。
阵列基板可包括显示区AA和非显示区NAA，非显示区NAA内可设置测试组TEG，测试组中包含多种晶体管，并且测试组中的多种晶体管对应于显示区中的多种晶体管，如测试组中包括对应显示区中驱动晶体管的驱动晶体管，两种驱动晶体管的参数一致，也即测试组中驱动晶体管的特性与显示区中驱动晶体管的特性相同。通过测试得到测试组中驱动晶体管的第一对应关系、第二对应关系，即相当于得到了显示区中驱动晶体管的第一对应关系与第二对应关系。由于测试组中驱动晶体管的栅极、漏极和源极均具有引线，可很方便地向该驱动晶体管施加第一预设电压、第二预设电压或者第三预设电压，而显示区中的驱动晶体管栅极、源极以及漏极不存在外接引线，施加第一预设电压、第二预设电压或者第三预设电压的难度较大；也即通过将预设驱动晶体管设置为位于非显示区NAA的电性薄膜晶体管测试组(Test Group，TEG)中的驱动晶体管，可极大地降低残影测试方法的实施难度。
残影评价公式为：
Figure PCTCN2021078054-appb-000001
其中，I(t) JND为预设驱动晶体管的电压切换后的第t时刻，阵列基板的残影评价值；I(t) A为预设驱动晶体管的电压由第一预设电压切换至第二预设电压后的第t时刻，预设驱动晶体管的源漏电流；I(t) B为预设驱动晶体管的电压由第三预设电压切换至第二预设电压后的第t时刻，预设驱动晶体管的源漏电流；I0 A为预设驱动晶体管在第一预设电压下的源漏电流；I0 B为预设驱动晶体管在第三预设电压下的源漏电流。
图4为一实施例提供的一种第一残影测试曲线的结果图，参考图4，实际曲线202表示预设驱动晶体管根据实测的源漏电流以及上述残影评价公式计算得到的残影评价值；拟合曲线201表示对实际曲线202拟合后得到的曲线，从图4中可看出，该拟合曲线与显示面板的实际残影曲线接近，但相比实际残影曲线表现形式更为清晰，更为明显，且通过实验验证可知，通过本实施例获取的第一残影测试曲线，与通过光学设备测试显示面板得到的第一残影测试曲线具有线性关系，因此只需要通过阵列基板非显示区NAA内的测试组TEG进行仿真残影测试就能得到反映由该阵列基板制成的显示面板的残影测试曲线，无需对该阵列基板蒸镀发光材料，在缩短测试周期同时也避免了物料的浪费。
残影测试方法还包括：在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第四预设电压后的预设时间内，获取预设驱动晶体管的源漏电流与时间的第三对应关系；在预设驱动晶体管的电压由第三预设电压切换至第四预设电压后的预设时间内，获取预设驱动晶体管的源漏电流与时间的第四对应关系；根据第三对应关系、第四对应关系及残影评价公式获取阵列基板的第二残影测试曲线，第二残影测试曲线为时间与残影评价值的对应关系；根据第一残影测试曲线及第二残影测试曲线获取阵列基板的拟合残影测试曲线。
第四预设电压为在第四灰阶条件下，阵列基板仿真发光对应的电压，第四灰阶介于第一灰阶和第三灰阶之间，且第四灰阶与第二灰阶不同，如当第二灰阶为48灰阶时，第四灰阶可为128灰阶。此时的残影评价公式中，I(t) A可表示预设驱动晶体管的电压由第一预设电压切换至第四预设电压后的第t时刻，预设驱动晶体管的源漏电流；I(t) B可表示预设驱动晶体管的电压由第三预设电压切换至第四预设电压后的第t时刻，预设驱动晶体管的源漏电流；由于第一残影测试曲线和第二残影测试曲线的形状相似，获取第一残影测试曲线和第二残影测试曲线之后，可拟合出阵列基板的第三残影测试曲线，例如在任意时刻t，第三残影测试曲线上对应的残影评价值，为在该时刻t第一残影测试曲线对应的残影评价值与在该时刻t第二残影测试曲线对应的残影评价值的平均值；将第三残影测试曲线作为阵列基板的残影测试曲线，可减少测试过程中的误差，也即第三残影测试曲线的准确度更高。
在获取第一对应关系及第二对应关系之前还包括：对预设驱动晶体管进行稳定性测试，和/或，对预设驱动晶体管进行T-Aging工艺。
可先对预设驱动晶体管进行稳定性测试(Id-Vg sweep)，以确定预设驱动晶体管的稳定性，若稳定性较好，则表明该预设驱动晶体管的性能较好，测试获得的第一残影测试曲线更为准确，若I(t) JND随着时间变化的变化量较小，则表明阵列基板对应的显示面板的残影越轻微。还可对预设驱动晶体管进行T-Aging(老化)工艺，以提高驱动晶体管的稳定性。
第一预设电压、第二预设电压、第三预设电压和第四预设电压通过电路仿真获取。
可通过电路仿真获取预设驱动晶体管在对应由该阵列基板制成的显示面板发光处于第一灰阶、第二灰阶、第三灰阶以及第四灰阶下的电压，也即第一预设电压、第二预设电压、第三预设电压以及第四预设电压，进而便于后续通过分别向预设驱动晶体管施加第一预设电压、第二预设电压、第三预设电压以及第四预设电压，以获取第一对应关系、第二对应关系、第三对应关系和第四对应关系。
在获取第一对应关系第二应对关系、第三应对关系及第四对应关系之前，还包括：调整第一预设电压，使得预设驱动晶体管在第一预设电压下的源漏电流恒定值为第一电流值；调整第三预设电压，使得预设驱动晶体管在第三预设电压下的源漏电流恒定值为第二电流值。
第一电流值可为阵列基板对应的由该阵列基板制成的显示面板在第一灰阶下发光时，驱动晶体管的实际电流值，例如，第一灰阶为255灰阶时，第一电流对应为40纳安，第三灰阶为0灰阶时，第二电流对应为0安，第一电流和第二电流分别对应于阵列基板所对应的由该阵列基板制成的显示面板在实际灰阶下的源漏电流。这样设置，可使得预设驱动晶体管在测试时的工作状态更接近实际工作状态，获得的第一残影测试曲线更加接近阵列基板对应的显示面板实际的残影曲线。
预设时间可大于或等于60秒。
若预设时间过短，则预设驱动晶体管的电压切换后，预设驱动晶体管的电流并没有工作在恒定值，获取的第一残影测试曲线不够完整，不能够完整地评价阵列基板对应的显示面板的残影性能。通过设置预设时间大于或等于60秒，可获取完整的第一残影测试曲线，进而能够有效地评价阵列基板对应的显示面板的残影性能。
示例性地，图5为一实施例提供的又一种时间与源漏电流的对应关系曲线 图，参考图5，阵列基板制作完成后，可先将阵列基板测试组中的驱动晶体管进行T-Aging工艺，以提高该驱动晶体管的稳定性；然后将驱动晶体管的电压施加为第二预设电压，即进行预热(Warm-up)，例如施加第二预设电压50秒，测试驱动晶体管的源漏电流在多个时刻的值(图5中第一对应关系曲线101的tA-tB段)；随后再将驱动晶体管的电压由第二预设电压切换至第一预设电压，并持续一段时间(如5分钟(minutes，min)-10min)，即压力(stress)过程，并测试驱动晶体管的源漏电流在多个时刻的值，源漏电流的稳定值即为I0 A(图5中第一对应关系曲线101的tB-t0段)；随后再将驱动晶体管的电压由第一预设电压切换至第二预设电压，并持续预设时间，得到源漏电流与时间的完整对应关系，其中，在该预设时间内，时间与源漏电流的对应关系即为第一对应关系(图5中第一对应关系曲线101的t0时刻及之后的曲线)。
在获取第二对应关系时，可先将阵列基板测试组中的驱动晶体管进行T-Aging工艺，以提高该驱动晶体管的稳定性；然后将驱动晶体管的电压施加为第二预设电压，即进行Warm-up，例如施加第二预设电压50秒，测试驱动晶体管的源漏电流在多个时刻的值(图5中第二对应关系曲线102的tA-tB段)；随后再将驱动晶体管的电压由第二预设电压切换至第三预设电压，并持续一段时间(如5min-10min)，即stress过程，并测试驱动晶体管的源漏电流在多个时刻的值，源漏电流的稳定值即为I0 B(图5中第二对应关系曲线102的tB-t0段)；随后再将驱动晶体管的电压由第三预设电压切换至第二预设电压，并持续预设时间，得到源漏电流与时间的完整对应关系，其中，在该预设时间内，时间与源漏电流的对应关系即为第二对应关系(图5中第二对应关系曲线102的t0时刻及之后的曲线)。
最后根据测试得到的第一对应关系、第二对应关系以及残影评价公式得到该阵列基板的第一残影测试曲线。同理，可根据以上方法测试得到的第三对应关系、第四对应关系以及残影评价公式得到该阵列基板的第二残影测试曲线。
图6为一实施例提供的一种残影测试装置的结构示意图，参考图6，残影测试装置包括：第一获取模块301，设置为在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第二预设电压的预设时间内，获取预设驱动晶体管的源漏电流与时间的第一对应关系；第二获取模块302，设置为在驱动晶体管的电压由第三预设电压切换至第二预设电压的预设时间内，获取预设驱动晶体管的源漏电流与时间的第二对应关系；其中，第一预设电压为在第一灰阶条件下，阵列基板仿真发光对应的电压，第二预设电压为在第二灰阶条件下，阵列基板仿真发光对应的电压，第三预设电压为在第三灰阶条件下，阵列基板仿真发光对应的电压，第二灰阶介于第一灰阶和第三灰阶之间；第一残影测试曲线为时间与残影评价值的对应关系。
可选地，残影评价公式为：
Figure PCTCN2021078054-appb-000002
其中，I(t) JND为预设驱动晶体管的电压切换后的第t时刻，阵列基板的残影评价值；I(t) A为预设驱动晶体管的电压由第一预设电压切换至第二预设电压后的第t时刻，预设驱动晶体管的源漏电流；I(t) B为预设驱动晶体管的电压由第三预设电压切换至第二预设电压后的第t时刻，预设驱动晶体管的源漏电流；I0 A为预设驱动晶体管在第一预设电压下的源漏电流；I0 B为预设驱动晶体管在第三预设电压下的源漏电流。
本实施例的残影测试装置对应于上述实施例的残影测试方法，其工作原理和方式参考上述实施例对于残影测试方法的描述，在此不再赘述，因其与上述实施例提供的残影测试方法具有相同的工作原理以及工作方式，因此也具有相同的效果，在此不再赘述。

Claims (20)

  1. 一种残影测试方法，包括：
    在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第二预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第一对应关系；
    在所述预设驱动晶体管的电压由第三预设电压切换至所述第二预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第二对应关系；
    根据所述第一对应关系、所述第二对应关系及残影评价公式获取所述阵列基板的第一残影测试曲线，其中，所述第一残影测试曲线为时间与残影评价值的对应关系。
  2. 根据权利要求1所述的残影测试方法，其中，
    所述第一预设电压为在第一灰阶条件下，所述阵列基板仿真发光对应的电压，所述第二预设电压为在第二灰阶条件下，所述阵列基板仿真发光对应的电压，所述第三预设电压为在第三灰阶条件下，所述阵列基板仿真发光对应的电压，所述第二灰阶介于所述第一灰阶和所述第三灰阶之间。
  3. 根据权利要求1所述的残影测试方法，其中，所述第一预设电压、所述第二预设电压和所述第三预设电压均包括所述预设驱动晶体管的栅极电压、源极电压和漏极电压。
  4. 根据权利要求1所述的残影测试方法，其中，所述残影评价公式为：
    Figure PCTCN2021078054-appb-100001
    其中，所述I(t) JND为所述预设驱动晶体管的电压切换后的第t时刻，所述阵列基板的残影评价值；所述I(t) A为所述预设驱动晶体管的电压由所述第一预设电压切换至所述第二预设电压后的第t时刻，所述预设驱动晶体管的源漏电流；所述I(t) B为所述预设驱动晶体管的电压由所述第三预设电压切换至所述第二预设电压后的第t时刻，所述预设驱动晶体管的源漏电流；所述I0 A为所述预设驱动晶体管在所述第一预设电压下的源漏电流；所述I0 B为所述预设驱动晶体管在所述第三预设电压下的源漏电流。
  5. 根据权利要求2所述的残影测试方法，还包括：
    在所述阵列基板中的预设驱动晶体管的电压由所述第一预设电压切换至第四预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第三对应关系；
    在所述预设驱动晶体管的电压由所述第三预设电压切换至所述第四预设电 压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第四对应关系；
    根据所述第三对应关系、所述第四对应关系及所述残影评价公式获取所述阵列基板的第二残影测试曲线，其中，所述第二残影测试曲线为时间与残影评价值的对应关系；
    根据所述第一残影测试曲线及所述第二残影测试曲线获取所述阵列基板的第三残影测试曲线；
    其中，所述第四预设电压为在第四灰阶条件下，所述阵列基板仿真发光对应的电压，所述第四灰阶介于所述第一灰阶和所述第三灰阶之间，所述第四灰阶不等于所述第二灰阶。
  6. 根据权利要求5所述的残影测试方法，其中，所述第一预设电压、所述第二预设电压、所述第三预设电压和所述第四预设电压通过电路仿真获取。
  7. 根据权利要求5所述的残影测试方法，在获取所述第一对应关系、所述第二对应关系、所述第三对应关系及所述第四对应关系之前还包括以下至少之一：
    对所述预设驱动晶体管进行稳定性测试；
    对所述预设驱动晶体管进行老化T-Aging工艺。
  8. 根据权利要求7所述的残影测试方法，在获取所述第一对应关系、所述第二对应关系、所述第三对应关系以及所述第四对应关系之前，还包括：
    调整所述第一预设电压，使得所述预设驱动晶体管在所述第一预设电压下的源漏电流恒定值为第一电流值；
    调整所述第三预设电压，使得所述预设驱动晶体管在所述第三预设电压下源漏电流恒定值为第二电流值。
  9. 根据权利要求1所述的残影测试方法，其中，
    所述预设时间大于或等于60秒。
  10. 根据权利要求1所述的残影测试方法，其中，所述预设驱动晶体管为位于所述阵列基板的非显示区的电性薄膜晶体管测试组中的驱动晶体管。
  11. 一种残影测试装置，包括：
    第一获取模块，设置为在阵列基板中的预设驱动晶体管的电压由第一预设电压切换至第二预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第一对应关系；
    第二获取模块，设置为在所述驱动晶体管的电压由第三预设电压切换至所述第二预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第二对应关系；
    第三获取模块，设置为根据所述第一对应关系、所述第二对应关系及残影评价公式获取所述阵列基板的第一残影测试曲线，其中，所述第一残影测试曲线为时间与残影评价值的对应关系。
  12. 根据权利要求11所述的残影测试装置，其中，所述残影评价公式为：
    Figure PCTCN2021078054-appb-100002
    其中，所述I(t) JND为所述预设驱动晶体管的电压切换后的第t时刻，所述阵列基板的残影评价值；所述I(t) A为所述预设驱动晶体管的电压由所述第一预设电压切换至所述第二预设电压后的第t时刻，所述预设驱动晶体管的源漏电流；所述I(t) B为所述预设驱动晶体管的电压由所述第三预设电压切换至所述第二预设电压后的第t时刻，所述预设驱动晶体管的源漏电流；所述I0 A为所述预设驱动晶体管在所述第一预设电压下的源漏电流；所述I0 B为所述预设驱动晶体管在所述第三预设电压下的源漏电流。
  13. 根据权利要求11所述的残影测试装置，其中，
    所述第一预设电压为在第一灰阶条件下，所述阵列基板仿真发光对应的电压，所述第二预设电压为在第二灰阶条件下，所述阵列基板仿真发光对应的电压，所述第三预设电压为在第三灰阶条件下，所述阵列基板仿真发光对应的电压，所述第二灰阶介于所述第一灰阶和所述第三灰阶之间。
  14. 根据权利要求11所述的残影测试装置，其中，所述第一预设电压、所述第二预设电压和所述第三预设电压均包括所述预设驱动晶体管的栅极电压、源极电压和漏极电压。
  15. 根据权利要求13所述的残影测试装置，还包括：
    第四获取模块，设置为在所述阵列基板中的预设驱动晶体管的电压由所述第一预设电压切换至第四预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第三对应关系；
    第五获取模块，设置为在所述预设驱动晶体管的电压由所述第三预设电压切换至所述第四预设电压后的预设时间内，获取所述预设驱动晶体管的源漏电流与时间的第四对应关系；
    第六获取模块，设置为根据所述第三对应关系、所述第四对应关系及所述残影评价公式获取所述阵列基板的第二残影测试曲线，其中，所述第二残影测试曲线为时间与残影评价值的对应关系；
    第七获取模块，设置为根据所述第一残影测试曲线及所述第二残影测试曲线获取所述阵列基板的第三残影测试曲线；
    其中，所述第四预设电压为在第四灰阶条件下，所述阵列基板仿真发光对应的电压，所述第四灰阶介于所述第一灰阶和所述第三灰阶之间，所述第四灰阶不等于所述第二灰阶。
  16. 根据权利要求15所述的残影测试装置，其中，所述第一预设电压、所述第二预设电压、所述第三预设电压和所述第四预设电压通过电路仿真获取。
  17. 根据权利要求15所述的残影测试装置，还包括：
    处理模块，设置为在获取所述第一对应关系、所述第二对应关系、所述第三对应关系及所述第四对应关系之前，执行以下至少之一：
    对所述预设驱动晶体管进行稳定性测试；
    对所述预设驱动晶体管进行老化T-Aging工艺。
  18. 根据权利要求17所述的残影测试装置，还包括：
    调整模块，设置为在获取所述第一对应关系、所述第二对应关系、所述第三对应关系以及所述第四对应关系之前，调整所述第一预设电压，使得所述预设驱动晶体管在所述第一预设电压下的源漏电流恒定值为第一电流值；调整所述第三预设电压，使得所述预设驱动晶体管在所述第三预设电压下源漏电流恒定值为第二电流值。
  19. 根据权利要求11所述的残影测试装置，其中，
    所述预设时间大于或等于60秒。
  20. 根据权利要求11所述的残影测试装置，其中，
    所述预设驱动晶体管为位于所述阵列基板的非显示区的电性薄膜晶体管测试组中的驱动晶体管。
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