WO2021189529A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2021189529A1
WO2021189529A1 PCT/CN2020/083652 CN2020083652W WO2021189529A1 WO 2021189529 A1 WO2021189529 A1 WO 2021189529A1 CN 2020083652 W CN2020083652 W CN 2020083652W WO 2021189529 A1 WO2021189529 A1 WO 2021189529A1
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WO
WIPO (PCT)
Prior art keywords
gate array
signal
circuit board
flexible circuit
start signal
Prior art date
Application number
PCT/CN2020/083652
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English (en)
French (fr)
Inventor
傅晓立
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US16/762,347 priority Critical patent/US20220108644A1/en
Publication of WO2021189529A1 publication Critical patent/WO2021189529A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the present disclosure relates to the field of display technology, in particular to display panels.
  • FIG. 1 is a block diagram of a display panel including a gate driving circuit in the prior art.
  • a chip on film (COF) 120 is provided between the printed circuit board 110 and the gate array substrate GOA1, and the level shifter 111 is provided on the printed circuit board 110.
  • COF chip on film
  • the gate array substrate GOA1 is electrically connected to the level shifter 111.
  • the high price of the level shifter coupled with the complexity of peripheral devices matching the level shifter, leads to an increase in the manufacturing cost of the panel in the prior art.
  • the number of clock pulses of the gate array substrate changes, it is often impossible to find a level shifter that can be used directly. It often requires multiple level shifters and corresponding peripheral circuit designs to complete the display panel, which affects design flexibility. sex.
  • the panel of the prior art cannot change the scanning direction of the gate driving circuit.
  • the high price of the level shifter coupled with the complexity of peripheral devices matching the level shifter, leads to an increase in the manufacturing cost of the panel in the prior art.
  • the number of clock pulses of the gate array substrate changes, it is often impossible to find a level shifter that can be used directly. It often requires multiple level shifters and corresponding peripheral circuit designs to complete the display panel, which affects design flexibility. sex.
  • the panel of the prior art cannot change the scanning direction of the gate driving circuit.
  • the present disclosure proposes a display panel, which can reduce the manufacturing cost of the panel, increase the flexibility of the panel circuit design structure, and control the scanning direction of the gate driving circuit.
  • a display panel which is characterized by comprising: a gate array substrate; a first flexible circuit board connected to the gate array substrate; a printed circuit board connected to the first flexible circuit board
  • the flexible circuit board is connected with a central control board (timing controller, T-CON), the central control board outputs the gate array driving signal;
  • the second flexible circuit board is arranged on the side edge of the gate array substrate;
  • a level shifter is arranged on the second flexible circuit board and is electrically connected to the central control board, and the level shifter (Level Shifter) raises the gate array driving signal.
  • the gate array control signal includes a plurality of clock control signals.
  • the number of the clock control signals is twelve.
  • the gate array driving signal is configured to include a low-frequency signal
  • the second flexible circuit board is configured to further include a low-frequency signal separation element
  • the low-frequency signal separation element is configured For converting the low-frequency signal into a first low-frequency signal and a second low-frequency signal.
  • the second flexible circuit board is configured to further include a scanning direction control element for controlling the scanning direction of the gate driving circuit, and the scanning direction is controlled by receiving a scanning direction control signal.
  • the scanning direction control element further includes a receiving unit that receives a scanning direction control signal.
  • the gate array driving signal is configured to include a start signal
  • the second flexible circuit board is configured to further include a start signal separation element, and the start signal is separated
  • the element is configured to convert the start signal into a first start signal and a second start signal.
  • the gate array driving signal is configured to include a left start signal and a right start signal
  • the second flexible circuit board is configured to further include a start signal conversion element
  • the start signal conversion element is configured to convert the left start signal and the right start signal into a first start signal and a second start signal.
  • the display panel provided by the present disclosure includes a gate array substrate; a first flexible circuit board connected to the gate array substrate; a printed circuit board connected to the first flexible circuit board and provided with a central control board , The central control board outputs the gate array drive signal; the second flexible circuit board is arranged on the side edge of the gate array substrate; and the level shifter is arranged on the second flexible circuit board, Electrically connected to the central control board, the level shifter raises the gate array driving signal, achieving the effect of reducing panel manufacturing costs, increasing panel design flexibility, and controlling the scanning direction of the gate driving circuit.
  • FIG. 1 shows a block diagram of a display panel in the prior art
  • FIG. 2 shows a block diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic block diagram of an integrated circuit of a film-on-chip package according to an embodiment of the present disclosure
  • FIG. 4 shows a block diagram of a chip-on-film package integrated circuit according to an embodiment of the present disclosure.
  • the display panel 200 includes a gate array substrate 30; a first flexible circuit board 20 connected to the gate array substrate 30; a printed circuit board 10 connected to the first flexible circuit board 20 and provided with a center A control board (timing controller, T-CON) 11, the central control board 11 outputs gate array drive signals; a second flexible circuit board 40, arranged on the side edge of the gate array substrate 30; and level shift
  • the level shifter 41 is arranged on the second flexible circuit board 40 and is electrically connected to the central control board 11.
  • the level shifter raises the gate array driving signal, and the level shifter 41 is set independently On the side edge of the gate array substrate 30, it is convenient to adjust and replace the components that convert the gate array driving signal, and increase the design flexibility of the panel driving circuit.
  • the second flexible circuit board 40 further includes a shift register (Shifter Register) and an output buffer (Output Buffer).
  • the shift register receives the gate array driving signal and generates a temporary The gate array drive signal is stored, and the level shifter raises the temporary storage gate array drive signal and transmits it to the output buffer.
  • the output buffer outputs the gate array control signal to control the opening and closing of the thin film transistor on the gate array substrate.
  • the level shifter 41, the shift register and the output buffer are coupled to form a thin-film-on-chip integrated circuit, which is arranged on the second flexible circuit board 40.
  • the gate array driving signal includes a frequency signal CPV, a high gate pulse signal VGH, a low gate pulse signal VGL, a power supply voltage VCC, and a ground voltage GND; or, in an embodiment of the present disclosure, the shift The bit register 310, the level shifter 320, and the output buffer 330 are electrically connected to each other and arranged on the second flexible circuit board 40.
  • the number of clock control signals is 12, including the first clock control signal CK1, the second clock control signal CK2, the third clock control signal CK3, and the fourth clock control signal CK4. , Fifth clock control signal CK5, sixth clock control signal CK6, seventh clock control signal CK7, eighth clock control signal CK8, ninth clock control signal CK9, tenth clock control signal CK10, The eleventh clock control signal CK11 and the twelfth clock control signal CK12.
  • the gate array driving signal includes a low-frequency signal LC
  • the thin-film-on-chip integrated circuit 300 includes a low-frequency signal separation module.
  • the low-frequency signal LC is converted into a first low-frequency signal LC1 and a second low-frequency signal LC2 through the low-frequency signal separation element. .
  • the number of signal channels for low-frequency signals is increased after the operation of the integrated circuit 300 of the film-on-chip-on-package package, which achieves the effect of increasing the design flexibility of the panel driving circuit and improving the accuracy of the gate driving circuit.
  • the second flexible circuit 40 board is configured to further include a scanning direction control element for controlling the scanning direction of the gate driving circuit, and the scanning direction is controlled by receiving the scanning direction control signal.
  • the scanning direction control element is coupled to the integrated circuit 300 of the chip-on-film package.
  • the gate array driving signal includes a start signal ST
  • the gate second flexible circuit board 40 is configured to include a start signal separation element
  • the start signal separation element converts the start signal These are the first start signal ST1 and the second start signal ST2.
  • the initial signal separation element is coupled to the integrated circuit 300 of the film-on-chip package.
  • the chip-on-film package integrated circuit also includes a signal input interface for receiving other control signals (Other Control Signal, OCS) and outputting other output channel signals (Other output channel, OCS).
  • OCS Operation Control Signal
  • OOC output channel
  • the OOC signal output interface is configured with the signal input interface and the signal output interface through the thin-film-on-chip integrated circuit 300 to achieve the effect of increasing the design flexibility of the panel drive circuit.
  • the signal input interface and the signal output interface are directly arranged on the second flexible circuit board 40 and are electrically connected to the shift register 310 and the output buffer 330, respectively.
  • FIG. 4 shows a block diagram of a thin film on chip integrated circuit 400 according to an embodiment of the present disclosure.
  • the gate array driving signal includes the left start signal STV1L and Right start signal STV1R.
  • the chip-on-film package integrated circuit 400 includes a start signal conversion element, and the start signal conversion element converts the left start signal STV1L and the right start signal STV1R into the first start signal ST1 and the second start signal ST2.
  • the TFT-on-chip integrated circuit 400 by configuring the TFT-on-chip integrated circuit 400 to output the gate array control signal including the first start signal ST1 and the second start signal ST2, the design flexibility of the panel driving circuit is increased and the gate driving circuit is improved. The effect of precision.
  • the start signal conversion element is obtained by converting the voltage, current, other electrical parameters, signal rising edge and falling edge, and/or signal frequency of the left start signal STV1L and the right start signal STV1R The first start signal ST1 and the second start signal ST2.
  • the display panel provided by the present disclosure includes a gate array substrate; a first flexible circuit board connected to the gate array substrate; a printed circuit board connected to the first flexible circuit board and provided with a central control Board, the center control board outputs the gate array drive signal; the second flexible circuit board is arranged on the side edge of the gate array substrate; and the level shifter is arranged on the second flexible circuit board , Is electrically connected to the central control board, and the level shifter raises the gate array driving signal, achieving the effect of reducing panel manufacturing cost, increasing panel design flexibility, and controlling the scanning direction of the gate driving circuit.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（100），包括闸极阵列基板（30）；第一软性电路板（20），与闸极阵列基板（30）连接；印刷电路板（10），与第一软性电路板（20）连接，设置有中心控制板（11），中心控制板（11）输出闸极阵列驱动讯号；第二软性电路板（40），设置于闸极阵列基板（30）的侧边缘；以及电平位移器（41），设置在第二软性电路板（40）上，与中心控制板（11）电连接，电平位移器（41）抬升闸极阵列驱动讯号，达到降低面板制造成本，增加面板设计灵活性，以及控制闸极驱动电路的扫描方向的效果。

Description

显示面板 技术领域
本揭示涉及显示技术领域，具体涉及显示面板。
 背景技术
请参阅图1，其为现有技术包含闸极驱动电路的显示面板方块示意图。如图1所示，在显示面板100中，印刷电路板110与闸极阵列基板GOA1之间设置有芯片承载薄膜(chip on film，COF)120，电平位移器111设置在印刷电路板110的内部，闸极阵列基板GOA1与电平位移器111电性连接。
然而，现有技术存在如下几个缺陷:
首先，电平位移器价格高，再加上搭配电平位移器的外围器件复杂，导致现有技术的面板制造成本增加。再者，随着闸极阵列基板时脉个数的改变，经常不能找到直接使用的电平位移器，常需要多个电平位移器并搭配对应的外围电路设计才能完成显示面板，影响设计灵活性。此外，现有技术的面板亦不能改变闸极驱动电路的扫描方向。
故，有需要提供一种新的显示面板，以解决现有技术存在的问题。
 技术问题
首先，电平位移器价格高，再加上搭配电平位移器的外围器件复杂，导致现有技术的面板制造成本增加。再者，随着闸极阵列基板时脉个数的改变，经常不能找到直接使用的电平位移器，常需要多个电平位移器并搭配对应的外围电路设计才能完成显示面板，影响设计灵活性。此外，现有技术的面板亦不能改变闸极驱动电路的扫描方向。
 技术解决方案
为解决上述问题，本揭示提出一种显示面板，其可达到降低面板制造成本，增加面板电路设计架构灵活性，以及控制闸极驱动电路的扫描方向的效果。
为达成上述目的，本揭示提供一种显示面板，其特征在于，包括:闸极阵列基板；第一软性电路板，与所述闸极阵列基板连接；印刷电路板，与所述第一软性电路板连接，设置有中心控制板(timing controller, T-CON)，所述中心控制板输出闸极阵列驱动讯号；第二软性电路板，设置于所述闸极阵列基板的侧边缘；电平位移器，设置在所述第二软性电路板上，与所述中心控制板电连接，所述电平位移器(Level Shifter)抬升所述闸极阵列驱动讯号。
于本揭示其中的一实施例中，所述第二软性电路板还包括移位暂存器(Shifter Register)以及输出缓冲器(Output Buffer)，所述移位暂存器接收闸极阵列驱动讯号并产生暂存闸极阵列驱动讯号，所述电平位移器 抬升所述暂存闸极阵列驱动讯号后传输至所述输出缓冲器，由所述输出缓冲器输出闸极阵列控制讯号控制所述闸极阵列基板上的薄膜电晶体开启和关闭。
于本揭示其中的一实施例中，所述闸极阵列控制讯号包含多个时脉控制讯号。
于本揭示其中的一实施例中，所述时脉控制讯号的数量是12个。
于本揭示其中的一实施例中，所述闸极阵列驱动讯号被配置为包含低频讯号，所述第二软性电路板被配置为还包含低频讯号分离元件，所述低频讯号分离元件被配置为用于将所述低频讯号转换为第一低频讯号及第二低频讯号。
于本揭示其中的一实施例中，所述第二软性电路板被配置为还包含控制所述闸极驱动电路扫描方向的扫描方向控制元件，通过接收扫描方向控制讯号控制扫描方向。
于本揭示其中的一实施例中，所述扫描方向控制元件还包含接收扫描方向控制讯号的接收单元。
于本揭示其中的一实施例中，所述闸极阵列驱动讯号被配置为包含起始讯号，所述第二软性电路板被配置为还包含起始讯号分离元件，所述起始讯号分离元件被配置为用于将所述起始讯号转换为第一起始讯号及第二起始讯号。
于本揭示其中的一实施例中，所述闸极阵列驱动讯号被配置为包含左起始讯号及右起始讯号，所述第二软性电路板被配置为还包含起始讯号转换元件，所述起始讯号转换元件被配置为用于将所述左起始讯号及右起始讯号转换为第一起始讯号及第二起始讯号。
由于本揭示所提供的显示面板包括闸极阵列基板；第一软性电路板，与所述闸极阵列基板连接；印刷电路板，与所述第一软性电路板连接，设置有中心控制板，所述中心控制板输出闸极阵列驱动讯号；第二软性电路板，设置于所述闸极阵列基板的侧边缘；以及电平位移器，设置在所述第二软性电路板上，与所述中心控制板电连接，所述电平位移器抬升所述闸极阵列驱动讯号，达到降低面板制造成本，增加面板设计灵活性，以及控制闸极驱动电路的扫描方向的效果。
 有益效果
由于本揭示所提供的显示面板包括闸极阵列基板；第一软性电路板，与所述闸极阵列基板连接；印刷电路板，与所述第一软性电路板连接，设置有中心控制板，所述中心控制板输出闸极阵列驱动讯号；第二软性电路板，设置于所述闸极阵列基板的侧边缘；以及电平位移器，设置在所述第二软性电路板上，与所述中心控制板电连接，所述电平位移器抬升所述闸极阵列驱动讯号，达到降低面板制造成本，增加面板设计灵活性，以及控制闸极驱动电路的扫描方向的效果。
 附图说明
图1显示现有技术的显示面板的方块示意图；
图2显示根据本揭示的一实施例的显示面板的方块示意图；
图3显示根据本揭示的一实施例的薄膜覆晶封装积体电路的方块示意图；
图4显示根据本揭示的一实施例的薄膜覆晶封装积体电路的方块示意图。
 本发明的实施方式
以下实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
请参阅图2，其显示根据本揭示的一实施例的显示面板的方块示意图。其中，显示面板200包含闸极阵列基板30；第一软性电路板20，与所述闸极阵列基板30连接；印刷电路板10，与所述第一软性电路板20连接，设置有中心控制板(timing controller, T-CON)11，所述中心控制板11输出闸极阵列驱动讯号；第二软性电路板40，设置于所述闸极阵列基板30的侧边缘；以及电平位移器41，设置在所述第二软性电路板40上，与所述中心控制板11电连接，所述电平位移器抬升所述闸极阵列驱动讯号，通过将电平位移器41独立设置于闸极阵列基板30侧边缘，便于调整及替换转换闸极阵列驱动讯号的元件，增加面板驱动电路的设计灵活性。
于本揭示的一实施例中，第二软性电路板40还包括移位暂存器(Shifter Register)以及输出缓冲器(Output Buffer)，移位暂存器接收闸极阵列驱动讯号并产生暂存闸极阵列驱动讯号，电平位移器抬升暂存闸极阵列驱动讯号后传输至输出缓冲器，由输出缓冲器输出闸极阵列控制讯号控制闸极阵列基板上的薄膜电晶体开启和关闭。
于本揭示的一实施例中，电平位移器41，移位暂存器及输出缓冲器耦合为薄膜覆晶封装积体电路设置在第二软性电路板40上。
请参阅图3，其显示根据本揭示的一实施例的薄膜覆晶封装积体电路的方块示意图。如图所示，薄膜覆晶封装积体电路300包括移位暂存器(Shifter Register)310、电平位移器 (Level Shifter)320、输出缓冲器(Output Buffer)330。其中，移位暂存器310、电平位移器 320与输出缓冲器330电性连接，所述移位暂存器310接收所述闸极阵列驱动讯号并产生暂存闸极阵列驱动讯号，电平位移器 320抬升所述暂存闸极阵列驱动讯号后传输至所述输出缓冲器330，由所述输出缓冲器330输出闸极阵列控制讯号。其中，所述闸极阵列驱动讯号包含频率讯号CPV、高闸极脉冲信号VGH、低闸极脉冲信号VGL、电源电压VCC、接地电压 GND；或者，于本揭示的一实施例中，所述移位暂存器310、电平位移器 320、输出缓冲器330彼此电连接并设置在所述第二软性电路板40上。
其中，闸极阵列控制讯号包含多个时脉控制讯号。换言之，通过薄膜覆晶封装积体电路300可控制具有多个输入通道的闸极阵列，达到增加面板驱动电路的设计灵活性的效果。
于图3的实施例中，时脉控制讯号的数量是12个，包含第一时脉控制讯号CK1、第二时脉控制讯号CK2、第三时脉控制讯号CK3、第四时脉控制讯号CK4、第五时脉控制讯号CK5、第六时脉控制讯号CK6、第七时脉控制讯号CK7、第八时脉控制讯号CK8、第九时脉控制讯号CK9、第十时脉控制讯号CK10、第十一时脉控制讯号CK11及第十二时脉控制讯号CK12。
其中，闸极阵列驱动讯号包含低频讯号LC，薄膜覆晶封装积体电路300包含低频讯号分离模组，通过低频讯号分离元件，将低频讯号LC转换为第一低频讯号LC1及第二低频讯号LC2。换言之，通过薄膜覆晶封装积体电路300运算后，低频讯号的讯号通道数目增加，达到增加面板驱动电路的设计灵活性及提高闸极驱动电路精准性的效果。
于本揭示的一实施例中，第二软性电路40板被配置为还包含控制闸极驱动电路扫描方向的扫描方向控制元件，通过接收扫描方向控制讯号控制扫描方向。或者，于本揭示的一实施例中，所述扫描方向控制元件耦合于薄膜覆晶封装积体电路300中。
其中，所述闸极阵列驱动讯号包含起始讯号ST，所述闸极第二软性电路板40被配置为包含起始讯号分离元件，所述起始讯号分离元件将所述起始讯号转换为第一起始讯号ST1及第二起始讯号ST2。换言之，通过将薄膜覆晶封装积体电路配置为输出的闸极阵列控制讯号包含第一起始讯号ST1及第二起始讯号ST2，达到增加面板驱动电路的设计灵活性及提高闸极驱动电路精准性的效果。或者，于本揭示的一实施例中，所述起始讯号分离元件耦合于薄膜覆晶封装积体电路300中。
其中，薄膜覆晶封装积体电路还包含接收其他控制讯号(Other Control Signal, OCS) OCS的讯号输入界面及输出其他输出通道讯号(Other output channel, OOC)OOC的讯号输出界面，通过述薄膜覆晶封装积体电路300设置讯号输入界面与讯号输出界面，达到增加面板驱动电路的设计灵活性的效果。或者，于本揭示的一实施例中，讯号输入界面及讯号输出界面直接设置在第二软性电路板40上并分别与移位暂存器310及输出缓冲器330电连接。
请参阅图4，图4显示根据本揭示的一实施例的薄膜覆晶封装积体电路400的方块示意图，其与图3实施例的差异在于，闸极阵列驱动讯号包含左起始讯号STV1L及右起始讯号STV1R。薄膜覆晶封装积体电路400包含起始讯号转换元件，起始讯号转换元件将左起始讯号STV1L及右起始讯号STV1R转换为第一起始讯号ST1及第二起始讯号ST2。换言之，通过将薄膜覆晶封装积体电路400配置为输出的闸极阵列控制讯号包含第一起始讯号ST1及第二起始讯号ST2，达到增加面板驱动电路的设计灵活性及提高闸极驱动电路精准性的效果。
于本揭示的一实施例中，起始讯号转换元件根据左起始讯号STV1L及右起始讯号STV1R的电压、电流、其他电性参数、讯号上升缘下降缘、及/或讯号频率转换而得到第一起始讯号ST1及第二起始讯号ST2。
由于本揭示所提供的显示面板，包括闸极阵列基板；第一软性电路板，与所述闸极阵列基板连接；印刷电路板，与所述第一软性电路板连接，设置有中心控制板，所述中心控制板输出闸极阵列驱动讯号；第二软性电路板，设置于所述闸极阵列基板的侧边缘；以及电平位移器，设置在所述第二软性电路板上，与所述中心控制板电连接，所述电平位移器抬升所述闸极阵列驱动讯号，达到降低面板制造成本，增加面板设计灵活性，以及控制闸极驱动电路的扫描方向的效果。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (20)

  1. 一种显示面板，包括:
    闸极阵列基板；
    第一软性电路板，与所述闸极阵列基板连接；
    印刷电路板，与所述第一软性电路板连接，设置有中心控制板，所述中心控制板输出闸极阵列驱动讯号；
    第二软性电路板，设置于所述闸极阵列基板的侧边缘；以及
    电平位移器，设置在所述第二软性电路板上，与所述中心控制板电连接，所述电平位移器抬升所述闸极阵列驱动讯号。
  2. 如权利要求1所述的显示面板，其中所述第二软性电路板还包括移位暂存器以及输出缓冲器，所述移位暂存器接收闸极阵列驱动讯号并产生暂存闸极阵列驱动讯号，所述电平位移器 抬升所述暂存闸极阵列驱动讯号后传输至所述输出缓冲器，由所述输出缓冲器输出闸极阵列控制讯号控制所述闸极阵列基板上的薄膜电晶体开启和关闭。
  3. 如权利要求2所述的显示面板，其中所述移位暂存器、所述电平位移器及所述输出缓冲器耦合为薄膜覆晶封装积体电路设置在所述第二软性电路板上。
  4. 如权利要求1所述的显示面板，其中所述闸极阵列控制讯号被配置为包含多个时脉控制讯号。
  5. 如权利要求4所述的显示面板，其中所述时脉控制讯号的数量是12个。
  6. 如权利要求1所述的显示面板，其中所述闸极阵列驱动讯号被配置为包含低频讯号，所述第二软性电路板被配置为还包含低频讯号分离元件，所述低频讯号分离元件被配置为用于将所述低频讯号转换为第一低频讯号及第二低频讯号。
  7. 如权利要求1所述的显示面板，其中所述第二软性电路板被配置为还包含控制所述闸极驱动电路扫描方向的扫描方向控制元件，通过接收扫描方向控制讯号控制扫描方向。
  8. 如权利要求7所述的显示面板，其中所述扫描方向控制元件还包含接收扫描方向控制讯号的接收单元。
  9. 如权利要求1所述的显示面板，其中所述闸极阵列驱动讯号被配置为包含起始讯号，所述第二软性电路板被配置为还包含起始讯号分离元件，所述起始讯号分离元件被配置为用于将所述起始讯号转换为第一起始讯号及第二起始讯号。
  10. 如权利要求1所述的显示面板，其中所述闸极阵列驱动讯号被配置为包含左起始讯号及右起始讯号，所述第二软性电路板被配置为还包含起始讯号转换元件，所述起始讯号转换元件被配置为用于将所述左起始讯号及右起始讯号转换为第一起始讯号及第二起始讯号。
  11. 一种显示面板，包括:
    闸极阵列基板；
    第一软性电路板，与所述闸极阵列基板连接；
    印刷电路板，与所述第一软性电路板连接，设置有中心控制板，所述中心控制板输出闸极阵列驱动讯号；
    第二软性电路板，设置于所述闸极阵列基板的侧边缘；以及
    电平位移器，设置在所述第二软性电路板上，与所述中心控制板电连接，所述电平位移器抬升所述闸极阵列驱动讯号；
    其中所述第二软性电路板还包括移位暂存器以及输出缓冲器，所述移位暂存器接收闸极阵列驱动讯号并产生暂存闸极阵列驱动讯号，所述电平位移器 抬升所述暂存闸极阵列驱动讯号后传输至所述输出缓冲器，由所述输出缓冲器输出闸极阵列控制讯号控制所述闸极阵列基板上的薄膜电晶体开启和关闭，所述闸极阵列控制讯号被配置为包含多个时脉控制讯号。
  12. 如权利要求11所述的显示面板，其中所述移位暂存器、所述电平位移器及所述输出缓冲器耦合为薄膜覆晶封装积体电路设置在所述第二软性电路板上。
  13. 如权利要求11所述的显示面板，其中所述时脉控制讯号的数量是12个。
  14. 如权利要求13所述的显示面板，其中所述闸极阵列驱动讯号被配置为包含低频讯号，所述第二软性电路板被配置为还包含低频讯号分离元件，所述低频讯号分离元件被配置为用于将所述低频讯号转换为第一低频讯号及第二低频讯号。
  15. 如权利要求11所述的显示面板，其中所述第二软性电路板被配置为还包含控制所述闸极驱动电路扫描方向的扫描方向控制元件，通过接收扫描方向控制讯号控制扫描方向。
  16. 如权利要求11所述的显示面板，其中所述扫描方向控制元件还包含接收扫描方向控制讯号的接收单元。
  17. 如权利要求11所述的显示面板，其中所述闸极阵列驱动讯号被配置为包含起始讯号，所述第二软性电路板被配置为还包含起始讯号分离元件，所述起始讯号分离元件被配置为用于将所述起始讯号转换为第一起始讯号及第二起始讯号。
  18. 如权利要求11所述的显示面板，其中所述闸极阵列驱动讯号被配置为包含左起始讯号及右起始讯号，所述第二软性电路板被配置为还包含起始讯号转换元件，所述起始讯号转换元件被配置为用于将所述左起始讯号及右起始讯号转换为第一起始讯号及第二起始讯号。
  19. 一种显示面板，包括:
    闸极阵列基板；
    第一软性电路板，与所述闸极阵列基板连接；
    印刷电路板，与所述第一软性电路板连接，设置有中心控制板，所述中心控制板输出闸极阵列驱动讯号；
    第二软性电路板，设置于所述闸极阵列基板的侧边缘；以及
    电平位移器，设置在所述第二软性电路板上，与所述中心控制板电连接，所述电平位移器抬升所述闸极阵列驱动讯号；
    其中所述扫描方向控制元件还包含接收扫描方向控制讯号的接收单元，所述闸极阵列驱动讯号被配置为包含起始讯号，所述第二软性电路板被配置为还包含起始讯号分离元件，所述起始讯号分离元件被配置为用于将所述起始讯号转换为第一起始讯号及第二起始讯号。
  20. 如权利要求19所述的显示面板，其中所述第二软性电路板还包括移位暂存器以及输出缓冲器，所述移位暂存器接收闸极阵列驱动讯号并产生暂存闸极阵列驱动讯号，所述电平位移器 抬升所述暂存闸极阵列驱动讯号后传输至所述输出缓冲器，由所述输出缓冲器输出闸极阵列控制讯号控制所述闸极阵列基板上的薄膜电晶体开启和关闭。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1841452A (zh) * 2005-03-30 2006-10-04 三洋爱普生映像元器件有限公司 显示装置
CN102110405A (zh) * 2009-12-24 2011-06-29 乐金显示有限公司 显示装置及控制其栅极脉冲调制的方法
KR20120100411A (ko) * 2011-03-04 2012-09-12 엘지디스플레이 주식회사 표시 장치
CN109712555A (zh) * 2019-02-25 2019-05-03 合肥京东方显示技术有限公司 控制电路板、附加电路板及显示装置
CN109859684A (zh) * 2017-11-30 2019-06-07 乐金显示有限公司 显示装置及其接口方法
CN110660370A (zh) * 2019-09-16 2020-01-07 昆山龙腾光电股份有限公司 信号调整电路和显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1571622A (zh) * 2003-07-18 2005-01-26 友达光电股份有限公司 分离式控制印刷电路板
KR20060020075A (ko) * 2004-08-31 2006-03-06 삼성전자주식회사 구동유닛 및 이를 갖는 표시장치
CN100454378C (zh) * 2004-11-19 2009-01-21 统宝光电股份有限公司 显示器的扫瞄线驱动装置及其显示装置
TW201317960A (zh) * 2011-10-28 2013-05-01 Au Optronics Corp 立體影像切換裝置及影像顯示裝置
KR102084716B1 (ko) * 2013-03-13 2020-03-05 삼성디스플레이 주식회사 표시 패널
CN106652929B (zh) * 2016-10-18 2019-11-05 武汉华星光电技术有限公司 显示模组及液晶显示屏
CN108417606B (zh) * 2018-03-21 2021-01-26 武汉华星光电半导体显示技术有限公司 基于柔性显示面板的全面屏显示装置
CN110619834B (zh) * 2019-08-20 2022-10-04 Tcl华星光电技术有限公司 多时脉电位转换电路及多时脉闸极驱动电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1841452A (zh) * 2005-03-30 2006-10-04 三洋爱普生映像元器件有限公司 显示装置
CN102110405A (zh) * 2009-12-24 2011-06-29 乐金显示有限公司 显示装置及控制其栅极脉冲调制的方法
KR20120100411A (ko) * 2011-03-04 2012-09-12 엘지디스플레이 주식회사 표시 장치
CN109859684A (zh) * 2017-11-30 2019-06-07 乐金显示有限公司 显示装置及其接口方法
CN109712555A (zh) * 2019-02-25 2019-05-03 合肥京东方显示技术有限公司 控制电路板、附加电路板及显示装置
CN110660370A (zh) * 2019-09-16 2020-01-07 昆山龙腾光电股份有限公司 信号调整电路和显示装置

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