WO2021184892A1 - 阵列基板及其驱动方法、显示装置 - Google Patents

阵列基板及其驱动方法、显示装置 Download PDF

Info

Publication number
WO2021184892A1
WO2021184892A1 PCT/CN2020/140310 CN2020140310W WO2021184892A1 WO 2021184892 A1 WO2021184892 A1 WO 2021184892A1 CN 2020140310 W CN2020140310 W CN 2020140310W WO 2021184892 A1 WO2021184892 A1 WO 2021184892A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
sub
control
control signal
transistor
Prior art date
Application number
PCT/CN2020/140310
Other languages
English (en)
French (fr)
Inventor
邢振周
王建军
董慧
刘媛媛
许俊波
袁先锋
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/432,888 priority Critical patent/US11763770B2/en
Publication of WO2021184892A1 publication Critical patent/WO2021184892A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method thereof, and a display device.
  • the liquid crystal display device mostly uses a polarity reversal driving method to drive the liquid crystal, so as to avoid the problem that the liquid crystal molecules are driven by a certain fixed voltage for a long period of time and cause voltage residue, which further affects the display effect.
  • a method for driving an array substrate includes: a plurality of sub-pixels, a plurality of gate lines, a plurality of data lines, a plurality of scanning signal transmission channels, at least one scanning control signal line, and a plurality of A data signal transmission channel, at least one data control signal line, a plurality of first control sub-circuits and a plurality of second control sub-circuits.
  • the plurality of sub-pixels are arranged in an array, one row of sub-pixels is coupled to one gate line, and one column of sub-pixels is coupled to one data line.
  • Each first control sub-circuit is coupled to the at least one scan control signal line, one scan signal transmission channel, and two gate lines; each second control sub-circuit is coupled to the at least one data control signal line and one data signal
  • the transmission channel is coupled with three data lines.
  • each first control sub-circuit The two rows of sub-pixels controlled by the two gate lines coupled to each first control sub-circuit are divided into a plurality of repeating units arranged in a row direction, and each repeating unit includes 6 sub-pixels arranged in 2 rows and 3 columns.
  • the driving method includes: one frame period includes a plurality of charging stages, and in each charging stage, 6 sub-pixels of each repeating unit controlled by two gate lines coupled to a first control sub-circuit are charged; each;
  • the charging phase includes 6 sub-charging phases, and each sub-pixel of each repeating unit is charged in each sub-charging phase.
  • the first control sub-circuit transmits the scan signal from the scan signal transmission channel to one of the two gate lines coupled to it under the control of the scan control signal transmitted by at least one scan control signal line Gate line to open a row of sub-pixels controlled by the gate line.
  • each second control sub-circuit transmits the data signal from the data signal transmission channel to a data line coupled to each repeating unit to control each repeating unit.
  • One of the sub-pixels is charged.
  • the data signal transmitted by each data signal transmission channel alternately changes between positive and negative voltages
  • the duration of the positive voltage and the negative voltage is three sub-charging stages
  • the data signal transmitted by any two adjacent data signal transmission channels The voltage has opposite polarity in the same sub-charging phase.
  • the 6 sub-pixels included in each repeating unit are respectively the first sub-pixel, the second sub-pixel, the third sub-pixel, the fourth sub-pixel, and the fifth sub-pixel in a clockwise or counter-clockwise order.
  • the 6 sub-charging stages included in each charging stage are the first sub-charging stage, the second sub-charging stage, the third sub-charging stage, the fourth sub-charging stage, the fifth sub-charging stage, and the sixth sub-charging stage. .
  • the first control sub-circuit transmits the scan signal from the scan signal transmission channel to the two coupled scan control signals under the control of the scan control signal transmitted by the at least one scan control signal line.
  • the first gate line in the gate line opens a row of sub-pixels controlled by the gate line.
  • Each second control sub-circuit transmits the data signal from the data signal transmission channel to the first of the three data lines coupled to each repeating unit under the control of the data control signal transmitted by the at least one data control signal line. Data lines to charge the first sub-pixel in each repeating unit.
  • the first control sub-circuit transmits the scan signal from the scan signal transmission channel to the two coupled scan signals under the control of the scan control signal transmitted by the at least one scan control signal line.
  • the first gate line in the gate line opens a row of sub-pixels controlled by the gate line.
  • each second control sub-circuit transmits the data signal from the data signal transmission channel to the third of the three data lines coupled to each repeating unit. Data lines to charge the third sub-pixel in each repeating unit.
  • the first control sub-circuit transmits the scan signal from the scan signal transmission channel to the two coupled scan control signals under the control of the scan control signal transmitted by the at least one scan control signal line.
  • the second gate line in the gate line opens a row of sub-pixels controlled by the gate line.
  • each second control sub-circuit transmits the data signal from the data signal transmission channel to the second one of the three data lines coupled to each repeating unit. Data lines to charge the fifth sub-pixel in each repeating unit.
  • the first control sub-circuit transmits the scan signal from the scan signal transmission channel to the two coupled scan control signals under the control of the scan control signal transmitted by the at least one scan control signal line.
  • the second gate line in the gate line opens a row of sub-pixels controlled by the gate line.
  • Each second control sub-circuit transmits the data signal from the data signal transmission channel to the first of the three data lines coupled to each repeating unit under the control of the data control signal transmitted by the at least one data control signal line. Data lines to charge the fourth sub-pixel in each repeating unit.
  • the first control sub-circuit transmits the scan signal from the scan signal transmission channel to the two coupled scan signals under the control of the scan control signal transmitted by the at least one scan control signal line.
  • the second gate line in the gate line opens a row of sub-pixels controlled by the gate line.
  • each second control sub-circuit transmits the data signal from the data signal transmission channel to the third of the three data lines coupled to each repeating unit. Data lines to charge the sixth sub-pixel in each repeating unit.
  • the first control sub-circuit transmits the scan signal from the scan signal transmission channel to the two coupled scan control signals under the control of the scan control signal transmitted by the at least one scan control signal line.
  • the first gate line in the gate line opens a row of sub-pixels controlled by the gate line.
  • each second control sub-circuit transmits the data signal from the data signal transmission channel to the second one of the three data lines coupled to each repeating unit. Data lines to charge the second sub-pixels in each repeating unit.
  • the first sub-pixel, the third sub-pixel, and the fifth sub-pixel in the odd-numbered repeating unit are charged with the first voltage
  • the second sub-pixel, the fourth sub-pixel, and the sixth sub-pixel are charged with the second voltage.
  • the first sub-pixel, the third sub-pixel and the fifth sub-pixel in the even-numbered repeating unit are charged with the second voltage
  • the second sub-pixel, the fourth sub-pixel and the sixth sub-pixel are charged with the first voltage.
  • the polarities of the first voltage and the second voltage are opposite.
  • the at least one scan control signal line includes a first scan control signal line and a second scan control signal line
  • the first control sub-circuit includes a first transistor and a second transistor
  • the first scan control signal transmitted by the first transistor in the first control sub-circuit on the first scan control signal line Is turned on under the control of, and transmits the scan signal from the scan signal transmission channel to the gate line to which it is coupled.
  • the second transistor in the first control sub-circuit transmits the second scan control on the second scan control signal line
  • the signal is turned on under the control of the signal, and the scan signal from the scan signal transmission channel is transmitted to the gate line to which it is coupled.
  • the at least one data control signal line includes a first data control signal line, a second data control signal line, and a third data control signal line
  • the second control sub-circuit includes a third transistor, a In the case of four transistors and a fifth transistor, in the first sub-charging phase, the third transistor in each second control sub-circuit is under the control of the first data control signal transmitted by the first data control signal line
  • the data signal from the data signal transmission channel is transmitted to the first data line of the three data lines corresponding to each repeating unit, so as to charge the first sub-pixel in each repeating unit.
  • the fifth transistor in each second control sub-circuit is turned on under the control of the third data control signal transmitted by the third data control signal line, and the signal from the data signal transmission channel is turned on.
  • the data signal is transmitted to the third data line among the three data lines corresponding to each repeating unit to charge the third sub-pixel in each repeating unit.
  • the fourth transistor in each second control sub-circuit is turned on under the control of the second data control signal transmitted by the second data control signal line, and the signal from the data signal transmission channel is turned on.
  • the data signal is transmitted to the second data line of the three data lines corresponding to each repeating unit to charge the fifth sub-pixel in each repeating unit.
  • the third transistor in each second control sub-circuit is turned on under the control of the first data control signal transmitted by the first data control signal line, and the data from the data signal transmission channel is turned on.
  • the data signal is transmitted to the first data line of the three data lines corresponding to each repeating unit to charge the fourth sub-pixel in each repeating unit.
  • the fifth transistor in each second control sub-circuit is turned on under the control of the third data control signal transmitted by the third data control signal line, and the signal from the data signal transmission channel is turned on.
  • the data signal is transmitted to the third data line among the three data lines corresponding to each repeating unit to charge the sixth sub-pixel in each repeating unit.
  • the fourth transistor in each second control sub-circuit is turned on under the control of the second data control signal transmitted by the second data control signal line, and the signal from the data signal transmission channel is turned on.
  • the data signal is transmitted to the second data line of the three data lines corresponding to each repeating unit to charge the second sub-pixel in each repeating unit.
  • the at least one data control signal line includes a first data control signal line and a second data control signal line
  • the second control sub-circuit includes a third transistor, a fourth transistor, and a switching unit
  • the third transistor in each second control sub-circuit is turned on under the control of the first data control signal transmitted by the first data control signal line to transmit the data signal
  • the data signal of the channel is transmitted to the first data line of the three data lines corresponding to each repeating unit to charge the first sub-pixel in each repeating unit.
  • the switch unit in each second control sub-circuit transmits the first data control signal on the first data control signal line and the second data control signal transmitted on the second data control signal line.
  • the data control signal is turned on under the control of the data signal transmission channel to transmit the data signal from the data signal transmission channel to the third data line of the three data lines corresponding to each repeating unit to charge the third sub-pixel in each repeating unit.
  • the fourth transistor in each second control sub-circuit is turned on under the control of the second data control signal transmitted by the second data control signal line, and the signal from the data signal transmission channel is turned on.
  • the data signal is transmitted to the second data line of the three data lines corresponding to each repeating unit to charge the fifth sub-pixel in each repeating unit.
  • the third transistor in each second control sub-circuit is turned on under the control of the first data control signal transmitted by the first data control signal line, and the data from the data signal transmission channel is turned on.
  • the data signal is transmitted to the first data line of the three data lines corresponding to each repeating unit to charge the fourth sub-pixel in each repeating unit.
  • the first data control signal transmitted by the switch unit in each second control sub-circuit on the first data control signal line and the second data control signal transmitted by the second data control signal line The data control signal is turned on under the control of the data signal transmission channel to transmit the data signal from the data signal transmission channel to the third data line of the three data lines corresponding to each repeating unit to charge the sixth sub-pixel in each repeating unit.
  • the fourth transistor in each second control sub-circuit is turned on under the control of the second data control signal transmitted by the second data control signal line, and the signal from the data signal transmission channel is turned on.
  • the data signal is transmitted to the second data line of the three data lines corresponding to each repeating unit to charge the second sub-pixel in each repeating unit.
  • an array substrate including: a plurality of sub-pixels, a plurality of gate lines, a plurality of data lines, a plurality of scan signal transmission channels, at least one scan control signal line, a plurality of data signal transmission channels, at least one data line A control signal line, a plurality of first control sub-circuits and a plurality of second control sub-circuits.
  • the plurality of sub-pixels are arranged in an array, one row of sub-pixels is coupled to one gate line, and one column of sub-pixels is coupled to one data line.
  • Each first control sub-circuit is coupled to the at least one scan control signal line, one scan signal transmission channel, and two gate lines; the first control sub-circuit is configured to connect to the at least one scan control signal line Under the control of the transmitted scan control signal, the scan signal transmitted by the scan signal transmission channel to which it is coupled is respectively transmitted to the two gate lines to which it is coupled, so as to turn on the two coupled to the two gate lines in a time-sharing manner.
  • Row sub-pixels are coupled to the at least one scan control signal line, one scan signal transmission channel, and two gate lines; the first control sub-circuit is configured to connect to the at least one scan control signal line Under the control of the transmitted scan control signal, the scan signal transmitted by the scan signal transmission channel to which it is coupled is respectively transmitted to the two gate lines to which it is coupled, so as to turn on the two coupled to the two gate lines in a time-sharing manner.
  • Each second control sub-circuit is coupled to the at least one data control signal line, one data signal transmission channel, and three data lines; the second control sub-circuit is configured to transmit on the at least one data control signal line Under the control of the data control signal, the data signal transmitted by the data signal transmission channel to which it is coupled is respectively transmitted to the three data lines to which it is coupled to time-sharing the sub-pixels coupled to the three data lines.
  • the sub-pixels whose gate lines are turned on are charged.
  • the plurality of sub-pixels are arranged in 2n rows and 3m columns; the array substrate includes 2n gate lines, 3m data lines, n scan signal transmission channels, m data signal transmission channels, and two scans.
  • the i-th first control sub-circuit is coupled to the i-th scan signal transmission channel, the 2i-1th gate line and the 2ith gate line; among them, 1 ⁇ i ⁇ n, i is a positive integer; the jth The second control sub-circuit is coupled to the j-th data signal transmission channel, the 3j-2th data line, the 3j-1th data line, and the 3jth data line; wherein, 1 ⁇ j ⁇ m, and j is a positive integer.
  • the at least one scan control signal line includes a first scan control signal line and a second scan control signal line; each of the first control sub-circuits includes a first transistor and a second transistor.
  • control electrode of the first transistor is coupled to the first scan control signal line, and the first electrode of the first transistor is coupled to the scan signal transmission channel coupled to the first control sub-circuit,
  • the second electrode of the first transistor is coupled to one of the two gate lines coupled to the first control sub-circuit.
  • the control electrode of the second transistor is coupled to the second scan control signal line, the first electrode of the second transistor is coupled to the scan signal transmission channel coupled to the first control sub-circuit, the The second electrode of the second transistor is coupled to the other of the two gate lines coupled to the first control sub-circuit.
  • the at least one data control signal line includes a first data control signal line and a second data control signal line; each of the second control sub-circuits includes a third transistor and a fourth transistor.
  • control electrode of the third transistor is coupled to the first data control signal line, and the first electrode of the third transistor is coupled to the data signal transmission channel coupled to the second control sub-circuit,
  • the second electrode of the third transistor is coupled to the first data line of the three data lines coupled to the second control sub-circuit.
  • the control electrode of the fourth transistor is coupled to the second data control signal line, the first electrode of the fourth transistor is coupled to the data signal transmission channel coupled to the second control sub-circuit, the The second electrode of the fourth transistor is coupled to the second data line of the three data lines coupled to the second control sub-circuit.
  • the at least one data control signal line further includes a third data control signal line; each of the second control sub-circuits further includes a fifth transistor.
  • control electrode of the fifth transistor is coupled to the third data control signal line
  • first electrode of the fifth transistor is coupled to the data signal transmission channel coupled to the second control sub-circuit
  • second electrode of the fifth transistor is coupled to the third data line of the three data lines coupled to the second control sub-circuit.
  • the second control sub-circuit further includes a switch unit that is coupled to the first data control signal line and the second data control signal line, and the switch unit is also connected to the first data control signal line and the second data control signal line.
  • the data signal transmission channel coupled to the second control sub-circuit is coupled to the third data line among the three data lines coupled to the second control sub-circuit.
  • the switch unit is configured to couple the first data control signal transmitted by the first data control signal line and the second data control signal transmitted by the second data control signal line.
  • the data signal transmitted by the data signal transmission channel is transmitted to the data line to which it is coupled.
  • the switch unit includes a sixth transistor and a seventh transistor, wherein the control electrode of the sixth transistor is coupled to the first data control signal line, and the first electrode of the sixth transistor The second electrode of the sixth transistor is coupled to the first electrode of the seventh transistor.
  • the control electrode of the seventh transistor is coupled to the second data control signal line, and the second electrode of the seventh transistor is coupled to the data line coupled to the switch unit.
  • the sixth transistor and the seventh transistor are of the same type
  • the third transistor and the fourth transistor are of the same type
  • the sixth transistor and the seventh transistor are of the same type It is different from the type of the third transistor and the fourth transistor.
  • the switch unit includes a NAND gate circuit and an eighth transistor.
  • the NAND gate circuit is coupled to the first data control signal line, the second data control signal line and the control electrode of the eighth transistor.
  • the NAND gate circuit is configured to output under the control of the first data control signal transmitted by the first data control signal line and the second data control signal transmitted by the second data control signal line A control signal for controlling the conduction of the eighth transistor.
  • the first pole of the eighth transistor is coupled to the data signal transmission channel coupled to the switch unit, and the second pole of the eighth transistor is coupled to the data line coupled to the switch unit.
  • the third transistor, the fourth transistor and the eighth transistor are of the same type.
  • the at least one scan control signal line extends along a column direction in which the plurality of sub-pixels are arranged, and the at least one data control signal line extends along a row direction in which the plurality of sub-pixels are arranged.
  • each sub-pixel includes a driving transistor; when the first control sub-circuit includes a first transistor and a second transistor, and the second control sub-circuit includes a third transistor and a fourth transistor, the first control sub-circuit includes a third transistor and a fourth transistor.
  • the gate, active layer, and source and drain of a transistor, the second transistor, the third transistor, and the fourth transistor are respectively connected to the gate, active layer, and source of the driving transistor
  • the electrode and the drain electrode are arranged on the same layer.
  • a display device including: the array substrate, the gate driving circuit, and the source driving circuit as described in any one of the above aspects.
  • the gate driving circuit has a plurality of scan signal output channels and at least one scan control signal output channel, each scan signal output channel is coupled to one scan signal transmission channel in the array substrate, and each scan control signal output channel It is coupled to a scan control signal line in the array substrate.
  • the source driving circuit includes a plurality of data signal output channels and at least one data control signal output channel, each data signal output channel is coupled to a data signal transmission channel in the array substrate, and each data control signal output The channel is coupled to a data control signal line in the array substrate.
  • the gate drive circuit includes two scan control signal output channels, and the source drive circuit includes two or three data control signal output channels.
  • FIG. 1 is a structural diagram of an array substrate according to some embodiments of related technologies
  • FIG. 2 is a structural diagram of a display device according to some embodiments of related technologies
  • FIG. 3 is a timing diagram of a driving method of an array substrate according to some embodiments of the related art
  • FIG. 4 is a structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 5 is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 6 is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 7 is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a timing diagram of a driving method of an array substrate according to some embodiments of the present disclosure.
  • FIG. 9 is another timing diagram of a driving method of an array substrate according to some embodiments of the present disclosure.
  • FIG. 10 is a charging sequence diagram of some sub-pixels in an array substrate according to some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the array substrate 20' in the liquid crystal display device includes: a plurality of sub-pixels 1 arranged in an array, a plurality of gate lines 2 and a plurality of data lines 3, each gate Line 2 is coupled to a row of sub-pixels 1, each data line 3 is coupled to a column of sub-pixels 1, a plurality of sub-pixels 1, a plurality of gate lines 2 and a plurality of data lines 3 are arranged on the base substrate in the array substrate 20' 201 on.
  • the liquid crystal display device 30' also includes a source drive circuit 302 and a gate drive circuit 301.
  • the source drive circuit 302 is connected to the array substrate 20' by bonding
  • the gate drive circuit 301 is connected to the array substrate 20' by bonding. It is connected to the array substrate 20' in a bonding manner, or the gate driving circuit 301 is integrated on the array substrate in a GOA (Gate on Array) manner.
  • GOA Gate on Array
  • the gate driving circuit 301 has a plurality of scanning signal output channels 3011, and each scanning signal output channel 3011 is coupled to a gate line 2 for outputting a scanning signal to the gate line 2 to open a row controlled by the gate line 2 Sub pixel 1.
  • the multiple scan signal output channels 3011 of the gate drive circuit 301 refer to the output terminals of the gate drive circuit 301, that is, the gate The signal output terminals of a plurality of shift registers included in the pole driving circuit 301.
  • the source driving circuit 302 has a plurality of data signal output channels 3021, and each data signal output channel 3021 is coupled to a data line 3 for outputting a data signal to the data line 3 to control one of the data lines 3
  • the turned-on sub-pixel 1 in the column of sub-pixels 1 is charged.
  • the scan signal output channels 3011 of the gate drive circuit 301 and the number of gate lines 2 in the array substrate 20' are equal, and the data signal output channels 3021 of the source drive circuit 302 are equal to the number of the data lines 3 in the array substrate 20'.
  • the number is equal.
  • the array substrate 20' includes 2n ⁇ 3m sub-pixels 1, 2n gate lines 2 and 3m data lines 3.
  • the gate driving circuit 301 has 2n scanning signal output channels 3011, and the source The driving circuit 302 has 3m data signal output channels 3021.
  • the commonly used polarity inversion driving methods for liquid crystal display devices include: Frame inversion, Row inversion, Column inversion, and Dot inversion. inversion).
  • the dot inversion method is that in one frame period, the voltages of the data signals charged in every two adjacent sub-pixels 1 have opposite polarities.
  • the dot inversion method has the advantages of less crosstalk and flicker, which can greatly improve the quality of the picture displayed by the display device and is widely used.
  • the driving process of the array substrate 20' shown in FIG. 1 in the dot inversion mode is: a frame period includes 2n charging stages s, respectively s1 to s2n, and each charging stage s pairs One row of sub-pixels 1 is charged.
  • a frame period includes 2n charging stages s, respectively s1 to s2n, and each charging stage s pairs One row of sub-pixels 1 is charged.
  • FIG. 3 only the first four charging stages s1 to s4 are shown, and the four charging stages s1 to s4 respectively charge the sub-pixels 1 in the first row to the fourth row.
  • the 2n scan signal output channels 3011 of the gate driving circuit 301 output scan signals one by one, so that the 2n gate lines 2 sequentially receive the scan signals, and the 2n rows of sub-pixels 1 are sequentially turned on.
  • the 3m data signal output channels 3021 of the source driver circuit 302 continuously output data signals, and each data signal output channel 3021 continues to output the data signal level alternately between positive and negative, and the duration of the positive voltage and the negative voltage is one.
  • the voltages of the data signals output by any two adjacent data signal output channels 3021 have opposite polarities in the same charging phase, and the duration of each level is one charging phase.
  • a corresponding gate line 2 receives the scan signal, turns on its corresponding row of sub-pixels 1, 3m data lines 3 receive data signals, and charges the data signals into the opened row.
  • the charging of the sub-pixels 1 in 2n rows is completed, and according to the level change mode of the data signal in the timing chart shown in FIG. 2, as shown in FIG. 1, in the multiple In each sub-pixel 1, the positive and negative polarities of the voltage charged in every two adjacent sub-pixels 1 are opposite, thereby realizing dot inversion.
  • the number of scanning signal output channels 3011 of the gate drive circuit 301 required is equal to the number of gate lines 2 (both are 2n), and the data signal output of the source drive circuit 302 is required
  • the number of channels 3021 is equal to the number of data lines 3 (both are 3m), and a larger number of channels increases the cost of the source driving circuit 302 and the gate driving circuit 301.
  • one frame period includes 2n charging stages s, and each charging stage charges a row of sub-pixels 1.
  • the data signal output by each data signal output channel 3021 of the source driving circuit 302 needs to switch between the positive and negative polarity of the voltage, that is, every charging stage s, each of the source driving circuit 302
  • the data signal output by the data signal output channels 3021 will switch between the positive and negative voltages after each sub-pixel 1 is charged.
  • the switching frequency is relatively high, and there are 3m data lines 3 and 3m data signals.
  • the output channel 3021 has a one-to-one correspondence, that is, every time each data line 3 charges a sub-pixel 1, the voltage on it will switch between positive and negative polarity.
  • the main source of panel power consumption The switching of the voltage polarity of the data signal received on the data line 3 greatly increases the power consumption of the liquid crystal display device 30'.
  • an array substrate 20 including: a plurality of sub-pixels 1, a plurality of gate lines 2, a plurality of data lines 3, and a plurality of scanning signal transmissions Channel 4, at least one scan control signal line 5, multiple data signal transmission channels 6, at least one data control signal line 7, multiple first control sub-circuits 8 and multiple second control sub-circuits 9.
  • each gate line 2 is coupled to a row of sub-pixels 1
  • each data line 3 is coupled to a column of sub-pixels 1.
  • the plurality of sub-pixels 1 are arranged in 2n rows and 3m columns, the number of the plurality of sub-pixels 1 is 2n ⁇ 3m, and the array substrate 20 includes 2n gate lines 2 and 3m data lines 3, wherein , N and m are positive integers.
  • Each first control sub-circuit 8 is coupled to the at least one scan control signal line 5, one scan signal transmission channel 4, and two gate lines 2, that is, one scan signal transmission channel 4 corresponds to two gate lines 2, as shown in FIG.
  • the array substrate 20 includes n scanning signal transmission channels 4.
  • the first control sub-circuit 8 is configured to, under the control of the scan control signal transmitted by the at least one scan control signal line 5, transmit the scan signal transmitted by the scan signal transmission channel 4 to which it is coupled, respectively.
  • the two connected gate lines 2 turn on the two rows of sub-pixels 1 coupled to the two gate lines 2 in a time-sharing manner.
  • Each second control sub-circuit 9 is coupled to the at least one data control signal line 7, one data signal transmission channel 6 and three data lines 3, that is, one data signal transmission channel 6 corresponds to three data lines 3, as shown in FIG.
  • the array substrate 20 includes m data signal transmission channels 6.
  • the second control sub-circuit 9 is configured to, under the control of the data control signal transmitted by the at least one data control signal line 7, respectively transmit the data signal transmitted by the data signal transmission channel 6 to which it is coupled
  • the three connected data lines 3 charge the sub-pixel 1 opened by the gate line 2 among the sub-pixels 1 coupled to the three data lines 3 in a time-sharing manner.
  • the array substrate 20 includes n scanning signal transmission channels 4, m data signal transmission channels 6, two scanning control signal lines 5, at least two data control signal lines 7, and n first control sub-circuits 8. And m second control sub-circuit 9.
  • the i-th first control sub-circuit 8 is coupled to the i-th scan signal transmission channel 4, the 2i-1th gate line 2 and the 2ith gate line 2; wherein, 1 ⁇ i ⁇ n, and i is a positive integer.
  • the i-th first control sub-circuit 8 is configured to transmit the scan of the i-th scan signal transmission channel 4 to which it is coupled under the control of the scan control signals transmitted by the two scan control signal lines 5
  • the signals are respectively transmitted to the 2i-1th gate line 2 and the 2ith gate line 2 to which they are coupled, so as to turn on the sub-pixels in the 2i-1th row and the 2ith row coupled by the two gate lines 2 in time division. 1.
  • the j-th second control sub-circuit 9 is coupled to the j-th data signal transmission channel 6, the 3j-2th data line 3, the 3j-1th data line 3, and the 3jth data line 3; wherein, 1 ⁇ j ⁇ m, j is a positive integer.
  • the j-th second control sub-circuit 9 is configured to transmit the j-th data signal transmission channel 6 to which it is coupled under the control of the data control signals transmitted by the at least two data control signal lines 7
  • the data signals are respectively transmitted to the 3j-2th data line 3, the 3j-1th data line 3, and the 3jth data line 3 to which they are coupled, so as to time-sharing the third data line 3 coupled to the three data lines 3
  • the sub-pixel 1 opened by the gate line 2 among the sub-pixels 1 in rows 3j-2, 3j-1, and 3j is charged.
  • some embodiments of the present disclosure also provide a display device 30.
  • the display device 30 includes the above-mentioned array substrate 20, a gate drive circuit 301 and a source drive circuit 302, wherein the source drive circuit 302
  • the gate driving circuit 301 is connected to the array substrate 20 in a bonding manner, and the gate driving circuit 301 is connected to the array substrate 20 in a bonding manner, or the gate driving circuit 301 is integrated on the array substrate in a GOA (Gate on Array) manner.
  • GOA Gate on Array
  • the gate driving circuit 301 has a plurality of scanning signal output channels 3011, and each scanning signal output channel 3011 is coupled to one scanning signal transmission channel 4 in the array substrate 20.
  • the source driving circuit 302 includes a plurality of data signal output channels 3021, and each data signal output channel 3021 is coupled to one data signal transmission channel 6 in the array substrate 20.
  • the gate driving circuit 301 also has at least one scan control signal output channel 3012, and each scan control signal output channel 3012 is coupled to one scan control signal line 5 in the array substrate 20.
  • the source driving circuit 302 also includes at least one data control signal output channel 3022, and each data control signal output channel 3022 is coupled to one data control signal line 7 in the array substrate 20.
  • the number of scan signal output channels 3011 of the gate drive circuit 301 required is equal to the number of scan signal transmission channels 4 in the array substrate 20 (both are n), and the required source drive
  • the number of data signal output channels 3021 of the circuit 302 is equal to the number of data signal transmission channels 6 in the array substrate 20 (both are m).
  • the gate drive circuit 301 in the display device 30' The number of scan signal output channels 3011 is 2n, and the number of data signal output channels 3021 of the source drive circuit 302 is 3m.
  • the scan signal of the gate drive circuit 301 The number of output channels 3011 is reduced by half, and the number of data signal output channels 3021 of the source driving circuit 302 is reduced by 2/3, thereby reducing the cost of the source driving circuit 302 and the gate driving circuit 301, and reducing the cost of the display device cost.
  • the driving method of the above-mentioned array substrate 20 is:
  • each repeating unit D includes 6 sub-pixels 1 arranged in 2 rows and 3 columns.
  • the array substrate 20 includes 2n ⁇ 3m sub-pixels 1, and the two rows of sub-pixels 1 controlled by the two gate lines 2 coupled to each first control sub-circuit 8 are divided into With m repeating units D, all sub-pixels 1 included in the array substrate 20 are divided into m ⁇ n repeating units D.
  • the driving method includes:
  • a frame period includes multiple charging stages T.
  • 6 sub-pixels 1 of each repeating unit D controlled by two gate lines 2 coupled to a first control sub-circuit 8 are charged.
  • the 6 sub-pixels 1 of each repeating unit D controlled by the two gate lines 2 coupled to the i-th first control sub-circuit 8 are charged.
  • Each charging phase T includes 6 sub-charging phases t, and one sub-pixel 1 of each repeating unit D is charged in each sub-charging phase t.
  • the array substrate 20 includes 2n ⁇ 3m sub-pixels 1, 2n gate lines 2, n scanning signal transmission channels 4, and n first control sub-circuits. 8. That is, one frame period includes n charging phases T, and in each charging phase T, two rows of sub-pixels 1 controlled by two gate lines 2 coupled by a first control sub-circuit 8 are charged, so as to achieve The 2n rows of sub-pixels 1 controlled by the 2n gate lines 2 coupled to the n first control sub-circuits 8 are charged in one frame period, so that all the sub-pixels 1 included in the array substrate 20 are charged with voltage.
  • the first control sub-circuit 8 transmits the scan signal from the scan signal transmission channel 4 to the two gates coupled to it under the control of the scan control signal transmitted by at least one scan control signal line 5.
  • a gate line 2 in the line 2 opens a row of sub-pixels 1 controlled by the gate line 2.
  • Each second control sub-circuit 9 transmits the data signal from the data signal transmission channel 6 to one data line 3 to which each repeating unit D is coupled under the control of the data control signal transmitted by at least one data control signal line 7. To charge one sub-pixel 1 in each repeating unit D.
  • each sub-charging phase t one row of sub-pixels 1 in the two rows of sub-pixels 1 corresponding to the two gate lines 2 coupled by a first control sub-circuit 8 is turned on.
  • One sub-pixel 1 in each repeating unit D is charged, that is, the two rows of sub-pixels 1 controlled by the two gate lines 2 are divided into m repeating units D.
  • each sub-pixel 1 is charged
  • stage t a total of m sub-pixels 1 are charged with voltage.
  • 6 sub-charging stages included in one charging stage 6 sub-pixels 1 in the m repeating units D are charged with voltage in turn.
  • the data signal transmitted by each data signal transmission channel 6 alternately changes between positive and negative voltages
  • the duration of the positive voltage and the negative voltage is three sub-charging phases t
  • any two adjacent data signal transmission channels 6 transmit
  • the voltage of the data signal has opposite polarity in the same sub-charging phase.
  • the timing of the data signal source1 transmitted by the first data signal transmission channel 6 is that the voltage is positive during the first three sub-charging phases t1 to t3.
  • the voltage is negative;
  • the time sequence of the data signal source2 transmitted by the second data signal transmission channel 6 is that in the first three sub-charging stages t1 ⁇ t3, the negative voltage is
  • the charging stage t4 ⁇ t6 is at a positive voltage. That is, the data signal transmitted by each data signal transmission channel 6 undergoes a voltage polarity switch every three sub-charging phases t.
  • the dot inversion driving method is adopted.
  • the three sub-pixels 1 charged in each repeating unit D are mutually exclusive
  • the charged voltages are all positive or negative voltages.
  • the three sub-pixels 1 charged in each repeating unit D are not adjacent to each other, And the charged voltages are all negative voltages or positive voltages, so that in each repeating unit D, the positive and negative polarities of the charged voltages of every two adjacent sub-pixels 1 are opposite.
  • the sub-pixel 1 at the same position The polarity of the charged voltage is opposite, so that in one frame period, after all sub-pixels 1 are charged, the positive and negative polarities of the charged voltages of every two adjacent sub-pixels 1 are opposite, so that sub-pixel 1 is realized. The points are reversed.
  • one frame period includes n charging phases T, and in each charging phase T, two rows controlled by two gate lines 2 coupled to a first control sub-circuit 8 are controlled.
  • the sub-pixel 1 is charged; in each sub-charging stage t, one sub-pixel 1 in each of the corresponding repeating units D in the two rows of sub-pixels 1 is charged, so that the two rows of sub-pixels 1 in one charging stage T are completed.
  • the 6 sub-pixels 1 in each of the corresponding repeating units D are charged, and the charging of all the sub-pixels 1 in the array substrate 20 is completed within one frame period.
  • the data signal transmitted by each data signal transmission channel 6 undergoes a voltage polarity switch every three sub-charging phases t, that is, in each charging phase T, each data signal transmission channel 6
  • the transmitted data signal will switch between the positive and negative polarity of the voltage after each time the three sub-pixels 1 are charged, so that the voltage on each data line 3 is switched at an interval of three sub-pixels in a repeating unit D.
  • the charging time of the pixel 1 is compared with the array substrate 20' in the related art. After each sub-pixel 1 is charged each time, the positive and negative voltages of each data line 3 are switched.
  • the present disclosure provides In the driving method corresponding to the array substrate 20, the switching frequency of the positive and negative polarity of the voltage in each data line 3 is reduced, so that the power consumption of the display device can be reduced.
  • every three data lines 3 correspond to a data signal transmission channel 6, and the data signal transmitted by each data signal transmission channel 6 undergoes a voltage polarity change every three sub-charging stages t.
  • the three data lines respectively receive the data signals in the three sub-charging phases t, so that the driving method corresponding to the array substrate 20 provided in the present disclosure is compared with the driving method corresponding to the array substrate 20' in the related art.
  • the switching frequency of the voltage polarity on each data line in the present disclosure is one third of the switching frequency of the voltage polarity on each data line in the related art.
  • the driving method of the array substrate 20 provided by some embodiments of the present disclosure can reduce the data signal transmitted by each data signal transmission channel 6 on the basis of improving the flicker and crosstalk phenomenon by using the dot driving method and improving the display effect. Therefore, the switching frequency of the voltage polarity on the corresponding data line 3 is reduced, and the effect of reducing the power consumption of the display panel is realized.
  • a specific driving method of the aforementioned array substrate 20 includes:
  • the 24 sub-pixels 1 are divided into 4 repeating units D, and the four repeating units D follow from the left To the right, the order from top to bottom is the first repeating unit D1, the second repeating unit D2, the third repeating unit D3, and the fourth repeating unit D4.
  • the 6 sub-pixels 1 included in each repeating unit D are respectively These are the first sub-pixel 11, the second sub-pixel 12, the third sub-pixel 13, the fourth sub-pixel 14, the fifth sub-pixel 15, and the sixth sub-pixel 16.
  • each repeating unit D is the first sub-pixel 11, and the remaining five sub-pixels are sequentially numbered from left to right and top to bottom as The second sub-pixel 12, the third sub-pixel 13, the fourth sub-pixel 14, the fifth sub-pixel 15, and the sixth sub-pixel 16.
  • the first gate line 2 and the second gate line 2 of the two gate lines 2 mentioned below are numbered in the order from top to bottom.
  • the three data lines 3 The first data line 3, the second data line 3, and the second data line 3 are numbered from left to right.
  • the 6 sub-charging stages t included in each charging stage T are the first sub-charging stage t1, the second sub-charging stage t2, the third sub-charging stage t3, and the fourth sub-charging stage. t4, the fifth sub-charging phase t5 and the sixth sub-charging phase t6.
  • the first charging stage T1 as an example, the 6 sub-charging stages t included in it will be introduced.
  • the first first control sub-circuit 8 transmits the scan signal Gate1 from the first scan signal transmission channel 4 to the two coupled to it.
  • the first gate line 2 of the gate lines 2 opens a row of sub-pixels 1 controlled by the gate line 2 (that is, the first row of sub-pixels 1 in FIG. 10).
  • Each second control sub-circuit 9 transmits the data signal from the data signal transmission channel 6 to the three data lines coupled to each repeating unit D under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the first data line 3 in 3 is to charge the first sub-pixel 11 in each repeating unit D.
  • the first second control sub-circuit 9 transmits data from the first data signal transmission channel under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the data signal Source1 of 6 is transmitted to the first data line 3 of the three data lines 3 coupled to the first repeating unit D1 to charge the first sub-pixel 11 in the first repeating unit D1, and is charged with a positive voltage .
  • the second second control sub-circuit 9 transmits the data signal Source2 from the second data signal transmission channel 6 to the second repeating unit under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the first data line 3 of the three data lines 3 coupled to D2 is to charge the first sub-pixel 11 in the second repeating unit D2, and is charged with a negative voltage.
  • the first first control sub-circuit 8 transmits the scan signal Gate1 from the first scan signal transmission channel 4 to the two coupled to it.
  • the first gate line 2 of the gate lines 2 opens a row of sub-pixels 1 controlled by the gate line 2 (that is, the first row of sub-pixels 1 in FIG. 10).
  • Each second control sub-circuit 9 transmits the data signal from the data signal transmission channel 6 to the three data lines coupled to each repeating unit D under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the third data line 3 in 3 is used to charge the third sub-pixel 13 in each repeating unit D.
  • the first second control sub-circuit 9 transmits data from the first data signal transmission channel under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the data signal Source1 of 6 is transmitted to the third data line 3 of the three data lines 3 coupled to the first repeating unit D1 to charge the third sub-pixel 13 in the first repeating unit D1, and is charged with a positive voltage .
  • the second second control sub-circuit 9 transmits the data signal Source2 from the second data signal transmission channel 6 to the second repeating unit under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the third data line 3 of the three data lines 3 coupled to D2 is to charge the third sub-pixel 13 in the second repeating unit D2, and is charged with a negative voltage.
  • the first first control sub-circuit 8 transmits the scan signal Gate1 from the first scan signal transmission channel 4 to the two coupled to it.
  • the second gate line 2 of the gate lines 2 opens a row of sub-pixels 1 controlled by the gate line 2 (ie, the second row of sub-pixels 1 in FIG. 10).
  • Each second control sub-circuit 9 transmits the data signal from the data signal transmission channel 6 to the three data lines coupled to each repeating unit D under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the second data line 3 in 3 is used to charge the fifth sub-pixel 15 in each repeating unit D.
  • the first second control sub-circuit 9 transmits data from the first data signal transmission channel under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the data signal Source1 of 6 is transmitted to the second data line 3 of the three data lines 3 coupled to the first repeating unit D1 to charge the fifth sub-pixel 15 in the first repeating unit D1, and is charged with a positive voltage .
  • the second second control sub-circuit 9 transmits the data signal Source2 from the second data signal transmission channel 6 to the second repeating unit under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the second data line 3 of the three data lines 3 coupled to D2 is used to charge the fifth sub-pixel 15 in the second repeating unit D2, and is charged with a negative voltage.
  • the first first control sub-circuit 8 transmits the scan signal Gate1 from the first scan signal transmission channel 4 to the two coupled to it.
  • the second gate line 2 of the gate lines 2 opens a row of sub-pixels 1 controlled by the gate line 2 (ie, the second row of sub-pixels 1 in FIG. 10).
  • Each second control sub-circuit 9 transmits the data signal from the data signal transmission channel 6 to the three data lines coupled to each repeating unit D under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the first data line 3 in 3 is used to charge the fourth sub-pixel 14 in each repeating unit D.
  • the first second control sub-circuit 9 transmits data from the first data signal transmission channel under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the data signal Source1 of 6 is transmitted to the first data line 3 of the three data lines 3 coupled to the first repeating unit D1 to charge the fourth sub-pixel 14 in the first repeating unit D1, and is charged with a negative voltage .
  • the second second control sub-circuit 9 transmits the data signal Source2 from the second data signal transmission channel 6 to the second repeating unit under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the first data line 3 of the three data lines 3 coupled to D2 is used to charge the fourth sub-pixel 14 in the second repeating unit D2 and is charged with a positive voltage.
  • the first first control sub-circuit 8 transmits the scan signal from the scan signal transmission channel 4 to the two gate lines to which it is coupled under the control of the scan control signal transmitted by the at least one scan control signal line 5.
  • the second gate line 2 in 2 opens a row of sub-pixels 1 controlled by the gate line 2 (that is, the second row of sub-pixels 1 in FIG. 10).
  • Each second control sub-circuit 9 transmits the data signal from the data signal transmission channel 6 to the three data lines coupled to each repeating unit D under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the third data line 3 in 3 is used to charge the sixth sub-pixel 16 in each repeating unit D.
  • the first second control sub-circuit 9 transmits data from the first data signal transmission channel under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the data signal Source1 of 6 is transmitted to the third data line 3 of the three data lines 3 coupled to the first repeating unit D1 to charge the sixth sub-pixel 16 in the first repeating unit D1, and is charged with a negative voltage .
  • the second second control sub-circuit 9 transmits the data signal Source2 from the second data signal transmission channel 6 to the second repeating unit under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the third data line 3 of the three data lines 3 coupled to D2 is used to charge the sixth sub-pixel 16 in the second repeating unit D2 and is charged with a positive voltage.
  • the first first control sub-circuit 8 transmits the scan signal Gate1 from the first scan signal transmission channel 4 to the two coupled to it.
  • the first gate line 2 of the gate lines 2 opens a row of sub-pixels 1 controlled by the gate line 2 (that is, the first row of sub-pixels 1 in FIG. 10).
  • Each second control sub-circuit 9 transmits the data signal from the data signal transmission channel 6 to the three data lines coupled to each repeating unit D under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the second data line 3 in 3 is used to charge the second sub-pixel 12 in each repeating unit D.
  • the first second control sub-circuit 9 transmits data from the first data signal transmission channel under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the data signal Source1 of 6 is transmitted to the second data line 3 of the three data lines 3 coupled to the first repeating unit D1 to charge the second sub-pixel 12 in the first repeating unit D1, and is charged with a negative voltage .
  • the second second control sub-circuit 9 transmits the data signal Source2 from the second data signal transmission channel 6 to the second repeating unit under the control of the data control signal transmitted by the at least one data control signal line 7.
  • the second data line 3 of the three data lines 3 coupled to D2 is used to charge the second sub-pixel 12 in the second repeating unit D2 and is charged with a positive voltage.
  • the charging of the two rows of sub-pixels 1 corresponding to the first scan signal transmission channel 4 is realized, and in the multiple repeating units D divided by the two rows of sub-pixels, each repeat
  • the charging sequence of the six sub-pixels 1 of the unit D is the first sub-pixel 11, the third sub-pixel 13, the fifth sub-pixel 15, the fourth sub-pixel 14, the sixth sub-pixel 16 and the second sub-pixel 12.
  • the first sub-pixel 11, the third sub-pixel 13, and the fifth sub-pixel 15 in the odd-numbered repeating unit D are charged with a first voltage (for example, a positive voltage)
  • the second sub-pixel 12 and the fourth sub-pixel 14 and the sixth sub-pixel 16 are charged with a second voltage (for example, a negative voltage)
  • the first sub-pixel 11, the third sub-pixel 13 and the fifth sub-pixel 15 in the even-numbered repeating unit D are charged with the second Voltage (for example, a negative voltage)
  • the second sub-pixel 12, the fourth sub-pixel 14, and the sixth sub-pixel 16 are charged with a first voltage (for example, a positive voltage).
  • the polarities of the first voltage and the second voltage are opposite.
  • the second charging stage T2 to the nth charging stage Tn in one frame period can be combined with FIG. 4, FIG. 8 to FIG. 10, and with reference to the description of the first charging stage T1, which will not be repeated here. In this way, in one frame period, the dot inversion of all the sub-pixels 1 in the array substrate 20 is realized.
  • the at least one scan control signal line 5 includes a first scan control signal line 51 and a second scan control signal line 52
  • each first control sub-circuit 8 includes The first transistor M1 and the second transistor M2.
  • the control electrode of the first transistor M1 is coupled to the first scan control signal line 51, the first electrode of the first transistor M1 is coupled to the scan signal transmission channel 4 coupled to the first control sub-circuit 8, and the first transistor M1 The second pole of is coupled to one of the two gate lines 2 coupled to the first control sub-circuit 8.
  • the first transistor M1 is configured to be turned on under the control of the first scan control signal GEN-1 transmitted by the first scan control signal line 51, and transmit the scan signal transmitted by the scan signal transmission channel 4 to which it is coupled A gate line 2 to which it is coupled.
  • the control electrode of the second transistor M2 is coupled to the second scan control signal line 52, the first electrode of the second transistor M2 is coupled to the scan signal transmission channel 4 coupled to the first control sub-circuit 8, and the second transistor M2 The second pole of is coupled to the other gate line 2 of the two gate lines 2 coupled to the first control sub-circuit 8.
  • the second transistor M2 is configured to be turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and transmit the scan signal transmitted by the scan signal transmission channel 4 to which it is coupled A gate line 2 to which it is coupled.
  • the first transistor M1 in the first control sub-circuit 8 transmits the first scan control signal GEN on the first scan control signal line 51 -1 is turned on under the control of -1 to transmit the scan signal from the scan signal transmission channel 4 to a gate line 2 to which it is coupled.
  • the second transistor M2 in the first control sub-circuit 8 transmits the second scan control signal GEN on the second scan control signal line 52 It is turned on under the control of -2, and transmits the scan signal from the scan signal transmission channel 4 to a gate line 2 to which it is coupled.
  • the at least one data control signal line 7 includes a first data control signal line 71 and a second data control signal line 72
  • each second control sub-circuit 9 includes The third transistor M3 and the fourth transistor M4.
  • the control electrode of the third transistor M3 is coupled to the first data control signal line 71, the first electrode of the third transistor M3 is coupled to the data signal transmission channel 6 coupled to the second control sub-circuit 9, and the third transistor M3 The second pole of is coupled to the first data line 3 of the three data lines 3 coupled to the second control sub-circuit 9.
  • the third transistor M3 is configured to be turned on under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71 to transmit the data signal transmitted by the data signal transmission channel 6 to which it is coupled A data line 3 to which it is coupled.
  • the control electrode of the fourth transistor M4 is coupled to the second data control signal line 72, the first electrode of the fourth transistor M4 is coupled to the data signal transmission channel 6 coupled to the second control sub-circuit 9, and the fourth transistor M4 The second pole of is coupled to the second data line 3 of the three data lines 3 coupled to the second control sub-circuit 9.
  • the fourth transistor M4 is configured to be turned on under the control of the second data control signal SEN-2 transmitted by the second data control signal line 72 to transmit the data signal transmitted by the data signal transmission channel 6 to which it is coupled A data line 3 to which it is coupled.
  • each first control sub-circuit 8 includes a first transistor M1 and a second transistor M2, and each second control sub-circuit 9 includes a third transistor M3.
  • the at least one data control signal line 7 further includes a third data control signal line 73, and each second control sub-circuit 9 further includes a fifth transistor M5.
  • the control electrode of the fifth transistor M5 is coupled to the third data control signal line 73, the first electrode of the fifth transistor M5 is coupled to the data signal transmission channel 6 coupled to the second control sub-circuit 9, and the fifth transistor M5 The second pole of is coupled to the second data line 3 of the three data lines 3 coupled to the second control sub-circuit 9.
  • the fifth transistor M5 is configured to be turned on under the control of the third data control signal SEN-3 transmitted by the third data control signal line 73 to transmit the data signal transmitted by the data signal transmission channel 6 to which it is coupled A data line 3 to which it is coupled.
  • the driving method includes:
  • One frame period includes n charging phases T, and each charging phase T includes 6 sub-charging phases t.
  • the following takes the first charging stage T1 and the second charging stage T2 as an example, and the first transistor M1 and the second transistor M2 included in the first control sub-circuit 8 and the third transistor M3 included in the second control sub-circuit 9
  • the fourth transistor M4 and the fifth transistor M5 are both N-type transistors as an example for description.
  • the first scan signal transmission channel 4 transmits the scan signal Gate1 to charge the corresponding two rows of sub-pixels 1 (that is, the first row of sub-pixels 1 and the second row of sub-pixels 1).
  • the repeating units D divided by the two rows of sub-pixels 1 are the first repeating unit D1 to the m-th repeating unit D from left to right.
  • Tk(tp) is used to represent the p-th sub-charging stage tp of the k-th charging stage Tk, and both k and p are positive integers.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the first scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the third transistor M3 in each second control sub-circuit 9 is turned on under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71, and transmits the data signal from the data signal transmission channel 6 to
  • the first data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the first sub-pixel 11 in each repeating unit D.
  • the level of the first data control signal SEN-1 is high, so that the third transistor M3 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the first data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the first sub-pixel 11 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t1) is a positive voltage, so the first sub-pixel 11 in the first repeating unit D1 is charged with a positive voltage.
  • the third transistor M3 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the first sub-pixel 11 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t1) is a negative voltage, so the first sub-pixel 11 in the second repeating unit D2 is Charge to negative voltage.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the first scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the fifth transistor M5 in each second control sub-circuit 9 is turned on under the control of the third data control signal SEN-3 transmitted by the third data control signal line 73, and transmits the data signal from the data signal transmission channel 6 to
  • the third data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the third sub-pixel 13 in each repeating unit D.
  • the level of the third data control signal SEN-3 is high, so that the fifth transistor M5 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the third data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to contact the third sub-pixel 13 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t2) is a positive voltage, so the third sub-pixel 13 in the first repeating unit D1 is charged with a positive voltage.
  • the fifth transistor M5 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the third one of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the third sub-pixel 13 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t2) is a negative voltage, so the third sub-pixel 13 in the second repeating unit D2 is Charge to negative voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will be from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the fourth transistor M4 in each second control sub-circuit 9 is turned on under the control of the second data control signal SEN-2 transmitted by the second data control signal line 72, and transmits the data signal from the data signal transmission channel 6 to
  • the second data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the fifth sub-pixel 15 in each repeating unit D.
  • the level of the second data control signal SEN-2 is high, so that the fourth transistor M4 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the second data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the fifth sub-pixel 15 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t3) is a positive voltage, so the fifth sub-pixel 15 in the first repeating unit D1 is charged with a positive voltage.
  • the fourth transistor M4 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the second of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the fifth sub-pixel 15 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t3) is a negative voltage, so the fifth sub-pixel 15 in the second repeating unit D2 is Charge to negative voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the third transistor M3 in each second control sub-circuit 9 is turned on under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71, and transmits the data signal from the data signal transmission channel 6 to
  • the first data line 3 of the three data lines 3 corresponding to each repeating unit D is to charge the fourth sub-pixel 14 in each repeating unit D.
  • the level of the first data control signal SEN-1 is high, so that the third transistor M3 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the first data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to contact the fourth sub-pixel 14 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t4) is a negative voltage, so the fourth sub-pixel 14 in the first repeating unit D1 is charged with a negative voltage.
  • the third transistor M3 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the fourth sub-pixel 14 in the second repeating unit D2, and the voltage of the data signal Source2 at T1 (t4) is a positive voltage, so the fourth sub-pixel 14 in the second repeating unit D2 is Charge positive voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the fifth transistor M5 in each second control sub-circuit 9 is turned on under the control of the third data control signal SEN-3 transmitted by the third data control signal line 73, and transmits the data signal from the data signal transmission channel 6 to
  • the third data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the sixth sub-pixel 16 in each repeating unit D.
  • the level of the third data control signal SEN-3 is high, so that the fifth transistor M5 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the third data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to contact the sixth sub-pixel 16 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t5) is a negative voltage, so the fourth sub-pixel 14 in the first repeating unit D1 is charged with a negative voltage.
  • the fifth transistor M5 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the third one of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the sixth sub-pixel 16 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t5) is a positive voltage, so the sixth sub-pixel 16 in the second repeating unit D2 is Charge positive voltage.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the fourth transistor M4 in each second control sub-circuit 9 is turned on under the control of the second data control signal SEN-2 transmitted by the second data control signal line 72, and transmits the data signal from the data signal transmission channel 6 to
  • the second data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the second sub-pixel 12 in each repeating unit D.
  • the level of the second data control signal SEN-2 is high, so that the fourth transistor M4 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the second data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the second sub-pixel 12 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t6) is a negative voltage, so the second sub-pixel 12 in the first repeating unit D1 is charged with a negative voltage.
  • the fourth transistor M4 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • Two data lines 3 are used to charge the second sub-pixel 12 in the second repeating unit D2, and the voltage of the data signal Source2 at T1 (t6) is a positive voltage, so the second sub-pixel 12 in the second repeating unit D2 It is charged with a positive voltage.
  • the second scanning signal transmission channel 4 transmits the scanning signal Gate2 to charge the corresponding two rows of sub-pixels 1 (that is, the third row of sub-pixels 1 and the fourth row of sub-pixels 1).
  • the driving process of the six sub-charging stages in the second charging stage T2 can be combined with the timing diagram shown in FIG. 8 and the above description of the six sub-charging stages in the first charging stage T1, which will not be repeated here.
  • the first transistor M1 and the second transistor M2 included in the first control sub-circuit 8 and the third transistor M3, the fourth transistor M4 and the fifth transistor M5 included in the second control sub-circuit 9 are all P Type transistor, corresponding to the first scan control signal GEN-1, the second scan control signal GEN-2, the first data control signal SEN-1, the second data control signal SEN-2, and the third data control signal SEN-3
  • the timing of is inverted on the basis of the timing shown in Figure 8.
  • each first control sub-circuit 8 includes a first transistor M1 and a second transistor M2
  • each second control sub-circuit 9 includes a first transistor M1 and a second transistor M2.
  • each second control sub-circuit 9 further includes a switch unit 91.
  • the switch unit 91 of the second control sub-circuit 9 is coupled to the first data control signal line 71 and the second data control signal line 72, and the switch unit 91 is also coupled to the data signal transmission channel 6 of the second control sub-circuit 9
  • the third data line 3 of the three data lines 3 coupled to the second control sub-circuit 9 is coupled.
  • the switch unit 91 is configured to control the first data control signal SEN-1 transmitted by the first data control signal line 71 and the second data control signal SEN-2 transmitted by the second data control signal line 72.
  • the data signal transmitted by the coupled data signal transmission channel 6 is transmitted to the data line 3 to which it is coupled.
  • the switch unit 91 includes a sixth transistor M6 and a seventh transistor M7.
  • the control electrode of the sixth transistor M6 is coupled to the first data control signal line 71, the first electrode of the sixth transistor M6 is coupled to the data signal transmission channel 6 coupled to the switch unit 91, and the second electrode of the sixth transistor M6 is The electrode is coupled to the first electrode of the seventh transistor M7.
  • the control electrode of the seventh transistor M7 is coupled to the second data control signal line 72, and the second electrode of the seventh transistor M7 is coupled to the data line 3 to which the switch unit 91 is coupled.
  • the sixth transistor M6 is turned on under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71, and the seventh transistor M7 is on the second data control signal line 72.
  • the transmitted second data control signal SEN-2 is turned on under the control, the data signal transmitted by the data signal transmission channel 6 to which the switch unit 91 is coupled can be transmitted to the data line 3 to which it is coupled.
  • the sixth transistor M6 and the seventh transistor M7 are of the same type
  • the third transistor M3 and the fourth transistor M4 are of the same type
  • the sixth transistor M6 and the seventh transistor M7 are of the same type as the third transistor M3 and M3.
  • the type of the fourth transistor M4 is different.
  • the third transistor M3 and the fourth transistor M4 are both N-type transistors
  • the sixth transistor M6 and the seventh transistor M7 are both P-type transistors.
  • the driving method includes:
  • One frame period includes n charging phases T, and each charging phase T includes 6 sub-charging phases t.
  • the first charging stage T1 and the second charging stage T2 are taken as examples, and the first transistor M1 and the second transistor M2 included in the first control sub-circuit 8 are both N-type transistors, and the second control sub-circuit 9 includes The third transistor M3 and the fourth transistor M4 are both N-type transistors, and the sixth transistor M6 and the seventh transistor M7 are both P-type transistors as an example for description.
  • the first scan signal transmission channel 4 transmits the scan signal Gate1 to charge the corresponding two rows of sub-pixels 1 (that is, the first row of sub-pixels 1 and the second row of sub-pixels 1).
  • the repeating units D divided by the two rows of sub-pixels 1 are the first repeating unit D1 to the m-th repeating unit D from left to right.
  • Tk(tp) is used to represent the p-th sub-charging stage tp of the k-th charging stage Tk, and both k and p are positive integers.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the first scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the third transistor M3 in each second control sub-circuit 9 is turned on under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71, and transmits the data signal from the data signal transmission channel 6 to
  • the first data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the first sub-pixel 11 in each repeating unit D.
  • the level of the first data control signal SEN-1 is high, so that the third transistor M3 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the first data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the first sub-pixel 11 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t1) is a positive voltage, so the first sub-pixel 11 in the first repeating unit D1 is charged with a positive voltage.
  • the third transistor M3 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the first sub-pixel 11 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t1) is a negative voltage, so the first sub-pixel 11 in the second repeating unit D2 is Charge to negative voltage.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the first scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the first data control signal SEN-1 transmitted by the switch unit 91 in each second control sub-circuit 9 on the first data control signal line 71 and the second data control signal SEN-2 transmitted by the second data control signal line 72 Is turned on under the control of the data signal transmission channel 6 to transmit the data signal from the data signal transmission channel 6 to the third data line 3 of the three data lines 3 corresponding to each repeating unit D, so as to connect the third sub-pixel 13 in each repeating unit D. Charge.
  • the levels of the first scan control signal GEN-1 and the second scan control signal GEN-2 are both low, so that the first second control sub-circuit 9 In the switch unit 91, the sixth transistor M6 and the seventh transistor M7 are both turned on, and the data signal Source1 from the first data signal transmission channel 6 is transmitted to the first of the three data lines 3 corresponding to the first repeating unit D1.
  • the three data lines 3 charge the third sub-pixel 13 in the first repeating unit D1, and the voltage of the data signal Source1 at T1(t2) is a positive voltage, so the third sub-pixel 13 in the first repeating unit D1 It is charged with a positive voltage.
  • the sixth transistor M6 and the seventh transistor M7 in the switch unit 91 are both turned on, and the data signal Source2 from the second data signal transmission channel 6 is transmitted to the second repeating unit
  • the third data line 3 of the three data lines 3 corresponding to D2 is used to charge the third sub-pixel 13 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t2) is a negative voltage, so the second The third sub-pixel 13 in the repeating unit D2 is charged with a negative voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will be from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the fourth transistor M4 in each second control sub-circuit 9 is turned on under the control of the second data control signal SEN-2 transmitted by the second data control signal line 72, and transmits the data signal from the data signal transmission channel 6 to
  • the second data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the fifth sub-pixel 15 in each repeating unit D.
  • the level of the second data control signal SEN-2 is high, so that the fourth transistor M4 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the second data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the fifth sub-pixel 15 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t3) is a positive voltage, so the fifth sub-pixel 15 in the first repeating unit D1 is charged with a positive voltage.
  • the fourth transistor M4 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the second of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the fifth sub-pixel 15 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t3) is a negative voltage, so the fifth sub-pixel 15 in the second repeating unit D2 is Charge to negative voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the third transistor M3 in each second control sub-circuit 9 is turned on under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71, and transmits the data signal from the data signal transmission channel 6 to
  • the first data line 3 of the three data lines 3 corresponding to each repeating unit D is to charge the fourth sub-pixel 14 in each repeating unit D.
  • the level of the first data control signal SEN-1 is high, so that the third transistor M3 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the first data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to contact the fourth sub-pixel 14 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t4) is a negative voltage, so the fourth sub-pixel 14 in the first repeating unit D1 is charged with a negative voltage.
  • the third transistor M3 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the fourth sub-pixel 14 in the second repeating unit D2, and the voltage of the data signal Source2 at T1 (t4) is a positive voltage, so the fourth sub-pixel 14 in the second repeating unit D2 is Charge positive voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the first data control signal SEN-1 transmitted by the switch unit 91 in each second control sub-circuit 9 on the first data control signal line 71 and the second data control signal SEN-2 transmitted by the second data control signal line 72 Is turned on under the control of the data signal transmission channel 6 to transmit the data signal from the data signal transmission channel 6 to the third data line 3 of the three data lines 3 corresponding to each repeating unit D, so as to connect the sixth sub-pixel 16 in each repeating unit D. Charge.
  • the levels of the first scan control signal GEN-1 and the second scan control signal GEN-2 are both low, so that the first second control sub-circuit 9 In the switch unit 91, the sixth transistor M6 and the seventh transistor M7 are both turned on, and the data signal Source1 from the first data signal transmission channel 6 is transmitted to the first of the three data lines 3 corresponding to the first repeating unit D1.
  • the three data lines 3 charge the sixth sub-pixel 16 in the first repeating unit D1, and the voltage of the data signal Source1 at T1 (t5) is a negative voltage, so the fourth sub-pixel 14 in the first repeating unit D1 It is charged with a negative voltage.
  • the sixth transistor M6 and the seventh transistor M7 in the switch unit 91 are both turned on, and the data signal Source2 from the second data signal transmission channel 6 is transmitted to the second repeating unit
  • the third data line 3 of the three data lines 3 corresponding to D2 is used to charge the sixth sub-pixel 16 in the second repeating unit D2, and the voltage of the data signal Source2 at T1 (t5) is a positive voltage, so the second The sixth sub-pixel 16 in the repeating unit D2 is charged with a positive voltage.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the fourth transistor M4 in each second control sub-circuit 9 is turned on under the control of the second data control signal SEN-2 transmitted by the second data control signal line 72, and transmits the data signal from the data signal transmission channel 6 to
  • the second data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the second sub-pixel 12 in each repeating unit D.
  • the level of the second data control signal SEN-2 is high, so that the fourth transistor M4 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the second data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the second sub-pixel 12 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t6) is a negative voltage, so the second sub-pixel 12 in the first repeating unit D1 is charged with a negative voltage.
  • the fourth transistor M4 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • Two data lines 3 are used to charge the second sub-pixel 12 in the second repeating unit D2, and the voltage of the data signal Source2 at T1 (t6) is a positive voltage, so the second sub-pixel 12 in the second repeating unit D2 It is charged with a positive voltage.
  • the second scanning signal transmission channel 4 transmits the scanning signal Gate2 to charge the corresponding two rows of sub-pixels 1 (that is, the third row of sub-pixels 1 and the fourth row of sub-pixels 1).
  • the driving process of the six sub-charging stages in the second charging stage T2 can be combined with the timing diagram shown in FIG. 9 and the above description of the six sub-charging stages in the first charging stage T1, which will not be repeated here.
  • the switch unit 91 includes a NAND circuit 911 and an eighth transistor M8.
  • the NAND circuit 911 is coupled to the first data control signal line 71, the second data control signal line 72 and the control electrode of the eighth transistor M8.
  • the NAND gate circuit 911 is configured to be under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71 and the second data control signal SEN-2 transmitted by the second data control signal line 72 , Outputting a control signal for controlling the conduction of the eighth transistor M8 to the control electrode of the eighth transistor M8.
  • the first pole of the eighth transistor M8 is coupled to the data signal transmission channel 6 to which the switch unit 91 is coupled, and the second pole of the eighth transistor M8 is coupled to the data line 3 to which the switch unit 91 is coupled.
  • the eighth transistor M8 is configured to be turned on under the control of the control signal output by the NAND circuit 911, and transmits the data signal transmitted by the data signal transmission channel 6 coupled to the switch unit 91 to the switch unit 91 The data line 3 to which it is coupled.
  • the NAND gate circuit 911 when the two signals input to the NAND gate circuit 911 are both high level (1), the output is low level (0). If the two signals of the NAND gate circuit 911 are input If at least one of the signals is low level (0), the output is high level (1). Therefore, exemplarily, at least one of the first data control signal SEN-1 transmitted by the first data control signal line 71 and the second data control signal SEN-2 transmitted by the second data control signal line 72 is At low level, the NAND circuit 911 can output a high-level signal. In the case where the eighth transistor M8 is an N-type transistor, the eighth transistor M8 is turned on under the control of the high-level signal to transmit the data signal to The data line 3 to which it is coupled.
  • the third transistor M3, the fourth transistor M4, and the eighth transistor M8 are of the same type.
  • the third transistor M3, the fourth transistor M4, and the eighth transistor M8 are all N-type. Transistor.
  • the driving method includes:
  • One frame period includes n charging phases T, and each charging phase T includes 6 sub-charging phases t.
  • the first charging stage T1 and the second charging stage T2 are taken as examples, and the first transistor M1 and the second transistor M2 included in the first control sub-circuit 8 are both N-type transistors, and the second control sub-circuit 9 includes The third transistor M3, the fourth transistor M4, and the eighth transistor M8 are all N-type transistors as an example for description.
  • the first scan signal transmission channel 4 transmits the scan signal Gate1 to charge the corresponding two rows of sub-pixels 1 (that is, the first row of sub-pixels 1 and the second row of sub-pixels 1).
  • the repeating units D divided by the two rows of sub-pixels 1 are the first repeating unit D1 to the m-th repeating unit D from left to right.
  • Tk(tp) is used to represent the p-th sub-charging stage tp of the k-th charging stage Tk, and both k and p are positive integers.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the first scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the third transistor M3 in each second control sub-circuit 9 is turned on under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71, and transmits the data signal from the data signal transmission channel 6 to
  • the first data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the first sub-pixel 11 in each repeating unit D.
  • the level of the first data control signal SEN-1 is high, so that the third transistor M3 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the first data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the first sub-pixel 11 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t1) is a positive voltage, so the first sub-pixel 11 in the first repeating unit D1 is charged with a positive voltage.
  • the third transistor M3 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the first sub-pixel 11 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t1) is a negative voltage, so the first sub-pixel 11 in the second repeating unit D2 is Charge to negative voltage.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the first scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the first data control signal SEN-1 transmitted by the switch unit 91 in each second control sub-circuit 9 on the first data control signal line 71 and the second data control signal SEN-2 transmitted by the second data control signal line 72 Is turned on under the control of the data signal transmission channel 6 to transmit the data signal from the data signal transmission channel 6 to the third data line 3 of the three data lines 3 corresponding to each repeating unit D, so as to connect the third sub-pixel 13 in each repeating unit D. Charge.
  • the levels of the first scan control signal GEN-1 and the second scan control signal GEN-2 are both low, so that the first second control sub-circuit 9 In the switch unit 91, the NAND circuit 911 outputs a high-level signal, and the eighth transistor M8 is turned on under the control of the high-level signal, and transmits the data signal Source1 from the first data signal transmission channel 6 to
  • the third data line 3 of the three data lines 3 corresponding to the first repeating unit D1 is used to charge the third sub-pixel 13 in the first repeating unit D1, and the voltage of the data signal Source1 at T1(t2) is a positive voltage Therefore, the third sub-pixel 13 in the first repeating unit D1 is charged with a positive voltage.
  • the NAND circuit 911 in the switch unit 91 outputs a high-level signal
  • the eighth transistor M8 is turned on under the control of the high-level signal to transfer the second data from
  • the data signal Source2 of the signal transmission channel 6 is transmitted to the third data line 3 of the three data lines 3 corresponding to the second repeating unit D2 to charge the third sub-pixel 13 in the second repeating unit D2, and the data signal Source2
  • the voltage at T1 (t2) is a negative voltage, so the third sub-pixel 13 in the second repeating unit D2 is charged with a negative voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will be from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the fourth transistor M4 in each second control sub-circuit 9 is turned on under the control of the second data control signal SEN-2 transmitted by the second data control signal line 72, and transmits the data signal from the data signal transmission channel 6 to
  • the second data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the fifth sub-pixel 15 in each repeating unit D.
  • the level of the second data control signal SEN-2 is high, so that the fourth transistor M4 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the second data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the fifth sub-pixel 15 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t3) is a positive voltage, so the fifth sub-pixel 15 in the first repeating unit D1 is charged with a positive voltage.
  • the fourth transistor M4 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the second of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the fifth sub-pixel 15 in the second repeating unit D2, and the voltage of the data signal Source2 at T1(t3) is a negative voltage, so the fifth sub-pixel 15 in the second repeating unit D2 is Charge to negative voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the third transistor M3 in each second control sub-circuit 9 is turned on under the control of the first data control signal SEN-1 transmitted by the first data control signal line 71, and transmits the data signal from the data signal transmission channel 6 to
  • the first data line 3 of the three data lines 3 corresponding to each repeating unit D is to charge the fourth sub-pixel 14 in each repeating unit D.
  • the level of the first data control signal SEN-1 is high, so that the third transistor M3 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the first data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to contact the fourth sub-pixel 14 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t4) is a negative voltage, so the fourth sub-pixel 14 in the first repeating unit D1 is charged with a negative voltage.
  • the third transistor M3 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • a data line 3 is used to charge the fourth sub-pixel 14 in the second repeating unit D2, and the voltage of the data signal Source2 at T1 (t4) is a positive voltage, so the fourth sub-pixel 14 in the second repeating unit D2 is Charge positive voltage.
  • the second transistor M2 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-2 transmitted by the second scan control signal line 52, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the second gate line 2) to which it is coupled, thereby turning on the second row of sub-pixels 1.
  • the first data control signal SEN-1 transmitted by the switch unit 91 in each second control sub-circuit 9 on the first data control signal line 71 and the second data control signal SEN-2 transmitted by the second data control signal line 72 Is turned on under the control of the data signal transmission channel 6 to transmit the data signal from the data signal transmission channel 6 to the third data line 3 of the three data lines 3 corresponding to each repeating unit D, so as to connect the sixth sub-pixel 16 in each repeating unit D. Charge.
  • the levels of the first scan control signal GEN-1 and the second scan control signal GEN-2 are both low, so that the first second control sub-circuit 9 In the switch unit 91, the NAND circuit 911 outputs a high-level signal, and the eighth transistor M8 is turned on under the control of the high-level signal, and transmits the data signal Source1 from the first data signal transmission channel 6 to the first data signal transmission channel 6
  • the third data line 3 of the three data lines 3 corresponding to one repeating unit D1 is used to charge the sixth sub-pixel 16 in the first repeating unit D1, and the voltage of the data signal Source1 at T1 (t5) is a negative voltage, Therefore, the fourth sub-pixel 14 in the first repeating unit D1 is charged with a negative voltage.
  • the NAND circuit 911 in the switch unit 91 outputs a high-level signal
  • the eighth transistor M8 is turned on under the control of the high-level signal to transfer the second data from
  • the data signal Source2 of the signal transmission channel 6 is transmitted to the third data line 3 of the three data lines 3 corresponding to the second repeating unit D2 to charge the sixth sub-pixel 16 in the second repeating unit D2, and the data signal Source2
  • the voltage at T1 (t5) is a positive voltage, so the sixth sub-pixel 16 in the second repeating unit D2 is charged with a positive voltage.
  • the first transistor M1 in the first first control sub-circuit 8 is turned on under the control of the second scan control signal GEN-1 transmitted by the first scan control signal line 51, and will come from the first
  • the scan signal of the scan signal transmission channel 4 is transmitted to the gate line 2 (ie, the first gate line 2) to which it is coupled, thereby turning on the first row of sub-pixels 1.
  • the fourth transistor M4 in each second control sub-circuit 9 is turned on under the control of the second data control signal SEN-2 transmitted by the second data control signal line 72, and transmits the data signal from the data signal transmission channel 6 to
  • the second data line 3 of the three data lines 3 corresponding to each repeating unit D is used to charge the second sub-pixel 12 in each repeating unit D.
  • the level of the second data control signal SEN-2 is high, so that the fourth transistor M4 in the first second control sub-circuit 9 is turned on,
  • the data signal Source1 from the first data signal transmission channel 6 is transmitted to the second data line 3 of the three data lines 3 corresponding to the first repeating unit D1, so as to communicate with the second sub-pixel 12 in the first repeating unit D1. It is charged, and the voltage of the data signal Source1 at T1 (t6) is a negative voltage, so the second sub-pixel 12 in the first repeating unit D1 is charged with a negative voltage.
  • the fourth transistor M4 in the second second control sub-circuit 9 is turned on to transmit the data signal Source2 from the second data signal transmission channel 6 to the first of the three data lines 3 corresponding to the second repeating unit D2.
  • Two data lines 3 are used to charge the second sub-pixel 12 in the second repeating unit D2, and the voltage of the data signal Source2 at T1 (t6) is a positive voltage, so the second sub-pixel 12 in the second repeating unit D2 It is charged with a positive voltage.
  • the second scanning signal transmission channel 4 transmits the scanning signal Gate2 to charge the corresponding two rows of sub-pixels 1 (that is, the third row of sub-pixels 1 and the fourth row of sub-pixels 1).
  • the driving process of the six sub-charging stages in the second charging stage T2 can be combined with the timing diagram shown in FIG. 9 and the above description of the six sub-charging stages in the first charging stage T1, which will not be repeated here.
  • the control electrode of the used transistor is the gate of the transistor
  • the first electrode may be the source
  • the second electrode may be the drain
  • the first electrode of the above-mentioned transistor may be It is the drain electrode and the source electrode of the second electrode, which is not limited in the present disclosure. Since the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain, The second pole is the source.
  • the at least one scan control signal line 5 extends along the column direction in which the plurality of sub-pixels 1 are arranged, and the at least One data control signal line 7 extends along the row direction in which the plurality of sub-pixels 1 are arranged.
  • the array substrate 20 includes a display area AA and a frame area BB.
  • a plurality of sub-pixels 1 a plurality of gate lines 2 and a plurality of data lines 3 are disposed in the display area AA, and
  • One scanning signal transmission channel 4 at least one scanning control signal line 5, a plurality of data signal transmission channels 6 and at least one data control signal line 7, a plurality of first control sub-circuits 8 and a plurality of second control sub-circuits 9 are arranged in Border area BB.
  • each sub-pixel 1 includes a driving transistor.
  • the first control sub-circuit 8 in the array substrate 20 includes a first transistor M1 and a second transistor M2, and the second control sub-circuit 9 includes a third transistor M3 and a fourth transistor M4.
  • the gate, active layer, source and drain of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are connected to the gate, active layer, and source of the driving transistor, respectively. Set on the same layer as the drain.
  • the film layers of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are arranged in the same layer corresponding to each film layer of the driving transistor in the sub-pixel 1, and are arranged on the array substrate 20.
  • each film layer can be formed simultaneously by using a patterning process at one time, thereby simplifying the preparation process and improving the preparation efficiency.
  • the driving transistor included in each sub-pixel 1 is an oxide thin film transistor (Oxide TFT).
  • the carrier mobility of the oxide thin film transistor is high, and the signal transmission The speed is faster and the cost is lower, which makes the array substrate 20 of the present disclosure more practical.
  • the display device 30 provided by some embodiments of the present disclosure includes an array substrate 20, a gate drive circuit 301, and a source drive circuit 302.
  • the display device 30 has the feature of saving scan signals in the gate drive circuit 301.
  • the advantages of the number of output channels 3011 and the number of data signal output channels 3021 of the source driving circuit 302 lead to lower cost, less flicker and crosstalk during the display process, and lower power consumption.
  • the display device 30 can be a TV, a mobile phone, a computer, a notebook computer, a tablet computer, a personal digital assistant (PDA), a vehicle-mounted computer, etc.
  • PDA personal digital assistant
  • the present disclosure does not limit this.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种阵列基板（20）的驱动方法，包括：一个帧周期包括多个充电阶段（T），在每个充电阶段（T）内对一个第一控制子电路（8）耦接的两条栅线（2）所控制的各重复单元（D）的6个子像素（1）进行充电；每个充电阶段（T）包括6个子充电阶段（t），在每个子充电阶段（t）内对每个重复单元（D）的一个子像素（1）进行充电；在每个子充电阶段（t），第一控制子电路（8）在至少一条扫描控制信号线（5）传输的扫描控制信号的控制下，将来自扫描信号传输通道（4）的扫描信号传输至其所耦接的两条栅线（2）中的一条栅线（2），以打开该条栅线（2）所控制的一行子像素（1）；每个第二控制子电路（9）在至少一条数据控制信号线（7）传输的数据控制信号的控制下，将来自数据信号传输通道（6）的数据信号传输至各重复单元（D）所耦接的一条数据线（3），以对各重复单元（D）中的一个子像素（1）充电，从而减少功耗。

Description

阵列基板及其驱动方法、显示装置
本申请要求于2020年03月18日提交的、申请号为202010191857.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其驱动方法、显示装置。
背景技术
目前，液晶显示装置多采用极性反转驱动方式进行液晶的驱动，以避免液晶分子因长期受某一固定电压的驱动而造成的电压残留，进而影响显示效果的问题。
发明内容
一方面，提供一种阵列基板的驱动方法，其中，所述阵列基板包括：多个子像素、多条栅线、多条数据线、多个扫描信号传输通道、至少一条扫描控制信号线、多个数据信号传输通道、至少一条数据控制信号线，多个第一控制子电路和多个第二控制子电路。所述多个子像素呈阵列式布置，一行子像素与一条栅线耦接，一列子像素与一条数据线耦接。每个第一控制子电路与所述至少一条扫描控制信号线、一个扫描信号传输通道和两条栅线耦接；每个第二控制子电路与所述至少一条数据控制信号线、一个数据信号传输通道和三条数据线耦接。
每个第一控制子电路耦接的两条栅线所控制的两行子像素划分为沿行方向排列的多个重复单元，每个重复单元包括排列成2行3列的6个子像素。
所述驱动方法包括：一个帧周期包括多个充电阶段，在每个充电阶段内对一个第一控制子电路耦接的两条栅线所控制的各重复单元的6个子像素进行充电；每个充电阶段包括6个子充电阶段，在每个子充电阶段内对每个重复单元的一个子像素进行充电。
在每个子充电阶段，第一控制子电路在至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的一条栅线，以打开该条栅线所控制的一行子像素。每个第二控制子电路在至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的一条数据线，以对各重复单元中的一个子像素充电。其中，每个数据信号传输通道所传输的数据信号呈正负电压交替变换，正电压和负电压的持续时长为三个子充电 阶段，且任意相邻两个数据信号传输通道所传输的数据信号的电压在同一子充电阶段极性相反。
在一些实施例中，每个所述重复单元所包括的6个子像素按照顺时针或者逆时针的顺序分别为第一子像素、第二子像素、第三子像素、第四子像素、第五子像素和第六子像素。每个所述充电阶段所包括的6个子充电阶段分别为第一子充电阶段、第二子充电阶段、第三子充电阶段、第四子充电阶段、第五子充电阶段和第六子充电阶段。
在所述第一子充电阶段，第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第一条栅线，以打开该栅线所控制的一行子像素。每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第一条数据线，以对各重复单元中的第一子像素充电。
在所述第二子充电阶段，第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第一条栅线，以打开该栅线所控制的一行子像素。每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第三条数据线，以对各重复单元中的第三子像素充电。
在所述第三子充电阶段，第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第二条栅线，以打开该栅线所控制的一行子像素。每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第二条数据线，以对各重复单元中的第五子像素充电。
在所述第四子充电阶段，第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第二条栅线，以打开该栅线所控制的一行子像素。每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第一条数据线，以对各重复单元中的第四子像素充电。
在所述第五子充电阶段，第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输 至其所耦接的两条栅线中的第二条栅线，以打开该栅线所控制的一行子像素。每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第三条数据线，以对各重复单元中的第六子像素充电。
在所述第六子充电阶段，第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第一条栅线，以打开该栅线所控制的一行子像素。每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第二条数据线，以对各重复单元中的第二子像素充电。
其中，第奇数个重复单元中的第一子像素、第三子像素和第五子像素被充入第一电压，第二子像素、第四子像素和第六子像素被充入第二电压；第偶数个重复单元中的第一子像素、第三子像素和第五子像素被充入第二电压，第二子像素、第四子像素和第六子像素被充入第一电压。其中，所述第一电压和所述第二电压的极性相反。
在一些实施例中，在所述至少一条扫描控制信号线包括第一扫描控制信号线和第二扫描控制信号线，所述第一控制子电路包括第一晶体管和第二晶体管的情况下，在所述第一子充电阶段、所述第二子充电阶段和所述第六子充电阶段，第一控制子电路中的第一晶体管在所述第一扫描控制信号线传输的第一扫描控制信号的控制下导通，将来自扫描信号传输通道的扫描信号传输至其所耦接的栅线。在所述第三子充电阶段、所述第四子充电阶段和所述第五子充电阶段，第一控制子电路中的第二晶体管在所述第二扫描控制信号线传输的第二扫描控制信号的控制下导通，将来自扫描信号传输通道的扫描信号传输至其所耦接的栅线。
在一些实施例中，在所述至少一条数据控制信号线包括第一数据控制信号线、第二数据控制信号线和第三数据控制信号线，所述第二控制子电路包括第三晶体管、第四晶体管和第五晶体管的情况下，在所述第一子充电阶段，每个第二控制子电路中的第三晶体管在所述第一数据控制信号线传输的第一数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第一条数据线，以对各重复单元中的第一子像素充电。在所述第二子充电阶段，每个第二控制子电路中的第五晶体管在所述第三数据控制信号线传输的第三数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第三条 数据线，以对各重复单元中第三子像素充电。
在所述第三子充电阶段，每个第二控制子电路中的第四晶体管在所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第二条数据线，以对各重复单元中的第五子像素充电。在所述第四子充电阶段，每个第二控制子电路中的第三晶体管在所述第一数据控制信号线传输的第一数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第一条数据线，以对各重复单元中的第四子像素充电。
在所述第五子充电阶段，每个第二控制子电路中的第五晶体管在所述第三数据控制信号线传输的第三数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第三条数据线，以对各重复单元中的第六子像素充电。在所述第六子充电阶段，每个第二控制子电路中的第四晶体管在所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第二条数据线，以对各重复单元中的第二子像素充电。
在一些实施例中，在所述至少一条数据控制信号线包括第一数据控制信号线和第二数据控制信号线，所述第二控制子电路包括第三晶体管、第四晶体管和开关单元的情况下，在所述第一子充电阶段，每个第二控制子电路中的第三晶体管在所述第一数据控制信号线传输的第一数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第一条数据线，以对各重复单元中的第一子像素充电。在所述第二子充电阶段，每个第二控制子电路中的开关单元在所述第一数据控制信号线传输的第一数据控制信号、及所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第三条数据线，以对各重复单元中第三子像素充电。
在所述第三子充电阶段，每个第二控制子电路中的第四晶体管在所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第二条数据线，以对各重复单元中的第五子像素充电。在所述第四子充电阶段，每个第二控制子电路中的第三晶体管在所述第一数据控制信号线传输的第一数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单 元对应的三条数据线中的第一条数据线，以对各重复单元中的第四子像素充电。
在所述第五子充电阶段，每个第二控制子电路中的开关单元在所述第一数据控制信号线传输的第一数据控制信号、及所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第三条数据线，以对各重复单元中的第六子像素充电。在所述第六子充电阶段，每个第二控制子电路中的第四晶体管在所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第二条数据线，以对各重复单元中的第二子像素充电。
另一方面，提供一种阵列基板，包括：多个子像素、多条栅线、多条数据线、多个扫描信号传输通道、至少一条扫描控制信号线、多个数据信号传输通道、至少一条数据控制信号线，多个第一控制子电路和多个第二控制子电路。所述多个子像素呈阵列式布置，一行子像素与一条栅线耦接，一列子像素与一条数据线耦接。
每个第一控制子电路与所述至少一条扫描控制信号线、一个扫描信号传输通道和两条栅线耦接；所述第一控制子电路被配置为，在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将其所耦接的扫描信号传输通道传输的扫描信号分别传输至其所耦接的两条栅线，以分时打开这两条栅线所耦接的两行子像素。每个第二控制子电路与所述至少一条数据控制信号线、一个数据信号传输通道和三条数据线耦接；所述第二控制子电路被配置为，在所述至少一条数据控制信号线传输的数据控制信号的控制下，将其所耦接的数据信号传输通道传输的数据信号分别传输至其所耦接的三条数据线，以分时对这三条数据线所耦接的子像素中被栅线打开的子像素充电。
在一些实施例中，所述多个子像素排列成2n行3m列；所述阵列基板包括2n条栅线、3m条数据线、n个扫描信号传输通道、m个数据信号传输通道、两条扫描控制信号线、至少两条数据控制信号线、n个第一控制子电路和m个第二控制子电路；其中，n和m为正整数。
第i个第一控制子电路与第i个扫描信号传输通道、第2i-1条栅线和第2i条栅线耦接；其中，1≤i≤n，i为正整数；第j个第二控制子电路与第j个数据信号传输通道、第3j-2条数据线、第3j-1条数据线和第3j条数据线耦接；其中，1≤j≤m，j为正整数。
在一些实施例中，所述至少一条扫描控制信号线包括第一扫描控制信号 线和第二扫描控制信号线；每个所述第一控制子电路包括第一晶体管和第二晶体管。
其中，所述第一晶体管的控制极与所述第一扫描控制信号线耦接，所述第一晶体管的第一极与所述第一控制子电路所耦接的扫描信号传输通道耦接，所述第一晶体管的第二极与所述第一控制子电路所耦接的两条栅线中的一条栅线耦接。所述第二晶体管的控制极与所述第二扫描控制信号线耦接，所述第二晶体管的第一极与所述第一控制子电路所耦接的扫描信号传输通道耦接，所述第二晶体管的第二极与所述第一控制子电路所耦接的两条栅线中的另一条栅线耦接。
在一些实施例中，所述至少一条数据控制信号线包括第一数据控制信号线和第二数据控制信号线；每个所述第二控制子电路包括第三晶体管和第四晶体管。
其中，所述第三晶体管的控制极与所述第一数据控制信号线耦接，所述第三晶体管的第一极与所述第二控制子电路所耦接的数据信号传输通道耦接，所述第三晶体管的第二极与所述第二控制子电路所耦接的三条数据线中的第一条数据线耦接。所述第四晶体管的控制极与所述第二数据控制信号线耦接，所述第四晶体管的第一极与所述第二控制子电路所耦接的数据信号传输通道耦接，所述第四晶体管的第二极与所述第二控制子电路所耦接的三条数据线中的第二条数据线耦接。
在一些实施例中，所述至少一条数据控制信号线还包括第三数据控制信号线；每个所述第二控制子电路还包括第五晶体管。
其中，所述第五晶体管的控制极与所述第三数据控制信号线耦接，所述第五晶体管的第一极与所述第二控制子电路所耦接的数据信号传输通道耦接，所述第五晶体管的第二极与所述第二控制子电路所耦接的三条数据线中的第三条数据线耦接。
在一些实施例中，所述第二控制子电路还包括开关单元，所述开关单元与所述第一数据控制信号线、所述第二数据控制信号线耦接，所述开关单元还与所述第二控制子电路所耦接的数据信号传输通道、所述第二控制子电路所耦接的三条数据线中的第三条数据线耦接。所述开关单元被配置为，在所述第一数据控制信号线传输的第一数据控制信号、及所述第二数据控制信号线传输的第二数据控制信号的控制下，将其所耦接的数据信号传输通道传输的数据信号传输至其所耦接的数据线。
在一些实施例中，所述开关单元包括第六晶体管和第七晶体管，其中， 所述第六晶体管的控制极与所述第一数据控制信号线耦接，所述第六晶体管的第一极与所述开关单元所耦接的数据信号传输通道耦接，所述第六晶体管的第二极与所述第七晶体管的第一极耦接。所述第七晶体管的控制极与所述第二数据控制信号线耦接，所述第七晶体管的第二极与所述开关单元所耦接的数据线耦接。
在一些实施例中，所述第六晶体管和所述第七晶体管的类型相同，所述第三晶体管和所述第四晶体管的类型相同，且所述第六晶体管和所述第七晶体管的类型与所述第三晶体管和所述第四晶体管的类型不同。
在一些实施例中，所述开关单元包括与非门电路和第八晶体管。其中，所述与非门电路与所述第一数据控制信号线、第二数据控制信号线和所述第八晶体管的控制极耦接。其中，所述与非门电路被配置为，在所述第一数据控制信号线传输的第一数据控制信号、及所述第二数据控制信号线传输的第二数据控制信号的控制下，输出控制所述第八晶体管导通的控制信号。所述第八晶体管的第一极与所述开关单元所耦接的数据信号传输通道耦接，所述第八晶体管的第二极与所述开关单元所耦接的数据线耦接。
在一些实施例中，所述第三晶体管、所述第四晶体管和所述第八晶体管的类型相同。
在一些实施例中，所述至少一条扫描控制信号线沿多个子像素排列的列方向延伸，所述至少一条数据控制信号线沿多个子像素排列的行方向延伸。
在一些实施例中，每个子像素包括驱动晶体管；在所述第一控制子电路包括第一晶体管和第二晶体管，第二控制子电路包括第三晶体管和第四晶体管的情况下，所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管的栅极、有源层、及源极和漏极分别与所述驱动晶体管的栅极、有源层、及源极和漏极同层设置。
又一方面，提供一种显示装置，包括：如上一方面任一实施例所述的阵列基板、栅极驱动电路和源极驱动电路。所述栅极驱动电路具有多个扫描信号输出通道和至少一个扫描控制信号输出通道，每个扫描信号输出通道与所述阵列基板中的一个扫描信号传输通道耦接，每个扫描控制信号输出通道与所述阵列基板中的一条扫描控制信号线耦接。所述源极驱动电路包括多个数据信号输出通道和至少至少一个数据控制信号输出通道，每个数据信号输出通道与所述阵列基板中的一个数据信号传输通道耦接，每个数据控制信号输出通道与所述阵列基板中的一条数据控制信号线耦接。
在一些实施例中，所述栅极驱动电路包括两个扫描控制信号输出通道， 所述源极驱动电路包括两个或三个数据控制信号输出通道。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术的一些实施例的阵列基板的结构图；
图2为根据相关技术的一些实施例的显示装置的结构图；
图3为根据相关技术的一些实施例的阵列基板的驱动方法的时序图；
图4为根据本公开的一些实施例的阵列基板的一种结构图；
图5为根据本公开的一些实施例的阵列基板的另一种结构图；
图6为根据本公开的一些实施例的阵列基板的又一种结构图；
图7为根据本公开的一些实施例的阵列基板的又一种结构图；
图8为根据本公开的一些实施例的阵列基板的驱动方法的一种时序图；
图9为根据本公开的一些实施例的阵列基板的驱动方法的另一种时序图；
图10为根据本公开的一些实施例的阵列基板中部分子像素的充电顺序图；
图11为根据本公开的一些实施例的显示装置的一种结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary  embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
相关技术中，如图1和图2所示，液晶显示装置中阵列基板20’包括：多个呈阵列式排布的子像素1，多条栅线2和多条数据线3，每条栅线2与一行子像素1耦接，每条数据线3与一列子像素1耦接，多个子像素1，多条栅线2和多条数据线3设置于阵列基板20’中的衬底基板201上。
请参见图2，液晶显示装置30’还包括源极驱动电路302和栅极驱动电路301，源极驱动电路302通过绑定(bonding)的方式与阵列基板20’连接，栅极驱动电路301通过绑定(bonding)的方式与阵列基板20’连接，或者，栅极驱动电路301通过GOA(Gate on Array)的方式集成在阵列基板上。
栅极驱动电路301具有多个扫描信号输出通道3011，每个扫描信号输出通道3011与一条栅线2耦接，用于输出扫描信号至栅线2，以打开该条栅线2所控制的一行子像素1。在栅极驱动电路301通过GOA(Gate on Array)的方式集成在阵列基板上的情况下，栅极驱动电路301的多个扫描信号输出通道3011是指栅极驱动电路301的输出端，即栅极驱动电路301所包括的多个移位寄存器的信号输出端。
源极驱动电路302具有多个数据信号输出通道3021，每个数据信号输出通道3021与一条数据线3耦接，用于输出数据信号至数据线3，以对该条数据线3所控制的一列子像素1中被打开的子像素1充电。
也就是说，栅极驱动电路301的扫描信号输出通道3011与阵列基板20’中栅线2的数量相等，源极驱动电路302的数据信号输出通道3021与阵列基板20’中的数据线3的数量相等，示例性地，阵列基板20’包括2n×3m个子像素1、2n条栅线2和3m条数据线3，相应地，栅极驱动电路301具有2n个扫描信号输出通道3011，源极驱动电路302具有3m个数据信号输出通道3021。
目前，液晶显示装置的常用的极性反转驱动方式包括：帧反转方式(Frame  inversion)、行反转方式(Row inversion)、列反转方式(Column inversion)、及点反转方式(Dot inversion)。其中，点反转方式为在一个帧周期内，每相邻两个子像素1被充入的数据信号的电压正负极性相反。点反转方式具有串扰(Crosstalk)及闪烁(flicker)现象较少的优点，能够使得显示装置所显示的画面的质量得到较大程度地改善，受到广泛应用。
参阅图3，在相关技术中，图1所示的阵列基板20’采用点反转方式的驱动过程为：一个帧周期包括2n个充电阶段s，分别为s1至s2n，每个充电阶段s对一行子像素1进行充电，图3中仅示出了前四个充电阶段s1～s4，该四个充电阶段s1～s4分别对第一行至第四行的子像素1进行充电。
在一个帧周期内，栅极驱动电路301的2n个扫描信号输出通道3011逐个输出扫描信号，从而2n条栅线2依次接收到扫描信号，将2n行子像素1依次打开。
源极驱动电路302的3m个数据信号输出通道3021持续输出数据信号，且每个数据信号输出通道3021持续所输出数据信号的电平正负交替变化，正电压和负电压的持续时长均为一个充电阶段s，且任意相邻两个数据信号输出通道3021所输出的数据信号的电压在同一充电阶段极性相反，每个电平的持续时长为一个充电阶段。
从而，在每个充电阶段，相应的一条栅线2接收到扫描信号，将其所对应的一行子像素1打开，3m条数据线3接收到数据信号，将数据信号充入被打开的该行子像素1中，从而在一个帧周期内，完成2n行子像素1的充电，并且，根据图2所示的时序图中数据信号的电平变化方式，如图1所示，在所述多个子像素1中，每相邻两个子像素1所充入的电压正负极性相反，从而实现了点反转。
在上述阵列基板20’中，所需要的栅极驱动电路301的扫描信号输出通道3011的数量与栅线2的数量相等(均为2n个)，所需要的源极驱动电路302的数据信号输出通道3021的数量与数据线3的数量相等(均为3m个)，较多的通道数使得源极驱动电路302和栅极驱动电路301的成本提升。
并且，在上述阵列基板20’所对应的点反转驱动方式中，一个帧周期包括2n个充电阶段s，每个充电阶段对一行子像素1进行充电。在每个充电阶段，源极驱动电路302的每个数据信号输出通道3021所输出的数据信号均要发生一次电压正负极性的切换，即每个充电阶段s，源极驱动电路302的每条数据信号输出通道3021所输出的数据信号，在每次对一个子像素1充电后，就要发生电压正负极性的切换，切换频率较高，而3m条数据线3与3m个数 据信号输出通道3021一一对应，即每条数据线3每次在对一个子像素1进行充电后，其上的电压发生一次正负极性切换，而在液晶显示装置中，面板功耗的主要来源在于数据线3上所接收的数据信号的电压极性的切换，这样就极大增加了液晶显示装置30’的功耗。
基于此，如图4所示，本公开的一些实施例提供一种阵列基板20，该阵列基板20包括：多个子像素1、多条栅线2、多条数据线3、多个扫描信号传输通道4、至少一条扫描控制信号线5、多个数据信号传输通道6、至少一条数据控制信号线7、多个第一控制子电路8和多个第二控制子电路9。
所述多个子像素1呈阵列式布置，每条栅线2与一行子像素1耦接，每条数据线3与一列子像素1耦接。
示例性地，所述多个子像素1排列成2n行3m列，所述多个子像素1的数量为2n×3m个，所述阵列基板20包括2n条栅线2和3m条数据线3，其中，n和m为正整数。
每个第一控制子电路8与所述至少一条扫描控制信号线5、一个扫描信号传输通道4和两条栅线2耦接，即一个扫描信号传输通道4对应两条栅线2，如图4所示，该阵列基板20包括n个扫描信号传输通道4。第一控制子电路8被配置为，在所述至少一条扫描控制信号线5传输的扫描控制信号的控制下，将其所耦接的扫描信号传输通道4传输的扫描信号分别传输至其所耦接的两条栅线2，以分时打开这两条栅线2所耦接的两行子像素1。
每个第二控制子电路9与所述至少一条数据控制信号线7、一个数据信号传输通道6和三条数据线3耦接，即一个数据信号传输通道6对应三条数据线3，如图4所示，该阵列基板20包括m个数据信号传输通道6。第二控制子电路9被配置为，在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将其所耦接的数据信号传输通道6传输的数据信号分别传输至其所耦接的三条数据线3，以分时对这三条数据线3所耦接的子像素1中被栅线2打开的子像素1充电。
示例性地，该阵列基板20包括n个扫描信号传输通道4、m个数据信号传输通道6、两条扫描控制信号线5、至少两条数据控制信号线7、n个第一控制子电路8和m个第二控制子电路9。
第i个第一控制子电路8与第i个扫描信号传输通道4、第2i-1条栅线2和第2i条栅线2耦接；其中，1≤i≤n，i为正整数。这样，第i个第一控制子电路8被配置为在所述两条扫描控制信号线5传输的扫描控制信号的控制下，将其所耦接的第i个扫描信号传输通道4传输的扫描信号分别传输至其所耦接 的第2i-1条栅线2和第2i条栅线2，以分时打开这两条栅线2所耦接的第2i-1行和第2i行子像素1。
第j个第二控制子电路9与第j个数据信号传输通道6、第3j-2条数据线3、第3j-1条数据线3和第3j条数据线3耦接；其中，1≤j≤m，j为正整数。这样，第j个第二控制子电路9被配置为，在所述至少两条数据控制信号线7传输的数据控制信号的控制下，将其所耦接的第j个数据信号传输通道6传输的数据信号分别传输至其所耦接的第3j-2条数据线3、第3j-1条数据线3和第3j条数据线3，以分时对这三条数据线3所耦接的第3j-2行、第3j-1行和第3j行子像素1中被栅线2打开的子像素1充电。
如图11所示，本公开的一些实施例还提供了一种显示装置30，该显示装置30包括上述阵列基板20，栅极驱动电路301和源极驱动电路302，其中，源极驱动电路302通过绑定的方式与阵列基板20连接，栅极驱动电路301通过绑定的方式与阵列基板20连接，或者，栅极驱动电路301通过GOA(Gate on Array)的方式集成在阵列基板上。
栅极驱动电路301具有多个扫描信号输出通道3011，每个扫描信号输出通道3011与阵列基板20中的一个扫描信号传输通道4耦接。源极驱动电路302包括多个数据信号输出通道3021，每个数据信号输出通道3021与阵列基板20中的一个数据信号传输通道6耦接。
另外，栅极驱动电路301还具有至少一个扫描控制信号输出通道3012，每个扫描控制信号输出通道3012与阵列基板20中的一个扫描控制信号线5耦接。源极驱动电路302还包括至少一个数据控制信号输出通道3022，每个数据控制信号输出通道3022与阵列基板20中的一个数据控制信号线7耦接。
在上述显示装置30中，所需要的栅极驱动电路301的扫描信号输出通道3011的数量与阵列基板20中的扫描信号传输通道4的数量相等(均为n个)，所需要的源极驱动电路302的数据信号输出通道3021的数量与阵列基板20中的数据信号传输通道6的数量相等(均为m个)，这样，相比相关技术中，显示装置30’中栅极驱动电路301的扫描信号输出通道3011的数量为2n个，源极驱动电路302的数据信号输出通道3021的数量为3m个，本公开的一些实施例所提供的显示装置30中，栅极驱动电路301的扫描信号输出通道3011的数量减少了一半，源极驱动电路302的数据信号输出通道3021的数量减少了2/3，从而降低了源极驱动电路302和栅极驱动电路301的成本，降低了显示装置的成本。
基于点反转驱动方式，上述阵列基板20的驱动方法为：
为了方便说明，将多个子像素1按以下方式进行划分，每个第一控制子电路8耦接的两条栅线2所控制的两行子像素1划分为沿行方向排列的多个重复单元D，每个重复单元D包括排列成2行3列的6个子像素1。示例性地，如图4～图7所示，阵列基板20包括2n×3m个子像素1，每个第一控制子电路8耦接的两条栅线2所控制的两行子像素1划分为m个重复单元D，阵列基板20所包括的所有子像素1划分为m×n个重复单元D。
结合图8～图10，该驱动方法包括：
一个帧周期包括多个充电阶段T，在每个充电阶段T内对一个第一控制子电路8耦接的两条栅线2所控制的各重复单元D的6个子像素1进行充电，在第i充电阶段T内对第i个第一控制子电路8耦接的两条栅线2所控制的各重复单元D的6个子像素1进行充电。每个充电阶段T包括6个子充电阶段t，在每个子充电阶段t内对每个重复单元D的一个子像素1进行充电。
示例性地，对于图4～图7所示的阵列基板20，该阵列基板20包括2n×3m个子像素1、2n条栅线2和n个扫描信号传输通道4和n个第一控制子电路8，也即一个帧周期包括n个充电阶段T，在每个充电阶段T内对一个第一控制子电路8耦接的两条栅线2所控制的两行子像素1进行充电，从而实现在一个帧周期内对n个第一控制子电路8所耦接的2n条栅线2所控制的2n行子像素1进行充电，使阵列基板20所包括的所有子像素1被充入电压。
在每个子充电阶段t，第一控制子电路8在至少一条扫描控制信号线5传输的扫描控制信号的控制下，将来自扫描信号传输通道4的扫描信号传输至其所耦接的两条栅线2中的一条栅线2，以打开该条栅线2所控制的一行子像素1。
每个第二控制子电路9在至少一条数据控制信号线7传输的数据控制信号的控制下，将来自数据信号传输通道6的数据信号传输至各重复单元D所耦接的一条数据线3，以对各重复单元D中的一个子像素1充电。
也就是说，如图10所示，在每个子充电阶段t，一个第一控制子电路8所耦接的两条栅线2所对应的两行子像素1中的一行子像素1被打开，各重复单元D中的一个子像素1被充电，即该两条栅线2所控制的两行子像素1被划分为m个重复单元D，在该m个重复单元D中，在每个子充电阶段t一共有m个子像素1被充入电压，在一个充电阶段所包括的6个子充电阶段内，该m个重复单元D中的6个子像素1依次被充入电压。
其中，每个数据信号传输通道6所传输的数据信号呈正负电压交替变换，正电压和负电压的持续时长为三个子充电阶段t，且任意相邻两个数据信号传 输通道6所传输的数据信号的电压在同一子充电阶段极性相反。
示例性地，如图8和图9所示，在每个充电阶段T，第一个数据信号传输通道6所传输的数据信号source1的时序为，在前三个子充电阶段t1～t3为正电压，在后三个子充电阶段t4～t6在为负电压；第二个数据信号传输通道6所传输的数据信号source2的时序为，在前三个子充电阶段t1～t3为负电压，在后三个子充电阶段t4～t6在为正电压。即每个数据信号传输通道6所传输的数据信号在每三个子充电阶段t发生一次电压极性的切换。
基于上述数据信号的电压极性变化方式，采用点反转驱动方式，在每个充电阶段T的前三个子充电阶段t1～t3，每个重复单元D中被充电的三个子像素1互不相邻，且被充入的电压均为正电压或者负电压，在每个充电阶段T的后三个子充电阶段t4～t6，每个重复单元D中被充电的三个子像素1互不相邻，且被充入的电压均为负电压或者正电压，从而实现了在每个重复单元D中，每相邻两个子像素1被充入的电压的正负极性相反。并且，由于任意相邻两个数据信号传输通道6所传输的数据信号的电压在同一子充电阶段极性相反，因此在行方向上每相邻两个重复单元D中，处于同一位置的子像素1的被充入的电压的极性相反，这样在一个帧周期内，所有子像素1充电完成后，每相邻两个子像素1被充入的电压的正负极性相反，实现了子像素1的点反转。
可见，在上述阵列基板20的驱动方法中，一个帧周期包括n个充电阶段T，在每个充电阶段T内对一个第一控制子电路8耦接的两条栅线2所控制的两行子像素1进行充电；在每个子充电阶段t，对两行子像素1中对应的各重复单元D中的一个子像素1进行充电，从而在一个充电阶段T内完成对两行子像素1中对应的各重复单元D中的6个子像素1进行充电，在一个帧周期内完成对阵列基板20中所有子像素1的充电。
并且，在上述驱动方法中，每个数据信号传输通道6所传输的数据信号在每三个子充电阶段t发生一次电压极性的切换，即在每个充电阶段T，每个数据信号传输通道6所传输的数据信号，在每次对三个子像素1进行充电后，发生电压正负极性的切换，从而使得每条数据线3上的电压发生切换的间隔时间为一个重复单元D中三个子像素1的充电时长，相比相关技术中的阵列基板20’中，在每次对一个子像素1进行充电后，每条数据线3上就发生电压正负极性的切换，本公开所提供的阵列基板20所对应的驱动方法，每条数据线3中的电压的正负极性切换频率降低，从而能够降低显示装置的功耗。
换言之，本公开所提供的阵列基板20中，每三条数据线3对应一个数据 信号传输通道6，每个数据信号传输通道6所传输的数据信号在每三个子充电阶段t发生一次电压极性的切换，三条数据线在该三个子充电阶段t内分别接收该数据信号，使得本公开所提供的阵列基板20对应的驱动方法，相比相关技术中阵列基板20’对应的驱动方法，在对同样数量的子像素进行充电的情况下，本公开每条数据线上的电压正负极性切换频率为相关技术中每条数据线上的电压正负极性切换频率的三分之一。
从而，本公开的一些实施例提供的阵列基板20的驱动方法，在实现利用点驱动方式改善闪烁和串扰现象，提高显示效果的基础上，能够降低每条数据信号传输通道6所传输的数据信号的电压正负极性的切换频率，从而相应的数据线3上电压极性的切换频率降低，实现了降低显示面板的功耗的效果。
在一些实施例中，上述阵列基板20的一种具体的驱动方法包括：
如图4和图10所示，以阵列基板20中的前4行且前6列子像素1为例，该24个子像素1被划分为4个重复单元D，该四个重复单元D按照从左至右，从上到下的顺序分别为第一重复单元D1、第二重复单元D2、第三重复单元D3和第四重复单元D4，每个所述重复单元D所包括的6个子像素1分别为第一子像素11、第二子像素12、第三子像素13、第四子像素14、第五子像素15和第六子像素16。
示例性地，如图10所示，以每个重复单元D中的左上角的子像素为第一子像素11，按照从左到右、从上到下的顺序对其余五个子像素依次编号为第二子像素12、第三子像素13、第四子像素14、第五子像素15和第六子像素16。对应该子像素的编号顺序，下述提到的两条栅线2中的第一条栅线2和第二条栅线2为按照从上到下的顺序进行编号，三条数据线3中的第一条数据线3、第二条数据线3、第二条数据线3为按照从左到右的顺序进行编号。
如图8和图9所示，每个充电阶段T所包括的6个子充电阶段t分别为第一子充电阶段t1、第二子充电阶段t2、第三子充电阶段t3、第四子充电阶段t4、第五子充电阶段t5和第六子充电阶段t6。以下以第一充电阶段T1为例，对其所包括的6的子充电阶段t进行介绍。
在第一子充电阶段t1：
第一个第一控制子电路8在所述至少一条扫描控制信号线5传输的扫描控制信号的控制下，将来自第一个扫描信号传输通道4的扫描信号Gate1传输至其所耦接的两条栅线2中的第一条栅线2，以打开该栅线2所控制的一行子像素1(即图10中的第一行子像素1)。
每个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控 制信号的控制下，将来自数据信号传输通道6的数据信号传输至各重复单元D所耦接的三条数据线3中的第一条数据线3，以对各重复单元D中的第一子像素11充电。
示例性地，如图4和图10所示，第一个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1所耦接的三条数据线3中的第一条数据线3，以对第一重复单元D1中的第一子像素11充电，且充入正电压。同时，第二个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2所耦接的三条数据线3中的第一条数据线3，以对第二重复单元D2中的第一子像素11充电，且充入负电压。
在第二子充电阶段t2：
第一个第一控制子电路8在所述至少一条扫描控制信号线5传输的扫描控制信号的控制下，将来自第一个扫描信号传输通道4的扫描信号Gate1传输至其所耦接的两条栅线2中的第一条栅线2，以打开该栅线2所控制的一行子像素1(即图10中的第一行子像素1)。
每个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自数据信号传输通道6的数据信号传输至各重复单元D所耦接的三条数据线3中的第三条数据线3，以对各重复单元D中的第三子像素13充电。
示例性地，如图4和图10所示，第一个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1所耦接的三条数据线3中的第三条数据线3，以对第一重复单元D1中的第三子像素13充电，且充入正电压。同时，第二个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2所耦接的三条数据线3中的第三条数据线3，以对第二重复单元D2中的第三子像素13充电，且充入负电压。
在第三子充电阶段t3：
第一个第一控制子电路8在所述至少一条扫描控制信号线5传输的扫描控制信号的控制下，将来自第一个扫描信号传输通道4的扫描信号Gate1传输至其所耦接的两条栅线2中的第二条栅线2，以打开该栅线2所控制的一行子像素1(即图10中的第二行子像素1)。
每个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自数据信号传输通道6的数据信号传输至各重复单元D所耦接的三条数据线3中的第二条数据线3，以对各重复单元D中的第五子像素15充电。
示例性地，如图4和图10所示，第一个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1所耦接的三条数据线3中的第二条数据线3，以对第一重复单元D1中的第五子像素15充电，且充入正电压。同时，第二个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2所耦接的三条数据线3中的第二条数据线3，以对第二重复单元D2中的第五子像素15充电，且充入负电压。
在第四子充电阶段t4：
第一个第一控制子电路8在所述至少一条扫描控制信号线5传输的扫描控制信号的控制下，将来自第一个扫描信号传输通道4的扫描信号Gate1传输至其所耦接的两条栅线2中的第二条栅线2，以打开该栅线2所控制的一行子像素1(即图10中的第二行子像素1)。
每个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自数据信号传输通道6的数据信号传输至各重复单元D所耦接的三条数据线3中的第一条数据线3，以对各重复单元D中的第四子像素14充电。
示例性地，如图4和图10所示，第一个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1所耦接的三条数据线3中的第一条数据线3，以对第一重复单元D1中的第四子像素14充电，且充入负电压。同时，第二个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2所耦接的三条数据线3中的第一条数据线3，以对第二重复单元D2中的第四子像素14充电，且充入正电压。
在第五子充电阶段t5：
第一个第一控制子电路8在所述至少一条扫描控制信号线5传输的扫描控制信号的控制下，将来自扫描信号传输通道4的扫描信号传输Gate1至其所耦接的两条栅线2中的第二条栅线2，以打开该栅线2所控制的一行子像素1 (即图10中的第二行子像素1)。
每个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自数据信号传输通道6的数据信号传输至各重复单元D所耦接的三条数据线3中的第三条数据线3，以对各重复单元D中的第六子像素16充电。
示例性地，如图4和图10所示，第一个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1所耦接的三条数据线3中的第三条数据线3，以对第一重复单元D1中的第六子像素16充电，且充入负电压。同时，第二个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2所耦接的三条数据线3中的第三条数据线3，以对第二重复单元D2中的第六子像素16充电，且充入正电压。
在第六子充电阶段t6：
第一个第一控制子电路8在所述至少一条扫描控制信号线5传输的扫描控制信号的控制下，将来自第一个扫描信号传输通道4的扫描信号Gate1传输至其所耦接的两条栅线2中的第一条栅线2，以打开该栅线2所控制的一行子像素1(即图10中的第一行子像素1)。
每个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自数据信号传输通道6的数据信号传输至各重复单元D所耦接的三条数据线3中的第二条数据线3，以对各重复单元D中的第二子像素12充电。
示例性地，如图4和图10所示，第一个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1所耦接的三条数据线3中的第二条数据线3，以对第一重复单元D1中的第二子像素12充电，且充入负电压。同时，第二个第二控制子电路9在所述至少一条数据控制信号线7传输的数据控制信号的控制下，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2所耦接的三条数据线3中的第二条数据线3，以对第二重复单元D2中的第二子像素12充电，且充入正电压。
这样，在第一充电阶段T1，实现了第一个扫描信号传输通道4所对应的两行子像素1的充电，且在该两行子像素1划分的多个重复单元D中，每个重复单元D的6个子像素1的充电顺序依次为第一子像素11、第三子像素13、 第五子像素15、第四子像素14、第六子像素16和第二子像素12。
并且，第奇数个重复单元D中的第一子像素11、第三子像素13和第五子像素15被充入第一电压(例如为正电压)，第二子像素12、第四子像素14和第六子像素16被充入第二电压(例如为负电压)，第偶数个重复单元D中的第一子像素11、第三子像素13和第五子像素15被充入第二电压(例如为负电压)，第二子像素12、第四子像素14和第六子像素16被充入第一电压(例如为正电压)。其中，所述第一电压和所述第二电压的极性相反。
一个帧周期中的第二充电阶段T2～第n充电阶段Tn可结合图4、图8～图10，及参考对第一充电阶段T1的描述，此处不再赘述。这样，在一个帧周期内，实现了阵列基板20中所有子像素1的点反转。
在一些实施例中，如图5～图7所示，所述至少一条扫描控制信号线5包括第一扫描控制信号线51和第二扫描控制信号线52，每个第一控制子电路8包括第一晶体管M1和第二晶体管M2。
第一晶体管M1的控制极与第一扫描控制信号线51耦接，第一晶体管M1的第一极与该第一控制子电路8所耦接的扫描信号传输通道4耦接，第一晶体管M1的第二极与该第一控制子电路8所耦接的两条栅线2中的一条栅线2耦接。第一晶体管M1被配置为在第一扫描控制信号线51所传输的第一扫描控制信号GEN-1的控制下导通，将其所耦接的扫描信号传输通道4所传输的扫描信号传输至其所耦接的一条栅线2。
第二晶体管M2的控制极与第二扫描控制信号线52耦接，第二晶体管M2的第一极与该第一控制子电路8所耦接的扫描信号传输通道4耦接，第二晶体管M2的第二极与该第一控制子电路8所耦接的两条栅线2中的另一条栅线2耦接。第二晶体管M2被配置为在第二扫描控制信号线52所传输的第二扫描控制信号GEN-2的控制下导通，将其所耦接的扫描信号传输通道4所传输的扫描信号传输至其所耦接的一条栅线2。
在上述实施例中，在每个充电阶段T，相应的第一控制子电路8的第一晶体管M1和第二晶体管M2的驱动过程为：
在第一子充电阶段t1、第二子充电阶段t2和第六子充电阶段t6，第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第一扫描控制信号GEN-1的控制下导通，将来自扫描信号传输通道4的扫描信号传输至其所耦接的一条栅线2。
在第三子充电阶段t3、第四子充电阶段t4和第五子充电阶段t5，第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控 制信号GEN-2的控制下导通，将来自扫描信号传输通道4的扫描信号传输至其所耦接的一条栅线2。
在一些实施例中，如图5～图7所示，所述至少一条数据控制信号线7包括第一数据控制信号线71和第二数据控制信号线72，每个第二控制子电路9包括第三晶体管M3和第四晶体管M4。
第三晶体管M3的控制极与第一数据控制信号线71耦接，第三晶体管M3的第一极与该第二控制子电路9所耦接的数据信号传输通道6耦接，第三晶体管M3的第二极与该第二控制子电路9所耦接的三条数据线3中的第一条数据线3耦接。第三晶体管M3被配置为在第一数据控制信号线71所传输的第一数据控制信号SEN-1的控制下导通，将其所耦接的数据信号传输通道6所传输的数据信号传输至其所耦接的一条数据线3。
第四晶体管M4的控制极与第二数据控制信号线72耦接，第四晶体管M4的第一极与该第二控制子电路9所耦接的数据信号传输通道6耦接，第四晶体管M4的第二极与该第二控制子电路9所耦接的三条数据线3中的第二条数据线3耦接。第四晶体管M4被配置为在第二数据控制信号线72所传输的第二数据控制信号SEN-2的控制下导通，将其所耦接的数据信号传输通道6所传输的数据信号传输至其所耦接的一条数据线3。
在一些实施例中，如图5所示，阵列基板20中，在每个第一控制子电路8包括第一晶体管M1和第二晶体管M2，每个第二控制子电路9包括第三晶体管M3和第四晶体管M4的基础上，所述至少一条数据控制信号线7还包括第三数据控制信号线73，每个第二控制子电路9还包括第五晶体管M5。
第五晶体管M5的控制极与第三数据控制信号线73耦接，第五晶体管M5的第一极与该第二控制子电路9所耦接的数据信号传输通道6耦接，第五晶体管M5的第二极与该第二控制子电路9所耦接的三条数据线3中的第二条数据线3耦接。第五晶体管M5被配置为在第三数据控制信号线73所传输的第三数据控制信号SEN-3的控制下导通，将其所耦接的数据信号传输通道6所传输的数据信号传输至其所耦接的一条数据线3。
对于图5所示的阵列基板20，结合图8所示出的时序图，其驱动方法包括：
一个帧周期包括n个充电阶段T，每个充电阶段T包括6个子充电阶段t。以下以第一充电阶段T1和第二充电阶段T2为例，且以第一控制子电路8所包括的第一晶体管M1和第二晶体管M2，第二控制子电路9所包括的第三晶体管M3、第四晶体管M4和第五晶体管M5均为N型晶体管为例进行说明。
在第一充电阶段T1，第一个扫描信号传输通道4传输扫描信号Gate1，对其所对应的两行子像素1(即第一行子像素1和第二行子像素1)进行充电，该两行子像素1所划分的重复单元D从左至右依次为第一重复单元D1至第m个重复单元D。以下以Tk(tp)表示第k充电阶段Tk的第p子充电阶段tp，k、p均为正整数。
在T1(t1)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第一扫描控制信号GEN-1的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的第三晶体管M3在第一数据控制信号线71传输的第一数据控制信号SEN-1的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第一条数据线3，以对各重复单元D中的第一子像素11充电。
如图5和图8所示，在T1(t1)，第一数据控制信号SEN-1的电平为高电平，从而第一个第二控制子电路9中的第三晶体管M3导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第一条数据线3，以对第一重复单元D1中的第一子像素11充电，且数据信号Source1在T1(t1)的电压为正电压，因此第一重复单元D1中的第一子像素11被充入正电压。同时第二个第二控制子电路9中的第三晶体管M3导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第一条数据线3，以对第二重复单元D2中的第一子像素11充电，且数据信号Source2在T1(t1)的电压为负电压，因此第二重复单元D2中的第一子像素11被充入负电压。
在T1(t2)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第一扫描控制信号GEN-1的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的第五晶体管M5在第三数据控制信号线73传输的第三数据控制信号SEN-3的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第三条数据线3，以对各重复单元D中的第三子像素13充电。
如图5和图8所示，在T1(t2)，第三数据控制信号SEN-3的电平为高电平，从而第一个第二控制子电路9中的第五晶体管M5导通，将来自第一个 数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第三条数据线3，以对第一重复单元D1中的第三子像素13充电，且数据信号Source1在T1(t2)的电压为正电压，因此第一重复单元D1中的第三子像素13被充入正电压。同时第二个第二控制子电路9中的第五晶体管M5导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第三条数据线3，以对第二重复单元D2中的第三子像素13充电，且数据信号Source2在T1(t2)的电压为负电压，因此第二重复单元D2中的第三子像素13被充入负电压。
在T1(t3)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的第四晶体管M4在第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第二条数据线3，以对各重复单元D中的第五子像素15充电。
如图5和图8所示，在T1(t3)，第二数据控制信号SEN-2的电平为高电平，从而第一个第二控制子电路9中的第四晶体管M4导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第二条数据线3，以对第一重复单元D1中的第五子像素15充电，且数据信号Source1在T1(t3)的电压为正电压，因此第一重复单元D1中的第五子像素15被充入正电压。同时第二个第二控制子电路9中的第四晶体管M4导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第二条数据线3，以对第二重复单元D2中的第五子像素15充电，且数据信号Source2在T1(t3)的电压为负电压，因此第二重复单元D2中的第五子像素15被充入负电压。
在T1(t4)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的第三晶体管M3在第一数据控制信号线71传输的第一数据控制信号SEN-1的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第一条数据线3，以 对各重复单元D中的第四子像素14充电。
如图5和图8所示，在T1(t4)，第一数据控制信号SEN-1的电平为高电平，从而第一个第二控制子电路9中的第三晶体管M3导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第一条数据线3，以对第一重复单元D1中的第四子像素14充电，且数据信号Source1在T1(t4)的电压为负电压，因此第一重复单元D1中的第四子像素14被充入负电压。同时第二个第二控制子电路9中的第三晶体管M3导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第一条数据线3，以对第二重复单元D2中的第四子像素14充电，且数据信号Source2在T1(t4)的电压为正电压，因此第二重复单元D2中的第四子像素14被充入正电压。
在T1(t5)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的第五晶体管M5在第三数据控制信号线73传输的第三数据控制信号SEN-3的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第三条数据线3，以对各重复单元D中的第六子像素16充电。
如图5和图8所示，在T1(t5)，第三数据控制信号SEN-3的电平为高电平，从而第一个第二控制子电路9中的第五晶体管M5导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第三条数据线3，以对第一重复单元D1中的第六子像素16充电，且数据信号Source1在T1(t5)的电压为负电压，因此第一重复单元D1中的第四子像素14被充入负电压。同时第二个第二控制子电路9中的第五晶体管M5导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第三条数据线3，以对第二重复单元D2中的第六子像素16充电，且数据信号Source2在T1(t5)的电压为正电压，因此第二重复单元D2中的第六子像素16被充入正电压。
在T1(t6)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第二扫描控制信号GEN-1的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的第四晶体管M4在第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第二条数据线3，以对各重复单元D中的第二子像素12充电。
如图5和图8所示，在T1(t6)，第二数据控制信号SEN-2的电平为高电平，从而第一个第二控制子电路9中的第四晶体管M4导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第二条数据线3，以对第一重复单元D1中的第二子像素12充电，且数据信号Source1在T1(t6)的电压为负电压，因此第一重复单元D1中的第二子像素12被充入负电压。同时，第二个第二控制子电路9中的第四晶体管M4导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第二条数据线3，以对第二重复单元D2中的第二子像素12充电，且数据信号Source2在T1(t6)的电压为正电压，因此第二重复单元D2中的第二子像素12被充入正电压。
在第二充电阶段T2，第二个扫描信号传输通道4传输扫描信号Gate2，对其所对应的两行子像素1(即第三行子像素1和第四行子像素1)进行充电，第二充电阶段T2中6个子充电阶段的驱动过程可结合图8所示的时序图，以及上述对第一充电阶段T1中6个子充电阶段的说明，此处不再赘述。
在一些示例中，第一控制子电路8所包括的第一晶体管M1和第二晶体管M2，第二控制子电路9所包括的第三晶体管M3、第四晶体管M4和第五晶体管M5均为P型晶体管，其对应的第一扫描控制信号GEN-1、第二扫描控制信号GEN-2、第一数据控制信号SEN-1、第二数据控制信号SEN-2和第三数据控制信号SEN-3的时序在图8所示的时序的基础上进行翻转即可。
在一些实施例中，如图6和图7所示，阵列基板20中，在每个第一控制子电路8包括第一晶体管M1和第二晶体管M2，每个第二控制子电路9包括第三晶体管M3和第四晶体管M4的基础上，每个第二控制子电路9还包括开关单元91。
第二控制子电路9的开关单元91与第一数据控制信号线71、第二数据控制信号线72耦接，开关单元91还与该第二控制子电路9所耦接的数据信号传输通道6、该第二控制子电路9所耦接的三条数据线3中的第三条数据线3耦接。
开关单元91被配置为，在第一数据控制信号线71传输的第一数据控制信号SEN-1、及第二数据控制信号线72传输的第二数据控制信号SEN-2的控 制下，将其所耦接的数据信号传输通道6传输的数据信号传输至其所耦接的数据线3。
如图6所示，在一些示例中，开关单元91包括第六晶体管M6和第七晶体管M7。
第六晶体管M6的控制极与第一数据控制信号线71耦接，第六晶体管M6的第一极与该开关单元91所耦接的数据信号传输通道6耦接，第六晶体管M6的第二极与所述第七晶体管M7的第一极耦接。
第七晶体管M7的控制极与第二数据控制信号线72耦接，第七晶体管M7的第二极与该开关单元91所耦接的数据线3耦接。
在上述开关单元91中，在第六晶体管M6在第一数据控制信号线71所传输的第一数据控制信号SEN-1的控制下导通，且第七晶体管M7在第二数据控制信号线72所传输的第二数据控制信号SEN-2的控制下导通的情况下，该开关单元91所耦接的数据信号传输通道6传输的数据信号能够传输至其所耦接的数据线3。
在一些实施例中，第六晶体管M6和第七晶体管M7的类型相同，第三晶体管M3和第四晶体管M4的类型相同，且第六晶体管M6和第七晶体管M7的类型与第三晶体管M3和第四晶体管M4的类型不同。
示例性地，如图6所示，第三晶体管M3和第四晶体管M4均为N型晶体管，第六晶体管M6和第七晶体管M7均为P型晶体管。
对于图6所示的阵列基板20，结合图9所示出的时序图，其驱动方法包括：
一个帧周期包括n个充电阶段T，每个充电阶段T包括6个子充电阶段t。以下以第一充电阶段T1和第二充电阶段T2为例，且以第一控制子电路8所包括的第一晶体管M1和第二晶体管M2均为N型晶体管，第二控制子电路9所包括的第三晶体管M3和第四晶体管M4均为N型晶体管，第六晶体管M6和第七晶体管M7均为P型晶体管为例进行说明。
在第一充电阶段T1，第一个扫描信号传输通道4传输扫描信号Gate1，对其所对应的两行子像素1(即第一行子像素1和第二行子像素1)进行充电，该两行子像素1所划分的重复单元D从左至右依次为第一重复单元D1至第m个重复单元D。以下以Tk(tp)表示第k充电阶段Tk的第p子充电阶段tp，k、p均为正整数。
在T1(t1)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第一扫描控制信号GEN-1的控制下导通，将来自第一个 扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的第三晶体管M3在第一数据控制信号线71传输的第一数据控制信号SEN-1的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第一条数据线3，以对各重复单元D中的第一子像素11充电。
如图6和图9所示，在T1(t1)，第一数据控制信号SEN-1的电平为高电平，从而第一个第二控制子电路9中的第三晶体管M3导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第一条数据线3，以对第一重复单元D1中的第一子像素11充电，且数据信号Source1在T1(t1)的电压为正电压，因此第一重复单元D1中的第一子像素11被充入正电压。同时第二个第二控制子电路9中的第三晶体管M3导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第一条数据线3，以对第二重复单元D2中的第一子像素11充电，且数据信号Source2在T1(t1)的电压为负电压，因此第二重复单元D2中的第一子像素11被充入负电压。
在T1(t2)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第一扫描控制信号GEN-1的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的开关单元91在第一数据控制信号线71传输的第一数据控制信号SEN-1、及第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第三条数据线3，以对各重复单元D中的第三子像素13充电。
如图6和图9所示，在T1(t2)，第一扫描控制信号GEN-1和第二扫描控制信号GEN-2的电平均为低电平，从而第一个第二控制子电路9中，开关单元91中的第六晶体管M6和第七晶体管M7均导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第三条数据线3，以对第一重复单元D1中的第三子像素13充电，且数据信号Source1在T1(t2)的电压为正电压，因此第一重复单元D1中的第三子像素13被充入正电压。同时第二个第二控制子电路9中，开关单元91中的第六晶体管M6和第七晶体管M7均导通，将来自第二个数据信号传输通道 6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第三条数据线3，以对第二重复单元D2中的第三子像素13充电，且数据信号Source2在T1(t2)的电压为负电压，因此第二重复单元D2中的第三子像素13被充入负电压。
在T1(t3)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的第四晶体管M4在第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第二条数据线3，以对各重复单元D中的第五子像素15充电。
如图6和图9所示，在T1(t3)，第二数据控制信号SEN-2的电平为高电平，从而第一个第二控制子电路9中的第四晶体管M4导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第二条数据线3，以对第一重复单元D1中的第五子像素15充电，且数据信号Source1在T1(t3)的电压为正电压，因此第一重复单元D1中的第五子像素15被充入正电压。同时第二个第二控制子电路9中的第四晶体管M4导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第二条数据线3，以对第二重复单元D2中的第五子像素15充电，且数据信号Source2在T1(t3)的电压为负电压，因此第二重复单元D2中的第五子像素15被充入负电压。
在T1(t4)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的第三晶体管M3在第一数据控制信号线71传输的第一数据控制信号SEN-1的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第一条数据线3，以对各重复单元D中的第四子像素14充电。
如图6和图9所示，在T1(t4)，第一数据控制信号SEN-1的电平为高电平，从而第一个第二控制子电路9中的第三晶体管M3导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条 数据线3中的第一条数据线3，以对第一重复单元D1中的第四子像素14充电，且数据信号Source1在T1(t4)的电压为负电压，因此第一重复单元D1中的第四子像素14被充入负电压。同时第二个第二控制子电路9中的第三晶体管M3导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第一条数据线3，以对第二重复单元D2中的第四子像素14充电，且数据信号Source2在T1(t4)的电压为正电压，因此第二重复单元D2中的第四子像素14被充入正电压。
在T1(t5)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的开关单元91在第一数据控制信号线71传输的第一数据控制信号SEN-1、及第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第三条数据线3，以对各重复单元D中的第六子像素16充电。
如图6和图9所示，在T1(t5)，第一扫描控制信号GEN-1和第二扫描控制信号GEN-2的电平均为低电平，从而第一个第二控制子电路9中，开关单元91中的第六晶体管M6和第七晶体管M7均导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第三条数据线3，以对第一重复单元D1中的第六子像素16充电，且数据信号Source1在T1(t5)的电压为负电压，因此第一重复单元D1中的第四子像素14被充入负电压。同时第二个第二控制子电路9中，开关单元91中的第六晶体管M6和第七晶体管M7均导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第三条数据线3，以对第二重复单元D2中的第六子像素16充电，且数据信号Source2在T1(t5)的电压为正电压，因此第二重复单元D2中的第六子像素16被充入正电压。
在T1(t6)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第二扫描控制信号GEN-1的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的第四晶体管M4在第二数据控制信号线72传 输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第二条数据线3，以对各重复单元D中的第二子像素12充电。
如图6和图9所示，在T1(t6)，第二数据控制信号SEN-2的电平为高电平，从而第一个第二控制子电路9中的第四晶体管M4导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第二条数据线3，以对第一重复单元D1中的第二子像素12充电，且数据信号Source1在T1(t6)的电压为负电压，因此第一重复单元D1中的第二子像素12被充入负电压。同时，第二个第二控制子电路9中的第四晶体管M4导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第二条数据线3，以对第二重复单元D2中的第二子像素12充电，且数据信号Source2在T1(t6)的电压为正电压，因此第二重复单元D2中的第二子像素12被充入正电压。
在第二充电阶段T2，第二个扫描信号传输通道4传输扫描信号Gate2，对其所对应的两行子像素1(即第三行子像素1和第四行子像素1)进行充电，第二充电阶段T2中6个子充电阶段的驱动过程可结合图9所示的时序图，以及上述对第一充电阶段T1中6个子充电阶段的说明，此处不再赘述。
如图7所示，在另一些示例中，开关单元91包括与非门电路911和第八晶体管M8。
与非门电路911与第一数据控制信号线71、第二数据控制信号线72和第八晶体管M8的控制极耦接。与非门电路911被配置为在第一数据控制信号线71所传输的第一数据控制信号SEN-1，以及第二数据控制信号线72所传输的第二数据控制信号SEN-2的控制下，输出控制第八晶体管M8导通的控制信号至第八晶体管M8的控制极。
第八晶体管M8的第一极与该开关单元91所耦接的数据信号传输通道6耦接，第八晶体管M8的第二极与该开关单元91所耦接的数据线3耦接。第八晶体管M8被配置为在与非门电路911所输出的控制信号的控制下导通，将该开关单元91所耦接的数据信号传输通道6所传输的数据信号，传输至该开关单元91所耦接的数据线3。
根据与非门电路911的特点，在输入与非门电路911的两个信号均为高电平(1)时，则输出为低电平(0)，若输入与非门电路911的两个信号中至少有一个为低电平(0)，则输出为高电平(1)。因此，示例性地，在第一数据控制信号线71所传输的第一数据控制信号SEN-1，以及第二数据控制信号线72所 传输的第二数据控制信号SEN-2中至少有一个为低电平时，与非门电路911能够输出高电平信号，在第八晶体管M8为N型晶体管的情况下，第八晶体管M8在该高电平信号的控制下导通，将数据信号传输至其所耦接的数据线3。
在一些实施例中，第三晶体管M3、第四晶体管M4和第八晶体管M8的类型相同，例如，如图7所示，第三晶体管M3、第四晶体管M4和第八晶体管M8均为N型晶体管。
对于图7所示的阵列基板20，结合图9所示出的时序图，其驱动方法包括：
一个帧周期包括n个充电阶段T，每个充电阶段T包括6个子充电阶段t。以下以第一充电阶段T1和第二充电阶段T2为例，且以第一控制子电路8所包括的第一晶体管M1和第二晶体管M2均为N型晶体管，第二控制子电路9所包括的第三晶体管M3、第四晶体管M4和第八晶体管M8均为N型晶体管为例进行说明。
在第一充电阶段T1，第一个扫描信号传输通道4传输扫描信号Gate1，对其所对应的两行子像素1(即第一行子像素1和第二行子像素1)进行充电，该两行子像素1所划分的重复单元D从左至右依次为第一重复单元D1至第m个重复单元D。以下以Tk(tp)表示第k充电阶段Tk的第p子充电阶段tp，k、p均为正整数。
在T1(t1)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第一扫描控制信号GEN-1的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的第三晶体管M3在第一数据控制信号线71传输的第一数据控制信号SEN-1的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第一条数据线3，以对各重复单元D中的第一子像素11充电。
如图7和图9所示，在T1(t1)，第一数据控制信号SEN-1的电平为高电平，从而第一个第二控制子电路9中的第三晶体管M3导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第一条数据线3，以对第一重复单元D1中的第一子像素11充电，且数据信号Source1在T1(t1)的电压为正电压，因此第一重复单元D1中的第一子像素11被充入正电压。同时第二个第二控制子电路9中的第三晶体管M3导通，将来自第二个数据信号传输通道6的数据信号Source2传输至 第二重复单元D2对应的三条数据线3中的第一条数据线3，以对第二重复单元D2中的第一子像素11充电，且数据信号Source2在T1(t1)的电压为负电压，因此第二重复单元D2中的第一子像素11被充入负电压。
在T1(t2)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第一扫描控制信号GEN-1的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的开关单元91在第一数据控制信号线71传输的第一数据控制信号SEN-1、及第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第三条数据线3，以对各重复单元D中的第三子像素13充电。
如图7和图9所示，在T1(t2)，第一扫描控制信号GEN-1和第二扫描控制信号GEN-2的电平均为低电平，从而第一个第二控制子电路9中，开关单元91中的与非门电路911输出高电平信号，第八晶体管M8在该高电平信号的控制下导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第三条数据线3，以对第一重复单元D1中的第三子像素13充电，且数据信号Source1在T1(t2)的电压为正电压，因此第一重复单元D1中的第三子像素13被充入正电压。同时第二个第二控制子电路9中，开关单元91中的与非门电路911输出高电平信号，第八晶体管M8在该高电平信号的控制下导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第三条数据线3，以对第二重复单元D2中的第三子像素13充电，且数据信号Source2在T1(t2)的电压为负电压，因此第二重复单元D2中的第三子像素13被充入负电压。
在T1(t3)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的第四晶体管M4在第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第二条数据线3，以对各重复单元D中的第五子像素15充电。
如图7和图9所示，在T1(t3)，第二数据控制信号SEN-2的电平为高电平，从而第一个第二控制子电路9中的第四晶体管M4导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第二条数据线3，以对第一重复单元D1中的第五子像素15充电，且数据信号Source1在T1(t3)的电压为正电压，因此第一重复单元D1中的第五子像素15被充入正电压。同时第二个第二控制子电路9中的第四晶体管M4导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第二条数据线3，以对第二重复单元D2中的第五子像素15充电，且数据信号Source2在T1(t3)的电压为负电压，因此第二重复单元D2中的第五子像素15被充入负电压。
在T1(t4)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的第三晶体管M3在第一数据控制信号线71传输的第一数据控制信号SEN-1的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第一条数据线3，以对各重复单元D中的第四子像素14充电。
如图7和图9所示，在T1(t4)，第一数据控制信号SEN-1的电平为高电平，从而第一个第二控制子电路9中的第三晶体管M3导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第一条数据线3，以对第一重复单元D1中的第四子像素14充电，且数据信号Source1在T1(t4)的电压为负电压，因此第一重复单元D1中的第四子像素14被充入负电压。同时第二个第二控制子电路9中的第三晶体管M3导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第一条数据线3，以对第二重复单元D2中的第四子像素14充电，且数据信号Source2在T1(t4)的电压为正电压，因此第二重复单元D2中的第四子像素14被充入正电压。
在T1(t5)，第一个第一控制子电路8中的第二晶体管M2在第二扫描控制信号线52传输的第二扫描控制信号GEN-2的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第二条栅线2)，从而将第二行子像素1打开。
每个第二控制子电路9中的开关单元91在第一数据控制信号线71传输 的第一数据控制信号SEN-1、及第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第三条数据线3，以对各重复单元D中的第六子像素16充电。
如图7和图9所示，在T1(t5)，第一扫描控制信号GEN-1和第二扫描控制信号GEN-2的电平均为低电平，从而第一个第二控制子电路9中，开关单元91中与非门电路911输出高电平信号，第八晶体管M8在该高电平信号的控制下导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第三条数据线3，以对第一重复单元D1中的第六子像素16充电，且数据信号Source1在T1(t5)的电压为负电压，因此第一重复单元D1中的第四子像素14被充入负电压。同时第二个第二控制子电路9中，开关单元91中的与非门电路911输出高电平信号，第八晶体管M8在该高电平信号的控制下导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第三条数据线3，以对第二重复单元D2中的第六子像素16充电，且数据信号Source2在T1(t5)的电压为正电压，因此第二重复单元D2中的第六子像素16被充入正电压。
在T1(t6)，第一个第一控制子电路8中的第一晶体管M1在第一扫描控制信号线51传输的第二扫描控制信号GEN-1的控制下导通，将来自第一个扫描信号传输通道4的扫描信号传输至其所耦接的栅线2(即第一条栅线2)，从而将第一行子像素1打开。
每个第二控制子电路9中的第四晶体管M4在第二数据控制信号线72传输的第二数据控制信号SEN-2的控制下导通，将来自数据信号传输通道6的数据信号传输至各重复单元D对应的三条数据线3中的第二条数据线3，以对各重复单元D中的第二子像素12充电。
如图7和图9所示，在T1(t6)，第二数据控制信号SEN-2的电平为高电平，从而第一个第二控制子电路9中的第四晶体管M4导通，将来自第一个数据信号传输通道6的数据信号Source1传输至第一重复单元D1对应的三条数据线3中的第二条数据线3，以对第一重复单元D1中的第二子像素12充电，且数据信号Source1在T1(t6)的电压为负电压，因此第一重复单元D1中的第二子像素12被充入负电压。同时，第二个第二控制子电路9中的第四晶体管M4导通，将来自第二个数据信号传输通道6的数据信号Source2传输至第二重复单元D2对应的三条数据线3中的第二条数据线3，以对第二重复 单元D2中的第二子像素12充电，且数据信号Source2在T1(t6)的电压为正电压，因此第二重复单元D2中的第二子像素12被充入正电压。
在第二充电阶段T2，第二个扫描信号传输通道4传输扫描信号Gate2，对其所对应的两行子像素1(即第三行子像素1和第四行子像素1)进行充电，第二充电阶段T2中6个子充电阶段的驱动过程可结合图9所示的时序图，以及上述对第一充电阶段T1中6个子充电阶段的说明，此处不再赘述。
本公开的一些实施例所提供的阵列基板20中，所采用的晶体管的控制极为晶体管的栅极，第一极可以为源极，第二极可以为漏极，或者上述晶体管的第一极可以为漏极，第二极为源极，本公开对此均不作限定。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在一些实施例中，如图4所示，在本公开的一些实施例所提供的阵列基板20中，所述至少一条扫描控制信号线5沿多个子像素1排列的列方向延伸，所述至少一条数据控制信号线7沿多个子像素1排列的行方向延伸。
在一些示例中，如图4所示，阵列基板20包括显示区AA和边框区BB，阵列基板20中多个子像素1、多条栅线2和多条数据线3设置于显示区AA，多个扫描信号传输通道4、至少一条扫描控制信号线5、多个数据信号传输通道6和至少一条数据控制信号线7、多个第一控制子电路8个多个第二控制子电路9设置于边框区BB。
在一些实施例中，每个子像素1包括驱动晶体管。如图5～图7所示，在阵列基板20中的第一控制子电路8包括第一晶体管M1和第二晶体管M2，第二控制子电路9包括第三晶体管M3和第四晶体管M4的情况下，第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4的栅极、有源层、及源极和漏极分别与驱动晶体管的栅极、有源层、及源极和漏极同层设置。
在上述实施例中，将第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4的各膜层与子像素1中的驱动晶体管各膜层对应同层设置，在阵列基板20的制备时，各膜层可以采用一次构图工艺，同步形成，从而简化了制备工艺，提高了制备效率。
在一些实施例中，本公开所提供的阵列基板20中，每个子像素1所包括的驱动晶体管为氧化物薄膜晶体管(Oxide TFT)，氧化物薄膜晶体管的载流 子迁移率较高，信号传输速率较快，且成本较低，从而使得本公开的阵列基板20的实用性更高。
如图11所示，本公开的一些实施例所提供的显示装置30包括阵列基板20、栅极驱动电路301和源极驱动电路302，该显示装置30具有节省栅极驱动电路301中的扫描信号输出通道3011的数量，以及源极驱动电路302的数据信号输出通道3021的数量的优点，从而使得成本降低，且在显示过程中，闪烁和串扰现象较少，且功耗降低。
该显示装置30可以为电视、手机、电脑、笔记本电脑、平板电脑、个人数字助理(personal digital assistant，PDA)、车载电脑等，本公开对此并不设限。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种阵列基板的驱动方法，其中，所述阵列基板包括：
    多个子像素、多条栅线和多条数据线；所述多个子像素呈阵列式布置，一行子像素与一条栅线耦接，一列子像素与一条数据线耦接；
    多个扫描信号传输通道、至少一条扫描控制信号线、多个数据信号传输通道和至少一条数据控制信号线；
    多个第一控制子电路，每个第一控制子电路与所述至少一条扫描控制信号线、一个扫描信号传输通道和两条栅线耦接；
    多个第二控制子电路，每个第二控制子电路与所述至少一条数据控制信号线、一个数据信号传输通道和三条数据线耦接；
    每个第一控制子电路耦接的两条栅线所控制的两行子像素划分为沿行方向排列的多个重复单元，每个重复单元包括排列成2行3列的6个子像素；
    所述驱动方法包括：
    一个帧周期包括多个充电阶段，在每个充电阶段内对一个第一控制子电路耦接的两条栅线所控制的各重复单元的6个子像素进行充电；每个充电阶段包括6个子充电阶段，在每个子充电阶段内对每个重复单元的一个子像素进行充电；
    在每个子充电阶段，
    第一控制子电路在至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的一条栅线，以打开该条栅线所控制的一行子像素；
    每个第二控制子电路在至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的一条数据线，以对各重复单元中的一个子像素充电；
    其中，每个数据信号传输通道所传输的数据信号呈正负电压交替变换，正电压和负电压的持续时长为三个子充电阶段，且任意相邻两个数据信号传输通道所传输的数据信号的电压在同一子充电阶段极性相反。
  2. 根据权利要求1所述的驱动方法，其中，
    每个所述重复单元所包括的6个子像素分别为第一子像素、第二子像素、第三子像素、第四子像素、第五子像素和第六子像素；
    每个所述充电阶段所包括的6个子充电阶段分别为第一子充电阶段、第二子充电阶段、第三子充电阶段、第四子充电阶段、第五子充电阶段和第六子充电阶段；
    在所述第一子充电阶段，
    第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第一条栅线，以打开该栅线所控制的一行子像素；
    每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第一条数据线，以对各重复单元中的第一子像素充电；
    在所述第二子充电阶段，
    第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第一条栅线，以打开该栅线所控制的一行子像素；
    每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第三条数据线，以对各重复单元中的第三子像素充电；
    在所述第三子充电阶段，
    第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第二条栅线，以打开该栅线所控制的一行子像素；
    每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第二条数据线，以对各重复单元中的第五子像素充电；
    在所述第四子充电阶段，
    第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第二条栅线，以打开该栅线所控制的一行子像素；
    每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第一条数据线，以对各重复单元中的第四子像素充电；
    在所述第五子充电阶段，
    第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第二条栅线，以打开该栅线所控制的一行子像素；
    每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接 的三条数据线中的第三条数据线，以对各重复单元中的第六子像素充电；
    在所述第六子充电阶段，
    第一控制子电路在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将来自扫描信号传输通道的扫描信号传输至其所耦接的两条栅线中的第一条栅线，以打开该栅线所控制的一行子像素；
    每个第二控制子电路在所述至少一条数据控制信号线传输的数据控制信号的控制下，将来自数据信号传输通道的数据信号传输至各重复单元所耦接的三条数据线中的第二条数据线，以对各重复单元中的第二子像素充电；
    其中，第奇数个重复单元中的第一子像素、第三子像素和第五子像素被充入第一电压，第二子像素、第四子像素和第六子像素被充入第二电压；第偶数个重复单元中的第一子像素、第三子像素和第五子像素被充入第二电压，第二子像素、第四子像素和第六子像素被充入第一电压；
    其中，所述第一电压和所述第二电压的极性相反。
  3. 根据权利要求2所述的驱动方法，其中，所述至少一条扫描控制信号线包括第一扫描控制信号线和第二扫描控制信号线；
    所述第一控制子电路包括第一晶体管和第二晶体管；
    在所述第一子充电阶段、所述第二子充电阶段和所述第六子充电阶段，第一控制子电路中的第一晶体管在所述第一扫描控制信号线传输的第一扫描控制信号的控制下导通，将来自扫描信号传输通道的扫描信号传输至其所耦接的栅线；
    在所述第三子充电阶段、所述第四子充电阶段和所述第五子充电阶段，第一控制子电路中的第二晶体管在所述第二扫描控制信号线传输的第二扫描控制信号的控制下导通，将来自扫描信号传输通道的扫描信号传输至其所耦接的栅线。
  4. 根据权利要求3所述的驱动方法，其中，所述至少一条数据控制信号线包括第一数据控制信号线、第二数据控制信号线和第三数据控制信号线；
    所述第二控制子电路包括第三晶体管、第四晶体管和第五晶体管；
    在所述第一子充电阶段，每个第二控制子电路中的第三晶体管在所述第一数据控制信号线传输的第一数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第一条数据线，以对各重复单元中的第一子像素充电；
    在所述第二子充电阶段，每个第二控制子电路中的第五晶体管在所述第三数据控制信号线传输的第三数据控制信号的控制下导通，将来自数据信号 传输通道的数据信号传输至各重复单元对应的三条数据线中的第三条数据线，以对各重复单元中第三子像素充电；
    在所述第三子充电阶段，每个第二控制子电路中的第四晶体管在所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第二条数据线，以对各重复单元中的第五子像素充电；
    在所述第四子充电阶段，每个第二控制子电路中的第三晶体管在所述第一数据控制信号线传输的第一数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第一条数据线，以对各重复单元中的第四子像素充电；
    在所述第五子充电阶段，每个第二控制子电路中的第五晶体管在所述第三数据控制信号线传输的第三数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第三条数据线，以对各重复单元中的第六子像素充电；
    在所述第六子充电阶段，每个第二控制子电路中的第四晶体管在所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第二条数据线，以对各重复单元中的第二子像素充电。
  5. 根据权利要求3所述的驱动方法，其中，所述至少一条数据控制信号线包括第一数据控制信号线和第二数据控制信号线，所述第二控制子电路包括第三晶体管、第四晶体管和开关单元，
    在所述第一子充电阶段，每个第二控制子电路中的第三晶体管在所述第一数据控制信号线传输的第一数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第一条数据线，以对各重复单元中的第一子像素充电；
    在所述第二子充电阶段，每个第二控制子电路中的开关单元在所述第一数据控制信号线传输的第一数据控制信号、及所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第三条数据线，以对各重复单元中第三子像素充电；
    在所述第三子充电阶段，每个第二控制子电路中的第四晶体管在所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第二条数据 线，以对各重复单元中的第五子像素充电；
    在所述第四子充电阶段，每个第二控制子电路中的第三晶体管在所述第一数据控制信号线传输的第一数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第一条数据线，以对各重复单元中的第四子像素充电；
    在所述第五子充电阶段，每个第二控制子电路中的开关单元在所述第一数据控制信号线传输的第一数据控制信号、及所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第三条数据线，以对各重复单元中的第六子像素充电；
    在所述第六子充电阶段，每个第二控制子电路中的第四晶体管在所述第二数据控制信号线传输的第二数据控制信号的控制下导通，将来自数据信号传输通道的数据信号传输至各重复单元对应的三条数据线中的第二条数据线，以对各重复单元中的第二子像素充电。
  6. 一种阵列基板，包括：
    多个子像素、多条栅线和多条数据线；所述多个子像素呈阵列式布置，一行子像素与一条栅线耦接，一列子像素与一条数据线耦接；
    多个扫描信号传输通道、至少一条扫描控制信号线、多个数据信号传输通道和至少一条数据控制信号线；
    多个第一控制子电路，每个第一控制子电路与所述至少一条扫描控制信号线、一个扫描信号传输通道和两条栅线耦接；所述第一控制子电路被配置为，在所述至少一条扫描控制信号线传输的扫描控制信号的控制下，将其所耦接的扫描信号传输通道传输的扫描信号分别传输至其所耦接的两条栅线，以分时打开这两条栅线所耦接的两行子像素；
    多个第二控制子电路，每个第二控制子电路与所述至少一条数据控制信号线、一个数据信号传输通道和三条数据线耦接；所述第二控制子电路被配置为，在所述至少一条数据控制信号线传输的数据控制信号的控制下，将其所耦接的数据信号传输通道传输的数据信号分别传输至其所耦接的三条数据线，以分时对这三条数据线所耦接的子像素中被栅线打开的子像素充电。
  7. 根据权利要求6所述的阵列基板，其中，
    所述多个子像素排列成2n行3m列；
    所述阵列基板包括2n条栅线、3m条数据线、n个扫描信号传输通道、m个数据信号传输通道、两条扫描控制信号线、至少两条数据控制信号线、n个 第一控制子电路和m个第二控制子电路；其中，n和m为正整数；
    第i个第一控制子电路与第i个扫描信号传输通道、第2i-1条栅线和第2i条栅线耦接；其中，1≤i≤n，i为正整数；
    第j个第二控制子电路与第j个数据信号传输通道、第3j-2条数据线、第3j-1条数据线和第3j条数据线耦接；其中，1≤j≤m，j为正整数。
  8. 根据权利要求6或7所述的阵列基板，其中，
    所述至少一条扫描控制信号线包括第一扫描控制信号线和第二扫描控制信号线；
    每个所述第一控制子电路包括第一晶体管和第二晶体管；其中，
    所述第一晶体管的控制极与所述第一扫描控制信号线耦接，所述第一晶体管的第一极与所述第一控制子电路所耦接的扫描信号传输通道耦接，所述第一晶体管的第二极与所述第一控制子电路所耦接的两条栅线中的一条栅线耦接；
    所述第二晶体管的控制极与所述第二扫描控制信号线耦接，所述第二晶体管的第一极与所述第一控制子电路所耦接的扫描信号传输通道耦接，所述第二晶体管的第二极与所述第一控制子电路所耦接的两条栅线中的另一条栅线耦接。
  9. 根据权利要求6～8中任一项所述的阵列基板，其中，
    所述至少一条数据控制信号线包括第一数据控制信号线和第二数据控制信号线；
    每个所述第二控制子电路包括第三晶体管和第四晶体管；其中，
    所述第三晶体管的控制极与所述第一数据控制信号线耦接，所述第三晶体管的第一极与所述第二控制子电路所耦接的数据信号传输通道耦接，所述第三晶体管的第二极与所述第二控制子电路所耦接的三条数据线中的第一条数据线耦接；
    所述第四晶体管的控制极与所述第二数据控制信号线耦接，所述第四晶体管的第一极与所述第二控制子电路所耦接的数据信号传输通道耦接，所述第四晶体管的第二极与所述第二控制子电路所耦接的三条数据线中的第二条数据线耦接。
  10. 根据权利要求9所述的阵列基板，其中，所述至少一条数据控制信号线还包括第三数据控制信号线；
    每个所述第二控制子电路还包括第五晶体管；其中，
    所述第五晶体管的控制极与所述第三数据控制信号线耦接，所述第五晶 体管的第一极与所述第二控制子电路所耦接的数据信号传输通道耦接，所述第五晶体管的第二极与所述第二控制子电路所耦接的三条数据线中的第三条数据线耦接。
  11. 根据权利要求9所述的阵列基板，其中，所述第二控制子电路还包括开关单元，
    所述开关单元与所述第一数据控制信号线、所述第二数据控制信号线耦接，所述开关单元还与所述第二控制子电路所耦接的数据信号传输通道、所述第二控制子电路所耦接的三条数据线中的第三条数据线耦接；
    所述开关单元被配置为，在所述第一数据控制信号线传输的第一数据控制信号、及所述第二数据控制信号线传输的第二数据控制信号的控制下，将其所耦接的数据信号传输通道传输的数据信号传输至其所耦接的数据线。
  12. 根据权利要求11所述的阵列基板，其中，所述开关单元包括第六晶体管和第七晶体管，其中，
    所述第六晶体管的控制极与所述第一数据控制信号线耦接，所述第六晶体管的第一极与所述开关单元所耦接的数据信号传输通道耦接，所述第六晶体管的第二极与所述第七晶体管的第一极耦接；
    所述第七晶体管的控制极与所述第二数据控制信号线耦接，所述第七晶体管的第二极与所述开关单元所耦接的数据线耦接。
  13. 根据权利要求12所述的阵列基板，其中，所述第六晶体管和所述第七晶体管的类型相同，所述第三晶体管和所述第四晶体管的类型相同，且所述第六晶体管和所述第七晶体管的类型与所述第三晶体管和所述第四晶体管的类型不同。
  14. 根据权利要求11所述的阵列基板，其中，所述开关单元包括与非门电路和第八晶体管，其中，
    所述与非门电路与所述第一数据控制信号线、第二数据控制信号线和所述第八晶体管的控制极耦接；
    其中，所述与非门电路被配置为，在所述第一数据控制信号线传输的第一数据控制信号、及所述第二数据控制信号线传输的第二数据控制信号的控制下，输出控制所述第八晶体管导通的控制信号；
    所述第八晶体管的第一极与所述开关单元所耦接的数据信号传输通道耦接，所述第八晶体管的第二极与所述开关单元所耦接的数据线耦接。
  15. 根据权利要求14所述的阵列基板，其中，所述第三晶体管、所述第四晶体管和所述第八晶体管的类型相同。
  16. 根据权利要求6～15中任一项所述的阵列基板，其中，所述至少一条扫描控制信号线沿多个子像素排列的列方向延伸，所述至少一条数据控制信号线沿多个子像素排列的行方向延伸。
  17. 根据权利要求6～16中任一项所述的阵列基板，其中，每个子像素包括驱动晶体管；
    在所述第一控制子电路包括第一晶体管和第二晶体管，第二控制子电路包括第三晶体管和第四晶体管的情况下，
    所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管的栅极、有源层、及源极和漏极分别与所述驱动晶体管的栅极、有源层、及源极和漏极同层设置。
  18. 一种显示装置，包括：
    如权利要求6～17中任一项所述的阵列基板；
    栅极驱动电路，所述栅极驱动电路具有多个扫描信号输出通道和至少一个扫描控制信号输出通道，每个扫描信号输出通道与所述阵列基板中的一个扫描信号传输通道耦接，每个扫描控制信号输出通道与所述阵列基板中的一条扫描控制信号线耦接；
    源极驱动电路，所述源极驱动电路包括多个数据信号输出通道和至少一个数据控制信号输出通道，每个数据信号输出通道与所述阵列基板中的一个数据信号传输通道耦接，每个数据控制信号输出通道与所述阵列基板中的一条数据控制信号线耦接。
  19. 根据权利要求18所述的显示装置，其中，所述栅极驱动电路包括两个扫描控制信号输出通道，所述源极驱动电路包括两个或三个数据控制信号输出通道。
PCT/CN2020/140310 2020-03-18 2020-12-28 阵列基板及其驱动方法、显示装置 WO2021184892A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/432,888 US11763770B2 (en) 2020-03-18 2020-12-28 Array substrate and method for driving the same, display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010191857.1 2020-03-18
CN202010191857.1A CN111240061B (zh) 2020-03-18 2020-03-18 阵列基板及其驱动方法、显示装置

Publications (1)

Publication Number Publication Date
WO2021184892A1 true WO2021184892A1 (zh) 2021-09-23

Family

ID=70873515

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/140310 WO2021184892A1 (zh) 2020-03-18 2020-12-28 阵列基板及其驱动方法、显示装置

Country Status (3)

Country Link
US (1) US11763770B2 (zh)
CN (1) CN111240061B (zh)
WO (1) WO2021184892A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111240061B (zh) * 2020-03-18 2021-09-14 合肥鑫晟光电科技有限公司 阵列基板及其驱动方法、显示装置
CN116092405A (zh) * 2022-12-12 2023-05-09 北京京东方技术开发有限公司 显示面板、显示驱动方法、显示驱动模组和显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101292277A (zh) * 2004-09-24 2008-10-22 统宝香港控股有限公司 主动式阵列液晶显示装置及其驱动方法
CN202075968U (zh) * 2011-06-02 2011-12-14 北京京东方光电科技有限公司 液晶显示模块
CN202084275U (zh) * 2011-06-15 2011-12-21 北京京东方光电科技有限公司 一种显示装置、显示面板及显示面板驱动装置
US20130222216A1 (en) * 2012-02-28 2013-08-29 Samsung Display Co., Ltd. Display apparatus and method of driving the same
CN104700802A (zh) * 2015-03-25 2015-06-10 南京中电熊猫液晶显示科技有限公司 一种液晶面板的驱动电路
CN106125427A (zh) * 2016-06-27 2016-11-16 武汉华星光电技术有限公司 液晶显示面板及液晶显示装置
CN106940992A (zh) * 2017-04-28 2017-07-11 武汉华星光电技术有限公司 一种显示面板驱动电路及其驱动方法
CN111240061A (zh) * 2020-03-18 2020-06-05 合肥鑫晟光电科技有限公司 阵列基板及其驱动方法、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007108457A (ja) * 2005-10-14 2007-04-26 Nec Electronics Corp 表示装置、データドライバｉｃ、ゲートドライバｉｃ、及び走査線駆動回路
TWI396915B (zh) * 2008-11-14 2013-05-21 Au Optronics Corp 液晶顯示器及其液晶顯示面板
CN102201215A (zh) * 2008-12-24 2011-09-28 北京京东方光电科技有限公司 Tft-lcd阵列基板及其驱动方法
CN102368133B (zh) 2011-10-14 2013-11-20 深圳市华星光电技术有限公司 液晶阵列及液晶显示面板
TW201513085A (zh) * 2013-09-25 2015-04-01 Chunghwa Picture Tubes Ltd 用以降低液晶顯示系統功耗的方法
CN105206242B (zh) * 2015-10-28 2017-11-07 京东方科技集团股份有限公司 驱动电路及其驱动方法、显示面板
CN105527737B (zh) * 2016-02-01 2019-01-22 深圳市华星光电技术有限公司 液晶显示面板及其驱动方法
CN108594554B (zh) 2018-05-09 2020-11-17 京东方科技集团股份有限公司 一种阵列基板，其驱动方法及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101292277A (zh) * 2004-09-24 2008-10-22 统宝香港控股有限公司 主动式阵列液晶显示装置及其驱动方法
CN202075968U (zh) * 2011-06-02 2011-12-14 北京京东方光电科技有限公司 液晶显示模块
CN202084275U (zh) * 2011-06-15 2011-12-21 北京京东方光电科技有限公司 一种显示装置、显示面板及显示面板驱动装置
US20130222216A1 (en) * 2012-02-28 2013-08-29 Samsung Display Co., Ltd. Display apparatus and method of driving the same
CN104700802A (zh) * 2015-03-25 2015-06-10 南京中电熊猫液晶显示科技有限公司 一种液晶面板的驱动电路
CN106125427A (zh) * 2016-06-27 2016-11-16 武汉华星光电技术有限公司 液晶显示面板及液晶显示装置
CN106940992A (zh) * 2017-04-28 2017-07-11 武汉华星光电技术有限公司 一种显示面板驱动电路及其驱动方法
CN111240061A (zh) * 2020-03-18 2020-06-05 合肥鑫晟光电科技有限公司 阵列基板及其驱动方法、显示装置

Also Published As

Publication number Publication date
CN111240061A (zh) 2020-06-05
CN111240061B (zh) 2021-09-14
US11763770B2 (en) 2023-09-19
US20220277703A1 (en) 2022-09-01

Similar Documents

Publication Publication Date Title
KR100865542B1 (ko) 표시장치용 타이밍 발생회로 및 이것을 탑재한 표시장치
CN107065366B (zh) 阵列基板及其驱动方法
US7564441B2 (en) Data processing circuit, display apparatus, and portable terminal
US20080150859A1 (en) Liquid crystal display device and method of driving the same
US20100225570A1 (en) Liquid crystal device with multi-dot inversion
WO2017031944A1 (zh) 像素单元驱动电路、驱动方法和显示装置
US8749724B2 (en) LCD panel
KR20040086836A (ko) 액티브 매트릭스 디스플레이 장치 및 그의 구동 방법
WO2021184892A1 (zh) 阵列基板及其驱动方法、显示装置
KR20140020783A (ko) 화소 유닛, 화소 구조, 디스플레이 장치 및 화소 구동 방법
US8836677B2 (en) Array substrate and driving method thereof
CN107967908B (zh) 显示基板及其驱动方法、显示面板
WO2019029079A1 (zh) 显示装置的驱动方法和驱动装置
US7525527B2 (en) Method for driving a liquid crystal display device
KR20130080053A (ko) 표시 장치 및 그 구동 방법
US11862216B2 (en) Shift register and driving method therefor, gate driver circuit, and display apparatus
US20130093747A1 (en) Lcd panel
CN104347043A (zh) 液晶显示面板及驱动液晶显示器的方法
TW201312535A (zh) 雙閘極液晶顯示面板驅動結構及驅動方法
CN101609233A (zh) 液晶显示面板
KR20090004234A (ko) 액정표시장치 및 그 구동방법
CN101308645A (zh) 有源矩阵式液晶显示装置的像素驱动方法
KR102027170B1 (ko) 액정표시장치 및 그 구동방법
US8665264B2 (en) LCD panel and LCD device
KR20140098406A (ko) 액정표시장치 및 그 구동방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20925567

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20925567

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20925567

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 20/04/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20925567

Country of ref document: EP

Kind code of ref document: A1