WO2021184138A1

WO2021184138A1 - Preparation process for thin film bulk acoustic wave resonator provided with flexible insulating substrate and circuit thereof

Info

Publication number: WO2021184138A1
Application number: PCT/CN2020/079378
Authority: WO
Inventors: 周长见; 吴子莹
Original assignee: 华南理工大学
Priority date: 2020-03-14
Filing date: 2020-03-14
Publication date: 2021-09-23

Abstract

A preparation process for a thin film bulk acoustic wave resonator that is provided with a flexible insulating substrate, and an oscillator circuit comprising the thin film bulk acoustic wave resonator that has the flexible substrate. The process comprises: providing a piezoelectric thin film wafer that has an interface layer and a piezoelectric thin film single crystal layer; providing a carrier wafer, and forming a flexible insulating material thin film layer on the carrier wafer; bonding the piezoelectric thin film wafer to the carrier wafer at a low temperature; peeling off a silicon substrate of the piezoelectric thin film wafer; preparing surface electrodes and bonding pads on the piezoelectric thin film single crystal layer to form a thin film bulk acoustic wave resonator; and using a process that integrated a similar method with a CMOS circuit. The process improves the process compatibility of the thin film bulk acoustic wave resonator and the CMOS circuit, and improves the working performance of the thin film bulk acoustic wave resonator.

Description

Preparation process and circuit of film bulk acoustic wave resonator with flexible insulating substrate

Technical field

The invention relates to microelectronic technology and integrated packaging technology, in particular to a process for preparing a thin film bulk acoustic resonator with a flexible insulating substrate and its circuit.

Background technique

In many electronic applications, resonators are used. For example, in many wireless communication devices, radio frequency and microwave frequency resonators are used as filters to improve signal reception and transmission. Filters usually include inductors and capacitors, and may also include resonators.

With the development of microelectronics technology, in order to adapt to smaller size and higher performance requirements, it is necessary to integrate electronic components including resonators into chips or circuits by means of microelectronics technology. It is common to reduce the package size of electronic devices or circuits to the order of millimeters or even micrometers. This poses many challenges to traditional electronic components prepared based on MEMS technology.

In order to reduce the size of the period, a type of resonator based on the piezoelectric effect has appeared. In piezoelectric-based resonators, acoustic resonance modes are generated in piezoelectric materials. These sound waves are converted into electric waves for use in electronic communications and their circuits. For example, electronic products require resonators for both frequency transmission and reception. One type of piezoelectric resonator is a bulk acoustic wave (BAW) resonator. Generally, there are two types of BAW resonators: film bulk acoustic resonators (FBAR) and solid-state mounted bulk acoustic resonators (SMR). Both FBAR and SMR include acoustic stacks placed above reflective elements. The reflective element of the FBAR is a cavity usually in the substrate over which the acoustic stack is mounted. The reflective element of the SMR is a Bragg reflector including alternating layers of high acoustic impedance layers and low acoustic impedance layers.

BAW resonators have the advantage of small size and are suitable for integrated circuit (IC) manufacturing tools and technologies. The FBAR comprises an acoustic stack, which especially comprises a layer of piezoelectric material arranged between two electrodes. Acoustic waves achieve resonance across the acoustic stack, and the resonant frequency of the waves is determined by the materials in the acoustic stack.

Generally speaking, a bulk acoustic wave (BAW) resonator has a layer of piezoelectric material between two conductive plates (electrodes) that can be formed on a thin diaphragm. For example, the piezoelectric material may be a thin film of various materials, such as aluminum nitride (AlN), zinc oxide (ZnO), or lead zirconate titanate (PZT). A thin film made of AlN is advantageous because it generally maintains piezoelectric properties at high temperatures (for example, higher than 400°C). However, AlN has a lower piezoelectric coefficient than both ZnO and PZT. In addition, commonly used piezoelectric materials also include LiTaO ₃ , LiNbO ₃ and so on.

In FBAR (film bulk acoustic resonator) devices, strain sensors, mechanical oscillators, and other electronic and microelectromechanical systems (MEMS) devices, it may be necessary to maintain the device's mechanical and chemical isolation from its surrounding environment. For example, if the moving device comes into contact with the overmolding compound of a typical microelectronic package, the performance of the FBAR device is severely degraded. For this purpose, many devices have complicated and expensive packaging processes and methods.

With the gradual beginning of 5G applications, radio frequency wireless communication requires high-quality, high-frequency resonance frequencies to improve communication speed and efficiency. Film bulk acoustic resonator (FBAR) has a broad application prospect in radio frequency communication systems due to its small size, high quality factor (Q), high endurance power, high resonant frequency, and compatibility with CMOS technology. There are two common FBAR structures. One adopts a longitudinal field excitation structure. The electrodes are placed on both sides of the piezoelectric substrate to form a sandwich structure of electrode/piezoelectric film/electrode. The other uses a transverse field excitation structure, and the electrodes are on the same side of the piezoelectric substrate. MEMS devices are usually bulk structures, which have larger dimensions in both the horizontal and vertical directions. On the other hand, the compatibility of the MEMS process and the CMOS process has always been a major problem faced by those skilled in the art. Although the two processes involve exposure, etching and other processes, the focus of the process and the size of the processed material layer are different. In order to solve the above compatibility problem, the process cost has to be provided or the performance of electronic components is sacrificed. The prior art of FBAR is mainly divided into two categories: one is to form an air gap on the lower surface of the FBAR, and the other is to form a Bragg reflector layer composed of multiple layers of materials under the FBAR. The common purpose of the two methods is to confine the sound wave in the piezoelectric film structure as much as possible, reduce loss, and increase the Q value of the device. In terms of process realization, the first prior art requires multiple thin film deposition, etching and formation of suspended structures, while the second method requires the preparation of ten multi-layer Bragg reflective layers and corresponding etching processes. As we all know, process processing on the basis of CMOS chips needs to meet compatibility requirements in terms of materials and processing temperatures. For example, if the processing temperature exceeds 350 degrees, CMOS chips will be damaged. Therefore, in the process of FBAR on-chip integration, complex processes should be avoided as much as possible. The above-mentioned existing FABR preparation schemes involve dozens of steps of photolithography and etching. Processes such as etching and film deposition are complex and have low yields, so it is difficult to apply them in actual products.

Compared with the vertical field excitation structure, the horizontal field only needs one step of photolithography and etching process in the electrode preparation process, and the process complexity is greatly reduced. At the same time, in order to confine the acoustic energy in the piezoelectric film, in addition to the above-mentioned solutions of forming an air gap and a Bragg reflective layer, the prior art also proposes to use a flexible material with low acoustic impedance as a support layer, and then directly sputter to prepare the piezoelectric film. Such as AlN and ZnO methods. Since the flexible material cannot withstand high temperatures, there are problems such as stress between the prepared piezoelectric film and the flexible substrate. The Q value of the currently prepared bulk acoustic wave device on the flexible substrate is relatively low, and the highest report does not exceed 200 (see Zhou C, Shu Y,Yang Y,et al. Flexible structured high-frequency film bulk acousticresonator for flexible wireless electronics[J].Journal of Micromechanics and Microengineering,2015,25(5):055003.), it is difficult to meet the application of actual CMOS circuit integration Require. Therefore, a technical solution to overcome at least the known structure and process improvement described above is needed. In addition, the prior art has not yet proposed a solution for directly integrating the FBAR of the lateral field excitation structure with the CMOS chip.

In order to realize the integration of FBAR and CMOS chips, the integration process of directly adopting the vertical field excitation structure is relatively high, and the device performance of the existing lateral field excitation structure is still relatively poor and lacks an integrated solution. By proposing an integrated method using a single crystal piezoelectric film and a flexible substrate, the present invention can realize a FBAR with a high-Q lateral field excitation structure, and can realize FBAR and CMOS by directly preparing a flexible cover material on a CMOS chip The direct integration of the chip, the process is simple, and the process steps can be implemented at room temperature, so it can better solve the integration compatibility problem of FBAR and CMOS, and provide solutions for a variety of applications based on FBAR.

Summary of the invention

One aspect of the present invention provides a process for preparing a thin film bulk acoustic resonator with a flexible insulating substrate, which includes the following steps:

a) Provide piezoelectric thin film wafers with an interface layer and a piezoelectric thin film single crystal layer;

b) Provide a carrier wafer and form a thin film layer of flexible insulating material on it;

c) Bonding the piezoelectric thin film wafer and the carrier wafer at low temperature;

d) Peel off the silicon substrate of the piezoelectric thin film wafer;

e) Prepare surface electrodes and solder pads on the piezoelectric thin film single crystal layer to form a thin film bulk acoustic wave resonator.

Among them, the flexible insulating material is one or more of polyvinyl alcohol (PVA), polyester (PET), polyimide (PI) or silicone (PDMS). Preferably, the flexible insulating material is polyimide. Amine (PI), which is formed by pyromellitic dianhydride (PMDA) and diaminodiphenyl ether (DDE) in a strong polar solvent through polycondensation and casting into a film, followed by imidization. The piezoelectric thin film single crystal layer is _{one or more of LiTaO 3} , LiNbO ₃ , AlN, ZnO, and PZT. Before bonding, the surface of the wafer is treated with O ₂ plasma. The silicon substrate of the piezoelectric thin film wafer is removed by KOH or TMAH wet etching or RIE etching method. After the piezoelectric thin film wafer and the carrier wafer are bonded at low temperature, they are annealed at a low temperature, and the annealing temperature is less than 250 degrees. The distance between the surface electrodes prepared on the piezoelectric thin film single crystal layer is 5 nm-100 μm. The thin film bulk acoustic resonator with flexible substrate has an operating frequency of 0.5GHz-10GHz.

Another aspect of the present invention provides a process for integrating a thin film bulk acoustic resonator and a CMOS circuit compatible with the CMOS process, which includes the following steps:

b) Provide a CMOS wafer with CMOS circuits, and form a thin film layer of flexible insulating material on the side of the wafer with the CMOS circuit interface;

c) Low-temperature bonding of piezoelectric thin-film wafers and CMOS wafers;

d) Peel off the silicon substrate of the piezoelectric thin film wafer;

e) Prepare surface electrodes on the piezoelectric thin film single crystal layer to form a thin film bulk acoustic resonator;

f) Etching exposes the electrical connection pads of the CMOS circuit on the CMOS wafer;

g) Prepare metal connecting wires to make the film bulk acoustic wave resonator and the CMOS circuit form an electrical connection.

Among them, the piezoelectric thin film single crystal layer is _{one or more of LiTaO 3} , LiNbO ₃ , AlN, ZnO, and PZT. Before bonding, the surface of the wafer can be treated with O ₂ plasma. The silicon substrate of the piezoelectric thin film wafer is removed by KOH or TMAH wet etching or RIE etching method. After the piezoelectric thin film wafer and the CMOS wafer are bonded at low temperature, they are annealed at a low temperature, and the annealing temperature is less than 250 degrees.

Another aspect of the present invention is to provide an on-chip integrated oscillator circuit of a thin film bulk acoustic wave resonator. The oscillator circuit includes NMOS tubes M1, M2, M3, PMOS tubes M4, M5, variable capacitors C1, C2, and capacitors. C3, input port Vin, output port Vout, power supply VDD and ground, and a single crystal piezoelectric layer thin film bulk acoustic resonator with a flexible substrate prepared by the foregoing method, one end of the thin film bulk acoustic resonator is connected to the input Vin and The drain of M4, the drain of M1, the gate of variable capacitors C1, M2, the gate of M5, the other end of the film bulk acoustic wave resonator is connected to output Vout and the drain of M5, the drain of M2, the variable The gates of capacitors C2, M1, and M4. The external voltage-controlled voltage Vc is used to control the values of capacitors C1 and C2. The source of PMOS transistors M4 and M5 is connected to VDD, and the source of M1 and M2 is connected to the drain of M3. , The source of M3 is grounded and controlled by the voltage Vb, and the bypass capacitor C3 is connected to the drain and source of M3.

Wherein, the thin film bulk acoustic wave resonator includes a substrate formed of a flexible insulating material, a piezoelectric thin film single crystal layer formed on the substrate and formed of a piezoelectric material, and a surface electrode located on the piezoelectric thin film single crystal layer. The flexible insulating material is one or more of polyvinyl alcohol (PA), polyester (PET), polyimide (PI) or silicone (PDMS). Preferably, the flexible insulating material is polyimide ( PI). The piezoelectric thin film single crystal layer is _{one or more of LiTaO 3} , LiNbO ₃ , AlN, ZnO, and PZT.

Description of the drawings

Figure 1A is a schematic diagram of the structure of a silicon-based thin film bulk acoustic resonator in the prior art

Figure 1B is a process flow of a silicon-based thin film bulk acoustic resonator in the prior art

Figure 1C is a test result of a silicon-based thin film bulk acoustic resonator in the prior art

2A is a schematic diagram of the structure of a flexible film material substrate in the prior art

Figure 2B is a process flow of a flexible film material substrate in the prior art

Figure 2C is a test result of a flexible film material substrate in the prior art

Figure 3A is a process flow of a thin film bulk acoustic resonator in a representative embodiment

Figure 3B is the S-parameter test result of the thin film bulk acoustic resonator in a representative embodiment

Figure 4 is a process flow of the integration of the thin film bulk acoustic wave resonator and the CMOS circuit in a representative embodiment

Figure 5 is a physical photo of the thin film bulk acoustic resonator prepared in a representative embodiment

Figure 6 is the S parameter test result of the thin film bulk acoustic resonator in a representative embodiment

Fig. 7A is an oscillator circuit including a thin film bulk acoustic resonator in a representative embodiment

FIG. 7B is a layout diagram of an oscillator circuit including a thin film bulk acoustic resonator in a representative embodiment

Reference number

101: Si substrate; 102: interface layer; 103: piezoelectric layer; 104: surface electrode; 105: air gap; 106: etched hole; 201: flexible substrate; 202: interface layer; 203: piezoelectric film; 204: Surface electrode; 301: SOI substrate material; 302: SOI intermediate interface layer; 303: SOI upper piezoelectric single crystal film; 304: carrier wafer; 305: flexible film; 306: surface electrode; 307: surface welding Disk; 401: integrated circuit substrate; 402: N or P well for making transistors; 403: interconnect metal line; 404: passivation layer on the surface of integrated circuit; 405: transistor source and drain contact area; 406: transistor gate electrode; 407 : Surface electrode and pad electrode; 408: Metal connection.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. In the description of the embodiments of the present invention, unless otherwise specified, "plurality" means two or more.

In general, it should be understood that the drawings and the various elements depicted therein are not drawn to scale. In addition, relative terms (for example, "above", "below", "top", "bottom", "upper", and "lower") are used to describe the relationship between various elements, as illustrated in the drawings. It should be understood that these relative terms cover different orientations of devices and/or elements in addition to the orientations depicted in the drawings. For example, if the device is inverted with respect to the view in the drawing, an element described as "above" another element (for example) will now be below the element.

FIG. 1A is a schematic diagram of a cross-sectional structure of a thin film bulk acoustic resonator in the prior art. Taking a silicon-based horizontal film bulk acoustic resonator as an example, in the longitudinal structure of the device, the surface electrode is located on the top of the device and on the upper part of the piezoelectric film. The material of the piezoelectric film can be one of AlN, ZnO, and PZT Or multiple. There is an interface layer between the piezoelectric film and the silicon substrate, which is also the support for the mask layer and the FBAR structure for making the cavity in the silicon substrate. The reflective structure of FBAR is a cavity in the bottom of the silicon substrate.

Figure 1B shows the manufacturing process flow of the silicon-based thin film bulk acoustic resonator.

1) Prepare a conventional Si wafer substrate 101;

2) The interface layer 102 is prepared by thermal oxidation, PECVD, sputtering, etc., and the interface layer is also a supporting layer to avoid the situation that the device will break after the air gap is formed;

3) The piezoelectric film layer 103 is prepared on the interface layer, for example, an AlN polycrystalline film is prepared by sputtering;

4) A patterned surface electrode 104 is formed on the piezoelectric film through processes such as photolithography, film electrode deposition and etching;

5) Etching the piezoelectric film and the interface layer through photolithography and etching processes to form the release hole 106;

6) The air gap 105 located on the silicon substrate 101 and located under the piezoelectric film 103 and the surface electrode 104 is formed by dry etching or wet process;

7) Other necessary steps, such as packaging, cutting and bonding, to form a single FBAR device.

According to the aforementioned process, the SiO2 interface layer and the piezoelectric film are prepared on the silicon substrate and then the surface electrodes are prepared, and the FBAR device is formed. After testing the prepared FBAR device, the result is shown in Figure 1C. S-parameter test results show that the GBAR device has an obvious resonance peak near the frequency of 2.48GHz, and its quality factor Q is 514.

2A is a schematic diagram of a cross-sectional structure of an FBAR device with a PI film material substrate in the prior art. In the longitudinal structure of the device, the surface electrode is located on the top of the device, and the piezoelectric film is located between the surface electrode and the flexible substrate. Since the flexible substrate has similar characteristics to the acoustic impedance of the air gap in the silicon substrate in the traditional silicon-based horizontal film bulk acoustic wave resonator device, there is no need to make additional air gaps on the flexible substrate, thus obtaining a relatively simple film in the longitudinal structure Bulk acoustic wave resonator.

Figure 2B shows the process flow of the flexible film material substrate FBAR:

1) Prepare flexible substrate 201, such as PI film, PET film, etc.;

2) Prepare the interface layer 202 on the flexible film, such as a metal film, etc.;

3) Prepare the piezoelectric film material 203 by sputtering or other preparation methods on the flexible material covered by the interface layer;

4) The surface electrode 204 is formed on the piezoelectric thin film material by photolithography, thin film electrode deposition, and etching processes;

5) Other necessary steps, such as packaging, cutting, wire bonding, etc., to form a single FBAR device.

According to the aforementioned process, after preparing Al interface layer and AlN piezoelectric film layer on PI, and preparing surface electrode, the S parameter test result of FBAR device is shown in Fig. 2C. Its resonance frequency is about 2.923 GHz, and the quality factor Q value is 15.

The manufacturing process of the thin film bulk acoustic resonator (FBAR) based on the flexible thin film substrate involved in the present invention, as shown in FIG. 3A, includes the following steps.

A piezoelectric thin film wafer having an interface layer and a piezoelectric thin film single crystal layer is provided. The interface layer may be SiO ₂ , and its longitudinal structure is similar to an SOI wafer, which is referred to as an SOI wafer with piezoelectric thin film in the present invention. Figure S1: In the longitudinal dimension of the section, the thickness of the piezoelectric thin film single crystal layer is 0.1um-50um, the thickness of the SiO ₂ interface layer is between 0.1um-5um, and the thickness of the silicon substrate layer is 350um-550um. The lateral dimensions of the wafer are common 3 inches, 4 inches, 5 inches, 8 inches, 12 inches, etc., which are not particularly limited. In one embodiment, the thickness of the piezoelectric thin film single crystal layer _{is 0.7 um, the thickness of the SiO 2} interface layer is 1.3 um, the thickness of the silicon substrate layer is 500 um, and the lateral dimension is 4 inches. The piezoelectric thin-film SOI wafers can be purchased through commercial channels, such as LiNbO3/SiO2/Si wafers provided by NanoLN. The piezoelectric thin-film SOI wafers can also be prepared according to the SOI technology known to those skilled in the art.

S2: Provide carrier wafers, which can be common wafers and can be purchased from any channel. The lateral dimension can match the aforementioned piezoelectric thin film SOI wafer. Then, a flexible insulating film is prepared on the carrier wafer. The flexible insulating film can be one or more of PI and PET. Take PI film as an example. PI film is a thin-film insulating material with excellent performance. It is formed by polycondensation and casting of pyromellitic dianhydride (PMDA) and diaminodiphenyl ether (DDE) in a strong polar solvent. It is made by imidization and has the advantages of high temperature resistance, oxidation resistance and good insulation. The exemplary preparation process is as follows: prepare PI solution with a ratio of 10%, spin-coating rotation speed of 1000 rpm, and rotation time of 40 s. A PI film with a thickness of about 10 μm can be prepared, and then baked on a 110° hot plate for 5 minutes , And raise the temperature of the hot plate to 200° for further baking for 30 minutes. The flexible film layer can also be directly prepared on the carrier wafer by direct bonding or printing.

S3: Bond the piezoelectric thin-film SOI wafer and the carrier wafer with a flexible insulating film on the surface at low temperature. In order to achieve a good bonding effect, before bonding, the surfaces of the piezoelectric thin film SOI wafer and the flexible insulating film on the carrier wafer are respectively treated with O2 plasma. The power of O2 plasma can be 50W-300W, and the processing time is 1min-5min. . During bonding, pressure is applied to the bonded piezoelectric thin film SOI wafer and carrier wafer, and pressure bonding can be carried out in a vacuum chamber. The temperature can be appropriately heated not higher than 250 degrees, and the pressure is 0.1MPa-5Mpa. Maintain for more than 2.5 hours. In one embodiment, annealing is performed on the piezoelectric thin film SOI wafer and the carrier wafer after the bonding is completed, and the retreat temperature is less than 250 degrees and the time is 2 hours.

S4: After the piezoelectric thin film SOI wafer and the carrier wafer are bonded, the silicon substrate of the piezoelectric thin film wafer is peeled off. The SOI substrate can be directly peeled off by etching the interface layer of the SOI wafer, or the silicon substrate of the piezoelectric thin film wafer can be removed by KOH or TMAH wet etching or RIE etching method, or by grinding the silicon substrate first Combined with the aforementioned wet etching or RIE etching method to remove.

S5: Prepare electrodes and bonding pads for electrical connection between the FBAR and the external circuit on the piezoelectric thin film single crystal layer. In one embodiment, the electrodes are formed by sputtering Pt, or Pt/Cr. Take the Pt/Cr electrode as an example, Pt 200nm/Cr 10nm, which is prepared by a vacuum sputtering process. The required electrodes are formed by photolithography and etching processes, the typical electrode spacing is 0.1um-50um, and the total electrode thickness is 100nm-300nm.

S6: Optionally, the carrier wafer is further removed through a step similar to S4 to obtain an FBAR device with only a flexible substrate. According to needs, the completed wafer-level FBAR is packaged and cut into individual FBAR devices.

In combination with the previous description, the present invention uses the low-temperature bonding process of the piezoelectric thin film SOI wafer and the carrier wafer with flexible insulating film to avoid processes that are incompatible with the CMOS standard process, such as large-scale wetness in the longitudinal direction. Method corrosion or sacrificial layer process. At the same time, the piezoelectric single crystal layer on the piezoelectric thin film SOI wafer is used to replace the piezoelectric thin film layer prepared by traditional sputtering, sol-gel and other processes, which greatly improves the performance of FBAR, meets 5G, and even more Highly demanding communication needs.

Using the aforementioned process, the piezoelectric single crystal LiTaO3 film is prepared and the FBAR device obtained by preparing the surface electrode. After testing, the resonant frequency of the resonator is 2.45 GHz, and the Q value of the device has been increased from less than 100 to 1390, as shown in Figure 3B. The greatly improved FBAR device and its references can meet the needs of a wide range of applications in the fields of CMOS circuit integration and filters.

Another aspect of the present invention is to combine the above-mentioned flexible thin film insulating substrate FBAR preparation process, and further illustrate the process of integrating the thin film bulk acoustic resonator and the CMOS circuit that is compatible with the CMOS process, as shown in FIG. 4, Including the following steps.

S1: Provide a piezoelectric thin-film SOI wafer with an interface layer and a piezoelectric thin-film single-crystal layer. The interface layer can be SiO ₂ , and its longitudinal and lateral dimensions are consistent with the previous description of the specification.

S2: Provide a CMOS wafer with a CMOS circuit. The CMOS circuit is prepared by the existing CMOS process, including but not limited to cleaning, drying, photolithography, deposition, etching, oxidation, chemical mechanical polishing and other processes. A wire bonding pad PAD is formed on the side of the CMOS wafer for bonding with the FBAR, and the PAD is exposed on the protective layer. Consistent with the previous description in the manual, the PI film is prepared on the surface of the CMOS wafer by a spin coating process. The PI film can also provide protection for the CMOS wafer and its CMOS circuit.

S3: Low-temperature bonding of the piezoelectric thin-film SOI wafer and the CMOS wafer with the PI flexible thin-film insulating layer on the surface. In order to achieve a good bonding effect, before bonding, the surfaces of the piezoelectric thin film SOI wafer and the flexible insulating film on the carrier wafer are respectively treated with O2 plasma. The power of O2 plasma can be 50W-300W, and the processing time is 1min-5min. During bonding, pressure is applied to the bonded piezoelectric thin film SOI wafer and carrier wafer, and pressure bonding can be carried out in a vacuum chamber. The temperature can be appropriately heated not higher than 250 degrees, and the pressure is 0.1MPa-5Mpa. Maintain for more than 2.5 hours. In one embodiment, annealing is performed on the piezoelectric thin film SOI wafer and the carrier wafer after the bonding is completed, and the retreat temperature is less than 250 degrees and the time is 2 hours.

S5: Prepare electrodes and bonding pads for electrical connection between the FBAR and the external circuit on the piezoelectric thin film single crystal layer. In one embodiment, Pt or Pt/Cr electrodes are sputtered. Take the Pt/Cr electrode as an example, Pt 200nm/Cr 10nm, which is prepared by a vacuum sputtering process. The required electrodes are formed by photolithography and time processing. The typical electrode spacing is 0.1um-50um, and the total electrode thickness is 100nm-300nm.

S6: Etching exposes the wire bonding pad PAD of the CMOS circuit for preparing a metal connection line to electrically connect the thin film bulk acoustic wave resonator and the CMOS circuit. According to needs, the wafer-level FBAR that completes the main process is packaged and cut into individual FBAR devices.

Fig. 5 shows the actual photo of the prepared thin film bulk acoustic wave resonator with PI flexible insulating substrate. It can be easily bent, so that it can be widely used in wearable devices, and maintain excellent performance parameters even after multiple bending.

Fig. 6 is a performance test result of a thin film bulk acoustic resonator FBAR of a representative embodiment. As shown in Figure 6, the test is performed in a wider frequency range. In terms of the Q value of FBAR, the Q value of the device obtained by using the piezoelectric film LiTaO3 and the flexible substrate PI can reach 2029, and the coupling coefficient can reach 4%. Its operating frequency can reach 7.26GHz, which is difficult to achieve with the prior art.

Another aspect of the present invention is to provide an on-chip integrated oscillator circuit of a thin film bulk acoustic wave resonator, as shown in FIG. 7A. The oscillator includes NMOS tubes M1, M2, M3, PMOS tubes M3, M4, variable capacitors C1, C2, and capacitor C3. Input port Vin, output port Vout, power supply VDD and ground, and FBAR. One end of the FBRA resonator is connected to the drain of input Vin and M4, the drain of M1, the gate of variable capacitors C1, M2, and the gate of M5. The other end of the FBAR resonator is connected to the output of Vout and the drain of M5, and the drain of M2. Drain, variable capacitor C2, gate of M1, gate of M4. The external voltage control voltage Vc is used to control the values of the capacitors C1 and C2. The sources of M4 and M5 are connected to VDD, the sources of M1 and M2 are connected to the drain of M3, M3 is a current source, and the source is grounded. Controlled by the voltage Vb, the bypass capacitor C3 is connected to the drain and source of M3.

In combination with the foregoing, since the FBAR process used in the present invention is fully compatible with the CMOS process, the manufacturing process of the CMOS circuit including the FBAR is greatly simplified, and the lateral size also has better matching. As shown in Fig. 7B, the size of the prepared circuit is 0.2mm*0.42mm.

Compared with the prior art, the main advantages of the present invention are: on the one hand, the excellent characteristics of the piezoelectric material single crystal layer on the piezoelectric thin film SOI wafer are used to avoid the piezoelectric growth in the traditional method such as sputtering and PECVD. Defects in the material layer. On the other hand, combined with the low acoustic impedance characteristics of the flexible material polyimide layer, the acoustic wave reflection occurs at the interface between the piezoelectric resonator and the polyimide layer, which reduces the acoustic wave leakage as much as possible, improves the Q value of the device, and ensures The FBAR device also has certain flexibility characteristics under the condition of the structural strength. Ingeniously adopting the process steps of separating the preparation of polyimide and CMOS circuits, solving the contradiction between the characteristics of polyimide and the process requirements of CMOS circuits, improving the film quality of electrodes and piezoelectric films, and improving FBAR devices The resonance performance is two orders of magnitude.

The foregoing descriptions are only preferred embodiments of the present invention, and are not used to limit the present invention. All technical solutions obtained by equivalent substitutions or equivalent transformations fall within the protection scope of the present invention.

Claims

A preparation process of a thin film bulk acoustic resonator with a flexible insulating substrate includes the following steps:

a) Provide piezoelectric thin film wafers with an interface layer and a piezoelectric thin film single crystal layer;

b) Provide a carrier wafer and form a thin film layer of flexible insulating material on it;

c) Bonding the piezoelectric thin film wafer and the carrier wafer at low temperature;

d) Peel off the silicon substrate of the piezoelectric thin film wafer;

e) Prepare a surface electrode on the piezoelectric thin film single crystal layer to form a thin film bulk acoustic resonator.
The manufacturing process of a film bulk acoustic resonator with a flexible insulating substrate according to claim 1, wherein the flexible insulating material is polyvinyl alcohol (PVA), polyester (PET), polyimide (PI) Or one or more of organosilicon (PDMS).
According to the manufacturing process of a thin film bulk acoustic resonator with a flexible insulating substrate according to claim 2, preferably, the flexible insulating material is polyimide (PI).
As claimed in claim 3, a thin film bulk acoustic resonator with a flexible insulating substrate, the polyimide (PI) flexible insulating material film layer is made of pyromellitic dianhydride (PMDA) and diamine-based Diphenyl ether (DDE) is polycondensed and cast into a film in a strong polar solvent and then imidized.
The manufacturing process of a thin film bulk acoustic resonator with a flexible insulating substrate according to claim 1, wherein the piezoelectric thin film single crystal layer is one or more of LiTaO 3 , LiNbO 3 , AlN, ZnO, and PZT .
The manufacturing process of a thin film bulk acoustic resonator with a flexible insulating substrate according to claim 1, wherein the surface of the wafer is treated with O 2 plasma before bonding.
According to a manufacturing process of a thin film bulk acoustic resonator with a flexible insulating substrate according to claim 1, the silicon substrate of the piezoelectric thin film wafer is removed by KOH or TMAH wet etching or RIE etching method.
According to the manufacturing process of a thin film bulk acoustic resonator with a flexible insulating substrate according to claim 1, after the piezoelectric thin film wafer and the carrier wafer are bonded at a low temperature, they are annealed at a low temperature, and the annealing temperature is less than 250 degrees.
The manufacturing process of a thin film bulk acoustic resonator with a flexible insulating substrate according to claim 1, wherein the surface electrode spacing prepared on the piezoelectric thin film single crystal layer is 5 nm-100 μm.
The manufacturing process of a thin film bulk acoustic wave resonator with a flexible insulating substrate according to claim 1, wherein the working frequency of the thin film bulk acoustic wave resonator is 0.5 GHz-10 GHz.
A process that is compatible with CMOS process and integrates thin film bulk acoustic resonator and CMOS circuit, including the following steps:

a) Provide piezoelectric thin film wafers with an interface layer and a piezoelectric thin film single crystal layer;

b) Provide a CMOS wafer with CMOS circuits, and form a thin film layer of flexible insulating material on the side of the wafer with the CMOS circuit interface;

c) Low-temperature bonding of piezoelectric thin-film wafers and CMOS wafers;

d) Peel off the silicon substrate of the piezoelectric thin film wafer;

e) Prepare surface electrodes on the piezoelectric thin film single crystal layer to form a thin film bulk acoustic resonator;

f) Etching exposes the electrical connection pads of the CMOS circuit on the CMOS wafer;

g) Prepare metal connecting wires to make the film bulk acoustic wave resonator and the CMOS circuit form an electrical connection.
The process for integrating the thin film bulk acoustic wave resonator and the CMOS circuit according to claim 11, wherein the piezoelectric thin film single crystal layer is one or more of LiTaO 3 , LiNbO 3 , AlN, ZnO, and PZT.
The process for integrating the thin film bulk acoustic resonator and the CMOS circuit according to claim 11, wherein the surface of the wafer is treated with O 2 plasma before bonding.
According to the process of integrating the thin film bulk acoustic wave resonator and the CMOS circuit according to claim 11, the silicon substrate of the piezoelectric thin film wafer is removed by the KOH or TMAH wet etching or RIE etching method.
According to the process of integrating the thin film bulk acoustic resonator and the CMOS circuit according to claim 11, after the piezoelectric thin film wafer and the CMOS wafer are bonded at a low temperature, they are annealed at a low temperature, and the annealing temperature is less than 250 degrees.
An on-chip integrated oscillator circuit of a thin film bulk acoustic wave resonator. The oscillator circuit includes three NMOS tubes M1, M2, M3, two PMOS tubes M4, M5, two variable capacitors C1, C2, and capacitor C3, Input port Vin, output port Vout, power supply VDD and ground, and a thin film bulk acoustic wave resonator with a flexible insulating substrate prepared by the method of claim 1, one end of which is connected to the input Vin and M4 Drain, drain of M1, gate of variable capacitor C1, M2, gate of M5, the other end of the film bulk acoustic wave resonator is connected to output Vout and drain of M5, drain of M2, variable capacitor C2 , The gate of M1, the gate of M4, the external voltage control voltage Vc is used to control the value of the capacitors C1 and C2, the source of the PMOS tube M4, M5 is connected to VDD, the source of M1, M2 is connected to the drain of M3, M3 The source is grounded and controlled by the voltage Vb, and the bypass capacitor C3 is connected to the drain and source of M3.
The on-chip integrated oscillator circuit of a thin film bulk acoustic wave resonator according to claim 16, said thin film bulk acoustic wave resonator comprising a substrate formed of a flexible insulating material, and a piezoelectric material formed on the substrate. Electric thin film single crystal layer, and surface electrodes on the piezoelectric thin film single crystal layer.
The on-chip integrated oscillator circuit of a film bulk acoustic resonator according to claim 16, wherein the flexible insulating material is polyvinyl alcohol (PA), polyester (PET), polyimide (PI) or silicone ( PDMS) one or more of them.
The on-chip integrated oscillator circuit of a thin film bulk acoustic wave resonator according to claim 16, preferably, the flexible insulating material is polyimide (PI).
The on-chip integrated oscillator circuit of a thin film bulk acoustic wave resonator according to claim 16, wherein the piezoelectric thin film single crystal layer is one or more of LiTaO 3 , LiNbO 3 , AlN, ZnO, and PZT.