WO2021189965A1 - Film bulk acoustic resonator and manufacturing method therefor - Google Patents

Film bulk acoustic resonator and manufacturing method therefor Download PDF

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Publication number
WO2021189965A1
WO2021189965A1 PCT/CN2020/135672 CN2020135672W WO2021189965A1 WO 2021189965 A1 WO2021189965 A1 WO 2021189965A1 CN 2020135672 W CN2020135672 W CN 2020135672W WO 2021189965 A1 WO2021189965 A1 WO 2021189965A1
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WO
WIPO (PCT)
Prior art keywords
layer
cavity
electrode
micro
bulk acoustic
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PCT/CN2020/135672
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French (fr)
Chinese (zh)
Inventor
黄河
罗海龙
李伟
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中芯集成电路(宁波)有限公司
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Publication of WO2021189965A1 publication Critical patent/WO2021189965A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details

Definitions

  • the invention relates to the field of semiconductor device manufacturing, in particular to a thin-film bulk acoustic wave resonator and a manufacturing method thereof.
  • the radio frequency filter is an important part of the radio frequency system. It can filter out the interference and noise outside the communication spectrum to meet the requirements of the radio frequency system and the communication protocol for the signal-to-noise ratio. Taking a mobile phone as an example, since each frequency band needs a corresponding filter, dozens of filters may need to be set in a mobile phone.
  • the thin film bulk acoustic wave resonator includes two thin film electrodes, and a piezoelectric thin film layer is arranged between the two thin film electrodes. Its working principle is to use the piezoelectric thin film layer to generate vibration under an alternating electric field.
  • the bulk acoustic wave propagating in the thickness direction of the electric film layer is transmitted to the interface between the upper and lower electrodes and the air to be reflected back, and then reflected back and forth inside the film to form an oscillation.
  • a standing wave oscillation is formed.
  • the traditionally manufactured cavity-type thin-film bulk acoustic resonator due to the limitation of the cavity formation process, cannot integrate micro devices in the substrate under the cavity, and can only achieve related functions by connecting the resonator with an external device, resulting in the device
  • the large volume and long leads make the integration of the resonator not high and cannot meet the demand for miniaturization of the device.
  • the invention discloses a thin film bulk acoustic wave resonator and a manufacturing method thereof, which can solve the problem of low integration of the thin film bulk acoustic wave resonator.
  • the present invention provides a thin film bulk acoustic wave resonator, including:
  • a carrier substrate including a first semiconductor layer and a first device layer
  • a first micro device the first micro device is embedded in the carrier substrate, and at least part of the first micro device is located in the first device layer;
  • the piezoelectric laminate structure covers the first cavity, and the piezoelectric laminate structure includes a first electrode, a piezoelectric layer, and a second electrode stacked in sequence from bottom to top; the first cavity is formed in the Located below the piezoelectric laminate structure before the piezoelectric laminate structure;
  • the first electrical connection structure connects the first micro-device and electrically leads the first micro-device.
  • the present invention also provides a method for manufacturing the film bulk acoustic resonator, which includes:
  • the piezoelectric laminate structure including a second electrode, a piezoelectric layer, and a first electrode arranged in sequence from bottom to top;
  • a carrier substrate is provided, the carrier substrate includes a first semiconductor layer and a first device layer, the first surface of the carrier substrate is embedded with a first micro device, and the side where the first device layer is The side where the first surface is located;
  • a first electrical connection structure is formed, and the first micro device is electrically connected to an external signal.
  • the first micro-device is formed in the carrier substrate in advance, which is separated from the manufacture of the resonator, and the process time is shortened.
  • the micro device can be fabricated separately, and does not need to be fabricated in the resonator manufacturing process, so that the resonator structure is prevented from being subjected to the process environment when the micro device is fabricated, and the stability of the resonator is improved. Since this structure bonds the carrier substrate to the dielectric layer by bonding, it is possible to pre-form the first micro-device in the carrier substrate.
  • micro devices are also formed in the cover substrate, which further improves the integration degree of the resonator.
  • the dielectric layer and the bonding surface of the carrier substrate are made of the same material, and can be directly bonded through atomic bonds, which improves the bonding strength and simplifies the process flow.
  • first conductive plug and the second conductive plug are located on the same side of the resonator, which facilitates the manufacturing process of the process.
  • the protrusions are arranged along the boundary of the effective resonance area to make the acoustic impedance mismatch between the inside of the effective resonance area and the area where the protrusions are located, effectively preventing the lateral leakage of sound waves, and improving the quality factor of the resonator;
  • the effective resonance area of the resonator is defined by the first groove and the second groove.
  • the first groove and the second groove respectively penetrate the first electrode and the second electrode, and the piezoelectric layer maintains a complete film layer. After etching, the structural strength of the resonator is ensured, and the yield of manufacturing the resonator is improved.
  • FIG. 1 shows a schematic diagram of the structure of a thin film bulk acoustic resonator of Embodiment 1. As shown in FIG. 1
  • FIGS. 2 to 11 show schematic structural diagrams corresponding to different steps of a method for manufacturing a thin-film bulk acoustic resonator according to the second embodiment.
  • first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section.
  • Spatial relationship terms such as “under”, “below”, “below”, “below”, “above”, “above”, etc., in It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of devices in use and operation. For example, if the device in the figure is turned over, then elements or features described as “under” or “below” or “under” other elements will be oriented “on” the other elements or features. Therefore, the exemplary terms “below” and “below” can include both an orientation of above and below. The device can be otherwise oriented (rotated by 90 degrees or other orientation) and the spatial descriptors used here are interpreted accordingly.
  • the method herein includes a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some steps may be omitted and/or some other steps not described herein may be added to this method. If the components in a certain drawing are the same as those in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings more clear, this specification will not describe all the same components. The reference numbers are shown in each figure.
  • FIG. 1 shows a schematic structural diagram of a thin film piezoelectric acoustic resonator of Embodiment 1. Please refer to FIG. 1.
  • the thin film bulk acoustic wave resonator includes:
  • a carrier substrate which includes a first semiconductor layer 100A and a first device layer 100B;
  • a first micro device 1000, the first micro device 1000 is embedded in the carrier substrate, and at least part of the first micro device 1000 is located in the first device layer 100B;
  • the dielectric layer 102 is bonded to the first device layer 100B, the dielectric layer 102 encloses a first cavity 110a, and the first cavity 110a exposes the surface of the carrier substrate;
  • the piezoelectric laminate structure covers the first cavity 110a.
  • the piezoelectric laminate structure includes a first electrode 103, a piezoelectric layer 104, and a second electrode 105 that are sequentially stacked from bottom to top.
  • the first cavity 110a is formed before the piezoelectric laminate structure, and is located under the piezoelectric laminate structure;
  • the first electrical connection structure is connected to the first micro-device, and the first electrical connection structure is used to supply power to the first micro-device.
  • the first cavity 110a is formed before the piezoelectric laminate structure, and is located below the piezoelectric laminate structure for explanation as follows:
  • the manufacturing process of the resonator is: The substrate is etched to form a cavity, the sacrificial layer material is filled in the cavity, and a piezoelectric laminate structure is formed above the sacrificial layer material and the substrate. After the sacrificial layer is released, a lower cavity is formed, and the piezoelectric laminate structure is suspended below Above the cavity.
  • a capping layer may be formed on the upper surface of the piezoelectric laminate, and the cavity between the capping layer and the piezoelectric laminate structure is the upper cavity.
  • the first cavity of the present invention corresponds to the lower cavity.
  • the carrier substrate of this embodiment is bonded to the dielectric layer after the first cavity is formed.
  • the carrier substrate needs to provide better support for the patterning process of the second electrode of the resonator, the production and patterning of the bonding layer, the production/grinding of the capping layer, or the production of the second electrical connection structure. Since this structure bonds the carrier substrate to the dielectric layer by bonding, it is possible to pre-form the first micro-device in the carrier substrate.
  • the lower cavity is formed by the sacrificial layer method, and the micro device cannot be formed at the bottom of the lower cavity. Before bonding the carrier substrate, the first micro-device is formed in the carrier substrate in advance to shorten the process time.
  • the micro device can be fabricated separately, and does not need to be fabricated in the resonator manufacturing process, so that the resonator structure is prevented from being subjected to the process environment when the micro device is fabricated, and the stability of the resonator is improved.
  • the carrier substrate includes a first semiconductor layer 100A and a first device layer 100B.
  • the first device layer 100B is close to the side where the first cavity 110a is located, and the first micro device 1000 It is at least partially formed in the first device layer 100B.
  • the first micro-device 1000 includes: a diode, a triode, a MOS transistor, an electrostatic discharge protection device, a resistor, a capacitor, or an inductor.
  • the first micro device 1000 may all be located in the device layer 100B.
  • the first micro device 1000 is a triode or a MOS transistor, its source and drain levels It may be located in the first semiconductor layer 100A.
  • the material of the first semiconductor layer 100A includes silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs) , Indium Phosphide (InP) or other III/V compound semiconductors.
  • the material of the first device layer 100B includes silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. The first device layer 100B and the dielectric layer 102 are combined by bonding.
  • the material of the dielectric layer 102 may be any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or ethyl silicate.
  • atomic bonding can be used to directly bond.
  • a bonding layer can be formed on the bonding surface of the two.
  • the materials of the bonding layer include silicon oxide, silicon nitride, polysilicon, and ethyl silicate. Or organic cured film.
  • the first device layer 100B and the dielectric layer are both silicon oxide, and atomic bonds are used for bonding, the bonding structure is strong and the process flow is simple.
  • a bonding layer structure is formed between the dielectric layer 101 and the carrier substrate. It can be seen from the materials of the dielectric layer and the bonding layer that the materials of the two may be the same or different.
  • the first cavity 110a is a closed cavity, and the first cavity 110a may be formed by etching the dielectric layer 102 through an etching process.
  • the shape of the bottom surface of the first cavity 110a is a rectangle, but in other embodiments of the present invention, the shape of the first cavity 110a on the bottom surface of the first electrode 103 may also be a circle, an ellipse, or a polygon other than a rectangle. For example, pentagons, hexagons, etc.
  • a piezoelectric stack structure is provided above the first cavity 110a, and the piezoelectric stack structure includes a first electrode 103, a piezoelectric layer 104, and a second electrode 105 in order from bottom to top.
  • the first electrode 103 is located on the dielectric layer 102
  • the piezoelectric layer 104 is located on the first electrode 103
  • the second electrode 105 is located on the piezoelectric layer 104.
  • the first electrode 103, the piezoelectric layer 104, and the second electrode 105 above the first cavity 110a are provided with an overlapping area in the direction perpendicular to the carrier substrate 100 as an effective resonant area, and the boundary of the effective resonant area is located at all. In the area surrounded by the first cavity 110a.
  • the shape of the effective resonance region is an irregular polygon, such as a pentagon or hexagon without parallel opposite sides.
  • the piezoelectric layer 104 covers the first cavity 110a, and covering the first cavity 110a should be understood to mean that the piezoelectric layer 104 is a complete film layer and has not been etched. It does not mean that the piezoelectric layer 104 completely covers the first cavity 110a to form a sealed cavity. Of course, the piezoelectric layer 104 can completely cover the first cavity 110a to form a sealed cavity.
  • the piezoelectric layer is not etched to ensure that the piezoelectric laminated structure has a certain thickness, so that the resonator has a certain structural strength. Improve the yield of resonators.
  • an etch stop layer is further provided between the dielectric layer 102 and the first electrode 103, and its material includes but is not limited to silicon nitride (Si3N4) and silicon oxynitride (SiON).
  • the etch stop layer can be used to increase the structural stability of the final manufactured thin film bulk acoustic wave resonator.
  • the etch stop layer has a lower etching rate than the dielectric layer 102, and can be used to etch the dielectric layer.
  • the layer 102 prevents over-etching during the process of forming the first cavity 110a, and protects the surface of the first electrode 103 located thereunder from damage, thereby improving the performance and reliability of the device.
  • the upper part of the piezoelectric laminate structure includes a bonding layer 106, the bonding layer 106 encloses a second cavity 110b, and the second cavity 110b exposes the surface of the piezoelectric laminate structure.
  • the second cavity 110b is located above the first cavity 110a. It also includes a cover substrate, which is disposed on the bonding layer 106 and covers the second cavity 110b.
  • a second micro device 2000 is embedded in the cover substrate on the side close to the second cavity 110 b.
  • the cover substrate has a double-layer structure, and includes a second semiconductor layer 200A and a second device layer 200B.
  • the second device layer 100B is close to the side where the second cavity 110b is located, and the first micro device 1000 is at least partially formed in the second device layer 200B.
  • the type of the second micro-device 1000 and the positional relationship with the cover substrate refer to the related description of the type of the first micro-device 1000 and the positional relationship with the carrier substrate.
  • the optional material of the second semiconductor layer 200A refer to the first semiconductor layer 100A.
  • the material types of the second device layer 200B refer to the material types of the first device layer 100B, which will not be repeated here.
  • the bonding layer 106 can be made of conventional bonding materials, such as silicon oxide, silicon nitride, silicon oxynitride, ethyl silicate, etc., or a bonding agent such as a light-curing material or a heat-curing material, such as an adhesive film (DieAttachFilm, DAF) or dry film (DryFilm), the production and patterning process is relatively simple.
  • the material of the bonding layer and the material of the capping substrate 200 may be the same, and the two are an integral structure, and the second cavity 110b is formed by forming a space in the film layer (forming the bonding layer 106 and the capping substrate 200).
  • the resonator further includes a first electrical connection structure connected to the first micro device 1000 and a second electrical connection structure connected to the second micro device 2000.
  • the first electrical connection structure is a first conductive plug 1001
  • the second electrical connection structure is a second conductive plug 2001.
  • the first conductive plug 1001 extends from the bottom surface of the carrier substrate to the first micro device 1000.
  • the second conductive plug 2001 extends from the bottom surface of the carrier substrate to the second micro device 2000.
  • the first conductive plug may extend from the top surface of the cover substrate to the first micro device.
  • the second conductive plug also extends from the top surface of the cover substrate to the second micro device.
  • the two conductive plugs are electrically connected to the micro device from the same side of the resonator.
  • the main consideration is that when the conductive plug is made, the opposite side of the conductive plug needs to be supported with a certain strength.
  • the side of the conductive plug (carrier substrate or cover substrate) needs to be thinned, and the thickness is about 100 microns.
  • the opposite side of the conductive plug (carrier substrate or cover substrate) is not The thickness is about a few hundred microns to provide a certain strength support for the manufacturing process.
  • the first conductive plug and the second conductive plug may be disposed on opposite sides of the resonator.
  • it may further include a third electrical connection structure, such as a third conductive plug, which electrically connects the first micro-device and the second micro-device.
  • first electrode lead-out part also includes a first electrode lead-out part and a second electrode lead-out part.
  • the first electrode lead-out part is used to introduce electrical signals into the first electrode 103 in the effective resonance region
  • the second electrode lead-out portion is used to lead electrical signals into the first electrode 103 in the effective resonance region.
  • the second electrode 105 in the effective resonance region. After the first electrode 103 and the second electrode 105 are energized, a pressure difference is generated on the upper and lower surfaces of the piezoelectric layer 104, forming a standing wave oscillation.
  • the conductive interconnect structure 120 is used to short-circuit the first electrode and the second electrode outside the effective resonance region.
  • the effective resonance region also includes the area where the piezoelectric layer, the first electrode, and the second electrode overlap each other in the direction perpendicular to the piezoelectric layer.
  • the first electrode and the second electrode are energized, the pressure difference between the upper and lower surfaces of the piezoelectric layer outside the effective resonance region can also be generated, and standing wave oscillation is also generated.
  • the standing wave oscillation outside the effective resonance region is undesirable.
  • the first electrode and the second electrode outside the effective resonance area are short-circuited to make the upper and lower voltages of the piezoelectric layer outside the effective resonance area consistent, and no standing wave oscillation can be generated outside the effective resonance area, which improves the Q value of the resonator.
  • the specific structures of the first electrode lead-out part, the second electrode lead-out part and the conductive interconnection structure 120 are as follows:
  • the first electrode lead-out part includes:
  • a first through hole 140 which penetrates through the lower layer structure of the first electrode 103 outside the effective resonance region, exposing the first electrode 103; a first conductive interconnection layer 141, covering the first electrode 103
  • the inner surface of a through hole 140 and a part of the surface of the carrier substrate 100 on the outer periphery of the first through hole 140 are connected to the first electrode 103; an insulating layer 160 covers the first conductive interconnection layer 141 and The surface of the carrier substrate 100; the conductive bumps 142 are arranged on the surface of the carrier substrate 100 and are electrically connected to the first conductive interconnection layer 141.
  • the second electrode lead-out part includes:
  • the second through hole 150, the second through hole 150 penetrates the lower structure of the first electrode 103 outside the effective resonance area, exposing the first electrode 103; the second conductive interconnection layer 151 covers the first electrode 103 The inner surface of the two through holes 150 and a part of the surface of the carrier substrate 100 on the periphery of the second through hole 150 are connected to the first electrode 103; an insulating layer 160 covers the second conductive interconnection layer 151 and The surface of the carrier substrate 100; second conductive bumps 152 are arranged on the surface of the carrier substrate 100 and are electrically connected to the second conductive interconnection layer 151.
  • a protrusion 40 is provided at the boundary of the effective resonance region, and the protrusion 40 is provided on the upper surface or the lower surface of the piezoelectric laminated structure; or, the protrusion 40 is partially provided on the piezoelectric
  • the upper surface of the laminated structure is partially disposed on the lower surface of the piezoelectric laminated structure.
  • all the protrusions 40 are located on the lower surface of the piezoelectric laminate structure. All are located on the side where the first cavity 110a is located.
  • the area surrounded by the protrusion 40 is an effective resonance area, and the outside of the protrusion 40 is an ineffective resonance area.
  • the first electrode 103, the piezoelectric layer 104, and the second electrode 105 in the effective resonance area overlap each other in a direction perpendicular to the carrier substrate 100.
  • the protrusions 40 may all be located on the upper surface of the piezoelectric laminate structure, away from the side where the first cavity 110a is located.
  • the protrusions 40 may also be partly arranged on the upper surface of the piezoelectric laminated structure and partly arranged on the lower surface of the piezoelectric laminated structure.
  • the projection of the protrusion 40 on the supporting substrate 100 forms a closed ring, such as a closed irregular polygon, a circle, or an ellipse.
  • the protrusion 40 causes the internal effective resonance area and the area where the protrusion 40 is located to mismatch the acoustic impedance, which can effectively prevent the lateral leakage of sound waves and improve the quality factor of the resonator.
  • the projection of the protrusion 40 on the carrier substrate 100 may not be a completely closed pattern. It should be understood that when the projection of the protrusion 40 on the carrier substrate 100 is a closed pattern, it is more beneficial to prevent the lateral leakage of sound waves.
  • the material of the protrusion 40 may be a conductive material or a dielectric material.
  • the material of the protrusion 40 is a conductive material, it may be the same as the material of the first electrode 103 or the second electrode 105.
  • the material of the protrusion 40 is In the case of the dielectric material, it can be any one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, but is not limited to the above materials.
  • the surface of the piezoelectric laminate structure further includes a first groove 130a and a second groove 130b.
  • the first groove 130a is located on the lower surface of the piezoelectric laminate structure on the side where the first cavity 110a is located. , Penetrates the first electrode 103 and surrounds the outer circumference of the area where the protrusion 40 is located.
  • the second groove 130b is located on the upper surface of the piezoelectric laminate structure, penetrates the second electrode 105, and surrounds the outer circumference of the area where the protrusion 40 is located.
  • the two ends of the first groove 130a and the two ends of the second groove 130b are arranged opposite to each other, so that the projections of the first groove 130a and the second groove 130b on the carrier substrate 100 The two junctions meet or have a gap.
  • the projection of the protrusion 40 on the piezoelectric layer 104 is a closed polygon, and the inner edges of the first groove 130a and the second groove 130b are arranged along the outer boundary of the protrusion 40, that is, The outer boundary of the protrusion 40 coincides with the inner edges of the first groove 130a and the second groove 130b.
  • the projections of the first grooves 130a and the second grooves 130b on the carrier substrate 100 are closed patterns, consistent with the shape of the projections 40 projected on the carrier substrate 100, and are located on the outer periphery of the projections formed by the projections 40 .
  • the protrusions 40 are ring-shaped (when the protrusions 40 are all located on the lower or upper surface of the piezoelectric laminate structure, the protrusions 40 constitute a ring; when the protrusions 40 are located on both surfaces of the piezoelectric laminate structure, The projections of the two parts together form an overall ring).
  • the first groove 130a surrounds part of the outer circumference of the protrusion 40
  • the second groove 130b surrounds the outer circumference of the remaining part of the protrusion 40 (here When the second groove 130b surrounds the outer circumference of the protrusion 40 means that it surrounds the outer circumference of the surface of the piezoelectric laminate structure in the area of the protrusion 40, and does not directly surround the outer circumference of the protrusion 40).
  • the first groove 130a may surround the piezoelectric laminate structure.
  • the second groove 130b may surround the outer circumference of the protrusion 40 on the upper surface of the piezoelectric laminate structure.
  • the present invention is not limited to this, as long as the first groove 130a and the second groove 130b cooperate with each other to surround the outer circumference of the area where the protrusion 40 is located.
  • the protrusion 40 causes the acoustic impedance of the inner region of the protrusion to be mismatched with the acoustic impedance of the area where the protrusion is located, and defines the boundary of the effective resonance region of the resonator.
  • the first groove 130a and the second groove 130b separate the first electrode 103 and the second electrode 105, respectively, so that the resonator cannot meet the working conditions (the working condition is that the first electrode 103, the piezoelectric layer 104 and the second electrode 105 are in The thickness direction overlaps each other), which further defines the boundary of the effective resonance region of the resonator.
  • the protrusion 40 causes the acoustic impedance to be mismatched by the addition of the mass.
  • the first groove 130a and the second groove 130b make the electrode end face contact with the air to make the acoustic impedance mismatch, and both play a role in preventing the leakage of the transverse wave. Improve the Q value of the resonator.
  • only the first trench 130a or the second trench 130b may be provided separately. Since the first electrode 103 and the second electrode 105 need to introduce electrical signals, the first trench 130a or the second trench 130b is not suitable to form a closed ring, and at this time, the first groove 130a or the second groove 130b cannot completely surround the area where the protrusion 40 is located.
  • the first groove 130a or the second groove 130b may be formed into a nearly closed ring shape, and the non-closed area is used to introduce electrical signals. This arrangement can simplify the process flow and reduce the cost of the resonator.
  • the conductive interconnection structure 120 includes two parts. It is electrically connected to the first electrode lead-out part. The other part of the conductive interconnect structure 120 is disposed in the outer area of the first trench 130a, connects the first electrode 103 and the second electrode 105, and is electrically connected to the second electrode lead-out portion through the first electrode 103. Both parts of the conductive interconnection structure 120 are provided with a region covering part of the surface of the second electrode 105. This region increases the contact area with the second electrode 105, reduces the contact resistance, and can prevent local high temperature caused by excessive current.
  • the second electrode lead-out portion is not directly electrically connected to the second electrode, but is connected to the first electrode outside the effective resonance region, and is electrically connected to the second electrode of the effective resonance region through the conductive interconnection structure 120.
  • the first electrode lead-out part is electrically connected to the first electrode inside the effective resonance zone, giving the first electrode lead-out part inside the effective resonance zone.
  • One electrode is powered, and the first electrode lead part is electrically connected to the second electrode outside the effective resonance area through the first electrode outside the effective resonance area and the conductive interconnection structure 120, and is not connected to the second electrode inside the effective resonance area.
  • the second electrode lead-out portion is connected to the first electrode outside the effective resonance area and the second electrode inside the effective resonance area to realize power supply to the second electrode inside the effective resonance area.
  • Embodiment 2 provides a method for manufacturing a thin film bulk acoustic resonator, including the following steps:
  • S02 forming a piezoelectric laminate structure on the temporary substrate, the piezoelectric laminate structure including a second electrode, a piezoelectric layer, and a first electrode arranged in sequence from bottom to top;
  • S05 Provide a carrier substrate, the carrier substrate includes a first semiconductor layer and a first device layer, the first surface of the carrier substrate is embedded with a first micro device, and the side where the first device layer is located is the carrier The side where the first surface of the substrate is located;
  • S06 Bond the carrier substrate to the dielectric layer, cover the first cavity, and make the first surface face the first cavity;
  • S08 Form a first electrical connection structure to electrically connect the first micro-device with an external signal.
  • FIGS. 2 to 11 show schematic diagrams of the structure at different stages of a method for manufacturing a thin film piezoelectric acoustic resonator according to Embodiment 2 of the present invention. Please refer to FIGS. 2 to 11 to describe each step in detail.
  • step S01 is performed: a temporary substrate 300 is provided.
  • the temporary substrate 300 may be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, can also be ceramic substrates such as alumina, quartz or glass substrates, etc.
  • step S02 forming a piezoelectric laminate structure on the temporary substrate 300, the piezoelectric laminate structure including a second electrode 105, a piezoelectric layer 104, and a first electrode arranged in sequence from bottom to top 103.
  • the materials of the second electrode 105 and the first electrode 103 can use any suitable conductive material or semiconductor material well known to those skilled in the art, wherein the conductive material can be a metal material with conductive properties, for example, made of molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), palladium (Pd) and other metals or laminates of the above metals, semiconductor materials such as Si, Ge, SiGe, SiC, SiGeC, etc.
  • the second electrode 105 and the first electrode 103 may be formed by physical vapor deposition or chemical vapor deposition methods such as magnetron sputtering, evaporation, or the like.
  • the material of the piezoelectric layer 104 can be aluminum nitride (AlN), zinc oxide (ZnO), lead zirconate titanate (PZT), lithium niobate (LiNbO3), quartz (Quartz), potassium niobate (KNbO3) or tantalic acid Piezoelectric materials with wurtzite crystal structure such as lithium (LiTaO3) and their combinations.
  • the piezoelectric layer 104 may further include rare earth metals, such as at least one of scandium (Sc), erbium (Er), yttrium (Y), and lanthanum (La).
  • the piezoelectric layer 104 may further include a transition metal, such as at least one of zirconium (Zr), titanium (Ti), manganese (Mn), and hafnium (Hf). kind.
  • the piezoelectric layer 104 can be deposited and formed by any suitable method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • the second electrode 105 and the first electrode 103 are made of metal molybdenum (Mo)
  • the piezoelectric layer 104 is made of aluminum nitride (AlN).
  • step S03 is performed: forming a dielectric layer 102 to cover the piezoelectric laminate structure.
  • the dielectric layer 102 is formed by physical vapor deposition or chemical vapor deposition.
  • the material of the dielectric layer 102 may be any suitable dielectric material, including but not limited to at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the like.
  • step S05 is performed: the dielectric layer 102 is patterned to form a first cavity 110 a, and the first cavity 110 a penetrates the dielectric layer 102.
  • the dielectric layer 102 is etched by an etching process to form a first cavity 110a and expose the first electrode layer 103 at the bottom.
  • the etching process may be a wet etching process or a dry etching process. Dry etching includes but is not limited to reactive ion etching (RIE), ion beam etching, and plasma etching.
  • RIE reactive ion etching
  • the depth and shape of the first cavity 110a depend on the depth and shape of the cavity required for the bulk acoustic wave resonator to be manufactured, that is, the depth of the first cavity 110a can be determined by the thickness of the dielectric layer 102 formed.
  • the shape of the bottom surface of the first cavity 110a can be a rectangle or a polygon other than a rectangle, such as a pentagon, a hexagon, an octagon, etc., and can also be a circle or an ellipse.
  • step S05 is performed: providing a carrier substrate, the carrier substrate includes a first semiconductor layer 100A and a first device layer 100B, the first surface of the carrier substrate is embedded with the first micro device 1000, and the second The side where a device layer 100B is located is the side where the first surface of the carrier substrate is located.
  • the material of the first semiconductor layer 100A, the material of the first device layer 100B, the type of the first micro-device 1000 and the structural relationship with the carrier substrate refer to the related description of Embodiment 1, which will not be repeated here.
  • step S06 is performed: bonding the carrier substrate to the dielectric layer 102, covering the first cavity 110a, and making the first surface face the first cavity 110a.
  • the material of the dielectric layer and the bonding method of the dielectric layer and the carrier substrate refer to the related description of Embodiment 1.
  • step S07 is performed: removing the temporary substrate.
  • the method of removing the temporary substrate can be mechanical grinding.
  • the first electrical connection structure and connecting the first micro device before forming the first electrical connection structure and connecting the first micro device, it further includes: forming a bonding layer 106 on the piezoelectric laminate structure, the bonding layer 106 encloses a second cavity 110b, which exposes the surface of the piezoelectric laminate structure, and the second cavity 110b is located above the first cavity 110a.
  • a cover substrate is provided, the cover substrate includes a second semiconductor layer 200A and a second device layer 200B, a second micro device 2000 is embedded on the first surface of the cover substrate, and the second device layer 200B is located on the side The first surface of the cover substrate is located on the side.
  • the cover substrate is disposed on the bonding layer 106 to cover the second cavity 110b, and the first surface of the cover substrate faces the second cavity 110b.
  • the material of the bonding layer 106 the material of the second semiconductor layer 200A, the material of the second device layer 200B, the type of the second micro device 2000 and the structure relationship with the cover substrate, please refer to the related description of Embodiment 1, which will not be repeated here. .
  • step S08 is performed: forming a first electrical connection structure, and electrically connecting the first micro-device with an external signal.
  • This embodiment also includes: forming a second electrical connection structure to electrically connect the second micro device with an external signal.
  • the first electrical connection structure and the second electrical connection structure are the first conductive plug 1001 and the second conductive plug 2001 respectively.
  • forming the first conductive plug 1001 and the second conductive plug 2001 includes: forming a first through hole (not shown in the figure) penetrating the supporting substrate from the supporting substrate side and penetrating the through holes.
  • the carrier substrate and the second through hole of the upper structure of the carrier substrate (the upper structure in this embodiment includes the dielectric layer 102, the piezoelectric laminate structure, the bonding layer 106, and part of the second device layer 200B) (not shown in the figure) (Shown), the first through hole exposes the first micro device 1000, the second through hole exposes the second micro device 2000, and the first through hole 1000 and the second through hole expose the second micro device 2000.
  • a conductive material is formed in the hole 2000 to form the first conductive plug 1001 and the second conductive plug 2001.
  • the first through hole and the second through hole may be formed by a dry etching process, and the conductive material may be formed in the first through hole and the second through hole by using an electroplating or electroless plating process.
  • forming the first conductive plug 1001 and the second conductive plug 2001 includes: forming a third through hole penetrating the cover substrate from the cover substrate side, and penetrating the cover substrate and The fourth through hole of the structure under the cover substrate, the third through hole exposes the second micro device, the fourth through hole exposes the first micro device, and the third through hole And a conductive material is formed in the fourth through hole to form the second conductive plug and the first conductive plug.
  • the above two conductive plugs are both formed on the same side of the resonator (the side where the carrier substrate is located or the side where the cover substrate is located), and the reason for this arrangement is referred to the related description of Embodiment 1.
  • the conductive plug is formed before the side of the carrier substrate, and it also includes the support of the cover substrate to reduce the thickness of the carrier substrate; the conductive plug is formed before the side of the cover substrate, and also includes the support of the carrier substrate to reduce the thickness. Cover the substrate.
  • it further includes forming a first electrode lead-out part and a second electrode lead-out part, the first electrode lead-out part is connected to the first electrode 103, and the second electrode lead-out part is connected to the second electrode 105.
  • the first electrode lead-out portion and the second electrode lead-out portion are located on the side of the carrier substrate.
  • the first electrode lead-out portion and the second electrode lead portion are also located on the side of the cover substrate in a preferred solution.
  • forming the first electrode lead-out part includes:
  • a through hole is formed through the lower layer structure of the first electrode 103 by an etching process, the through hole exposes the first electrode 103, and a first conductive interconnection layer is formed in the through hole by an electroplating process or a physical vapor deposition process 141.
  • the first conductive interconnection layer 141 covers the inner surface of the through hole and a part of the surface of the carrier substrate 100 on the periphery of the through hole, and is connected to the first electrode 103;
  • An insulating layer 160 is formed on the surface of a conductive interconnection layer 141 by a deposition process; first conductive bumps 142 are formed on the surface of the carrier substrate, and the first conductive bumps 142 are electrically connected to the first conductive interconnection layer 141. connect.
  • Forming the second electrode lead-out portion includes:
  • An etching process is used to form a through hole penetrating the lower layer structure of the first electrode 103, the through hole exposes the second electrode 105, and a second conductive interconnection layer 151 is formed in the through hole through a deposition process or an electroplating process,
  • the second conductive interconnection layer 151 covers the inner surface of the through hole and a part of the surface of the carrier substrate on the periphery of the through hole, and is connected to the second electrode 105;
  • the insulating layer 160 is formed by a deposition process; a second conductive bump 152 is formed on the surface of the carrier substrate 100, and the second conductive bump 152 is electrically connected to the second conductive interconnect layer 151.

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  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

A film bulk acoustic resonator and a manufacturing method therefor. The film bulk acoustic resonator comprises: a bearing substrate, the bearing substrate comprising a first semiconductor layer (100A) and a first device layer (100B); a first micro device (1000), the first micro device (1000) being embedded in the bearing substrate, and at least a part of the first micro device (1000) being located in the first device layer (100B); a dielectric layer (102), bonded onto the first device layer (100B), the dielectric layer (102) encloses to form a first cavity (110a), the first cavity (110a) exposing from the surface of the bearing substrate; a piezoelectric lamination structure, covering the first cavity (110a), the piezoelectric lamination structure comprising, from bottom to top, a first electrode (103), a piezoelectric layer (104) and a second electrode (105) stacked sequentially; the first cavity (110a) being formed before the piezoelectric lamination structure and located below the piezoelectric lamination structure; and a first electrical connection structure, being connected to the first micro device (1000) and electrically leading out the first micro device (1000).

Description

一种薄膜体声波谐振器及其制造方法Thin film bulk acoustic wave resonator and manufacturing method thereof 技术领域Technical field
本发明涉及半导体器件制造领域,尤其涉及一种薄膜体声波谐振器及其制造方法。The invention relates to the field of semiconductor device manufacturing, in particular to a thin-film bulk acoustic wave resonator and a manufacturing method thereof.
背景技术Background technique
随着无线通讯技术的不断发展,为了满足各种无线通讯终端的多功能化需求,终端设备需要能够利用不同的载波频谱传输数据,同时,为了在有限的带宽内支持足够的数据传输率,对于射频系统也提出了严格的性能要求。射频滤波器是射频系统的重要组成部分,可以将通信频谱外的干扰和噪声滤出以满足射频系统和通信协议对于信噪比的需求。以手机为例,由于每一个频带需要有对应的滤波器,一台手机中可能需要设置数十个滤波器。With the continuous development of wireless communication technology, in order to meet the multi-functional requirements of various wireless communication terminals, terminal equipment needs to be able to use different carrier frequency spectrums to transmit data. At the same time, in order to support sufficient data transmission rates within a limited bandwidth, The radio frequency system also puts forward strict performance requirements. The radio frequency filter is an important part of the radio frequency system. It can filter out the interference and noise outside the communication spectrum to meet the requirements of the radio frequency system and the communication protocol for the signal-to-noise ratio. Taking a mobile phone as an example, since each frequency band needs a corresponding filter, dozens of filters may need to be set in a mobile phone.
通常,薄膜体声波谐振器包括两个薄膜电极,并且两个薄膜电极之间设有压电薄膜层,其工作原理为利用压电薄膜层在交变电场下产生振动,该振动激励出沿压电薄膜层厚度方向传播的体声波,此声波传至上下电极与空气交界面被反射回来,进而在薄膜内部来回反射,形成震荡。当声波在压电薄膜层中传播正好是半波长的奇数倍时,形成驻波震荡。Generally, the thin film bulk acoustic wave resonator includes two thin film electrodes, and a piezoelectric thin film layer is arranged between the two thin film electrodes. Its working principle is to use the piezoelectric thin film layer to generate vibration under an alternating electric field. The bulk acoustic wave propagating in the thickness direction of the electric film layer is transmitted to the interface between the upper and lower electrodes and the air to be reflected back, and then reflected back and forth inside the film to form an oscillation. When the sound wave propagates in the piezoelectric film layer exactly an odd multiple of the half wavelength, a standing wave oscillation is formed.
技术问题technical problem
但是,传统制作出的空腔型薄膜体声波谐振器,由于空腔的形成工艺受限,空腔下方的衬底中无法集成微器件,只能通过外部器件连接谐振器实现相关功能,导致器件体积大、引线长,使谐振器的集成度不高,无法满足器件小型化的需求。However, the traditionally manufactured cavity-type thin-film bulk acoustic resonator, due to the limitation of the cavity formation process, cannot integrate micro devices in the substrate under the cavity, and can only achieve related functions by connecting the resonator with an external device, resulting in the device The large volume and long leads make the integration of the resonator not high and cannot meet the demand for miniaturization of the device.
技术解决方案Technical solutions
本发明揭示了一种薄膜体声波谐振器及其制造方法,能够解决薄膜体声波谐振器集成度不高的问题。The invention discloses a thin film bulk acoustic wave resonator and a manufacturing method thereof, which can solve the problem of low integration of the thin film bulk acoustic wave resonator.
为解决上述技术问题,本发明提供了一种薄膜体声波谐振器,包括:In order to solve the above technical problems, the present invention provides a thin film bulk acoustic wave resonator, including:
承载衬底,所述承载基底包括第一半导体层和第一器件层;A carrier substrate, the carrier substrate including a first semiconductor layer and a first device layer;
第一微器件,所述第一微器件嵌入于所述承载衬底中,且所述第一微器件的至少部分位于所述第一器件层中;A first micro device, the first micro device is embedded in the carrier substrate, and at least part of the first micro device is located in the first device layer;
介质层,键合于所述第一器件层上,所述介质层围成第一空腔,所述第一空腔暴露出所述承载衬底的表面;A dielectric layer, bonded to the first device layer, the dielectric layer encloses a first cavity, and the first cavity exposes the surface of the carrier substrate;
压电叠层结构,覆盖所述第一空腔,所述压电叠层结构从下至上包括依次层叠的第一电极、压电层和第二电极;所述第一空腔形成于所述压电叠层结构之前,位于所述压电叠层结构的下方;The piezoelectric laminate structure covers the first cavity, and the piezoelectric laminate structure includes a first electrode, a piezoelectric layer, and a second electrode stacked in sequence from bottom to top; the first cavity is formed in the Located below the piezoelectric laminate structure before the piezoelectric laminate structure;
第一电连接结构,连接所述第一微器件,将所述第一微器件电性引出。The first electrical connection structure connects the first micro-device and electrically leads the first micro-device.
本发明还提供了一种薄膜体声波谐振器的制造方法,包括:The present invention also provides a method for manufacturing the film bulk acoustic resonator, which includes:
提供临时衬底;Provide temporary substrate;
在所述临时衬底上形成压电叠层结构,所述压电叠层结构包括由下至上依次设置的第二电极、压电层、第一电极;Forming a piezoelectric laminate structure on the temporary substrate, the piezoelectric laminate structure including a second electrode, a piezoelectric layer, and a first electrode arranged in sequence from bottom to top;
形成介质层,覆盖所述压电叠层结构;Forming a dielectric layer to cover the piezoelectric laminate structure;
图形化所述介质层,形成第一空腔,所述第一空腔贯穿所述介质层;Patterning the dielectric layer to form a first cavity, and the first cavity penetrates the dielectric layer;
提供承载衬底,所述承载基底包括第一半导体层和第一器件层,所述承载衬底的第一表面嵌入有第一微器件,所述第一器件层所在侧为所述承载基底的第一表面所在侧;A carrier substrate is provided, the carrier substrate includes a first semiconductor layer and a first device layer, the first surface of the carrier substrate is embedded with a first micro device, and the side where the first device layer is The side where the first surface is located;
键合所述承载衬底至所述介质层上、覆盖所述第一空腔,并使所述第一表面朝向所述第一空腔;Bonding the carrier substrate to the dielectric layer, covering the first cavity, and making the first surface face the first cavity;
去除所述临时衬底; Removing the temporary substrate;
形成第一电连接结构,将所述第一微器件与外部信号电连接。A first electrical connection structure is formed, and the first micro device is electrically connected to an external signal.
有益效果Beneficial effect
本发明的有益效果在于: The beneficial effects of the present invention are:
在键合承载衬底前,在承载衬底中预先形成第一微器件,与谐振器的制作分开,缩短制程时间。微器件可以单独制作,不用在谐振器制造流程中制作,避免谐振器结构承受制作微器件时的工艺环境,提高谐振器的稳定性。由于本结构是通过键合的方式将承载衬底键合在介质层上,使在承载衬底中预先形成第一微器件成为可能。Before bonding the carrier substrate, the first micro-device is formed in the carrier substrate in advance, which is separated from the manufacture of the resonator, and the process time is shortened. The micro device can be fabricated separately, and does not need to be fabricated in the resonator manufacturing process, so that the resonator structure is prevented from being subjected to the process environment when the micro device is fabricated, and the stability of the resonator is improved. Since this structure bonds the carrier substrate to the dielectric layer by bonding, it is possible to pre-form the first micro-device in the carrier substrate.
进一步地,封盖基板中也形成有微器件,进一步提高了谐振器的集成度。Further, micro devices are also formed in the cover substrate, which further improves the integration degree of the resonator.
进一步地,介质层与承载衬底键合面(第一器件层)的材质相同,可以通过原子键直接键合,提高键合强度,简化工艺流程。Further, the dielectric layer and the bonding surface of the carrier substrate (the first device layer) are made of the same material, and can be directly bonded through atomic bonds, which improves the bonding strength and simplifies the process flow.
进一步地,第一导电插塞和第二导电插塞位于谐振器的同侧,方便工艺的制造流程。Furthermore, the first conductive plug and the second conductive plug are located on the same side of the resonator, which facilitates the manufacturing process of the process.
进一步地,沿有效谐振区的边界设置凸起,使有效谐振区内部和凸起所在的区域声阻抗失配,有效防止声波的横向泄露,提高了谐振器的品质因数;Further, the protrusions are arranged along the boundary of the effective resonance area to make the acoustic impedance mismatch between the inside of the effective resonance area and the area where the protrusions are located, effectively preventing the lateral leakage of sound waves, and improving the quality factor of the resonator;
进一步地,通过第一沟槽和第二沟槽定义出谐振器的有效谐振区,第一沟槽和第二沟槽分别贯穿第一电极和第二电极,压电层保持完整的膜层未经过刻蚀,保证了谐振器的结构强度,提高了制造谐振器的成品率。Further, the effective resonance area of the resonator is defined by the first groove and the second groove. The first groove and the second groove respectively penetrate the first electrode and the second electrode, and the piezoelectric layer maintains a complete film layer. After etching, the structural strength of the resonator is ensured, and the yield of manufacturing the resonator is improved.
附图说明Description of the drawings
通过结合附图对本发明示例性实施例进行更详细的描述,本发明的上述以及其它目的、特征和优势将变得更加明显,在本发明示例性实施例中,相同的参考标号通常代表相同部件。Through a more detailed description of the exemplary embodiments of the present invention in conjunction with the accompanying drawings, the above and other objectives, features and advantages of the present invention will become more apparent. In the exemplary embodiments of the present invention, the same reference numerals generally represent the same components. .
图1示出了实施例1的一种薄膜体声波谐振器的结构示意图。FIG. 1 shows a schematic diagram of the structure of a thin film bulk acoustic resonator of Embodiment 1. As shown in FIG.
图2至图11示出了实施例2的一种薄膜体声波谐振器的制造方法的不同步骤对应的结构示意图。2 to 11 show schematic structural diagrams corresponding to different steps of a method for manufacturing a thin-film bulk acoustic resonator according to the second embodiment.
附图标记说明:Description of reference signs:
100A-第一半导体层;100B-第一器件层;1000-第一微器件;1001-第一导电插塞;101-键合层;102介质层;103-第一电极;104-压电层;105-第二电极; 106-接合层; 110a-第一空腔;110b-第二空腔;120-导电互连结构;130a-第一沟槽;130b-第二沟槽; 141-第一导电互连层;142-第一导电凸起;151-第二导电互连层;152-第二导电凸起;160-绝缘层;200A-第二半导体层;200B-第二器件层;2000-第二微器件;2001-第二导电插塞;40-凸起;300-临时衬底。100A-first semiconductor layer; 100B-first device layer; 1000-first micro device; 1001-first conductive plug; 101-bonding layer; 102 dielectric layer; 103-first electrode; 104-piezoelectric layer 105-second electrode; 106-bonding layer; 110a-first cavity; 110b-second cavity; 120-conductive interconnection structure; 130a-first trench; 130b-second trench; 141-th A conductive interconnection layer; 142-first conductive bump; 151-second conductive interconnection layer; 152-second conductive bump; 160-insulating layer; 200A-second semiconductor layer; 200B-second device layer; 2000-Second Micro Device; 2001-Second Conductive Plug; 40-Bump; 300-Temporary Substrate.
本发明的实施方式Embodiments of the present invention
以下结合附图和具体实施例对本发明作进一步详细说明。根据下面的说明和附图,本发明的优点和特征将更清楚,然而,需说明的是,本发明技术方案的构思可按照多种不同的形式实施,并不局限于在此阐述的特定实施例。附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。Hereinafter, the present invention will be further described in detail with reference to the drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will be clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in many different forms and is not limited to the specific implementation set forth herein. example. The drawings all adopt a very simplified form and all use imprecise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
应当明白,当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本发明教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" other elements or layers, it can be directly on the other elements or layers. On a layer, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. Floor. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section.
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等,在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语意图还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,然后,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。Spatial relationship terms such as "under", "below", "below", "below", "above", "above", etc., in It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of devices in use and operation. For example, if the device in the figure is turned over, then elements or features described as "under" or "below" or "under" other elements will be oriented "on" the other elements or features. Therefore, the exemplary terms "below" and "below" can include both an orientation of above and below. The device can be otherwise oriented (rotated by 90 degrees or other orientation) and the spatial descriptors used here are interpreted accordingly.
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时,单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”,当在该说明书中使用时,确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。The purpose of the terms used here is only to describe specific embodiments and not as a limitation of the present invention. When used herein, the singular forms "a", "an" and "the/the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "composition" and/or "including", when used in this specification, determine the existence of the described features, integers, steps, operations, elements and/or components, but do not exclude one or more other The existence or addition of features, integers, steps, operations, elements, parts, and/or groups. As used herein, the term "and/or" includes any and all combinations of related listed items.
如果本文的方法包括一系列步骤,且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序,且一些的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。若某附图中的构件与其他附图中的构件相同,虽然在所有附图中都可轻易辨认出这些构件,但为了使附图的说明更为清楚,本说明书不会将所有相同构件的标号标于每一图中。If the method herein includes a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some steps may be omitted and/or some other steps not described herein may be added to this method. If the components in a certain drawing are the same as those in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings more clear, this specification will not describe all the same components. The reference numbers are shown in each figure.
实施例1Example 1
本实施例提供了一种薄膜体声波谐振器,图1示出了实施例1的一种薄膜压电声波谐振器的结构示意图,请参考图1,所述薄膜体声波谐振器包括:This embodiment provides a thin film bulk acoustic wave resonator. FIG. 1 shows a schematic structural diagram of a thin film piezoelectric acoustic resonator of Embodiment 1. Please refer to FIG. 1. The thin film bulk acoustic wave resonator includes:
承载衬底,所述承载衬底包括第一半导体层100A和第一器件层100B;A carrier substrate, which includes a first semiconductor layer 100A and a first device layer 100B;
第一微器件1000,所述第一微器件1000嵌入于所述承载衬底中,且所述第一微器件1000的至少部分位于所述第一器件层100B中;A first micro device 1000, the first micro device 1000 is embedded in the carrier substrate, and at least part of the first micro device 1000 is located in the first device layer 100B;
介质层102,键合于所述第一器件层100B上,所述介质层102围成第一空腔110a,所述第一空腔110a暴露出所述承载衬底的表面;The dielectric layer 102 is bonded to the first device layer 100B, the dielectric layer 102 encloses a first cavity 110a, and the first cavity 110a exposes the surface of the carrier substrate;
压电叠层结构,覆盖所述第一空腔110a,所述压电叠层结构从下至上包括依次层叠的第一电极103、压电层104和第二电极105,所述第一空腔110a形成于所述压电叠层结构之前,位于所述压电叠层结构的下方;The piezoelectric laminate structure covers the first cavity 110a. The piezoelectric laminate structure includes a first electrode 103, a piezoelectric layer 104, and a second electrode 105 that are sequentially stacked from bottom to top. The first cavity 110a is formed before the piezoelectric laminate structure, and is located under the piezoelectric laminate structure;
第一电连接结构,连接于所述第一微器件,所述第一电连接结构用于对所述第一微器件供电。The first electrical connection structure is connected to the first micro-device, and the first electrical connection structure is used to supply power to the first micro-device.
需要说明的是,所述第一空腔110a形成于所述压电叠层结构之前,位于所述压电叠层结构的下方做如下解释:现有技术中,谐振器在制造过程为,在基板上刻蚀形成空腔,在空腔中填充牺牲层材料,在牺牲层材料和基板的上方形成压电叠层结构,释放牺牲层后,形成下空腔,压电叠层结构悬空于下空腔之上。压电叠层结构形成之后还可以在压电叠层的上表面形成封盖层,封盖层与压电叠层结构之间的空腔为上空腔。本发明的第一空腔对应于下空腔。本实施例的承载衬底是在形成第一空腔后键合在介质层上的。承载衬底需要为谐振器第二电极的图案化制程、接合层的制作及图案化、封盖层的制作/研磨,或者第二电连接结构的制作等提供较好的支撑。由于本结构是通过键合的方式将承载衬底键合在介质层上,使在承载衬底中预先形成第一微器件成为可能。通过牺牲层的方法形成下空腔,无法在下空腔的底部形成微器件。在键合承载衬底前,在承载衬底中预先形成第一微器件,缩短制程时间。微器件可以单独制作,不用在谐振器制造流程中制作,避免谐振器结构承受制作微器件时的工艺环境,提高谐振器的稳定性。It should be noted that the first cavity 110a is formed before the piezoelectric laminate structure, and is located below the piezoelectric laminate structure for explanation as follows: In the prior art, the manufacturing process of the resonator is: The substrate is etched to form a cavity, the sacrificial layer material is filled in the cavity, and a piezoelectric laminate structure is formed above the sacrificial layer material and the substrate. After the sacrificial layer is released, a lower cavity is formed, and the piezoelectric laminate structure is suspended below Above the cavity. After the piezoelectric laminate structure is formed, a capping layer may be formed on the upper surface of the piezoelectric laminate, and the cavity between the capping layer and the piezoelectric laminate structure is the upper cavity. The first cavity of the present invention corresponds to the lower cavity. The carrier substrate of this embodiment is bonded to the dielectric layer after the first cavity is formed. The carrier substrate needs to provide better support for the patterning process of the second electrode of the resonator, the production and patterning of the bonding layer, the production/grinding of the capping layer, or the production of the second electrical connection structure. Since this structure bonds the carrier substrate to the dielectric layer by bonding, it is possible to pre-form the first micro-device in the carrier substrate. The lower cavity is formed by the sacrificial layer method, and the micro device cannot be formed at the bottom of the lower cavity. Before bonding the carrier substrate, the first micro-device is formed in the carrier substrate in advance to shorten the process time. The micro device can be fabricated separately, and does not need to be fabricated in the resonator manufacturing process, so that the resonator structure is prevented from being subjected to the process environment when the micro device is fabricated, and the stability of the resonator is improved.
具体地,本实施例中,所述承载基底包括第一半导体层100A和第一器件层100B,所述第一器件层100B靠近所述第一空腔110a所在侧,所述第一微器件1000至少部分形成于所述第一器件层100B中。所述第一微器件1000包括:二极管、三极管、MOS晶体管、静电释放保护器件、电阻、电容或电感。当所述第一微器件1000为电阻、电容或电感时,第一微器件1000可以全部位于所述器件层100B中,当第一微器件1000为三极管、MOS晶体管时,其源级和漏级可以位于第一半导体层100A中。Specifically, in this embodiment, the carrier substrate includes a first semiconductor layer 100A and a first device layer 100B. The first device layer 100B is close to the side where the first cavity 110a is located, and the first micro device 1000 It is at least partially formed in the first device layer 100B. The first micro-device 1000 includes: a diode, a triode, a MOS transistor, an electrostatic discharge protection device, a resistor, a capacitor, or an inductor. When the first micro device 1000 is a resistor, a capacitor, or an inductor, the first micro device 1000 may all be located in the device layer 100B. When the first micro device 1000 is a triode or a MOS transistor, its source and drain levels It may be located in the first semiconductor layer 100A.
第一半导体层100A的材料包括硅(Si)、锗(Ge)、锗硅(SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V化合物半导体等。第一器件层100B的材料包括氧化硅、氮化硅、氮氧化硅、碳氮化硅。第一器件层100B和介质层102通过键合的方式进行结合。介质层102的材料可以是任意适合的介电材料,包括但不限于氧化硅、氮化硅、氮氧化硅、碳氮化硅或硅酸乙酯。当第一器件层100B和介质层102的材料相同时,可以采用原子键键合直接进行键合。当第一器件层100B和介质层102的材料不同时,可以在两者的键合面形成键合层,所述键合层的材料包括:氧化硅、氮化硅、多晶硅、硅酸乙酯或有机固化膜。本实施例,第一器件层100B和介质层均为氧化硅,采用原子键进行键合,键合结构强且工艺流程简单。当通过键合层进行键合时,在所述介质层101与所述承载衬底之间形成有一层键合层结构。通过介质层与键合层的材料可知,两者的材料可以相同也可以不同。The material of the first semiconductor layer 100A includes silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs) , Indium Phosphide (InP) or other III/V compound semiconductors. The material of the first device layer 100B includes silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. The first device layer 100B and the dielectric layer 102 are combined by bonding. The material of the dielectric layer 102 may be any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or ethyl silicate. When the materials of the first device layer 100B and the dielectric layer 102 are the same, atomic bonding can be used to directly bond. When the materials of the first device layer 100B and the dielectric layer 102 are different, a bonding layer can be formed on the bonding surface of the two. The materials of the bonding layer include silicon oxide, silicon nitride, polysilicon, and ethyl silicate. Or organic cured film. In this embodiment, the first device layer 100B and the dielectric layer are both silicon oxide, and atomic bonds are used for bonding, the bonding structure is strong and the process flow is simple. When bonding is performed through a bonding layer, a bonding layer structure is formed between the dielectric layer 101 and the carrier substrate. It can be seen from the materials of the dielectric layer and the bonding layer that the materials of the two may be the same or different.
本实施例中,第一空腔110a为封闭的空腔,第一空腔110a可以通过刻蚀工艺刻蚀介质层102形成。第一空腔110a的底面的形状为矩形,但在本发明的其他实施例中,第一空腔110a在第一电极103底面的形状还可以是圆形、椭圆形或是矩形以外的多边形,例如五边形、六边形等。In this embodiment, the first cavity 110a is a closed cavity, and the first cavity 110a may be formed by etching the dielectric layer 102 through an etching process. The shape of the bottom surface of the first cavity 110a is a rectangle, but in other embodiments of the present invention, the shape of the first cavity 110a on the bottom surface of the first electrode 103 may also be a circle, an ellipse, or a polygon other than a rectangle. For example, pentagons, hexagons, etc.
第一空腔110a的上方设有压电叠层结构,压电叠层结构从下至上依次包括第一电极103、压电层104和第二电极105。第一电极103位于介质层102上,压电层104位于第一电极103上,第二电极105位于压电层104上。第一空腔110a的上方的第一电极103、压电层104和第二电极105在垂直于承载衬底100的方向上设有重叠区域为有效谐振区,所述有效谐振区的边界位于所述第一空腔110a包围的区域内。有效谐振区的形状为不规则多边形,如不存在平行对边的五边形、六边形等。A piezoelectric stack structure is provided above the first cavity 110a, and the piezoelectric stack structure includes a first electrode 103, a piezoelectric layer 104, and a second electrode 105 in order from bottom to top. The first electrode 103 is located on the dielectric layer 102, the piezoelectric layer 104 is located on the first electrode 103, and the second electrode 105 is located on the piezoelectric layer 104. The first electrode 103, the piezoelectric layer 104, and the second electrode 105 above the first cavity 110a are provided with an overlapping area in the direction perpendicular to the carrier substrate 100 as an effective resonant area, and the boundary of the effective resonant area is located at all. In the area surrounded by the first cavity 110a. The shape of the effective resonance region is an irregular polygon, such as a pentagon or hexagon without parallel opposite sides.
本实施例中,压电层104遮盖所述第一空腔110a,遮盖所述第一空腔110a应当理解为压电层104为完整的膜层,没有经过刻蚀。并不意味着压电层104将第一空腔110a全部遮盖,形成密封的空腔。当然,压电层104可以完全遮盖第一空腔110a,形成密封的空腔。压电层不经过刻蚀可以保证压电叠层结构具有一定的厚度,使谐振器具有一定的结构强度。提高制作谐振器的成品率。In this embodiment, the piezoelectric layer 104 covers the first cavity 110a, and covering the first cavity 110a should be understood to mean that the piezoelectric layer 104 is a complete film layer and has not been etched. It does not mean that the piezoelectric layer 104 completely covers the first cavity 110a to form a sealed cavity. Of course, the piezoelectric layer 104 can completely cover the first cavity 110a to form a sealed cavity. The piezoelectric layer is not etched to ensure that the piezoelectric laminated structure has a certain thickness, so that the resonator has a certain structural strength. Improve the yield of resonators.
在一个实施例中,介质层102与第一电极103之间还设置有刻蚀停止层,其材质包括但不限于氮化硅(Si3N4)和氮氧化硅(SiON)。刻蚀停止层一方面可以用于增加最终制造的薄膜体声波谐振器的结构稳定性,另一方面,刻蚀停止层与介质层102相比具有较低的刻蚀速率,可以在刻蚀介质层102形成第一空腔110a的过程中防止过刻蚀,保护位于其下的第一电极103的表面不受到损伤,从而提高器件性能与可靠性。In one embodiment, an etch stop layer is further provided between the dielectric layer 102 and the first electrode 103, and its material includes but is not limited to silicon nitride (Si3N4) and silicon oxynitride (SiON). On the one hand, the etch stop layer can be used to increase the structural stability of the final manufactured thin film bulk acoustic wave resonator. On the other hand, the etch stop layer has a lower etching rate than the dielectric layer 102, and can be used to etch the dielectric layer. The layer 102 prevents over-etching during the process of forming the first cavity 110a, and protects the surface of the first electrode 103 located thereunder from damage, thereby improving the performance and reliability of the device.
本实施例中,压电叠层的结构上方包括接合层106,所述接合层106围成第二空腔110b,所述第二空腔110b暴露出所述压电叠层结构的表面,所述第二空腔110b位于所述第一空腔110a上方。还包括封盖基板,设置于接合层106上,并覆盖所述第二空腔110b。本实施例中,所述封盖基板中靠近所述第二空腔110b侧嵌入有第二微器件2000。In this embodiment, the upper part of the piezoelectric laminate structure includes a bonding layer 106, the bonding layer 106 encloses a second cavity 110b, and the second cavity 110b exposes the surface of the piezoelectric laminate structure. The second cavity 110b is located above the first cavity 110a. It also includes a cover substrate, which is disposed on the bonding layer 106 and covers the second cavity 110b. In this embodiment, a second micro device 2000 is embedded in the cover substrate on the side close to the second cavity 110 b.
本实施例中,封盖基板为双层结构,包括第二半导体层200A和第二器件层200B。所述第二器件层100B靠近所述第二空腔110b所在侧,所述第一微器件1000至少部分形成于所述第二器件层200B中。第二微器件1000的种类及与封盖基板的位置关系参照第一微器件1000的种类及与承载衬底的位置关系的相关描述,第二半导体层200A的可选材料参照第一半导体层100A的材料种类,第二器件层200B的可选材料参照第一器件层100B的材料种类,此处不在赘述。接合层106可以采用常规的键合材料,例如氧化硅、氮化硅、氮氧化硅、硅酸乙酯等,也可以是光固化材料或热固化材料等黏结剂,例如粘片膜(DieAttachFilm,DAF)或干膜(DryFilm),制作和图案化工艺相对简单。接合层的材料和封盖基板200的材料可以相同,两者为一体结构,第二空腔110b通过在膜层(形成接合层106和封盖基板200)中形成空间而形成。In this embodiment, the cover substrate has a double-layer structure, and includes a second semiconductor layer 200A and a second device layer 200B. The second device layer 100B is close to the side where the second cavity 110b is located, and the first micro device 1000 is at least partially formed in the second device layer 200B. For the type of the second micro-device 1000 and the positional relationship with the cover substrate, refer to the related description of the type of the first micro-device 1000 and the positional relationship with the carrier substrate. For the optional material of the second semiconductor layer 200A, refer to the first semiconductor layer 100A. For the material types of the second device layer 200B, refer to the material types of the first device layer 100B, which will not be repeated here. The bonding layer 106 can be made of conventional bonding materials, such as silicon oxide, silicon nitride, silicon oxynitride, ethyl silicate, etc., or a bonding agent such as a light-curing material or a heat-curing material, such as an adhesive film (DieAttachFilm, DAF) or dry film (DryFilm), the production and patterning process is relatively simple. The material of the bonding layer and the material of the capping substrate 200 may be the same, and the two are an integral structure, and the second cavity 110b is formed by forming a space in the film layer (forming the bonding layer 106 and the capping substrate 200).
为了给第一微器件1000和第二微器件2000供电,谐振器还包括连接于第一微器件1000的第一电连接结构以及连接于第二微器件2000的第二电连接结构,本实施例中,第一电连接结构为第一导电插塞1001,第二电连接结构为第二导电插塞2001。In order to supply power to the first micro device 1000 and the second micro device 2000, the resonator further includes a first electrical connection structure connected to the first micro device 1000 and a second electrical connection structure connected to the second micro device 2000. This embodiment Among them, the first electrical connection structure is a first conductive plug 1001, and the second electrical connection structure is a second conductive plug 2001.
本实施例中,第一导电插塞1001从所述承载衬底的底面延伸至所述第一微器件1000。第二导电插塞2001从所述承载衬底的底面延伸至所述第二微器件2000。In this embodiment, the first conductive plug 1001 extends from the bottom surface of the carrier substrate to the first micro device 1000. The second conductive plug 2001 extends from the bottom surface of the carrier substrate to the second micro device 2000.
在另一个实施例中,第一导电插塞可以从所述封盖基板的顶面延伸至所述第一微器件。第二导电插塞也从所述封盖基板的顶面延伸至所述第二微器件。以上两种情况两导电插塞都是从谐振器的同侧电连接于微器件。主要是考虑制作导电插塞时导电插塞的相对侧需要有一定强度的支撑。在制作导电插塞时,制作导电插塞的一侧(承载衬底或封盖基板)需要进行减薄处理,厚度约100微米,导电插塞的相对侧(承载衬底或封盖基板)不做减薄处理,厚度约几百微米,为制造工艺的提供一定强度的支撑。当然,在工艺条件允许的情况下,第一导电插塞和第二导电插塞可以设置于谐振器的相对两侧。在一个实施例中,还可以包括第三电连接结构,如第三导电插塞,将第一微器件和第二微器件进行电连接。In another embodiment, the first conductive plug may extend from the top surface of the cover substrate to the first micro device. The second conductive plug also extends from the top surface of the cover substrate to the second micro device. In the above two cases, the two conductive plugs are electrically connected to the micro device from the same side of the resonator. The main consideration is that when the conductive plug is made, the opposite side of the conductive plug needs to be supported with a certain strength. When making conductive plugs, the side of the conductive plug (carrier substrate or cover substrate) needs to be thinned, and the thickness is about 100 microns. The opposite side of the conductive plug (carrier substrate or cover substrate) is not The thickness is about a few hundred microns to provide a certain strength support for the manufacturing process. Of course, if the process conditions permit, the first conductive plug and the second conductive plug may be disposed on opposite sides of the resonator. In an embodiment, it may further include a third electrical connection structure, such as a third conductive plug, which electrically connects the first micro-device and the second micro-device.
本实施例中,还包括第一电极引出部、第二电极引出部,第一电极引出部用于将电信号引入有效谐振区的第一电极103,第二电极引出部用于将电信号引入有效谐振区的第二电极105。第一电极103和第二电极105通电后,压电层104上下表面产生压差,形成驻波振荡。导电互连结构120用于将有效谐振区外的第一电极和第二电极短接。由图可知,有效谐振区外也包含在垂直于压电层方向上压电层、第一电极、第二电极相互重叠的区域。当第一电极和第二电极通电,有效谐振区外部的压电层表面上下也能够产生压差,也产生了驻波振荡,然而有效谐振区外部的驻波振荡是不希望发生的,本实施例将有效谐振区外部的第一电极和第二电极短接,使有效谐振区外部的压电层上下电压一致,有效谐振区外部不能够产生驻波振荡,提高了谐振器的Q值。具体的第一电极引出部、第二电极引出部和导电互连结构120的结构如下:In this embodiment, it also includes a first electrode lead-out part and a second electrode lead-out part. The first electrode lead-out part is used to introduce electrical signals into the first electrode 103 in the effective resonance region, and the second electrode lead-out portion is used to lead electrical signals into the first electrode 103 in the effective resonance region. The second electrode 105 in the effective resonance region. After the first electrode 103 and the second electrode 105 are energized, a pressure difference is generated on the upper and lower surfaces of the piezoelectric layer 104, forming a standing wave oscillation. The conductive interconnect structure 120 is used to short-circuit the first electrode and the second electrode outside the effective resonance region. It can be seen from the figure that the effective resonance region also includes the area where the piezoelectric layer, the first electrode, and the second electrode overlap each other in the direction perpendicular to the piezoelectric layer. When the first electrode and the second electrode are energized, the pressure difference between the upper and lower surfaces of the piezoelectric layer outside the effective resonance region can also be generated, and standing wave oscillation is also generated. However, the standing wave oscillation outside the effective resonance region is undesirable. For example, the first electrode and the second electrode outside the effective resonance area are short-circuited to make the upper and lower voltages of the piezoelectric layer outside the effective resonance area consistent, and no standing wave oscillation can be generated outside the effective resonance area, which improves the Q value of the resonator. The specific structures of the first electrode lead-out part, the second electrode lead-out part and the conductive interconnection structure 120 are as follows:
第一电极引出部包括:The first electrode lead-out part includes:
第一通孔140,所述第一通孔140贯穿有效谐振区外部的所述第一电极103的下层结构,暴露出所述第一电极103;第一导电互连层141,覆盖所述第一通孔140的内表面、及第一通孔140外周的所述承载衬底100的部分表面,与所述第一电极103连接;绝缘层160,覆盖所述第一导电互连层141和所述承载衬底100的表面;导电凸起142,设置于所述承载衬底100的表面、与所述第一导电互连层电141连接。A first through hole 140, which penetrates through the lower layer structure of the first electrode 103 outside the effective resonance region, exposing the first electrode 103; a first conductive interconnection layer 141, covering the first electrode 103 The inner surface of a through hole 140 and a part of the surface of the carrier substrate 100 on the outer periphery of the first through hole 140 are connected to the first electrode 103; an insulating layer 160 covers the first conductive interconnection layer 141 and The surface of the carrier substrate 100; the conductive bumps 142 are arranged on the surface of the carrier substrate 100 and are electrically connected to the first conductive interconnection layer 141.
所述第二电极引出部包括:The second electrode lead-out part includes:
第二通孔150,所述第二通孔150贯穿有效谐振区外部的所述第一电极103的下层结构,暴露出所述第一电极103;第二导电互连层151,覆盖所述第二通孔150的内表面、及第二通孔150外周的所述承载衬底100的部分表面,与所述第一电极103连接;绝缘层160,覆盖所述第二导电互连层151和所述承载衬底100的表面;第二导电凸起152,设置于所述承载衬底100的表面、与所述第二导电互连层电151连接。The second through hole 150, the second through hole 150 penetrates the lower structure of the first electrode 103 outside the effective resonance area, exposing the first electrode 103; the second conductive interconnection layer 151 covers the first electrode 103 The inner surface of the two through holes 150 and a part of the surface of the carrier substrate 100 on the periphery of the second through hole 150 are connected to the first electrode 103; an insulating layer 160 covers the second conductive interconnection layer 151 and The surface of the carrier substrate 100; second conductive bumps 152 are arranged on the surface of the carrier substrate 100 and are electrically connected to the second conductive interconnection layer 151.
本实施例中,有效谐振区边界处设置有凸起40,所述凸起40设置于所述压电叠层结构上表面或下表面;或,所述凸起40部分设置于所述压电叠层结构的上表面,部分设置于所述压电叠层结构的下表面。In this embodiment, a protrusion 40 is provided at the boundary of the effective resonance region, and the protrusion 40 is provided on the upper surface or the lower surface of the piezoelectric laminated structure; or, the protrusion 40 is partially provided on the piezoelectric The upper surface of the laminated structure is partially disposed on the lower surface of the piezoelectric laminated structure.
本实施例中,所述凸起40全部位于压电叠层结构的下表面。全部位于第一空腔110a所在的一侧。所述凸起40包围的区域为有效谐振区,凸起40外部为无效谐振区。所述有效谐振区内的所述第一电极103、压电层104和第二电极105在垂直于所述承载衬底100方向上相互重叠。在其他实施例中,所述凸起40可以全部位于压电叠层结构的上表面,背离第一空腔110a所在侧。所述凸起40还可以部分设置于所述压电叠层结构的上表面,部分设置于所述压电叠层结构的下表面。In this embodiment, all the protrusions 40 are located on the lower surface of the piezoelectric laminate structure. All are located on the side where the first cavity 110a is located. The area surrounded by the protrusion 40 is an effective resonance area, and the outside of the protrusion 40 is an ineffective resonance area. The first electrode 103, the piezoelectric layer 104, and the second electrode 105 in the effective resonance area overlap each other in a direction perpendicular to the carrier substrate 100. In other embodiments, the protrusions 40 may all be located on the upper surface of the piezoelectric laminate structure, away from the side where the first cavity 110a is located. The protrusions 40 may also be partly arranged on the upper surface of the piezoelectric laminated structure and partly arranged on the lower surface of the piezoelectric laminated structure.
本实施例中,所述凸起40在承载衬底100上的投影围成封闭的环形,如封闭的不规则多边形、圆形或椭圆形。所述凸起40使其内部有效谐振区和凸起40所在的区域声阻抗失配,可以有效防止声波的横向泄露,提高谐振器的品质因数。在其他实施例中,所述凸起40在承载衬底100上的投影可以不是完全封闭的图形。应当理解,当凸起40在承载衬底100上的投影为封闭图形时,更有利于防止声波的横向泄露。In this embodiment, the projection of the protrusion 40 on the supporting substrate 100 forms a closed ring, such as a closed irregular polygon, a circle, or an ellipse. The protrusion 40 causes the internal effective resonance area and the area where the protrusion 40 is located to mismatch the acoustic impedance, which can effectively prevent the lateral leakage of sound waves and improve the quality factor of the resonator. In other embodiments, the projection of the protrusion 40 on the carrier substrate 100 may not be a completely closed pattern. It should be understood that when the projection of the protrusion 40 on the carrier substrate 100 is a closed pattern, it is more beneficial to prevent the lateral leakage of sound waves.
所述凸起40的材料可以为导电材料也可以为介质材料,当凸起40的材料为导电材料时,可以和第一电极103或第二电极105的材料相同,当凸起40的材料为介质材料时,可以为氧化硅、氮化硅、氮氧化硅或碳氮化硅中的任意一种,但不限于以上材料。The material of the protrusion 40 may be a conductive material or a dielectric material. When the material of the protrusion 40 is a conductive material, it may be the same as the material of the first electrode 103 or the second electrode 105. When the material of the protrusion 40 is In the case of the dielectric material, it can be any one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, but is not limited to the above materials.
本实施例中,压电叠层结构的表面还包括第一沟槽130a和第二沟槽130b,第一沟槽130a位于压电叠层结构的下表面、所述第一空腔110a所在侧,贯穿所述第一电极103,环绕于所述凸起40所在区域的外周。第二沟槽130b位于压电叠层结构的上表面,贯穿所述第二电极105,环绕于所述凸起40所在区域的外周。第一沟槽130a的两个端部与第二沟槽130b的两个端部相对设置,使所述第一沟槽130a与所述第二沟槽130b在所述承载衬底100的投影的两个交界处相接或设有间隙。本实施例中,所述凸起40在压电层104的投影为封闭的多边形,第一沟槽130a和第二沟槽130b的内边缘沿着所述凸起40的外边界设置,即所述凸起40的外边界与第一沟槽130a和所述第二沟槽130b的内边缘重合。第一沟槽130a与第二沟槽130b在所述承载衬底100的投影为封闭的图形,与凸起40在承载衬底100的投影的图形形状一致,位于凸起40形成的投影的外周。In this embodiment, the surface of the piezoelectric laminate structure further includes a first groove 130a and a second groove 130b. The first groove 130a is located on the lower surface of the piezoelectric laminate structure on the side where the first cavity 110a is located. , Penetrates the first electrode 103 and surrounds the outer circumference of the area where the protrusion 40 is located. The second groove 130b is located on the upper surface of the piezoelectric laminate structure, penetrates the second electrode 105, and surrounds the outer circumference of the area where the protrusion 40 is located. The two ends of the first groove 130a and the two ends of the second groove 130b are arranged opposite to each other, so that the projections of the first groove 130a and the second groove 130b on the carrier substrate 100 The two junctions meet or have a gap. In this embodiment, the projection of the protrusion 40 on the piezoelectric layer 104 is a closed polygon, and the inner edges of the first groove 130a and the second groove 130b are arranged along the outer boundary of the protrusion 40, that is, The outer boundary of the protrusion 40 coincides with the inner edges of the first groove 130a and the second groove 130b. The projections of the first grooves 130a and the second grooves 130b on the carrier substrate 100 are closed patterns, consistent with the shape of the projections 40 projected on the carrier substrate 100, and are located on the outer periphery of the projections formed by the projections 40 .
应当理解,凸起40为环形(当凸起40全部位于压电叠层结构的下表面或上表面时,凸起40构成环形;当凸起40位于压电叠层结构的两个表面时,两部分凸起的投影共同构成一个整体环形)。当凸起40全部位于压电叠层结构的上表面或下表面,第一沟槽130a环绕于部分所述凸起40的外周,第二沟槽130b环绕于剩余部分凸起40的外周(此时第二沟槽130b环绕于凸起40的外周意思为环绕于凸起40所述区域的压电叠层结构表面的外周,并不直接环绕于凸起40的外周)。当所述凸起40部分设置于所述压电叠层结构的上表面,部分设置于所述压电叠层结构的下表面时,第一沟槽130a可以环绕于位于压电叠层结构下表面的凸起40的外周,第二沟槽130b可以环绕于位于压电叠层结构上表面的凸起40的外周。但本发明并不限于此,只要第一沟槽130a和第二沟槽130b相互配合环绕于凸起40所在区域的外周即可。It should be understood that the protrusions 40 are ring-shaped (when the protrusions 40 are all located on the lower or upper surface of the piezoelectric laminate structure, the protrusions 40 constitute a ring; when the protrusions 40 are located on both surfaces of the piezoelectric laminate structure, The projections of the two parts together form an overall ring). When all the protrusions 40 are located on the upper or lower surface of the piezoelectric laminate structure, the first groove 130a surrounds part of the outer circumference of the protrusion 40, and the second groove 130b surrounds the outer circumference of the remaining part of the protrusion 40 (here When the second groove 130b surrounds the outer circumference of the protrusion 40 means that it surrounds the outer circumference of the surface of the piezoelectric laminate structure in the area of the protrusion 40, and does not directly surround the outer circumference of the protrusion 40). When the protrusion 40 is partially disposed on the upper surface of the piezoelectric laminate structure and partially disposed on the lower surface of the piezoelectric laminate structure, the first groove 130a may surround the piezoelectric laminate structure. On the outer circumference of the protrusion 40 on the surface, the second groove 130b may surround the outer circumference of the protrusion 40 on the upper surface of the piezoelectric laminate structure. However, the present invention is not limited to this, as long as the first groove 130a and the second groove 130b cooperate with each other to surround the outer circumference of the area where the protrusion 40 is located.
凸起40使凸起内部区域的声阻抗和凸起所在区域的声阻抗失配,界定了谐振器有效谐振区的边界。第一沟槽130a和第二沟槽130b分别将第一电极103和第二电极105隔断,使谐振器不能满足工作条件(工作条件为第一电极103、压电层104和第二电极105在厚度方向上相互重叠),进一步界定了谐振器的有效谐振区的边界。凸起40通过质量块的添加使声阻抗失配,第一沟槽130a和第二沟槽130b通过使电极端面和空气接触,使声阻抗失配,两者均起到阻止横波泄露的问题,提高了谐振器的Q值。当然,在其他实施例中,也可以只单独设置第一沟槽130a或第二沟槽130b,由于第一电极103和第二电极105需要引入电信号,第一沟槽130a或第二沟槽130b不适宜形成封闭的环形,此时第一沟槽130a或第二沟槽130b不能完全包围凸起40所在的区域。可以将第一沟槽130a或第二沟槽130b构成接近封闭的环形,非封闭的区域用于引入电信号。这种设置方式可以简化工艺流程,降低谐振器成本。The protrusion 40 causes the acoustic impedance of the inner region of the protrusion to be mismatched with the acoustic impedance of the area where the protrusion is located, and defines the boundary of the effective resonance region of the resonator. The first groove 130a and the second groove 130b separate the first electrode 103 and the second electrode 105, respectively, so that the resonator cannot meet the working conditions (the working condition is that the first electrode 103, the piezoelectric layer 104 and the second electrode 105 are in The thickness direction overlaps each other), which further defines the boundary of the effective resonance region of the resonator. The protrusion 40 causes the acoustic impedance to be mismatched by the addition of the mass. The first groove 130a and the second groove 130b make the electrode end face contact with the air to make the acoustic impedance mismatch, and both play a role in preventing the leakage of the transverse wave. Improve the Q value of the resonator. Of course, in other embodiments, only the first trench 130a or the second trench 130b may be provided separately. Since the first electrode 103 and the second electrode 105 need to introduce electrical signals, the first trench 130a or the second trench 130b is not suitable to form a closed ring, and at this time, the first groove 130a or the second groove 130b cannot completely surround the area where the protrusion 40 is located. The first groove 130a or the second groove 130b may be formed into a nearly closed ring shape, and the non-closed area is used to introduce electrical signals. This arrangement can simplify the process flow and reduce the cost of the resonator.
本实施例中,还包括导电互连结构120,导电互连结构120包括两部分,一部分设置于第二沟槽130b的外部区域,连接第一电极103和第二电极105,通过第一电极103与第一电极引出部电连接。导电互连结构120的另一部分设置于第一沟槽130a的外部区域,连接第一电极103和第二电极105,通过第一电极103与第二电极引出部电连接。两部分导电互连结构120均设有覆盖第二电极105部分表面的区域,此区域增大了与第二电极105的接触面积,减少了接触阻抗,能够防止电流过大引起的局部高温。In this embodiment, it further includes a conductive interconnection structure 120. The conductive interconnection structure 120 includes two parts. It is electrically connected to the first electrode lead-out part. The other part of the conductive interconnect structure 120 is disposed in the outer area of the first trench 130a, connects the first electrode 103 and the second electrode 105, and is electrically connected to the second electrode lead-out portion through the first electrode 103. Both parts of the conductive interconnection structure 120 are provided with a region covering part of the surface of the second electrode 105. This region increases the contact area with the second electrode 105, reduces the contact resistance, and can prevent local high temperature caused by excessive current.
需要说明的是,第二电极引出部并不直接与第二电极电连接,而是连接于有效谐振区外部的第一电极,通过导电互连结构120与有效谐振区的第二电极电连接。可以看出,第一电极引出部和第二电极引出部在结构上一致,只是设置的位置不同,第一电极引出部与有效谐振区内部的第一电极电连接,给有效谐振区内部的第一电极供电,第一电极引出部通过有效谐振区外部的第一电极和导电互连结构120与有效谐振区外部的第二电极电连接,并不连接于有效谐振区内部的第二电极。同理,第二电极引出部连接于有效谐振区外部的第一电极和有效谐振区内部的第二电极,实现对有效谐振区内部的第二电极供电。It should be noted that the second electrode lead-out portion is not directly electrically connected to the second electrode, but is connected to the first electrode outside the effective resonance region, and is electrically connected to the second electrode of the effective resonance region through the conductive interconnection structure 120. It can be seen that the first electrode lead-out part and the second electrode lead-out part are identical in structure, but the positions are different. The first electrode lead-out part is electrically connected to the first electrode inside the effective resonance zone, giving the first electrode lead-out part inside the effective resonance zone. One electrode is powered, and the first electrode lead part is electrically connected to the second electrode outside the effective resonance area through the first electrode outside the effective resonance area and the conductive interconnection structure 120, and is not connected to the second electrode inside the effective resonance area. In the same way, the second electrode lead-out portion is connected to the first electrode outside the effective resonance area and the second electrode inside the effective resonance area to realize power supply to the second electrode inside the effective resonance area.
实施例2Example 2
实施例2提供了一种薄膜体声波谐振器的制造方法,包括以下步骤:Embodiment 2 provides a method for manufacturing a thin film bulk acoustic resonator, including the following steps:
S01:提供临时衬底;S01: Provide temporary substrate;
S02:在所述临时衬底上形成压电叠层结构,所述压电叠层结构包括由下至上依次设置的第二电极、压电层、第一电极;S02: forming a piezoelectric laminate structure on the temporary substrate, the piezoelectric laminate structure including a second electrode, a piezoelectric layer, and a first electrode arranged in sequence from bottom to top;
S03:形成介质层,覆盖所述压电叠层结构;S03: forming a dielectric layer to cover the piezoelectric laminate structure;
S04:图形化所述介质层,形成第一空腔,所述第一空腔贯穿所述介质层;S04: Pattern the dielectric layer to form a first cavity, and the first cavity penetrates the dielectric layer;
S05:提供承载衬底,所述承载基底包括第一半导体层和第一器件层,所述承载衬底的第一表面嵌入有第一微器件,所述第一器件层所在侧为所述承载基底的第一表面所在侧;S05: Provide a carrier substrate, the carrier substrate includes a first semiconductor layer and a first device layer, the first surface of the carrier substrate is embedded with a first micro device, and the side where the first device layer is located is the carrier The side where the first surface of the substrate is located;
S06:键合所述承载衬底至所述介质层上、覆盖所述第一空腔,并使所述第一表面朝向所述第一空腔;S06: Bond the carrier substrate to the dielectric layer, cover the first cavity, and make the first surface face the first cavity;
S07:去除所述临时衬底;S07: Remove the temporary substrate;
S08:形成第一电连接结构,将所述第一微器件与外部信号电连接。S08: Form a first electrical connection structure to electrically connect the first micro-device with an external signal.
需要说明的是,S0N并不用于限定步骤的先后顺序。图2至图11示出了根据本发明实施例2的一种薄膜压电声波谐振器的制造方法不同阶段的结构示意图,请参考图2至图11,详细说明各步骤。It should be noted that SON is not used to limit the sequence of steps. 2 to 11 show schematic diagrams of the structure at different stages of a method for manufacturing a thin film piezoelectric acoustic resonator according to Embodiment 2 of the present invention. Please refer to FIGS. 2 to 11 to describe each step in detail.
参考图2,执行步骤S01:提供临时衬底300。Referring to FIG. 2, step S01 is performed: a temporary substrate 300 is provided.
临时衬底300可以是以下所提到的材料中的至少一种:硅(Si)、锗(Ge)、锗硅(SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V化合物半导体,也可为氧化铝等的陶瓷基底、石英或玻璃基底等。The temporary substrate 300 may be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, can also be ceramic substrates such as alumina, quartz or glass substrates, etc.
参考图3,执行步骤S02:在所述临时衬底300上形成压电叠层结构,所述压电叠层结构包括由下至上依次设置的第二电极105、压电层104、第一电极103。Referring to FIG. 3, perform step S02: forming a piezoelectric laminate structure on the temporary substrate 300, the piezoelectric laminate structure including a second electrode 105, a piezoelectric layer 104, and a first electrode arranged in sequence from bottom to top 103.
第二电极105和第一电极103的材料可以使用本领域技术人员熟知的任意合适的导电材料或半导体材料,其中,导电材料可以为具有导电性能的金属材料,例如,由钼(Mo)、铝(Al)、铜(Cu)、钨(W)、钽(Ta)、铂(Pt)、钌(Ru)、铑(Rh)、铱(Ir)、铬(Cr)、钛(Ti)、金(Au)、锇(Os)、铼(Re)、钯(Pd)等金属中一种制成或由上述金属形成的叠层制成,半导体材料例如是Si、Ge、SiGe、SiC、SiGeC等。可以通过磁控溅射、蒸镀等物理气相沉积或者化学气相沉积方法形成第二电极105和第一电极103。压电层104的材料可以使用氮化铝(AlN)、氧化锌(ZnO)、锆钛酸铅(PZT)、铌酸锂(LiNbO3)、石英(Quartz)、铌酸钾(KNbO3)或钽酸锂(LiTaO3)等具有纤锌矿型结晶结构的压电材料及它们的组合。当压电层104包括氮化铝(AlN)时,压电层104还可包括稀土金属,例如钪(Sc)、铒(Er)、钇(Y)和镧(La)中的至少一种。此外,当压电层104包括氮化铝(AlN)时,压电层104还可包括过渡金属,例如锆(Zr)、钛(Ti)、锰(Mn)和铪(Hf)中的至少一种。可以使用化学气相沉积、物理气相沉积或原子层沉积等本领域技术人员熟知的任何适合的方法沉积形成压电层104。可选的,本实施例中,第二电极105和第一电极103由金属钼(Mo)制成,压电层104由氮化铝(AlN)制成。The materials of the second electrode 105 and the first electrode 103 can use any suitable conductive material or semiconductor material well known to those skilled in the art, wherein the conductive material can be a metal material with conductive properties, for example, made of molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), palladium (Pd) and other metals or laminates of the above metals, semiconductor materials such as Si, Ge, SiGe, SiC, SiGeC, etc. . The second electrode 105 and the first electrode 103 may be formed by physical vapor deposition or chemical vapor deposition methods such as magnetron sputtering, evaporation, or the like. The material of the piezoelectric layer 104 can be aluminum nitride (AlN), zinc oxide (ZnO), lead zirconate titanate (PZT), lithium niobate (LiNbO3), quartz (Quartz), potassium niobate (KNbO3) or tantalic acid Piezoelectric materials with wurtzite crystal structure such as lithium (LiTaO3) and their combinations. When the piezoelectric layer 104 includes aluminum nitride (AlN), the piezoelectric layer 104 may further include rare earth metals, such as at least one of scandium (Sc), erbium (Er), yttrium (Y), and lanthanum (La). In addition, when the piezoelectric layer 104 includes aluminum nitride (AlN), the piezoelectric layer 104 may further include a transition metal, such as at least one of zirconium (Zr), titanium (Ti), manganese (Mn), and hafnium (Hf). kind. The piezoelectric layer 104 can be deposited and formed by any suitable method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Optionally, in this embodiment, the second electrode 105 and the first electrode 103 are made of metal molybdenum (Mo), and the piezoelectric layer 104 is made of aluminum nitride (AlN).
参考图4,执行步骤S03:形成介质层102,覆盖所述压电叠层结构。Referring to FIG. 4, step S03 is performed: forming a dielectric layer 102 to cover the piezoelectric laminate structure.
通过物理气相沉积或化学气相沉积形成介质层102。介质层102的材料可以是任意适合的介电材料,包括但不限于氧化硅、氮化硅、氮氧化硅、碳氮化硅等材料中的至少一种。The dielectric layer 102 is formed by physical vapor deposition or chemical vapor deposition. The material of the dielectric layer 102 may be any suitable dielectric material, including but not limited to at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the like.
参考图5,执行步骤S05:图形化所述介质层102,形成第一空腔110a,所述第一空腔110a贯穿所述介质层102。Referring to FIG. 5, step S05 is performed: the dielectric layer 102 is patterned to form a first cavity 110 a, and the first cavity 110 a penetrates the dielectric layer 102.
通过刻蚀工艺刻蚀介质层102形成第一空腔110a,并暴露出底部的第一电极层103。该刻蚀工艺可以是湿法刻蚀或者干法刻蚀工艺,干法刻蚀包括但不限于反应离子刻蚀(RIE)、离子束刻蚀、等离子体刻蚀。第一空腔110a的深度和形状均取决于待制造的体声波谐振器所需空腔的深度和形状,即可以通过形成介质层102的厚度来确定第一空腔110a的深度。第一空腔110a底面的形状可以为矩形或是矩形以外的多边形,例如五边形、六边形、八边形等,也可以为圆形或椭圆形。The dielectric layer 102 is etched by an etching process to form a first cavity 110a and expose the first electrode layer 103 at the bottom. The etching process may be a wet etching process or a dry etching process. Dry etching includes but is not limited to reactive ion etching (RIE), ion beam etching, and plasma etching. The depth and shape of the first cavity 110a depend on the depth and shape of the cavity required for the bulk acoustic wave resonator to be manufactured, that is, the depth of the first cavity 110a can be determined by the thickness of the dielectric layer 102 formed. The shape of the bottom surface of the first cavity 110a can be a rectangle or a polygon other than a rectangle, such as a pentagon, a hexagon, an octagon, etc., and can also be a circle or an ellipse.
参考图6,执行步骤S05:提供承载衬底,所述承载基底包括第一半导体层100A和第一器件层100B,所述承载衬底的第一表面嵌入有第一微器件1000,所述第一器件层100B所在侧为所述承载基底的第一表面所在侧。第一半导体层100A的材质、第一器件层100B的材质,第一微器件1000的种类及与承载衬底的结构关系参照实施例1的相关描述,此处不再赘述。Referring to FIG. 6, step S05 is performed: providing a carrier substrate, the carrier substrate includes a first semiconductor layer 100A and a first device layer 100B, the first surface of the carrier substrate is embedded with the first micro device 1000, and the second The side where a device layer 100B is located is the side where the first surface of the carrier substrate is located. For the material of the first semiconductor layer 100A, the material of the first device layer 100B, the type of the first micro-device 1000 and the structural relationship with the carrier substrate, refer to the related description of Embodiment 1, which will not be repeated here.
参考图7,执行步骤S06:键合所述承载衬底至所述介质层102上、覆盖所述第一空腔110a,并使所述第一表面朝向所述第一空腔110a。介质层的材料以及介质层与承载衬底的键合方式参照实施例1的相关描述。Referring to FIG. 7, step S06 is performed: bonding the carrier substrate to the dielectric layer 102, covering the first cavity 110a, and making the first surface face the first cavity 110a. For the material of the dielectric layer and the bonding method of the dielectric layer and the carrier substrate, refer to the related description of Embodiment 1.
参考图8,执行步骤S07:去除所述临时衬底。去除临时衬底的方法可以采用机械研磨。Referring to FIG. 8, step S07 is performed: removing the temporary substrate. The method of removing the temporary substrate can be mechanical grinding.
参考图9和图10,本实施例中,在形成第一电连接结构,连接所述第一微器件之前还还包括:在所述压电叠层结构上形成接合层106,所述接合层106围成第二空腔110b,所述第二空腔110b暴露出所述压电叠层结构的表面,所述第二空腔110b位于所述第一空腔110a上方。提供封盖基板,所述封盖基板包括第二半导体层200A和第二器件层200B,所述承盖基板的第一表面嵌入有第二微器件2000,所述第二器件层200B所在侧为所述封盖基板的第一表面所在侧。将所述封盖基板设置于所述接合层106上、覆盖所述第二空腔110b,并使所述封盖基板的第一表面朝向所述第二空腔110b。结合层106的材料、第二半导体层200A的材质、第二器件层200B的材质,第二微器件2000的种类及与封盖基板的结构关系参照实施例1的相关描述,此处不再赘述。9 and 10, in this embodiment, before forming the first electrical connection structure and connecting the first micro device, it further includes: forming a bonding layer 106 on the piezoelectric laminate structure, the bonding layer 106 encloses a second cavity 110b, which exposes the surface of the piezoelectric laminate structure, and the second cavity 110b is located above the first cavity 110a. A cover substrate is provided, the cover substrate includes a second semiconductor layer 200A and a second device layer 200B, a second micro device 2000 is embedded on the first surface of the cover substrate, and the second device layer 200B is located on the side The first surface of the cover substrate is located on the side. The cover substrate is disposed on the bonding layer 106 to cover the second cavity 110b, and the first surface of the cover substrate faces the second cavity 110b. For the material of the bonding layer 106, the material of the second semiconductor layer 200A, the material of the second device layer 200B, the type of the second micro device 2000 and the structure relationship with the cover substrate, please refer to the related description of Embodiment 1, which will not be repeated here. .
参考图11,执行步骤S08:形成第一电连接结构,将所述第一微器件与外部信号电连接。本实施例例中还包括:形成第二电连接结构,将所述第二微器件与外部信号电连接。第一电连接结构和第二电连接结构分别为第一导电插塞1001和第二导电插塞2001。本实施例中,形成第一导电插塞1001和第二导电插塞2001包括:从所述承载衬底侧形成贯穿所述承载衬底的第一通孔(图中未示出)以及贯穿所述承载衬底及所述承载衬底上方结构(本实施例中上方结构包括介质层102,压电叠层结构、接合层106以及部分第二器件层200B)的第二通孔(图中未示出),所述第一通孔暴露出所述第一微器件1000,所述第二通孔暴露出所述第二微器件2000,在所述第一通孔1000和所述第二通孔2000中形成导电材料,以形成所述第一导电插塞1001及所述第二导电插塞2001。形成第一通孔和第二通孔可以采用干法刻蚀工艺,在第一通孔和第二通孔中形成导电材料可以采用电镀或化镀工艺。Referring to FIG. 11, step S08 is performed: forming a first electrical connection structure, and electrically connecting the first micro-device with an external signal. This embodiment also includes: forming a second electrical connection structure to electrically connect the second micro device with an external signal. The first electrical connection structure and the second electrical connection structure are the first conductive plug 1001 and the second conductive plug 2001 respectively. In this embodiment, forming the first conductive plug 1001 and the second conductive plug 2001 includes: forming a first through hole (not shown in the figure) penetrating the supporting substrate from the supporting substrate side and penetrating the through holes. The carrier substrate and the second through hole of the upper structure of the carrier substrate (the upper structure in this embodiment includes the dielectric layer 102, the piezoelectric laminate structure, the bonding layer 106, and part of the second device layer 200B) (not shown in the figure) (Shown), the first through hole exposes the first micro device 1000, the second through hole exposes the second micro device 2000, and the first through hole 1000 and the second through hole expose the second micro device 2000. A conductive material is formed in the hole 2000 to form the first conductive plug 1001 and the second conductive plug 2001. The first through hole and the second through hole may be formed by a dry etching process, and the conductive material may be formed in the first through hole and the second through hole by using an electroplating or electroless plating process.
在另一个实施例中,形成第一导电插塞1001和第二导电插塞2001包括:从所述封盖基板侧形成贯穿所述封盖基板的第三通孔以及贯穿所述封盖基板及所述封盖基板下方结构的第四通孔,所述第三通孔暴露出所述第二微器件,所述第四通孔暴露出所述第一微器件,在所述第三通孔和所述第四通孔中形成导电材料,以形成所述第二导电插塞及所述第一导电插塞。In another embodiment, forming the first conductive plug 1001 and the second conductive plug 2001 includes: forming a third through hole penetrating the cover substrate from the cover substrate side, and penetrating the cover substrate and The fourth through hole of the structure under the cover substrate, the third through hole exposes the second micro device, the fourth through hole exposes the first micro device, and the third through hole And a conductive material is formed in the fourth through hole to form the second conductive plug and the first conductive plug.
以上两导电插塞均形成于谐振器的同侧(承载衬底所在侧或封盖基板所在侧),这样设置的原因参照实施例1的相关描述。导电插塞形成于承载衬底所在侧之前,还包括以封盖基板为支撑,减薄承载衬底;导电插塞形成于封盖基板所在侧之前,还包括以承载衬底为支撑,减薄封盖基板。The above two conductive plugs are both formed on the same side of the resonator (the side where the carrier substrate is located or the side where the cover substrate is located), and the reason for this arrangement is referred to the related description of Embodiment 1. The conductive plug is formed before the side of the carrier substrate, and it also includes the support of the cover substrate to reduce the thickness of the carrier substrate; the conductive plug is formed before the side of the cover substrate, and also includes the support of the carrier substrate to reduce the thickness. Cover the substrate.
本实施例中,还包括形成第一电极引出部和第二电极引出部,所述第一电极引出部连接于所述第一电极103,所述第二电极引出部连接于所述第二电极105,所述第一电极引出部、所述第二电极引出部位于所述承载衬底所在侧。当第一导电插塞及所述第二导电插塞位于封盖基板所在侧时,第一电极引出部、所述第二电极引出部优选方案中也位于封盖基板所在侧。In this embodiment, it further includes forming a first electrode lead-out part and a second electrode lead-out part, the first electrode lead-out part is connected to the first electrode 103, and the second electrode lead-out part is connected to the second electrode 105. The first electrode lead-out portion and the second electrode lead-out portion are located on the side of the carrier substrate. When the first conductive plug and the second conductive plug are located on the side of the cover substrate, the first electrode lead-out portion and the second electrode lead portion are also located on the side of the cover substrate in a preferred solution.
其中形成所述第一电极引出部包括:Wherein forming the first electrode lead-out part includes:
通过刻蚀工艺形成贯穿所述第一电极103下层结构的通孔,所述通孔暴露出所述第一电极103,在通孔中通过电镀工艺或物理气相沉积工艺形成第一导电互连层141,所述第一导电互连层141覆盖所述通孔的内表面、及所述通孔外周的所述承载衬底100的部分表面,与所述第一电极103连接;在所述第一导电互连层141表面通过沉积工艺形成绝缘层160;在所述承载衬底的表面形成第一导电凸起142,所述第一导电凸起142与所述第一导电互连层141电连接。A through hole is formed through the lower layer structure of the first electrode 103 by an etching process, the through hole exposes the first electrode 103, and a first conductive interconnection layer is formed in the through hole by an electroplating process or a physical vapor deposition process 141. The first conductive interconnection layer 141 covers the inner surface of the through hole and a part of the surface of the carrier substrate 100 on the periphery of the through hole, and is connected to the first electrode 103; An insulating layer 160 is formed on the surface of a conductive interconnection layer 141 by a deposition process; first conductive bumps 142 are formed on the surface of the carrier substrate, and the first conductive bumps 142 are electrically connected to the first conductive interconnection layer 141. connect.
形成所述第二电极引出部包括:Forming the second electrode lead-out portion includes:
通过刻蚀工艺形成贯穿所述第一电极103下层结构的通孔,所述通孔暴露出所述第二电极105,在通孔中通过沉积工艺或电镀工艺形成第二导电互连层151,所述第二导电互连层151覆盖通孔内表面、及通孔外周的所述承载衬底的部分表面,与所述第二电极105连接;在所述第二导电互连层151表面通过沉积工艺形成绝缘层160;在所述承载衬底100的表面形成第二导电凸起152,所述第二导电凸起152与所述第二导电互连层151电连接。An etching process is used to form a through hole penetrating the lower layer structure of the first electrode 103, the through hole exposes the second electrode 105, and a second conductive interconnection layer 151 is formed in the through hole through a deposition process or an electroplating process, The second conductive interconnection layer 151 covers the inner surface of the through hole and a part of the surface of the carrier substrate on the periphery of the through hole, and is connected to the second electrode 105; The insulating layer 160 is formed by a deposition process; a second conductive bump 152 is formed on the surface of the carrier substrate 100, and the second conductive bump 152 is electrically connected to the second conductive interconnect layer 151.
需要说明的是,本说明书中的各个实施例均采用相关的方式描述,各个实施例之间相同相似的部分互相参见即可,每个实施例重点说明的都是与其他实施例的不同之处。尤其,对于方法实施例而言,由于其基本相似于结构实施例,所以描述的比较简单,相关之处参见方法实施例的部分说明即可。It should be noted that the various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. . In particular, as for the method embodiment, since it is basically similar to the structural embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment.
上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes or modifications made by a person of ordinary skill in the field of the present invention based on the above disclosure shall fall within the protection scope of the claims.
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Claims (26)

  1. 一种薄膜体声波谐振器,其特征在于,包括:A thin film bulk acoustic wave resonator, characterized in that it comprises:
    承载衬底,所述承载基底包括第一半导体层和第一器件层;A carrier substrate, the carrier substrate including a first semiconductor layer and a first device layer;
    第一微器件,所述第一微器件嵌入于所述承载衬底中,且所述第一微器件的至少部分位于所述第一器件层中;A first micro device, the first micro device is embedded in the carrier substrate, and at least part of the first micro device is located in the first device layer;
    介质层,键合于所述第一器件层上,所述介质层围成第一空腔,所述第一空腔暴露出所述承载衬底的表面;A dielectric layer, bonded to the first device layer, the dielectric layer encloses a first cavity, and the first cavity exposes the surface of the carrier substrate;
    压电叠层结构,覆盖所述第一空腔,所述压电叠层结构从下至上包括依次层叠的第一电极、压电层和第二电极; A piezoelectric laminate structure covering the first cavity, the piezoelectric laminate structure including a first electrode, a piezoelectric layer, and a second electrode that are sequentially stacked from bottom to top;
    第一电连接结构,连接所述第一微器件,将所述第一微器件电性引出。The first electrical connection structure connects the first micro-device and electrically leads the first micro-device.
  2. 如权利要求1所述的薄膜体声波谐振器,其特征在于,还包括:The thin film bulk acoustic resonator of claim 1, further comprising:
    接合层,设置于所述压电叠层结构上方,所述接合层围成第二空腔,所述第二空腔暴露出所述压电叠层结构的表面,所述第二空腔与所述第一空腔在压电叠层结构上的投影有重叠部分;The bonding layer is disposed above the piezoelectric laminate structure, the bonding layer encloses a second cavity, and the second cavity exposes the surface of the piezoelectric laminate structure, and the second cavity is connected to The projection of the first cavity on the piezoelectric laminated structure has an overlapping part;
    封盖基板,设置于所述接合层上,并覆盖所述第二空腔。The cover substrate is arranged on the bonding layer and covers the second cavity.
  3. 如权利要求2所述的薄膜体声波谐振器,其特征在于,所述封盖基板包括第二半导体层和第二器件层,所述第二器件层靠近所述第二空腔所在侧;还包括:The thin film bulk acoustic resonator of claim 2, wherein the cover substrate comprises a second semiconductor layer and a second device layer, the second device layer is close to the side where the second cavity is located; and include:
    第二微器件,所述第二微器件嵌入于所述封盖基板中,且所述第二微器件的至少部分位于所述第二器件层中;A second micro device, the second micro device is embedded in the cover substrate, and at least part of the second micro device is located in the second device layer;
    第二电连接结构,连接于所述第二微器件,将所述第二微器件电性引出。The second electrical connection structure is connected to the second micro-device and electrically leads the second micro-device.
  4. 如权利要求1所述的薄膜体声波谐振器,其特征在于,所述第一电连接结构包括:5. The thin film bulk acoustic resonator of claim 1, wherein the first electrical connection structure comprises:
    第一导电插塞,所述第一导电插塞从所述承载衬底的底面延伸至所述第一微器件或;所述第一导电插塞从所述封盖基板的顶面延伸至所述第一微器件。The first conductive plug, the first conductive plug extends from the bottom surface of the carrier substrate to the first micro-device or; the first conductive plug extends from the top surface of the cover substrate to the The first micro-device.
  5. 如权利要求3所述的薄膜体声波谐振器,其特征在于,所述第二电连接结构包括:The thin film bulk acoustic resonator of claim 3, wherein the second electrical connection structure comprises:
    第二导电插塞,所述第二导电插塞从所述承载衬底的底面延伸至所述第一微器件或;所述第二导电插塞从所述封盖基板的顶面延伸至所述第二微器件。Second conductive plug, the second conductive plug extends from the bottom surface of the carrier substrate to the first micro-device or; the second conductive plug extends from the top surface of the cover substrate to the The second micro device.
  6. 如权利要求3所述的薄膜体声波谐振器,其特征在于,还包括第三电连接结构,所述第三电连接结构连接第一微器件与所述第二微器件。3. The thin film bulk acoustic resonator of claim 3, further comprising a third electrical connection structure, the third electrical connection structure connecting the first micro-device and the second micro-device.
  7. 如权利要求3所述的薄膜体声波谐振器,其特征在于,所述第一微器件和/或所述第二微器件包括:8. The thin film bulk acoustic resonator according to claim 3, wherein the first micro-device and/or the second micro-device comprises:
    二极管、三极管、MOS晶体管、静电释放保护器件、电阻、电容或电感。Diodes, triodes, MOS transistors, electrostatic discharge protection devices, resistors, capacitors or inductors.
  8. 如权利要求1所述的薄膜体声波谐振器,其特征在于,所述第一器件层的材料包括:氧化硅、氮化硅、氮氧化硅或碳氮化硅。The thin film bulk acoustic resonator of claim 1, wherein the material of the first device layer comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
  9. 如权利要求1所述的薄膜体声波谐振器,其特征在于,所述介质层的材料包括氧化硅、氮化硅、氮氧化硅、碳氮化硅或硅酸乙酯。The thin film bulk acoustic resonator of claim 1, wherein the material of the dielectric layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or ethyl silicate.
  10. 如权利要求1所述的薄膜体声波谐振器,其特征在于,所述介质层与所述第一器件层的材质相同,所述键合方式包括:原子键键合。5. The thin film bulk acoustic resonator of claim 1, wherein the dielectric layer and the first device layer are made of the same material, and the bonding method includes atomic bonding.
  11. 如权利要求1所述的薄膜体声波谐振器,其特征在于,还包括键合层,设置于所述介质层与所述承载衬底之间。8. The thin film bulk acoustic resonator of claim 1, further comprising a bonding layer disposed between the dielectric layer and the carrier substrate.
  12. 如权利要求11所述的薄膜体声波谐振器,其特征在于,所述键合层的材料包括:氧化硅、氮化硅、多晶硅、硅酸乙酯或有机固化膜。11. The thin film bulk acoustic resonator of claim 11, wherein the bonding layer is made of silicon oxide, silicon nitride, polysilicon, ethyl silicate, or organic cured film.
  13. 如权利要求12所述的薄膜体声波谐振器,其特征在于,所述介质层与所述键合层的材料相同。The thin film bulk acoustic resonator according to claim 12, wherein the material of the dielectric layer and the bonding layer are the same.
  14. 如权利要求1所述的薄膜体声波谐振器,其特征在于,还包括:The thin film bulk acoustic resonator of claim 1, further comprising:
    第一沟槽,位于所述第一空腔围成的区域内部,贯穿所述第一电极,或贯穿所述第一电极和所述压电层;A first groove, located inside the area enclosed by the first cavity, penetrates the first electrode, or penetrates the first electrode and the piezoelectric layer;
    第二沟槽,位于所述第二空腔围成的区域内部,在横向方向上与所述第一沟槽相对设置,贯穿所述第二电极,或贯穿所述第二电极和所述压电层;The second groove is located inside the area enclosed by the second cavity, is disposed opposite to the first groove in the lateral direction, and penetrates the second electrode, or penetrates the second electrode and the pressure Electric layer
    所述第一沟槽与所述第二沟槽在所述承载衬底的投影的两个交界处相接或设有间隙。The first groove and the second groove meet or are provided with a gap at two junctions of the projection of the carrier substrate.
  15. 如权利要求1所述的薄膜体声波谐振器,其特征在于,所述第一电极、压电层和第二电极在垂直于所述承载衬底方向上相互重叠的区域为有效谐振区,所述有效谐振区的边界位于所述第一空腔包围的区域内,所述有效谐振区边界处设置有凸起,所述凸起设置于所述压电叠层结构上表面或下表面;或,The thin film bulk acoustic resonator of claim 1, wherein the area where the first electrode, the piezoelectric layer, and the second electrode overlap each other in a direction perpendicular to the carrier substrate is an effective resonance area, so The boundary of the effective resonance region is located in the area surrounded by the first cavity, and protrusions are provided at the boundary of the effective resonance region, and the protrusions are provided on the upper surface or the lower surface of the piezoelectric laminate structure; or ,
    所述凸起部分设置于所述压电叠层结构的上表面,部分设置于所述压电叠层结构的下表面。The protruding part is arranged on the upper surface of the piezoelectric laminated structure, and partly arranged on the lower surface of the piezoelectric laminated structure.
  16. 一种薄膜体声波谐振器的制造方法,其特征在于,包括:A method for manufacturing a thin film bulk acoustic wave resonator, which is characterized in that it comprises:
    提供临时衬底;Provide temporary substrate;
    在所述临时衬底上形成压电叠层结构,所述压电叠层结构包括由下至上依次设置的第二电极、压电层、第一电极;Forming a piezoelectric laminate structure on the temporary substrate, the piezoelectric laminate structure including a second electrode, a piezoelectric layer, and a first electrode arranged in sequence from bottom to top;
    形成介质层,覆盖所述压电叠层结构;Forming a dielectric layer to cover the piezoelectric laminate structure;
    图形化所述介质层,形成第一空腔,所述第一空腔贯穿所述介质层;Patterning the dielectric layer to form a first cavity, and the first cavity penetrates the dielectric layer;
    提供承载衬底,所述承载衬底包括第一半导体层和第一器件层,所述承载衬底中嵌入有第一微器件,且所述第一微器件的至少部分位于所述第一器件层中;A carrier substrate is provided, the carrier substrate includes a first semiconductor layer and a first device layer, a first micro device is embedded in the carrier substrate, and at least part of the first micro device is located in the first device Layer
    键合所述承载衬底的所述第一器件层至所述介质层上、覆盖所述第一空腔;Bonding the first device layer of the carrier substrate to the dielectric layer to cover the first cavity;
    去除所述临时衬底; Removing the temporary substrate;
    形成第一电连接结构,将所述第一微器件电性引出。A first electrical connection structure is formed, and the first micro-device is electrically drawn out.
  17. 如权利要求16所述的薄膜体声波谐振器的制造方法,其特征在于,去除所述临时衬底后、形成第一电连接结构前还包括:16. The method of manufacturing a thin film bulk acoustic resonator according to claim 16, wherein after removing the temporary substrate and before forming the first electrical connection structure, the method further comprises:
    在所述压电叠层结构上形成接合层,所述接合层围成第二空腔,所述第二空腔暴露出所述压电叠层结构的表面,所述第二空腔位于所述第一空腔上方;A bonding layer is formed on the piezoelectric laminate structure, the bonding layer encloses a second cavity, the second cavity exposes the surface of the piezoelectric laminate structure, and the second cavity is located at the Above the first cavity;
    提供封盖基板,将所述封盖基板设置于所述接合层上、覆盖所述第二空腔,并使所述封盖基板的第一表面朝向所述第二空腔。A cover substrate is provided, the cover substrate is disposed on the bonding layer, covers the second cavity, and the first surface of the cover substrate faces the second cavity.
  18. 如权利要求17所述的薄膜体声波谐振器的制造方法,其特征在于,所述封盖基板的第一表面嵌入有第二微器件,将所述封盖基板设置于所述接合层上后还包括:形成第二电连接结构,将所述第二微器件与外部信号电连接。The method for manufacturing a thin film bulk acoustic resonator according to claim 17, wherein the first surface of the cover substrate is embedded with a second micro device, and the cover substrate is placed on the bonding layer. It also includes: forming a second electrical connection structure to electrically connect the second micro device with an external signal.
  19. 如权利要求18所述的薄膜体声波谐振器的制造方法,其特征在于,所述第一电连接结构为第一导电插塞,所述第二电连接结构为第二导电插塞,形成所述第一电连接结构和所述第二电连接结构包括:The method for manufacturing a thin film bulk acoustic resonator according to claim 18, wherein the first electrical connection structure is a first conductive plug, and the second electrical connection structure is a second conductive plug to form a The first electrical connection structure and the second electrical connection structure include:
    从所述承载衬底侧形成贯穿所述承载衬底的第一通孔以及贯穿所述承载衬底及所述承载衬底上方结构的第二通孔,所述第一通孔暴露出所述第一微器件,所述第二通孔暴露出所述第二微器件,在所述第一通孔和所述第二通孔中形成导电材料,以形成所述第一导电插塞及所述第二导电插塞。A first through hole that penetrates the carrier substrate and a second through hole that penetrates the carrier substrate and the upper structure of the carrier substrate are formed from the carrier substrate side, and the first through hole exposes the The first micro device, the second through hole exposes the second micro device, and a conductive material is formed in the first through hole and the second through hole to form the first conductive plug and the second through hole. Mentioned second conductive plug.
  20. 如权利要求18所述的薄膜体声波谐振器的制造方法,其特征在于,所述第一电连接结构为第一导电插塞,所述第二电连接结构为第二导电插塞,形成所述第一电连接结构和所述第二电连接结构包括:The method for manufacturing a thin film bulk acoustic resonator according to claim 18, wherein the first electrical connection structure is a first conductive plug, and the second electrical connection structure is a second conductive plug to form a The first electrical connection structure and the second electrical connection structure include:
    从所述封盖基板侧形成贯穿所述封盖基板的第三通孔以及贯穿所述封盖基板及所述封盖基板下方结构的第四通孔,所述第三通孔暴露出所述第二微器件,所述第四通孔暴露出所述第一微器件,在所述第三通孔和所述第四通孔中形成导电材料,以形成所述第二导电插塞及所述第一导电插塞。A third through hole penetrating the cover substrate and a fourth through hole penetrating through the cover substrate and the structure below the cover substrate are formed from the cover substrate side, and the third through hole exposes the The second micro device, the fourth through hole exposes the first micro device, and a conductive material is formed in the third through hole and the fourth through hole to form the second conductive plug and the Mentioned first conductive plug.
  21. 如权利要求19或20所述的薄膜体声波谐振器的制造方法,其特征在于,所述制造方法还包括:形成第一电极引出部和第二电极引出部,所述第一电极引出部连接于所述第一电极,所述第二电极引出部连接于所述第二电极,所述第一电极引出部、所述第二电极引出部、所述第二导电插塞、所述第一导电插塞的引出端全部位于所述封盖基板所在侧或所述承载衬底所在侧。The method of manufacturing a thin-film bulk acoustic resonator according to claim 19 or 20, wherein the manufacturing method further comprises: forming a first electrode lead-out portion and a second electrode lead-out portion, and the first electrode lead-out portion is connected to In the first electrode, the second electrode lead-out part is connected to the second electrode, the first electrode lead-out part, the second electrode lead-out part, the second conductive plug, the first All the lead-out ends of the conductive plugs are located on the side where the cover substrate is located or the side where the carrier substrate is located.
  22. 如权利要求16所述的薄膜体声波谐振器的制造方法,其特征在于, 形成所述第一空腔后、键合所述承载衬底前,还包括:16. The method for manufacturing a thin film bulk acoustic resonator according to claim 16, wherein after forming the first cavity and before bonding the carrier substrate, the method further comprises:
    对所述第一电极,或所述第一电极和所述压电层进行图形化,形成有效谐振区的部分边界;Patterning the first electrode, or the first electrode and the piezoelectric layer, to form a partial boundary of the effective resonance region;
    去除所述临时衬底后,还包括:After removing the temporary substrate, it also includes:
    对所述第二电极,或所述第二电极和所述压电层进行图形化,形成有效谐振区的另一部分边界,所述有效谐振区的边界位于所述第一空腔和所述第二空腔在所述压电层方向上投影重叠的区域内。The second electrode, or the second electrode and the piezoelectric layer are patterned to form another part of the boundary of the effective resonance region, and the boundary of the effective resonance region is located between the first cavity and the first cavity. The two cavities are projected and overlapped in the direction of the piezoelectric layer.
  23. 如权利要求18所述的薄膜体声波谐振器的制造方法,其特征在于,所述第一微器件和/或所述第二微器件包括:The method for manufacturing a thin film bulk acoustic resonator according to claim 18, wherein the first micro-device and/or the second micro-device comprises:
    二极管、三极管、MOS晶体管、静电释放保护器件、电阻、电容或电感。Diodes, triodes, MOS transistors, electrostatic discharge protection devices, resistors, capacitors or inductors.
  24. 24、如权利要求16所述的薄膜体声波谐振器的制造方法,其特征在于,所述第一器件层的材质包括:氧化硅、氮化硅、氮氧化硅、碳氮化硅。24. The method of manufacturing a thin film bulk acoustic resonator according to claim 16, wherein the material of the first device layer includes silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.
  25. 如权利要求24所述的薄膜体声波谐振器的制造方法,其特征在于,所述介质层的材料与所述第一器件层的材料相同,在所述介质层上键合所述承载衬底包括:通过原子键直接键合。The method for manufacturing a thin film bulk acoustic resonator according to claim 24, wherein the material of the dielectric layer is the same as the material of the first device layer, and the carrier substrate is bonded to the dielectric layer Including: direct bonding through atomic bonds.
  26. 如权利要求16所述的薄膜体声波谐振器的制造方法,其特征在于,在所述介质层上键合所述承载衬底包括:16. The method for manufacturing a thin film bulk acoustic resonator according to claim 16, wherein bonding the carrier substrate on the dielectric layer comprises:
    在所述介质层的表面形成键合层,通过所述键合层键合所述介质层与所述承载衬底,所述介质层与所述键合层的材料相同。A bonding layer is formed on the surface of the dielectric layer, and the dielectric layer and the carrier substrate are bonded through the bonding layer, and the dielectric layer and the bonding layer are made of the same material.
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CN114899303B (en) * 2022-07-08 2022-10-18 深圳新声半导体有限公司 Semiconductor device with a plurality of semiconductor chips
CN115602684A (en) * 2022-08-12 2023-01-13 东科半导体(安徽)股份有限公司(Cn) Integrated structure and preparation method thereof

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