WO2021179415A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2021179415A1
WO2021179415A1 PCT/CN2020/087623 CN2020087623W WO2021179415A1 WO 2021179415 A1 WO2021179415 A1 WO 2021179415A1 CN 2020087623 W CN2020087623 W CN 2020087623W WO 2021179415 A1 WO2021179415 A1 WO 2021179415A1
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WO
WIPO (PCT)
Prior art keywords
sub
electrode
pixel electrode
main
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/087623
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English (en)
French (fr)
Inventor
陈亚妮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
TCL China Star Optoelectronics Technology Co Ltd
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Filing date
Publication date
Application filed by TCL China Star Optoelectronics Technology Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US16/971,335 priority Critical patent/US20210286224A1/en
Publication of WO2021179415A1 publication Critical patent/WO2021179415A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to the field of display technology, and in particular to a display panel.
  • a pixel structure includes two sub-pixels: Pixels (main pixels) and sub-pixels (sub pixels), the pixel electrode ITO of each sub-pixel is a "m-shaped", divided into 4 display domain areas.
  • 8-domain display technology is to make the main pixel electrode and sub The voltages of the pixel electrodes are different, resulting in a difference in the rotation angle of the liquid crystal molecules, which promotes the improvement of the viewing angle.
  • Figure 2 is an equivalent circuit diagram of the prior art provided by this disclosure.
  • the scan line 1 (Gate) turns on two thin film transistors (T1 and T2), and the signal of the data line 2 (Data) passes through
  • the hole 6 and the via hole 7 enter the main pixel 3 and the sub pixel 4, and the voltage part of the sub pixel 4 is released to the common electrode 5 by the deep and shallow holes 8 through T3, so as to realize that the voltage of the main pixel 3 and the sub pixel 4 are different.
  • via holes 6 and via holes 7 are respectively provided on both sides of the scan line 1, occupying part of the opening of the pixel structure, resulting in a decrease in light transmittance, which cannot meet the increasing demand for transmittance.
  • the pixel unit of the existing display panel is provided with via holes on both sides of the scan line, so that the aperture ratio of the pixel unit is reduced, and the light transmittance is reduced. Therefore, it is necessary to provide a display panel to improve this defect.
  • the embodiments of the present disclosure provide a display panel, which is used to solve the problem that the aperture ratio of the pixel unit is reduced due to the via holes provided on both sides of the scan line in the pixel unit of the existing display panel, and the light transmittance is reduced.
  • An embodiment of the present disclosure provides a display panel, which includes a first substrate on which a plurality of sub-pixel units arranged in an array, a plurality of data lines extending in a first direction, and a plurality of data lines perpendicular to the Scan lines extending in the first direction;
  • the sub-pixel unit includes a sub-pixel electrode and a plurality of thin film transistors.
  • the sub-pixel electrode includes a main sub-pixel electrode and a sub-sub-pixel electrode.
  • the main sub-pixel electrode includes a first part, a second part, and a connection between the first part and the
  • the peripheral connecting part of the second part forms an accommodating space between the first part and the second part and the peripheral connecting part, and the sub-pixel electrode is disposed in the accommodating space and is connected to
  • the scan line of the sub-pixel unit is arranged on a side of the second part away from the first part.
  • the main sub-pixel electrode includes a first main And the sub-sub-pixel electrode is divided into a plurality of domain regions.
  • the first stem electrode only includes a vertical stem electrode extending along the first direction, and the vertical stem electrode divides the main sub-pixel electrode into a plurality of domain regions.
  • the sub-pixel electrode further includes a plurality of branch electrodes located in the domain area, and the plurality of branch electrodes located in the same domain area are arranged in parallel and spaced apart from each other. The extension directions of the branch electrodes in the two domain regions are different.
  • one of the plurality of thin film transistors is connected to the sub-pixel electrode through the first via hole, and the first via hole is disposed in the accommodating space and is connected to The second main electrode overlaps.
  • the second stem electrode includes a vertical stem electrode extending along the first direction and a horizontal stem electrode extending perpendicular to the first direction, and the first via is provided in the The intersection of the vertical main electrode and the horizontal main electrode.
  • the plurality of thin film transistors includes a first thin film transistor and a second thin film transistor, the first thin film transistor is connected to the main sub-pixel electrode, and the second thin film transistor is connected to the sub sub-pixel electrode.
  • a common electrode is further provided on the first substrate, the plurality of thin film transistors further include a third thin film transistor, the gate of the third thin film transistor is connected to the scan line, and the second The source and drain of the three thin film transistors are respectively connected to the second thin film transistor and the common electrode.
  • the common electrode and the scan line are arranged on the same layer.
  • the peripheral connection portion includes two strip electrodes extending along the first direction, and the two strip electrodes are respectively disposed on both sides of the main sub-pixel electrode.
  • An embodiment of the present disclosure also provides a display panel, including a first substrate on which a plurality of sub-pixel units arranged in an array, a plurality of data lines extending in a first direction, and a plurality of data lines perpendicular to the The scan line extending in the first direction;
  • the sub-pixel unit includes a sub-pixel electrode and a plurality of thin film transistors, the sub-pixel electrode includes a main sub-pixel electrode, a sub-sub-pixel electrode, and a plurality of branch electrodes, and the main sub-pixel electrode includes a first part, a second part, and a connection point.
  • the main sub-pixel electrode includes a first main electrode
  • the auxiliary sub-pixel electrode includes a second main electrode
  • the first main electrode and the second main electrode connect the main sub-pixel electrode and the auxiliary sub-pixel electrode, respectively.
  • the branch electrodes are respectively located in the domain regions, and the plurality of branch electrodes located in the same domain region are arranged in parallel and spaced apart from each other, and two adjacent domain regions The extension directions of the branch electrodes are different.
  • the first stem electrode only includes a vertical stem electrode extending along the first direction, and the vertical stem electrode divides the main sub-pixel electrode into a plurality of domain regions.
  • one of the plurality of thin film transistors is connected to the sub-pixel electrode through the first via hole, and the first via hole is disposed in the accommodating space and is connected to The second main electrode overlaps.
  • the second stem electrode includes a vertical stem electrode extending along the first direction and a horizontal stem electrode extending perpendicular to the first direction, and the first via is provided in the The intersection of the vertical main electrode and the horizontal main electrode.
  • the plurality of thin film transistors includes a first thin film transistor and a second thin film transistor, the first thin film transistor is connected to the main sub-pixel electrode, and the second thin film transistor is connected to the sub sub-pixel electrode.
  • a common electrode is further provided on the first substrate, the plurality of thin film transistors further include a third thin film transistor, the gate of the third thin film transistor is connected to the scan line, and the second The source and drain of the three thin film transistors are respectively connected to the second thin film transistor and the common electrode.
  • the common electrode and the scan line are arranged on the same layer.
  • the peripheral connection portion includes two strip electrodes extending along the first direction, and the two strip electrodes are respectively disposed on both sides of the main sub-pixel electrode.
  • An embodiment of the present disclosure further provides a display panel, including a first substrate, on which a plurality of sub-pixel units arranged in an array, a plurality of data lines extending in a first direction, and a plurality of The scan line extending in the first direction;
  • the sub-pixel unit includes a sub-pixel electrode and a plurality of thin film transistors, the sub-pixel electrode includes a main sub-pixel electrode, a sub-sub-pixel electrode, and a plurality of branch electrodes, and the main sub-pixel electrode includes a first part, a second part, and a connection point.
  • the main sub-pixel electrode includes a first main electrode, the first main electrode includes only a vertical main electrode extending in the first direction, and the auxiliary sub-pixel electrode includes a second main electrode, the vertical main electrode And the second main electrode respectively divide the main sub-pixel electrode and the sub-sub-pixel electrode into a plurality of domain regions, the branch electrodes are respectively located in the domain regions, and a plurality of The branch electrodes are arranged parallel to each other and spaced apart, and the extension directions of the branch electrodes in two adjacent domain regions are different.
  • one of the plurality of thin film transistors is connected to the sub-pixel electrode through the first via hole, and the first via hole is disposed in the accommodating space and is connected to The second main electrode overlaps.
  • the display panel provided by the embodiments of the present disclosure divides the main sub-pixel electrode into a first part, a second part, and a peripheral connection part connecting the first part and the second part, and disposes the sub-sub-pixel electrode on the display panel.
  • the first part and the second part and the peripheral connecting part form the accommodating space, and the scan line is arranged on the side of the second part away from the first part, so that the main sub-pixel electrode and the sub-sub-pixel electrode are both located on the same side of the scan line, Therefore, it is not necessary to arrange the via holes connecting the main sub-pixel electrode and the sub-sub-pixel electrode on both sides of the scan line respectively, so as to increase the opening area of the sub-pixel unit, thereby improving the light transmittance of the sub-pixel unit.
  • FIG. 1 is a schematic diagram of the pixel structure of the prior art provided by the present disclosure
  • FIG. 2 is an equivalent circuit diagram of the prior art provided by this disclosure.
  • FIG. 3 is a schematic diagram of the structure of a pixel unit provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic structural diagram of a pixel unit provided by an embodiment of the present disclosure.
  • the display panel includes a first substrate on which a plurality of sub-pixel units 11 arranged in an array and a plurality of sub-pixel units 11 arranged in an array are provided.
  • a data line 12 extending in one direction and a plurality of scan lines 13 extending perpendicular to the first direction, wherein each data line 12 is connected to a corresponding column of the sub-pixel units 11, and each scan line 13 is connected to a corresponding One row of the sub-pixel units 11.
  • the sub-pixel unit 11 includes a sub-pixel electrode and a thin film transistor disposed on one side of the sub-pixel electrode.
  • the sub-pixel electrode includes a main sub-pixel electrode A and a sub-sub-pixel electrode B.
  • the main sub-pixel electrode A includes a first portion A1 disposed oppositely. And the second part A2, and the peripheral connecting part A3 connecting the first part A1 and the second part A2.
  • the main sub-pixel electrode A includes a first main electrode 111, and the first main electrode 111 is provided in both the first part A1 and the second part A2.
  • the first main electrode 111 separates the first part A1 and the second part A1 respectively.
  • the two parts A2 are divided into a plurality of domain regions, and each domain region is provided with a branch electrode 113.
  • the first stem electrode 111 only includes the first vertical stem electrode 1111 extending along the first direction.
  • the first vertical stem electrode 1111 divides the first part A1 into two domain regions, and also divides the second part into Two domain regions form 4 domain regions, and branch electrodes 113 are provided in each of the above 4 domain regions.
  • the peripheral connecting portion A3 includes two strip electrodes extending along the first direction.
  • the two strip electrodes are respectively disposed on both sides of the first portion A1 and the second portion A2, and are located between the main sub-pixel electrode A and the adjacent Between data lines 12.
  • the two ends of the branch electrode 113 can be respectively connected to the first vertical main electrode 1111 and the peripheral connection part A3, of course, it can also only be connected to any one of the first vertical main electrode 1111 and the peripheral connection part A3, which is not limited here. .
  • an accommodating space is formed between the first part A1, the second part A2 and the peripheral connecting part A3, and the sub-pixel electrode B is disposed in the accommodating space.
  • the sub-sub-pixel electrode B includes a second main electrode 112, and the second main electrode 112 also divides the sub-sub-pixel electrode B into a plurality of domain regions.
  • the second stem electrode 112 includes a second vertical stem electrode 1121 extending along a first direction and a horizontal stem electrode 1122 extending perpendicular to the first direction.
  • the second vertical stem electrode 1121 and the horizontal stem electrode are vertically intersecting.
  • the sub-sub-pixel electrode B is divided into four domain regions, and the four domain regions are also provided with branch electrodes 113 respectively, thereby forming a "m"-shaped sub-pixel electrode structure, which is in line with the four domain regions of the main sub-pixel electrode A. Together, the 8-domain structure of the sub-pixel unit 11 is formed.
  • the liquid crystal deflection angle in the domain region of the sub-pixel electrode B is smaller, and the liquid crystal deflection angle in the domain region of the main sub-pixel electrode A is larger and larger, thus forming
  • the multi-viewing angle surrounding structure reduces the difference in birefringence of liquid crystal molecules at different viewing angles, and alleviates the degree of color shift in the case of large viewing angles.
  • the plurality of branch electrodes 113 located in the same domain area are arranged parallel to each other and spaced apart, and the extension directions of the branch electrodes in two adjacent domain areas are different.
  • the branch electrodes 113 in each domain area respectively extend along directions at an angle of 45°, 135°, -135°, and -45° with the first direction.
  • the sub-pixel structure of the display panel provided by the embodiments of the present disclosure is an 8-domain 3T type.
  • the sub-pixel unit 111 includes a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3.
  • the first thin film transistor T1 is connected to the main sub-pixel.
  • the pixel electrode A, the second thin film transistor T2 are connected to the sub-pixel electrode B, and the third thin film transistor T3 is connected to the common electrode C.
  • the gate of the first thin film transistor T1 is connected to the scan line 13, the source is connected to the data line 12, and the drain is connected to the main sub-pixel electrode A through a second via V2 provided between the scan line 13 and the sub-pixel electrode.
  • the gate of the second thin film transistor T2 is connected to the scan line 13, and the source is connected to the data line 12.
  • the drain of the second thin film transistor T2 can only pass through
  • the wiring arranged in the second metal layer extends to the first via hole V1 arranged in the accommodating space to be connected to the sub-pixel electrode B, the gate of the third thin film transistor T3 is connected to the scan line, and the source is connected to the second thin film
  • the drain of the transistor T2 is connected, and the drain is connected to the common electrode C through the deep and shallow holes V3.
  • the first via hole V1 should overlap the second trunk electrode 112, and the wiring connecting the second thin film transistor T2 and the sub-pixel electrode B should overlap the first vertical trunk electrode 1111 and the second vertical trunk electrode 1121 In this way, the non-display portion formed by poor alignment at the position of the second main electrode 112 is used to cover the first via hole V1 and the wiring, so there is no need to separately set the position of the opening for the first via hole V1, which can improve the The opening area of the pixel unit 11 improves the light transmittance.
  • the first via hole V1 should be provided at the intersection of the second vertical main electrode 1121 and the horizontal main electrode 1122. In this way, the first via hole V1 and the wiring can be best covered, so as to increase the opening area of the sub-pixel unit 11 and increase the light transmittance.
  • the scan line 13 connecting the sub-pixel unit 11 is arranged on the side of the second part A2 away from the first part A1, so that the first via hole V1 and the second via hole V2 are both located near the scan line 13 One side of the pixel electrode, thereby reducing the area occupied by the above-mentioned via hole, so as to increase the opening area of the sub-pixel unit.
  • the conductive channels formed between the source and drain of the first thin film transistor T1 and the second thin film transistor T2 are both U-shaped, and the U-shaped openings are all facing the second portion A2, so that the first thin film transistor
  • the orientations of T1 and the second thin film transistor T2 are the same, which reduces the difficulty of the manufacturing process and facilitates process control.
  • the display panel provided by the embodiments of the present disclosure divides the main sub-pixel electrode into a first part, a second part, and a peripheral connection part connecting the first part and the second part, and disposes the sub-sub-pixel electrode on the display panel.
  • the first part and the second part and the peripheral connecting part form the accommodating space, and the scan line is arranged on the side of the second part away from the first part, so that the main sub-pixel electrode and the sub-sub-pixel electrode are both located on the same side of the scan line, Therefore, it is not necessary to arrange the via holes connecting the main sub-pixel electrode and the sub-sub-pixel electrode on both sides of the scan line respectively, so as to increase the opening area of the sub-pixel unit, thereby improving the light transmittance of the sub-pixel unit.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
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Abstract

一种显示面板，显示面板的主子像素电极（A）分为第一部分（A1）、第二部分（A2）和周边连接部分（A3），并将副子像素电极（B）设置于第一部分（A1）与第二部分（A2）和周边连接部分（A3）形成的容置空间内，扫描线（13）设置于第二部分（A2）远离第一部分（A1）的一侧，使得主、副子像素电极（A、B）均位于扫描线（13）的同一侧，以此增大子像素单元（11）的开口面积，提高子像素单元（11）的光线穿透率。

Description

显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
对于负型液晶显示面板，液晶分子在不同视野角度下的双折射率的差异较大，导致了大视角情况下产生色偏的问题。
目前，改善由于大视角产生色偏问题的主要方法是8畴显示技术，如图1为本揭示提供的现有技术的3T8畴型像素结构示意图所示，即一个像素结构包括两个子像素：主子像素（main pixel）和副子像素（sub pixel），每个子像素的像素电极ITO都是“米字型”，分成4个显示畴区。8畴显示技术是通过漏电使main pixel电极和sub pixel电极的电压不同，因而产生液晶分子转动角度的差异，促使视角得到改善。
 技术问题
图2为本揭示提供的现有技术的等效电路图，结合图1和图2，扫描线1（Gate）打开两颗薄膜晶体管（T1和T2），数据线2（Data）的信号分别通过过孔6和过孔7进入main pixel 3和sub pixel 4，并通过T3将sub pixel 4的电压部分利用深浅孔8释放到公共电极5上，以实现main pixel 3和sub pixel 4的电压不同。然而，此像素结构中，扫描线1两侧分别设有过孔6和过孔7，占用了部分像素结构的开口部分，导致光线的穿透率降低，无法满足日益增加的穿透率需求。
综上所述，现有显示面板的像素单元中因扫描线两侧均设有过孔使得像素单元开口率减小，导致光线的穿透率降低。故，有必要提供一种显示面板来改善这一缺陷。
 技术解决方案
本揭示实施例提供一种显示面板，用于解决现有显示面板的像素单元中因扫描线两侧均设有过孔使得像素单元开口率减小，导致光线的穿透率降低的问题。
本揭示实施例提供一种显示面板，包括第一基板，所述第一基板上设有阵列排布的多个子像素单元以及多条沿第一方向延伸的数据线和多条沿垂直于所述第一方向延伸的扫描线；
所述子像素单元包括子像素电极以及多个薄膜晶体管，所述子像素电极包括主子像素电极和副子像素电极，所述主子像素电极包括第一部分、第二部分和连接所述第一部分和所述第二部分的周边连接部分，所述第一部分与所述第二部分以及所述周边连接部分之间形成一容置空间，所述副子像素电极设置于所述容置空间内，连接所述子像素单元的所述扫描线设置于所述第二部分远离所述第一部分的一侧。
根据本揭示一实施例，所述主子像素电极包括第一主干电极，所述副子像素电极包括第二主干电极，所述第一主干电极和所述第二主干电极分别将所述主子像素电极和所述副子像素电极划分成多个畴区。
根据本揭示一实施例，所述第一主干电极仅包括沿所述第一方向延伸的竖直主干电极，所述竖直主干电极将所述主子像素电极划分成多个畴区。
根据本揭示一实施例，所述子像素电极还包括多个位于所述畴区内的分支电极，位于同一所述畴区内的多个所述分支电极之间相互平行且间隔设置，相邻两个所述畴区内的所述分支电极的延伸方向不同。
根据本揭示一实施例，多个所述薄膜晶体管的其中之一通过所述第一过孔与所述副子像素电极连接，所述第一过孔设置于所述容置空间内，并与所述第二主干电极重叠。
根据本揭示一实施例，所述第二主干电极包括沿所述第一方向延伸的竖直主干电极和沿垂直于所述第一方向延伸的水平主干电极，所述第一过孔设置于所述竖直主干电极与所述水平主干电极相交处。
根据本揭示一实施例，多个所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管与所述主子像素电极连接，所述第二薄膜晶体管连接所述副子像素电极。
根据本揭示一实施例，所述第一基板上还设有公共电极，多个所述薄膜晶体管还包括第三薄膜晶体管，所述第三薄膜晶体管的栅极连接所述扫描线，所述第三薄膜晶体管的源极和漏极分别连接所述第二薄膜晶体管和所述公共电极。
根据本揭示一实施例，所述公共电极与所述扫描线设置于同一层。
根据本揭示一实施例，所述周边连接部分包括两条沿所述第一方向延伸的条状电极，两条所述条状电极分别设置于所述主子像素电极两侧。
本揭示实施例还提供一种显示面板，包括第一基板，所述第一基板上设有阵列排布的多个子像素单元以及多条沿第一方向延伸的数据线和多条沿垂直于所述第一方向延伸的扫描线；
所述子像素单元包括子像素电极以及多个薄膜晶体管，所述子像素电极包括主子像素电极、副子像素电极以及多个分支电极，所述主子像素电极包括第一部分、第二部分和连接所述第一部分和所述第二部分的周边连接部分，所述第一部分与所述第二部分以及所述周边连接部分之间形成一容置空间，所述副子像素电极设置于所述容置空间内，连接所述子像素单元的所述扫描线设置于所述第二部分远离所述第一部分的一侧；
所述主子像素电极包括第一主干电极，所述副子像素电极包括第二主干电极，所述第一主干电极和所述第二主干电极分别将所述主子像素电极和所述副子像素电极划分成多个畴区，所述分支电极分别位于所述畴区内，位于同一所述畴区内的多个所述分支电极之间相互平行且间隔设置，相邻两个所述畴区内的所述分支电极的延伸方向不同。
根据本揭示一实施例，所述第一主干电极仅包括沿所述第一方向延伸的竖直主干电极，所述竖直主干电极将所述主子像素电极划分成多个畴区。
根据本揭示一实施例，多个所述薄膜晶体管的其中之一通过所述第一过孔与所述副子像素电极连接，所述第一过孔设置于所述容置空间内，并与所述第二主干电极重叠。
根据本揭示一实施例，所述第二主干电极包括沿所述第一方向延伸的竖直主干电极和沿垂直于所述第一方向延伸的水平主干电极，所述第一过孔设置于所述竖直主干电极与所述水平主干电极相交处。
根据本揭示一实施例，多个所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管与所述主子像素电极连接，所述第二薄膜晶体管连接所述副子像素电极。
根据本揭示一实施例，所述第一基板上还设有公共电极，多个所述薄膜晶体管还包括第三薄膜晶体管，所述第三薄膜晶体管的栅极连接所述扫描线，所述第三薄膜晶体管的源极和漏极分别连接所述第二薄膜晶体管和所述公共电极。
根据本揭示一实施例，所述公共电极与所述扫描线设置于同一层。
根据本揭示一实施例，所述周边连接部分包括两条沿所述第一方向延伸的条状电极，两条所述条状电极分别设置于所述主子像素电极两侧。
本揭示实施例还提供一种显示面板，包括第一基板，所述第一基板上设有阵列排布的多个子像素单元以及多条沿第一方向延伸的数据线和多条沿垂直于所述第一方向延伸的扫描线；
所述子像素单元包括子像素电极以及多个薄膜晶体管，所述子像素电极包括主子像素电极、副子像素电极以及多个分支电极，所述主子像素电极包括第一部分、第二部分和连接所述第一部分和所述第二部分的周边连接部分，所述第一部分与所述第二部分以及所述周边连接部分之间形成一容置空间，所述副子像素电极设置于所述容置空间内，连接所述子像素单元的所述扫描线设置于所述第二部分远离所述第一部分的一侧；
所述主子像素电极包括第一主干电极，所述第一主干电极仅包括沿所述第一方向延伸的竖直主干电极，所述副子像素电极包括第二主干电极，所述竖直主干电极和所述第二主干电极分别将所述主子像素电极和所述副子像素电极划分成多个畴区，所述分支电极分别位于所述畴区内，位于同一所述畴区内的多个所述分支电极之间相互平行且间隔设置，相邻两个所述畴区内的所述分支电极的延伸方向不同。
根据本揭示一实施例，多个所述薄膜晶体管的其中之一通过所述第一过孔与所述副子像素电极连接，所述第一过孔设置于所述容置空间内，并与所述第二主干电极重叠。
 有益效果
本揭示实施例的有益效果：本揭示实施例提供的显示面板通过将主子像素电极分为第一部分、第二部分以及连接第一部分和第二部分的周边连接部分，并将副子像素电极设置于第一部分与第二部分以及周边连接部分形成的容置空间内，并将扫描线设置于第二部分远离第一部分的一侧，使得主子像素电极和副子像素电极均位于扫描线的同一侧，因此无需将连接主子像素电极和副子像素电极的过孔分别设置于扫描线两侧，增大子像素单元的开口面积，从而提高子像素单元的光线穿透率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本揭示提供的现有技术的像素结构示意图；
图2为本揭示提供的现有技术的等效电路图；
图3为本揭示实施例提供的像素单元的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本揭示实施例提供一种显示面板，下面结合图3进行详细说明。如图3所示，图3为本揭示实施例提供的像素单元的结构示意图，显示面板包括第一基板，所述第一基板上设有阵列排布的多个子像素单元11以及多条沿第一方向延伸的数据线12以及多条沿垂直于所述第一方向延伸的扫描线13，其中，每一条数据线12连接对应的一列所述子像素单元11，每一条扫描线13连接对应的一行所述子像素单元11。
子像素单元11包括子像素电极以及设置于子像素电极一侧的薄膜晶体管，所述子像素电极包括主子像素电极A和副子像素电极B，所述主子像素电极A包括相对设置的第一部分A1和第二部分A2，以及连接第一部分A1和第二部分A2的周边连接部分A3。
如图3所示，主子像素电极A包括第一主干电极111，且第一部分A1和第二部分A2内均设有所述第一主干电极111，第一主干电极111分别将第一部分A1和第二部分A2划分成多个畴区，每一畴区内均设有分支电极113。
具体地，第一主干电极111仅包括沿第一方向延伸的第一竖直主干电极1111，第一竖直主干电极1111将第一部分A1划分成两个畴区，同样也将第二部分划分成两个畴区，从而形成4个畴区，上述4个畴区内均设有分支电极113。
周边连接部分A3包括两条沿所述第一方向延伸的条状电极，两条所述条状电极分别设置于第一部分A1和第二部分A2的两侧，并且位于主子像素电极A与相邻数据线12之间。分支电极113的两端可分别连接第一竖直主干电极1111和周边连接部分A3，当然也可以只连接第一竖直主干电极1111和周边连接部分A3中的其中任意一个，此处不做限制。
如图3所示，第一部分A1与第二部分A2以及周边连接部分A3之间形成一容置空间，副子像素电极B设置于所述容置空间内。副子像素电极B包括第二主干电极112，第二主干电极112同样将副子像素电极B划分成多个畴区。
具体地，第二主干电极112包括沿第一方向延伸的第二竖直主干电极1121和沿垂直于第一方向延伸的水平主干电极1122，第二竖直主干电极1121和水平主干电极垂直交叉设置，将副子像素电极B划分成4个畴区，4个畴区内同样分别设有分支电极113，从而形成“米”字型的子像素电极结构，与主子像素电极A的四个畴区共同构成子像素单元11的8畴结构。在显示面板的显示过程中，在一定的灰阶电压下，副子像素电极B的畴区内的液晶偏转角度较小，主子像素电极A的畴区内的液晶偏转较大较大，从而形成多视角包围结构，减小液晶分子在不同视野角度下的双折射率的差异，缓解在大视角情况下产生色偏的程度。
进一步的，位于同一所述畴区内的多个分支113电极之间相互平行且间隔设置，相邻两个所述畴区内的所述分支电极的延伸方向不同。
优选的，各个畴区内的分支电极113分别沿与第一方向呈45°、135°、-135°及-45°夹角的方向延伸。
本揭示实施例提供的显示面板的子像素结构为8畴3T型，子像素单元111包括第一薄膜晶体管T1、第二薄膜晶体管T2以及第三薄膜晶体管T3，其中，第一薄膜晶体管T1连接主子像素电极A，第二薄膜晶体管T2连接副子像素电极B，第三薄膜晶体管T3连接公共电极C。
具体地，第一薄膜晶体管T1的栅极连接扫描线13，源极连接数据线12，漏极通过设置于扫描线13与子像素电极之间的第二过孔V2与主子像素电极A连接。第二薄膜晶体管T2的栅极连接扫描线13，源极连接数据线12，由于副子像素电极B设置于第一部分A1与第二部分A2之间，第二薄膜晶体管T2的漏极只能通过设置于第二金属层中的走线延伸至设置于容置空间内的第一过孔V1与副子像素电极B连接，第三薄膜晶体管T3的栅极连接扫描线，源极与第二薄膜晶体管T2的漏极连接，漏极通过深浅孔V3与公共电极C连接。
进一步的，第一过孔V1应与第二主干电极112重叠，连接第二薄膜晶体管T2与副子像素电极B的走线应与第一竖直主干电极1111和第二竖直主干电极1121重合，以此利用第二主干电极112所处位置由于配向不良形成的非显示部分掩盖所述第一过孔V1以及走线，因此无需为第一过孔V1单独设置开孔的位置，可提高子像素单元11的开口面积，提升光线的透过率。
优选的，第一过孔V1应设置于第二竖直主干电极1121与水平主干电极1122的相交处。如此，可使得第一过孔V1和走线得到最好的掩盖，以便于提高子像素单元11的开口面积，提升光线的透过率。
如图3所示，连接所述子像素单元11的扫描线13设置于第二部分A2远离第一部分A1的一侧，使得第一过孔V1和第二过孔V2均位于扫描线13靠近子像素电极的一侧，以此减小上述过孔所占用的面积，以提高子像素单元的开口面积。此外，第一薄膜晶体管T1和第二薄膜晶体管T2的源极和漏极之间形成的导电沟道均为U型，且U型的开口均朝向第二部分A2，以此使得第一薄膜晶体管T1和第二薄膜晶体管T2的朝向一直，降低制作工艺的难度，有利于工艺的管控。
本揭示实施例的有益效果：本揭示实施例提供的显示面板通过将主子像素电极分为第一部分、第二部分以及连接第一部分和第二部分的周边连接部分，并将副子像素电极设置于第一部分与第二部分以及周边连接部分形成的容置空间内，并将扫描线设置于第二部分远离第一部分的一侧，使得主子像素电极和副子像素电极均位于扫描线的同一侧，因此无需将连接主子像素电极和副子像素电极的过孔分别设置于扫描线两侧，增大子像素单元的开口面积，从而提高子像素单元的光线穿透率。
综上所述，虽然本揭示以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种显示面板，包括第一基板，所述第一基板上设有阵列排布的多个子像素单元以及多条沿第一方向延伸的数据线和多条沿垂直于所述第一方向延伸的扫描线；
    所述子像素单元包括子像素电极以及多个薄膜晶体管，所述子像素电极包括主子像素电极和副子像素电极，所述主子像素电极包括第一部分、第二部分和连接所述第一部分和所述第二部分的周边连接部分，所述第一部分与所述第二部分以及所述周边连接部分之间形成一容置空间，所述副子像素电极设置于所述容置空间内，连接所述子像素单元的所述扫描线设置于所述第二部分远离所述第一部分的一侧。
  2. 如权利要求1所述的显示面板，其中，所述主子像素电极包括第一主干电极，所述副子像素电极包括第二主干电极，所述第一主干电极和所述第二主干电极分别将所述主子像素电极和所述副子像素电极划分成多个畴区。
  3. 如权利要求2所述的显示面板，其中，所述第一主干电极仅包括沿所述第一方向延伸的竖直主干电极，所述竖直主干电极将所述主子像素电极划分成多个畴区。
  4. 如权利要求2所述的显示面板，其中，所述子像素电极还包括多个位于所述畴区内的分支电极，位于同一所述畴区内的多个所述分支电极之间相互平行且间隔设置，相邻两个所述畴区内的所述分支电极的延伸方向不同。
  5. 如权利要求2所述的显示面板，其中，多个所述薄膜晶体管的其中之一通过所述第一过孔与所述副子像素电极连接，所述第一过孔设置于所述容置空间内，并与所述第二主干电极重叠。
  6. 如权利要求5所述的显示面板，其中，所述第二主干电极包括沿所述第一方向延伸的竖直主干电极和沿垂直于所述第一方向延伸的水平主干电极，所述第一过孔设置于所述竖直主干电极与所述水平主干电极相交处。
  7. 如权利要求6所述的显示面板，其中，多个所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管与所述主子像素电极连接，所述第二薄膜晶体管连接所述副子像素电极。
  8. 如权利要求7所述的显示面板，其中，所述第一基板上还设有公共电极，多个所述薄膜晶体管还包括第三薄膜晶体管，所述第三薄膜晶体管的栅极连接所述扫描线，所述第三薄膜晶体管的源极和漏极分别连接所述第二薄膜晶体管和所述公共电极。
  9. 如权利要求8所述的显示面板，其中，所述公共电极与所述扫描线设置于同一层。
  10. 如权利要求9所述的显示面板，其中，所述周边连接部分包括两条沿所述第一方向延伸的条状电极，两条所述条状电极分别设置于所述主子像素电极两侧。
  11. 一种显示面板，包括第一基板，所述第一基板上设有阵列排布的多个子像素单元以及多条沿第一方向延伸的数据线和多条沿垂直于所述第一方向延伸的扫描线；
    所述子像素单元包括子像素电极以及多个薄膜晶体管，所述子像素电极包括主子像素电极、副子像素电极以及多个分支电极，所述主子像素电极包括第一部分、第二部分和连接所述第一部分和所述第二部分的周边连接部分，所述第一部分与所述第二部分以及所述周边连接部分之间形成一容置空间，所述副子像素电极设置于所述容置空间内，连接所述子像素单元的所述扫描线设置于所述第二部分远离所述第一部分的一侧；
    所述主子像素电极包括第一主干电极，所述副子像素电极包括第二主干电极，所述第一主干电极和所述第二主干电极分别将所述主子像素电极和所述副子像素电极划分成多个畴区，所述分支电极分别位于所述畴区内，位于同一所述畴区内的多个所述分支电极之间相互平行且间隔设置，相邻两个所述畴区内的所述分支电极的延伸方向不同。
  12. 如权利要求11所述的显示面板，其中，所述第一主干电极仅包括沿所述第一方向延伸的竖直主干电极，所述竖直主干电极将所述主子像素电极划分成多个畴区。
  13. 如权利要求11所述的显示面板，其中，多个所述薄膜晶体管的其中之一通过所述第一过孔与所述副子像素电极连接，所述第一过孔设置于所述容置空间内，并与所述第二主干电极重叠。
  14. 如权利要求13所述的显示面板，其中，所述第二主干电极包括沿所述第一方向延伸的竖直主干电极和沿垂直于所述第一方向延伸的水平主干电极，所述第一过孔设置于所述竖直主干电极与所述水平主干电极相交处。
  15. 如权利要求14所述的显示面板，其中，多个所述薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管与所述主子像素电极连接，所述第二薄膜晶体管连接所述副子像素电极。
  16. 如权利要求15所述的显示面板，其中，所述第一基板上还设有公共电极，多个所述薄膜晶体管还包括第三薄膜晶体管，所述第三薄膜晶体管的栅极连接所述扫描线，所述第三薄膜晶体管的源极和漏极分别连接所述第二薄膜晶体管和所述公共电极。
  17. 如权利要求16所述的显示面板，其中，所述公共电极与所述扫描线设置于同一层。
  18. 如权利要求17所述的显示面板，其中，所述周边连接部分包括两条沿所述第一方向延伸的条状电极，两条所述条状电极分别设置于所述主子像素电极两侧。
  19. 一种显示面板，包括第一基板，所述第一基板上设有阵列排布的多个子像素单元以及多条沿第一方向延伸的数据线和多条沿垂直于所述第一方向延伸的扫描线；
    所述子像素单元包括子像素电极以及多个薄膜晶体管，所述子像素电极包括主子像素电极、副子像素电极以及多个分支电极，所述主子像素电极包括第一部分、第二部分和连接所述第一部分和所述第二部分的周边连接部分，所述第一部分与所述第二部分以及所述周边连接部分之间形成一容置空间，所述副子像素电极设置于所述容置空间内，连接所述子像素单元的所述扫描线设置于所述第二部分远离所述第一部分的一侧；
    所述主子像素电极包括第一主干电极，所述第一主干电极仅包括沿所述第一方向延伸的竖直主干电极，所述副子像素电极包括第二主干电极，所述竖直主干电极和所述第二主干电极分别将所述主子像素电极和所述副子像素电极划分成多个畴区，所述分支电极分别位于所述畴区内，位于同一所述畴区内的多个所述分支电极之间相互平行且间隔设置，相邻两个所述畴区内的所述分支电极的延伸方向不同。
  20. 如权利要求19所述的显示面板，其中，多个所述薄膜晶体管的其中之一通过所述第一过孔与所述副子像素电极连接，所述第一过孔设置于所述容置空间内，并与所述第二主干电极重叠。
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Publication number Priority date Publication date Assignee Title
CN112859403A (zh) 2021-03-01 2021-05-28 Tcl华星光电技术有限公司 液晶显示面板
CN113589601B (zh) * 2021-07-09 2022-10-04 Tcl华星光电技术有限公司 显示面板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110096282A1 (en) * 2009-10-28 2011-04-28 Samsung Electronics Co., Ltd. Liquid crystal display
CN102236211A (zh) * 2010-04-22 2011-11-09 三星电子株式会社 液晶显示器
CN204406004U (zh) * 2015-03-06 2015-06-17 京东方科技集团股份有限公司 阵列基板和显示装置
CN107589602A (zh) * 2017-10-17 2018-01-16 深圳市华星光电半导体显示技术有限公司 一种具有新型像素设计的液晶显示面板
CN207020431U (zh) * 2017-10-17 2018-02-16 深圳市华星光电半导体显示技术有限公司 一种具有新型像素设计的液晶显示面板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090103461A (ko) * 2008-03-28 2009-10-01 삼성전자주식회사 액정 표시 장치
CN104280965A (zh) * 2014-10-29 2015-01-14 深圳市华星光电技术有限公司 显示面板及其中像素结构和驱动方法
CN104698643A (zh) * 2015-03-23 2015-06-10 深圳市华星光电技术有限公司 电容分压式低色偏像素电路
CN106773404B (zh) * 2016-12-29 2020-09-08 深圳市华星光电技术有限公司 广视角像素结构及阵列基板
CN106950768B (zh) * 2017-03-03 2019-12-24 深圳市华星光电技术有限公司 像素单元及其驱动方法
CN107015403B (zh) * 2017-04-05 2019-05-31 深圳市华星光电半导体显示技术有限公司 阵列基板
CN107515499B (zh) * 2017-09-20 2021-01-12 Tcl华星光电技术有限公司 液晶显示面板
CN109164623A (zh) * 2018-09-21 2019-01-08 深圳市华星光电技术有限公司 一种阵列基板、显示面板及显示装置
CN109725470B (zh) * 2018-12-25 2021-02-26 惠科股份有限公司 显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110096282A1 (en) * 2009-10-28 2011-04-28 Samsung Electronics Co., Ltd. Liquid crystal display
CN102236211A (zh) * 2010-04-22 2011-11-09 三星电子株式会社 液晶显示器
CN204406004U (zh) * 2015-03-06 2015-06-17 京东方科技集团股份有限公司 阵列基板和显示装置
CN107589602A (zh) * 2017-10-17 2018-01-16 深圳市华星光电半导体显示技术有限公司 一种具有新型像素设计的液晶显示面板
CN207020431U (zh) * 2017-10-17 2018-02-16 深圳市华星光电半导体显示技术有限公司 一种具有新型像素设计的液晶显示面板

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