WO2021169082A1

WO2021169082A1 - Chip and capacitive isolation circuit

Info

Publication number: WO2021169082A1
Application number: PCT/CN2020/094885
Authority: WO
Inventors: 应峰
Original assignee: 思瑞浦微电子科技（苏州）股份有限公司
Priority date: 2020-02-28
Filing date: 2020-06-08
Publication date: 2021-09-02
Also published as: CN111181547A

Abstract

A chip and a capacitive isolation circuit. The isolation circuit comprises: a first chip (10) comprising several signal sending units and/or signal receiving units and several clock generating units and/or clock receiving units; a second chip (20) comprising several signal receiving units and/or signal sending units and several clock receiving units and/or clock generating units; and several isolation capacitors (32) located between the signal sending units and the signal receiving units and the clock generating units and the clock receiving units of the first chip (10) and the second chip (20), the clock generating units and the clock receiving units being used for generating or receiving clock signals to modulate or demodulate the signals transmitted in the signal paths of the first chip (10) and the second chip (20). A signal is modulated by using a clock, and the signal transmitted between chips is a modulated signal, which has a strong ability to suppress common-mode disturbance; the number of isolation capacitors is reduced, thereby greatly reducing the costs of a circuit.

Description

Chip and capacitive isolation circuit

Technical field

The invention belongs to the technical field of isolation circuits, and specifically relates to a chip and a capacitive isolation circuit.

Background technique

The isolation circuit is used for signal transmission between two circuits. The two circuits are in different voltage domains, and the voltage difference between the two can reach several thousand volts, so there can be no direct current path between them. Capacitors are widely used to isolate DC signals and allow AC signals to pass through. Therefore, capacitive isolation circuits are an important realization method for isolation circuits. But if the voltage to be isolated is very high, such as several thousand volts, then the production cost of the isolation capacitor is very high, accounting for the main cost of the entire circuit.

1 shows a schematic diagram of a capacitive isolation circuit in the prior art, which includes a signal sending unit 11', a signal receiving unit 21', and an isolation capacitor located between the signal sending unit 11' and the signal receiving unit 21' 31'. Its working principle is as follows:

The signal sending unit 11' sends a square wave signal to the isolation capacitor 31';

Due to the DC isolation characteristics of the isolation capacitor 31', after passing the isolation capacitor 31', the signal becomes two pulse signals up and down, corresponding to the rising edge and the falling edge of the square wave signal respectively;

The signal receiving unit 21' restores the pulse signal to a square wave signal, thereby realizing the transmission of the square wave signal from the signal sending unit 11' to the signal receiving unit 21'.

The disadvantage of this capacitive isolation circuit is its weak anti-common-mode interference capability.

2 shows a schematic diagram of another capacitive isolation circuit in the prior art, which includes a signal sending unit 11', a signal receiving unit 21', and an isolation between the signal sending unit 11' and the signal receiving unit 21' The capacitors 31' and 32' each have a pair of isolation capacitors on each signal path. Its working principle is as follows:

The signal sending unit 11' modulates the signal into a differential high frequency AC signal and sends it to the pair of isolation capacitors 31' and 32';

Since the signal has been modulated into a high-frequency AC signal, it can be transmitted to the signal receiving unit 21' through the isolation capacitor;

The signal receiving unit 21' restores the differential modulation signal to a square wave signal, thereby realizing the transmission of the square wave signal from the signal sending unit 11' to the signal receiving unit 21'.

The disadvantages of this capacitive isolation circuit are:

Since the signal is a differential signal, it has a strong ability to suppress common mode interference;

Each signal path requires a pair of independent isolation capacitors. As shown in Figure 3, when there are 4 signal paths, 8 independent isolation capacitors are required, and the circuit cost is significantly higher.

Therefore, in view of the above technical problems, it is necessary to provide a chip and a capacitive isolation circuit.

Summary of the invention

The purpose of the present invention is to provide a chip and a capacitive isolation circuit to improve the suppression ability of common mode disturbances.

In order to achieve the foregoing objective, the technical solution provided by an embodiment of the present invention is as follows:

A chip comprising a number of signal sending units and/or signal receiving units, and a number of clock generating units and/or clock receiving units, the chip forming a signal path through the signal sending unit and/or signal receiving unit and an external circuit , The clock generating unit and the clock receiving unit are used to generate or receive a clock signal to modulate or demodulate the signal transmitted in the signal path.

In an embodiment, the chip includes a number of signal sending units and a clock generating unit, and the clock generating unit is used to generate a clock signal to modulate the signal transmitted in the signal path.

In an embodiment, the chip includes a plurality of signal receiving units and a clock receiving unit, and the clock receiving unit is configured to receive a clock signal to demodulate the signal transmitted in the signal path.

The technical solution provided by an embodiment of the present invention is as follows:

A capacitive isolation circuit, the isolation circuit comprising:

The first chip includes several signal sending units and/or signal receiving units, and several clock generating units and/or clock receiving units;

The second chip includes several signal receiving units and/or signal sending units, and several clock receiving units and/or clock generating units;

A number of isolation capacitors are located between the signal sending unit and the signal receiving unit, and the clock generating unit and the clock receiving unit of the first chip and the second chip;

Wherein, a signal path is formed between the first chip and the second chip through a signal sending unit and a signal receiving unit. The clock generating unit and the clock receiving unit are used to generate or receive a clock signal to modulate or demodulate the first chip and the second chip. The signal transmitted in the signal path of the chip.

In an embodiment, the isolation circuit includes:

The first chip includes a plurality of first signal sending units and first clock generating units;

The second chip includes a number of second signal receiving units and second clock receiving units. The first signal sending unit and the second signal receiving unit constitute a first signal path;

A number of isolation capacitors are located between the first signal sending unit and the second signal receiving unit, and between the first clock generating unit and the second clock receiving unit. The first clock generating unit is used to generate a clock signal to modulate the transmission in the first signal path. Signal, the second clock receiving unit is used to receive the clock signal to demodulate the signal transmitted in the first signal path.

In an embodiment, in the isolation circuit:

The first chip also includes a number of first signal receiving units;

The second chip also includes a number of second signal sending units, and the first signal receiving unit and the second signal sending unit constitute a second signal path;

The isolation capacitor is also located between the first signal receiving unit and the second signal sending unit. The first clock generating unit is also used to generate a clock signal to demodulate the signal transmitted in the second signal path, and the second clock receiving unit is also used to receive The clock signal modulates the signal transmitted in the second signal path.

In an embodiment, in the isolation circuit:

The first chip also includes a number of first signal receiving units and first clock receiving units;

The second chip also includes a number of second signal sending units and second clock generating units, and the first signal receiving unit and the second signal sending unit constitute a second signal path;

The isolation capacitor is also located between the first signal receiving unit and the second signal sending unit. The second clock generating unit is used to generate a clock signal to modulate the signal transmitted in the second signal path, and the second clock receiving unit is used to receive the clock signal to modulate the signal transmitted in the second signal path. Demodulate the signal transmitted in the second signal path.

In an embodiment, the isolation circuit includes N+1 isolation capacitors, and N is the number of signal paths between the first chip and the second chip.

In an embodiment, the isolation circuit includes N+2 isolation capacitors, and N is the number of signal paths between the first chip and the second chip.

In an embodiment, the isolation capacitor is a single capacitor or is composed of multiple capacitors in series.

Compared with the prior art, the present invention has the following advantages:

The present invention uses a clock to modulate the signal, and the signal transmitted between the chips is a modulated signal, which has a strong ability to suppress common mode disturbances;

The invention reduces the number of isolation capacitors and greatly reduces the circuit cost.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a schematic diagram of a capacitive isolation circuit in the prior art;

Fig. 2 is a schematic diagram of a capacitive isolation circuit in another prior art;

FIG. 3 is a schematic diagram of still another capacitive isolation circuit in the prior art;

4 is a schematic diagram of a capacitive isolation circuit in the first embodiment of the present invention;

5 is a schematic diagram of a capacitive isolation circuit in a second embodiment of the invention;

6 is a schematic diagram of a capacitive isolation circuit in the third embodiment of the present invention;

Fig. 7 is a schematic diagram of a capacitive isolation circuit in a fourth embodiment of the present invention;

Fig. 8 is a timing diagram of signal modulation using OOK and PSK modulation methods for the clock in the present invention.

Detailed ways

Hereinafter, the present invention will be described in detail with reference to the embodiments shown in the drawings. However, these embodiments do not limit the present invention, and the structural, method, or functional changes made by those skilled in the art based on these embodiments are all included in the protection scope of the present invention.

The invention discloses a chip. The chip includes a number of signal sending units and/or signal receiving units, and a number of clock generating units and/or clock receiving units. The chip forms a signal through the signal sending unit and/or signal receiving unit and an external circuit. The channel, the clock generating unit and the clock receiving unit are used to generate or receive a clock signal to modulate or demodulate the signal transmitted in the signal channel.

The invention also discloses a capacitive isolation circuit, which includes:

Among them, a signal path is formed between the first chip and the second chip through a signal sending unit and a signal receiving unit. The clock generating unit and the clock receiving unit are used to generate or receive clock signals to modulate or demodulate the signals of the first chip and the second chip. The signal transmitted in the signal path.

The chip and isolation circuit of the present invention will be further described below in conjunction with specific embodiments.

4 shows a schematic diagram of a capacitive isolation circuit in the first embodiment of the present invention. The isolation circuit includes a first chip 10, a second chip 20, and two isolation capacitors. The first chip 10 and the second chip 20 are located separately In different voltage domains, they are separated by isolation capacitors.

Specifically, the first chip 10 in this embodiment includes a first signal sending unit 11 and a first clock generating unit 12, and the second chip 20 includes a second signal receiving unit 21 and a second clock receiving unit 22.

The first signal sending unit 11 and the second signal receiving unit 21 are separated by an isolation capacitor 31, the first clock generating unit 12 and the second clock receiving unit 22 are separated by an isolation capacitor 32, and the first signal sending unit 11 It forms a first signal path with the second signal receiving unit 21, and the first signal path is a path for signal transmission from the first chip to the second chip.

Among them, the first clock generating unit 12 is used to generate a clock signal, the generated clock signal is used to modulate the signal sent by the first signal sending unit 11, the second clock receiving unit 22 is used to receive a clock signal, and the received clock signal is used for decoding. The signal received by the second signal receiving unit 21 is adjusted.

As shown in Figure 8, the clock signal in this embodiment can be used to modulate the signal using OOK (On-Off Keying, On-Off Keying) modulation, or PSK (Phase Shift Keying) and other modulation methods. The clock demodulation is sufficient, and the specific modulation method belongs to the prior art, and will not be repeated here. In addition, the clock signal shown in FIG. 8 is only a preferred clock signal in this embodiment, and other forms of clock signals may also be used in other embodiments, which will not be illustrated here.

It should be understood that the isolation capacitor must be able to withstand the maximum voltage difference between the chips on both sides. If it cannot withstand it, two or more capacitors can be used in series to achieve this without affecting the analysis of signal transmission.

In this embodiment, the signal transmitted between the chips is a modulated signal, which has a strong ability to suppress common mode disturbances.

In addition, each signal path only needs to have an independent isolation capacitor, and there is an independent isolation capacitor between the clock generating unit and the clock receiving unit, so the entire circuit only needs N+1 isolation capacitors, and N is the number of signal paths (this In the embodiment, N=1). Compared with the prior art, the number of isolation capacitors is reduced, and the circuit cost also has obvious advantages.

5 shows a schematic diagram of a capacitive isolation circuit in a second embodiment of the present invention. The isolation circuit includes a first chip 10, a second chip 20, and three isolation capacitors. The first chip 10 and the second chip 20 are located separately In different voltage domains, they are separated by isolation capacitors.

Specifically, the first chip 10 in this embodiment includes a first signal sending unit 11, a first clock generating unit 12, and a first signal receiving unit 13, and the second chip 20 includes a second signal receiving unit 21, A second clock receiving unit 22 and a second signal sending unit 23.

The first signal sending unit 11 and the second signal receiving unit 21 are separated by an isolation capacitor 31, the first clock generating unit 12 and the second clock receiving unit 22 are separated by an isolation capacitor 32, and the first signal receiving unit 13 It is separated from the second signal sending unit 23 by an isolation capacitor 33, the first signal sending unit 11 and the second signal receiving unit 21 constitute a first signal path, and the first signal receiving unit 13 and the second signal sending unit 23 constitute A second signal path, the first signal path is a path for signal transmission from the first chip to the second chip, and the second signal path is a path for signal transmission from the second chip to the first chip.

Among them, the first clock generating unit 12 is used to generate a clock signal, the generated clock signal is used to modulate the signal sent by the first signal sending unit 11, the second clock receiving unit 22 is used to receive a clock signal, and the received clock signal is used for decoding. The signal received by the second signal receiving unit 21 is adjusted. In addition, the clock signal received by the second clock receiving unit 22 is also used to modulate the signal sent by the second signal sending unit 23, and the clock signal generated by the first clock generating unit 12 is also used to demodulate the signal received by the first signal receiving unit 13 .

Similarly, the way in which the clock signal modulates the signal in this embodiment can adopt OOK (On-Off Keying, On-Off Keying) modulation, or PSK (Phase Shift Keying) and other modulation methods, which only need to be decoded by clock. Just adjust, and the specific modulation method belongs to the prior art, and will not be repeated here.

In addition, each signal path only needs to have an independent isolation capacitor, and there is an independent isolation capacitor between the clock generating unit and the clock receiving unit, so the entire circuit only needs N+1 isolation capacitors, and N is the number of signal paths (this In the embodiment, N=2). Compared with the prior art, the number of isolation capacitors is reduced, and the circuit cost also has obvious advantages.

6 shows a schematic diagram of a capacitive isolation circuit in a third embodiment of the present invention. The isolation circuit includes a first chip 10, a second chip 20, and five isolation capacitors. The first chip 10 and the second chip 20 are located separately In different voltage domains, they are separated by isolation capacitors.

Specifically, the first chip 10 in this embodiment includes two first signal sending units 11, a first clock generating unit 12, and two first signal receiving units 13, and the second chip 20 includes two second signal receiving units. Unit 21, a second clock receiving unit 22 and two second signal sending units 23.

The first signal sending unit 11 and the second signal receiving unit 21 are separated by an isolation capacitor 31, the first clock generating unit 12 and the second clock receiving unit 22 are separated by an isolation capacitor 32, and the first signal receiving unit 13 It is separated from the second signal sending unit 23 by an isolation capacitor 33, the first signal sending unit 11 and the second signal receiving unit 21 constitute two first signal paths, the first signal receiving unit 13 and the second signal sending unit 23 Two second signal paths are formed, the first signal path is a path for signal transmission from the first chip to the second chip, and the second signal path is a path for signal transmission from the second chip to the first chip.

The process of modulating or demodulating the signal by the first clock generating unit 12 and the second clock receiving unit 22 in this embodiment is the same as that in the second embodiment, and will not be repeated here.

In addition, each signal path only needs to have an independent isolation capacitor, and there is an independent isolation capacitor between the clock generating unit and the clock receiving unit, so the entire circuit only needs N+1 isolation capacitors, and N is the number of signal paths (this In the embodiment, N=4). Compared with the prior art, the number of isolation capacitors is reduced, and the circuit cost also has obvious advantages.

7 is a schematic diagram of a capacitive isolation circuit in a fourth embodiment of the present invention. The isolation circuit includes a first chip 10, a second chip 20, and six isolation capacitors. The first chip 10 and the second chip 20 are located separately In different voltage domains, they are separated by isolation capacitors.

Specifically, the first chip 10 in this embodiment includes two first signal sending units 11, a first clock generating unit 12, two first signal receiving units 13, and a first clock receiving unit 14. The second chip 20 includes two second signal receiving units 21, one second clock receiving unit 22, two second signal sending units 23, and one second clock generating unit 24.

The first signal sending unit 11 and the second signal receiving unit 21 are separated by an isolation capacitor 31, the first clock generating unit 12 and the second clock receiving unit 22 are separated by an isolation capacitor 32, and the first signal receiving unit 13 It is separated from the second signal sending unit 23 by an isolation capacitor 33, the first clock receiving unit 14 and the second clock generating unit 24 are separated by an isolation capacitor 34, the first signal sending unit 11 and the second signal receiving unit 21 constitutes two first signal paths, the first signal receiving unit 13 and the second signal sending unit 23 constitute two second signal paths, the first signal path is the path for signal transmission from the first chip to the second chip, and the second The signal path is the path through which signals are transmitted from the second chip to the first chip.

Among them, the first clock generating unit 12 is used to generate a clock signal, the generated clock signal is used to modulate the signal sent by the first signal sending unit 11, and the second clock receiving unit 22 is used to receive the clock signal sent by the first clock generating unit 12 , The received clock signal is used to demodulate the signal received by the second signal receiving unit 21; the second clock generating unit 24 is used to generate a clock signal, and the generated clock signal is used to modulate the signal sent by the second signal sending unit 23, the first The clock receiving unit 14 is used for receiving the clock signal sent by the second clock generating unit 24, and the received clock signal is used for demodulating the signal received by the first signal receiving unit 21.

In this embodiment, the process of modulating or demodulating signals by the first clock generating unit 12 and the second clock receiving unit 22, and the second clock generating unit 24 and the first clock receiving unit 14 is the same as that of the second embodiment, here Do not repeat it.

In addition, each signal path only needs an independent isolation capacitor. There is an independent isolation capacitor between the clock generating unit and the clock receiving unit. The first signal path shares a clock, and the second signal path shares a clock. The total circuit is Two clocks are required, so the entire circuit only needs N+2 isolation capacitors, and N is the number of signal paths (N=4 in this embodiment), which reduces the number of isolation capacitors compared with the prior art, and the circuit cost also has obvious advantages.

It should be understood that the number of signal sending units, signal receiving units, clock generating units, and clock receiving units in the isolation circuit and chip of the present invention is not limited to the numbers in the above-mentioned embodiments, and the clock is used to modulate the signal transmitted through the signal path. The technical solutions of demodulation and demodulation all belong to the protection scope of the present invention.

It can be seen from the above technical solutions that the present invention has the following beneficial effects:

For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description, and therefore it is intended to fall within the claims. All changes within the meaning and scope of the equivalent elements of are included in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

In addition, it should be understood that although this specification is described in accordance with the embodiments, not each embodiment only includes an independent technical solution. This narration in the specification is only for clarity, and those skilled in the art should regard the specification as a whole The technical solutions in the various embodiments can also be appropriately combined to form other implementations that can be understood by those skilled in the art.

Claims

A chip, characterized in that the chip includes a number of signal sending units and/or signal receiving units, and a number of clock generating units and/or clock receiving units, and the chip communicates with an external device through the signal sending unit and/or signal receiving unit. The circuit constitutes a signal path, and the clock generating unit and the clock receiving unit are used to generate or receive a clock signal to modulate or demodulate the signal transmitted in the signal path.
The chip according to claim 1, wherein the chip comprises a plurality of signal sending units and a clock generating unit, and the clock generating unit is used to generate a clock signal to modulate the signal transmitted in the signal path.
The chip according to claim 1, wherein the chip includes a plurality of signal receiving units and a clock receiving unit, and the clock receiving unit is used to receive a clock signal to demodulate the signal transmitted in the signal path.
A capacitive isolation circuit, characterized in that the isolation circuit includes:

The first chip includes several signal sending units and/or signal receiving units, and several clock generating units and/or clock receiving units;

The second chip includes several signal receiving units and/or signal sending units, and several clock receiving units and/or clock generating units;

A number of isolation capacitors are located between the signal sending unit and the signal receiving unit, and the clock generating unit and the clock receiving unit of the first chip and the second chip;

Wherein, a signal path is formed between the first chip and the second chip through a signal sending unit and a signal receiving unit. The clock generating unit and the clock receiving unit are used to generate or receive a clock signal to modulate or demodulate the first chip and the second chip. The signal transmitted in the signal path of the chip.
The capacitive isolation circuit according to claim 4, wherein the isolation circuit comprises:

The first chip includes a plurality of first signal sending units and first clock generating units;

The second chip includes a number of second signal receiving units and second clock receiving units. The first signal sending unit and the second signal receiving unit constitute a first signal path;

A number of isolation capacitors are located between the first signal sending unit and the second signal receiving unit, and between the first clock generating unit and the second clock receiving unit. The first clock generating unit is used to generate a clock signal to modulate the transmission in the first signal path. Signal, the second clock receiving unit is used to receive the clock signal to demodulate the signal transmitted in the first signal path.
The capacitive isolation circuit according to claim 5, wherein in the isolation circuit:

The first chip also includes a number of first signal receiving units;

The second chip also includes a number of second signal sending units, and the first signal receiving unit and the second signal sending unit constitute a second signal path;

The isolation capacitor is also located between the first signal receiving unit and the second signal sending unit. The first clock generating unit is also used to generate a clock signal to demodulate the signal transmitted in the second signal path, and the second clock receiving unit is also used to receive The clock signal modulates the signal transmitted in the second signal path.
The capacitive isolation circuit according to claim 5, wherein in the isolation circuit:

The first chip also includes a number of first signal receiving units and first clock receiving units;

The second chip also includes a number of second signal sending units and second clock generating units, and the first signal receiving unit and the second signal sending unit constitute a second signal path;

The isolation capacitor is also located between the first signal receiving unit and the second signal sending unit. The second clock generating unit is used to generate a clock signal to modulate the signal transmitted in the second signal path, and the second clock receiving unit is used to receive the clock signal to modulate the signal transmitted in the second signal path. Demodulate the signal transmitted in the second signal path.
The capacitive isolation circuit according to claim 5 or 6, wherein the isolation circuit includes N+1 isolation capacitors, and N is the number of signal paths between the first chip and the second chip.
7. The capacitive isolation circuit according to claim 7, wherein the isolation circuit includes N+2 isolation capacitors, and N is the number of signal paths between the first chip and the second chip.
The capacitive isolation circuit according to claim 4, wherein the isolation capacitor is a single capacitor or is composed of multiple capacitors in series.