CN111181547A - Chip and capacitive isolation circuit - Google Patents
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- CN111181547A CN111181547A CN202010122355.3A CN202010122355A CN111181547A CN 111181547 A CN111181547 A CN 111181547A CN 202010122355 A CN202010122355 A CN 202010122355A CN 111181547 A CN111181547 A CN 111181547A
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- 238000002955 isolation Methods 0.000 title claims abstract description 125
- 239000003990 capacitor Substances 0.000 claims abstract description 78
- 230000005764 inhibitory process Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Abstract
The invention discloses a chip and a capacitive isolation circuit, wherein the isolation circuit comprises: the first chip comprises a plurality of signal sending units and/or signal receiving units and a plurality of clock generating units and/or clock receiving units; the second chip comprises a plurality of signal receiving units and/or signal sending units and a plurality of clock receiving units and/or clock generating units; the isolation capacitors are positioned between the signal sending units and the signal receiving units of the first chip and the second chip, and between the clock generating unit and the clock receiving unit; the clock generating unit and the clock receiving unit are used for generating or receiving clock signals to modulate or demodulate signals transmitted in signal paths of the first chip and the second chip. The invention adopts the clock to modulate the signal, the signal transmitted between chips is a modulated signal, and the invention has stronger inhibition capability to common mode disturbance; the invention reduces the number of the isolation capacitors and greatly reduces the circuit cost.
Description
Technical Field
The invention belongs to the technical field of isolation circuits, and particularly relates to a chip and a capacitive isolation circuit.
Background
The isolation circuit is used for signal transmission between two circuits which are respectively in different voltage domains, and the voltage difference between the two circuits can reach several kilovolts, so that a direct current path cannot be arranged between the two circuits. Capacitors are widely used to isolate dc signals and allow ac signals to pass through, so capacitive isolation circuits are an important implementation of isolation circuits. However, if the voltage required for isolation is high, for example, several kilovolts, the production cost of the isolation capacitor is high, which accounts for the major cost of the whole circuit.
Referring to fig. 1, a schematic diagram of a prior art capacitive isolation circuit is shown, which includes a signal transmitting unit 11 ', a signal receiving unit 21 ', and an isolation capacitor 31 ' between the signal transmitting unit 11 ' and the signal receiving unit 21 '. The working principle is as follows:
the signal sending unit 11 'sends a square wave signal to the isolation capacitor 31';
due to the direct-current isolation characteristic of the isolation capacitor 31 ', after passing through the isolation capacitor 31', the signal is changed into an upper pulse signal and a lower pulse signal which respectively correspond to the rising edge and the falling edge of the square wave signal;
the signal receiving unit 21 ' restores the pulse signal to a square wave signal, thereby realizing transmission of the square wave signal from the signal transmitting unit 11 ' to the signal receiving unit 21 '.
The capacitive isolation circuit has the disadvantage of poor common mode interference resistance.
Referring to fig. 2, a schematic diagram of another prior art capacitive isolation circuit is shown, which includes a signal transmitting unit 11 ', a signal receiving unit 21', and isolation capacitors 31 'and 32' located between the signal transmitting unit 11 'and the signal receiving unit 21', and a pair of isolation capacitors is respectively disposed on each signal path. The working principle is as follows:
the signal transmitting unit 11 ' modulates the signal into a differential high-frequency alternating-current signal and transmits the signal to the pair of isolation capacitors 31 ' and 32 ';
since the signal has been modulated into a high frequency alternating current signal, it can be transmitted to the signal receiving unit 21' through the isolation capacitor;
the signal receiving unit 21 ' restores the differential modulated signal to a square wave signal, thereby realizing transmission of the square wave signal from the signal transmitting unit 11 ' to the signal receiving unit 21 '.
The disadvantages of the capacitive isolation circuit are:
the signal is a differential signal, so that the signal has stronger inhibition capability on common-mode interference;
each signal path needs to have a pair of independent isolation capacitors, as shown in fig. 3, when there are 4 signal paths, 8 independent isolation capacitors are needed, and the circuit cost is significantly high.
Therefore, in order to solve the above-mentioned problems, it is necessary to provide a chip and a capacitive isolation circuit.
Disclosure of Invention
The invention aims to provide a chip and a capacitive isolation circuit to improve the common mode disturbance rejection capability.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a chip comprises a plurality of signal sending units and/or signal receiving units and a plurality of clock generating units and/or clock receiving units, wherein the chip and an external circuit form a signal path through the signal sending units and/or the signal receiving units, and the clock generating units and the clock receiving units are used for generating or receiving clock signals to modulate or demodulate signals transmitted in the signal path.
In one embodiment, the chip includes a number of signal sending units and a clock generation unit for generating a clock signal to modulate signals transmitted in the signal path.
In one embodiment, the chip includes a plurality of signal receiving units and a clock receiving unit, wherein the clock receiving unit is configured to receive a clock signal to demodulate signals transmitted in the signal path.
The technical scheme provided by one embodiment of the invention is as follows:
a capacitive isolation circuit, the isolation circuit comprising:
the first chip comprises a plurality of signal sending units and/or signal receiving units and a plurality of clock generating units and/or clock receiving units;
the second chip comprises a plurality of signal receiving units and/or signal sending units and a plurality of clock receiving units and/or clock generating units;
the isolation capacitors are positioned between the signal sending units and the signal receiving units of the first chip and the second chip, and between the clock generating unit and the clock receiving unit;
the first chip and the second chip form a signal path through the signal sending unit and the signal receiving unit, and the clock generating unit and the clock receiving unit are used for generating or receiving clock signals to modulate or demodulate signals transmitted in the signal paths of the first chip and the second chip.
In one embodiment, the isolation circuit includes:
the first chip comprises a plurality of first signal sending units and a first clock generating unit;
the second chip comprises a plurality of second signal receiving units and second clock receiving units, and the first signal sending unit and the second signal receiving units form a first signal path;
and the plurality of isolation capacitors are positioned between the first signal sending unit and the second signal receiving unit as well as between the first clock generating unit and the second clock receiving unit, the first clock generating unit is used for generating a clock signal to modulate the signal transmitted in the first signal path, and the second clock receiving unit is used for receiving the clock signal to demodulate the signal transmitted in the first signal path.
In one embodiment, the isolation circuit includes:
the first chip also comprises a plurality of first signal receiving units;
the second chip also comprises a plurality of second signal sending units, and the first signal receiving units and the second signal sending units form a second signal path;
the isolation capacitor is further located between the first signal receiving unit and the second signal transmitting unit, the first clock generating unit is further configured to generate a clock signal to demodulate the signal transmitted in the second signal path, and the second clock receiving unit is further configured to receive the clock signal to modulate the signal transmitted in the second signal path.
In one embodiment, the isolation circuit includes:
the first chip also comprises a plurality of first signal receiving units and a first clock receiving unit;
the second chip also comprises a plurality of second signal sending units and a second clock generating unit, and the first signal receiving unit and the second signal sending units form a second signal path;
the isolation capacitor is also located between the first signal receiving unit and the second signal transmitting unit, the second clock generating unit is used for generating a clock signal to modulate the signal transmitted in the second signal path, and the second clock receiving unit is used for receiving the clock signal to demodulate the signal transmitted in the second signal path.
In one embodiment, the isolation circuit includes N +1 isolation capacitors, where N is the number of signal paths between the first chip and the second chip.
In one embodiment, the isolation circuit includes N +2 isolation capacitors, where N is the number of signal paths between the first chip and the second chip.
In one embodiment, the isolation capacitor is a single capacitor or is formed by connecting a plurality of capacitors in series.
Compared with the prior art, the invention has the following advantages:
the invention adopts the clock to modulate the signal, the signal transmitted between chips is a modulated signal, and the invention has stronger inhibition capability to common mode disturbance;
the invention reduces the number of the isolation capacitors and greatly reduces the circuit cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of a prior art capacitive isolation circuit;
FIG. 2 is a schematic diagram of another prior art capacitive isolation circuit;
FIG. 3 is a schematic diagram of a capacitive isolation circuit according to still another prior art;
FIG. 4 is a schematic diagram of a capacitive isolation circuit according to a first embodiment of the present invention;
FIG. 5 is a schematic diagram of a capacitive isolation circuit according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a capacitive isolation circuit in a third embodiment of the present invention;
FIG. 7 is a schematic diagram of a capacitive isolation circuit in a fourth embodiment of the present invention;
fig. 8 is a timing diagram of the clock modulating the signal by OOK and PSK modulation according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
The invention discloses a chip, which comprises a plurality of signal sending units and/or signal receiving units and a plurality of clock generating units and/or clock receiving units, wherein the chip forms a signal path with an external circuit through the signal sending units and/or the signal receiving units, and the clock generating units and the clock receiving units are used for generating or receiving clock signals to modulate or demodulate signals transmitted in the signal path.
The invention also discloses a capacitive isolation circuit, comprising:
the first chip comprises a plurality of signal sending units and/or signal receiving units and a plurality of clock generating units and/or clock receiving units;
the second chip comprises a plurality of signal receiving units and/or signal sending units and a plurality of clock receiving units and/or clock generating units;
the isolation capacitors are positioned between the signal sending units and the signal receiving units of the first chip and the second chip, and between the clock generating unit and the clock receiving unit;
the first chip and the second chip form a signal path through the signal sending unit and the signal receiving unit, and the clock generating unit and the clock receiving unit are used for generating or receiving clock signals to modulate or demodulate signals transmitted in the signal paths of the first chip and the second chip.
The chip and the isolation circuit of the present invention are further described with reference to the following embodiments.
Referring to fig. 4, a schematic diagram of a capacitive isolation circuit according to a first embodiment of the present invention is shown, the isolation circuit includes a first chip 10, a second chip 20, and two isolation capacitors, the first chip 10 and the second chip 20 are respectively located in different voltage domains, and the two isolation capacitors are separated by the isolation capacitors.
Specifically, the first chip 10 in the present embodiment includes a first signal transmitting unit 11 and a first clock generating unit 12, and the second chip 20 includes a second signal receiving unit 21 and a second clock receiving unit 22.
The first signal transmitting unit 11 and the second signal receiving unit 21 are separated by an isolation capacitor 31, the first clock generating unit 12 and the second clock receiving unit 22 are separated by an isolation capacitor 32, and the first signal transmitting unit 11 and the second signal receiving unit 21 form a first signal path, which is a path through which signals are transmitted from the first chip to the second chip.
The first clock generating unit 12 is configured to generate a clock signal, the generated clock signal is used to modulate the signal transmitted by the first signal transmitting unit 11, the second clock receiving unit 22 is configured to receive the clock signal, and the received clock signal is used to demodulate the signal received by the second signal receiving unit 21.
Referring to fig. 8, in this embodiment, the clock signal may modulate the signal by OOK (On-off keying) modulation or PSK (phase shift keying), which only needs to be demodulated by the clock, and the specific modulation method belongs to the prior art and is not described herein again. In addition, the clock signal shown in fig. 8 is only one preferred clock signal in the present embodiment, and other clock signals may be adopted in other embodiments, which are not illustrated herein.
It should be understood that the isolation capacitor must be able to withstand the maximum voltage difference between the chips on both sides, and if it cannot withstand this, it can be implemented by connecting two or more capacitors in series, without affecting the analysis of the signal transmission.
In the embodiment, the signals transmitted between the chips are modulation signals, and the common-mode disturbance is restrained strongly.
In addition, each signal path only needs to have an independent isolation capacitor, and an independent isolation capacitor is arranged between the clock generation unit and the clock receiving unit, so that the whole circuit only needs N +1 isolation capacitors, and N is the number of the signal paths (in the embodiment, N is 1), thereby reducing the number of the isolation capacitors compared with the prior art, and having obvious advantages in circuit cost.
Referring to fig. 5, a schematic diagram of a capacitive isolation circuit according to a second embodiment of the present invention is shown, the isolation circuit includes a first chip 10, a second chip 20, and three isolation capacitors, the first chip 10 and the second chip 20 are respectively located in different voltage domains, and the two chips are separated by the isolation capacitors.
Specifically, the first chip 10 in this embodiment includes a first signal transmitting unit 11, a first clock generating unit 12, and a first signal receiving unit 13, and the second chip 20 includes a second signal receiving unit 21, a second clock receiving unit 22, and a second signal transmitting unit 23.
The first signal transmitting unit 11 and the second signal receiving unit 21 are separated by an isolation capacitor 31, the first clock generating unit 12 and the second clock receiving unit 22 are separated by an isolation capacitor 32, the first signal receiving unit 13 and the second signal transmitting unit 23 are separated by an isolation capacitor 33, the first signal transmitting unit 11 and the second signal receiving unit 21 form a first signal path, the first signal receiving unit 13 and the second signal transmitting unit 23 form a second signal path, the first signal path is a path for transmitting signals from the first chip to the second chip, and the second signal path is a path for transmitting signals from the second chip to the first chip.
The first clock generating unit 12 is configured to generate a clock signal, the generated clock signal is used to modulate the signal transmitted by the first signal transmitting unit 11, the second clock receiving unit 22 is configured to receive the clock signal, and the received clock signal is used to demodulate the signal received by the second signal receiving unit 21. In addition, the clock signal received by the second clock receiving unit 22 is also used for modulating the signal transmitted by the second signal transmitting unit 23, and the clock signal generated by the first clock generating unit 12 is also used for demodulating the signal received by the first signal receiving unit 13.
Similarly, in this embodiment, the clock signal may modulate the signal by OOK (On-off keying) modulation or PSK (phase shift keying), which only needs to demodulate the clock signal, and the specific modulation method belongs to the prior art and is not described herein again.
It should be understood that the isolation capacitor must be able to withstand the maximum voltage difference between the chips on both sides, and if it cannot withstand this, it can be implemented by connecting two or more capacitors in series, without affecting the analysis of the signal transmission.
In the embodiment, the signals transmitted between the chips are modulation signals, and the common-mode disturbance is restrained strongly.
In addition, each signal path only needs to have an independent isolation capacitor, and an independent isolation capacitor is arranged between the clock generation unit and the clock receiving unit, so that the whole circuit only needs N +1 isolation capacitors, and N is the number of the signal paths (N is 2 in the embodiment), thereby reducing the number of the isolation capacitors compared with the prior art, and having obvious advantages in circuit cost.
Referring to fig. 6, a schematic diagram of a capacitive isolation circuit according to a third embodiment of the present invention is shown, where the isolation circuit includes a first chip 10, a second chip 20, and five isolation capacitors, and the first chip 10 and the second chip 20 are respectively located in different voltage domains, and are separated by the isolation capacitors.
Specifically, the first chip 10 in the present embodiment includes two first signal transmitting units 11, one first clock generating unit 12, and two first signal receiving units 13, and the second chip 20 includes two second signal receiving units 21, one second clock receiving unit 22, and two second signal transmitting units 23.
The first signal transmitting unit 11 and the second signal receiving unit 21 are separated by an isolation capacitor 31, the first clock generating unit 12 and the second clock receiving unit 22 are separated by an isolation capacitor 32, the first signal receiving unit 13 and the second signal transmitting unit 23 are separated by an isolation capacitor 33, the first signal transmitting unit 11 and the second signal receiving unit 21 form two first signal paths, the first signal receiving unit 13 and the second signal transmitting unit 23 form two second signal paths, the first signal path is a path for transmitting signals from the first chip to the second chip, and the second signal path is a path for transmitting signals from the second chip to the first chip.
The process of modulating or demodulating the signal by the first clock generating unit 12 and the second clock receiving unit 22 in this embodiment is the same as that in the second embodiment, and is not repeated here.
In the embodiment, the signals transmitted between the chips are modulation signals, and the common-mode disturbance is restrained strongly.
In addition, each signal path only needs to have an independent isolation capacitor, and an independent isolation capacitor is arranged between the clock generation unit and the clock receiving unit, so that the whole circuit only needs N +1 isolation capacitors, and N is the number of the signal paths (N is 4 in the embodiment), thereby reducing the number of the isolation capacitors compared with the prior art, and having obvious advantages in circuit cost.
Referring to fig. 7, a schematic diagram of a capacitive isolation circuit according to a fourth embodiment of the present invention is shown, the isolation circuit includes a first chip 10, a second chip 20, and six isolation capacitors, the first chip 10 and the second chip 20 are respectively located in different voltage domains, and the two chips are separated by the isolation capacitors.
Specifically, the first chip 10 in the present embodiment includes two first signal transmitting units 11, one first clock generating unit 12, two first signal receiving units 13, and one first clock receiving unit 14, and the second chip 20 includes two second signal receiving units 21, one second clock receiving unit 22, two second signal transmitting units 23, and one second clock generating unit 24.
The first signal transmitting unit 11 and the second signal receiving unit 21 are separated by an isolation capacitor 31, the first clock generating unit 12 and the second clock receiving unit 22 are separated by an isolation capacitor 32, the first signal receiving unit 13 and the second signal transmitting unit 23 are separated by an isolation capacitor 33, the first clock receiving unit 14 and the second clock generating unit 24 are separated by an isolation capacitor 34, the first signal transmitting unit 11 and the second signal receiving unit 21 form two first signal paths, the first signal receiving unit 13 and the second signal transmitting unit 23 form two second signal paths, the first signal path is a path for transmitting signals from the first chip to the second chip, and the second signal path is a path for transmitting signals from the second chip to the first chip.
The first clock generating unit 12 is configured to generate a clock signal, where the generated clock signal is used to modulate the signal sent by the first signal sending unit 11, the second clock receiving unit 22 is configured to receive the clock signal sent by the first clock generating unit 12, and the received clock signal is used to demodulate the signal received by the second signal receiving unit 21; the second clock generating unit 24 is configured to generate a clock signal, the generated clock signal is used to modulate the signal transmitted by the second signal transmitting unit 23, the first clock receiving unit 14 is configured to receive the clock signal transmitted by the second clock generating unit 24, and the received clock signal is used to demodulate the signal received by the first signal receiving unit 21.
The process of modulating or demodulating signals by the first clock generating unit 12 and the second clock receiving unit 22, and the second clock generating unit 24 and the first clock receiving unit 14 in this embodiment is the same as that in the second embodiment, and is not repeated here.
It should be understood that the isolation capacitor must be able to withstand the maximum voltage difference between the chips on both sides, and if it cannot withstand this, it can be implemented by connecting two or more capacitors in series, without affecting the analysis of the signal transmission.
In the embodiment, the signals transmitted between the chips are modulation signals, and the common-mode disturbance is restrained strongly.
In addition, each signal path only needs to have an independent isolation capacitor, an independent isolation capacitor is arranged between the clock generation unit and the clock receiving unit, the first signal path shares one clock, the second signal path shares one clock, and the whole circuit needs two clocks in total, so that the whole circuit only needs N +2 isolation capacitors, N is the number of the signal paths (N is 4 in the embodiment), and compared with the prior art, the number of the isolation capacitors is reduced, and the circuit cost also has obvious advantages.
It should be understood that the numbers of the signal sending units, the signal receiving units, the clock generating units and the clock receiving units in the isolation circuit and the chip of the invention are not limited to the numbers in the above embodiments, and all technical solutions that use a clock to modulate and demodulate signals transmitted by a signal path belong to the protection scope of the invention.
According to the technical scheme, the invention has the following beneficial effects:
the invention adopts the clock to modulate the signal, the signal transmitted between chips is a modulated signal, and the invention has stronger inhibition capability to common mode disturbance;
the invention reduces the number of the isolation capacitors and greatly reduces the circuit cost.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A chip is characterized by comprising a plurality of signal sending units and/or signal receiving units and a plurality of clock generating units and/or clock receiving units, wherein the chip and an external circuit form a signal path through the signal sending units and/or the signal receiving units, and the clock generating units and the clock receiving units are used for generating or receiving clock signals to modulate or demodulate signals transmitted in the signal path.
2. The chip of claim 1, wherein the chip comprises a plurality of signal sending units and a clock generating unit, and the clock generating unit is configured to generate a clock signal to modulate signals transmitted in the signal path.
3. The chip of claim 1, wherein the chip comprises a plurality of signal receiving units and a clock receiving unit, and the clock receiving unit is configured to receive a clock signal to demodulate signals transmitted in the signal path.
4. A capacitive isolation circuit, the isolation circuit comprising:
the first chip comprises a plurality of signal sending units and/or signal receiving units and a plurality of clock generating units and/or clock receiving units;
the second chip comprises a plurality of signal receiving units and/or signal sending units and a plurality of clock receiving units and/or clock generating units;
the isolation capacitors are positioned between the signal sending units and the signal receiving units of the first chip and the second chip, and between the clock generating unit and the clock receiving unit;
the first chip and the second chip form a signal path through the signal sending unit and the signal receiving unit, and the clock generating unit and the clock receiving unit are used for generating or receiving clock signals to modulate or demodulate signals transmitted in the signal paths of the first chip and the second chip.
5. The capacitive isolation circuit of claim 4, wherein the isolation circuit comprises:
the first chip comprises a plurality of first signal sending units and a first clock generating unit;
the second chip comprises a plurality of second signal receiving units and second clock receiving units, and the first signal sending unit and the second signal receiving units form a first signal path;
and the plurality of isolation capacitors are positioned between the first signal sending unit and the second signal receiving unit as well as between the first clock generating unit and the second clock receiving unit, the first clock generating unit is used for generating a clock signal to modulate the signal transmitted in the first signal path, and the second clock receiving unit is used for receiving the clock signal to demodulate the signal transmitted in the first signal path.
6. A capacitive isolation circuit as claimed in claim 5, wherein in the isolation circuit:
the first chip also comprises a plurality of first signal receiving units;
the second chip also comprises a plurality of second signal sending units, and the first signal receiving units and the second signal sending units form a second signal path;
the isolation capacitor is further located between the first signal receiving unit and the second signal transmitting unit, the first clock generating unit is further configured to generate a clock signal to demodulate the signal transmitted in the second signal path, and the second clock receiving unit is further configured to receive the clock signal to modulate the signal transmitted in the second signal path.
7. A capacitive isolation circuit as claimed in claim 5, wherein in the isolation circuit:
the first chip also comprises a plurality of first signal receiving units and a first clock receiving unit;
the second chip also comprises a plurality of second signal sending units and a second clock generating unit, and the first signal receiving unit and the second signal sending units form a second signal path;
the isolation capacitor is also located between the first signal receiving unit and the second signal transmitting unit, the second clock generating unit is used for generating a clock signal to modulate the signal transmitted in the second signal path, and the second clock receiving unit is used for receiving the clock signal to demodulate the signal transmitted in the second signal path.
8. The capacitive isolation circuit of claim 5 or 6, wherein the isolation circuit comprises N +1 isolation capacitors, and N is the number of signal paths between the first chip and the second chip.
9. The capacitive isolation circuit of claim 7, wherein the isolation circuit comprises N +2 isolation capacitors, and N is the number of signal paths between the first chip and the second chip.
10. The capacitive isolation circuit of claim 4 wherein the isolation capacitor is a single capacitor or is comprised of a plurality of capacitors in series.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010122355.3A CN111181547A (en) | 2020-02-28 | 2020-02-28 | Chip and capacitive isolation circuit |
| PCT/CN2020/094885 WO2021169082A1 (en) | 2020-02-28 | 2020-06-08 | Chip and capacitive isolation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010122355.3A CN111181547A (en) | 2020-02-28 | 2020-02-28 | Chip and capacitive isolation circuit |
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| CN111181547A true CN111181547A (en) | 2020-05-19 |
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| CN202010122355.3A Pending CN111181547A (en) | 2020-02-28 | 2020-02-28 | Chip and capacitive isolation circuit |
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| WO (1) | WO2021169082A1 (en) |
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|---|---|---|---|---|
| WO2021169082A1 (en) * | 2020-02-28 | 2021-09-02 | 思瑞浦微电子科技（苏州）股份有限公司 | Chip and capacitive isolation circuit |
| CN112073051A (en) * | 2020-08-27 | 2020-12-11 | 苏州纳芯微电子股份有限公司 | Digital isolation chip |
| CN112073051B (en) * | 2020-08-27 | 2022-03-11 | 苏州纳芯微电子股份有限公司 | Digital isolation chip |
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| Publication number | Publication date |
|---|---|
| WO2021169082A1 (en) | 2021-09-02 |
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Application publication date: 20200519 |