WO2021156700A1 - 半導体装置、及び撮像装置 - Google Patents

半導体装置、及び撮像装置 Download PDF

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Publication number
WO2021156700A1
WO2021156700A1 PCT/IB2021/050568 IB2021050568W WO2021156700A1 WO 2021156700 A1 WO2021156700 A1 WO 2021156700A1 IB 2021050568 W IB2021050568 W IB 2021050568W WO 2021156700 A1 WO2021156700 A1 WO 2021156700A1
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Prior art keywords
transistor
insulator
conductor
oxide
terminal
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Ceased
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PCT/IB2021/050568
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English (en)
French (fr)
Japanese (ja)
Inventor
井上広樹
米田誠一
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN202180013110.XA priority Critical patent/CN115053514A/zh
Priority to US17/796,916 priority patent/US12363991B2/en
Priority to KR1020227029933A priority patent/KR102959950B1/ko
Priority to JP2021575094A priority patent/JP7693562B2/ja
Publication of WO2021156700A1 publication Critical patent/WO2021156700A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025093865A priority patent/JP2025126183A/ja
Priority to US19/259,822 priority patent/US20260013205A1/en
Ceased legal-status Critical Current

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    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
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    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
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    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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    • H10D30/67—Thin-film transistors [TFT]
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    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
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    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/024—Manufacture or treatment of image sensors covered by group H10F39/12 of coatings or optical elements
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    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/184—Infrared image sensors
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    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
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    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
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    • H10F39/10—Integrated devices
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    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/189—X-ray, gamma-ray or corpuscular radiation imagers

Definitions

  • One aspect of the present invention relates to a semiconductor device and an imaging device.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical field of the invention disclosed in the present specification and the like relates to a product, an operation method, or a manufacturing method.
  • one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter). Therefore, more specifically, the technical fields of one aspect of the present invention disclosed in the present specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, power storage devices, image pickup devices, storage devices, signal processing devices, and sensors. , Processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods.
  • Logic circuits can be classified into, for example, static logic circuits, dynamic logic circuits, pseudo logic circuits, and the like. Since a dynamic logic circuit is a circuit that operates by temporarily holding data, a transistor leakage current becomes a problem as compared with a static logic circuit. If the leakage current of the transistor is large, the data held by the dynamic logic circuit will be destroyed. Leakage current is caused in part by the off-current that flows out when the transistor is in the off state.
  • Patent Document 1 and Patent Document 2 disclose that a transistor whose channel is formed of an oxide semiconductor is provided to reduce a leakage current of a dynamic logic circuit.
  • the manufacturing process of the semiconductor device may be shortened by using the same material as the material contained in the channel forming region of a plurality of transistors of the semiconductor device.
  • the material a metal oxide containing indium, gallium, zinc and the like can be used.
  • a metal oxide containing indium (for example, In oxide) or a metal oxide containing zinc (for example, Zn oxide) an n-type semiconductor can be produced, but a p-type semiconductor has mobility and reliability. Difficult to produce in terms of sex. Therefore, when manufacturing a semiconductor device, it is preferable to use a unipolar circuit composed of transistors (n-channel transistors) including n-type semiconductors. However, since the unipolar circuit does not include a transistor (p-channel type transistor) including a p-type semiconductor, the circuit area tends to be large unlike a CMOS circuit.
  • a level shifter (referred to as a negative voltage level shifter) that shifts the input potential to VSSL, which is a lower potential, is configured as a unipolar circuit including an n-channel transistor.
  • VSS which is an input signal
  • the gate-source voltage of the n-channel transistor may be higher than the threshold voltage.
  • the channel transistor may not turn off. If the n-channel transistor is not turned off, the negative voltage level shifter has a circuit configuration in which a steady current flows, so that power consumption may increase.
  • the level shifter has not only the function of a negative voltage level shifter but also the function of a positive voltage level shifter that shifts the input potential to a higher potential. Further, it is preferable that the level shifter has a circuit configuration in which only either a negative voltage level shifter or a positive voltage level shifter functions, depending on the situation.
  • One aspect of the present invention is to provide a semiconductor device having a function of shifting an input voltage to a lower voltage or a higher voltage. Alternatively, one aspect of the present invention is to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention is to provide a semiconductor device having a reduced circuit area.
  • one aspect of the present invention is to provide a novel semiconductor device.
  • one aspect of the present invention is to provide an imaging device having the above-mentioned semiconductor device.
  • the problem of one aspect of the present invention is not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are issues not mentioned in this item, which are described below. Issues not mentioned in this item can be derived from descriptions in the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention solves at least one of the above-listed problems and other problems. It should be noted that one aspect of the present invention does not need to solve all of the above-listed problems and other problems.
  • One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance, an input terminal, and an output terminal.
  • the first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the output terminal.
  • the second terminal of the second transistor is electrically connected to the first terminal of the third transistor.
  • the first terminal of the fourth transistor is electrically connected to the gate of the second transistor and the first terminal of the first capacitance, and the second terminal of the first capacitance is electrically connected to the input terminal.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor may each have the same polarity.
  • the first potential is input to the input terminal
  • the second potential is input to the second terminal of the first transistor
  • the second potential of the third transistor is used.
  • the first transistor has a function of precharging the output terminal to the second potential when the first transistor is on.
  • the second transistor preferably has a function of turning on or off according to the first potential input to the input terminal when the fourth transistor is in the off state.
  • the second potential is precharged to the output terminal, the first transistor is turned off, and then the third transistor is turned on, so that the potential of the output terminal is changed to the second potential or the second potential. It is preferable to have a function of setting three potentials.
  • one aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance, an input terminal, and an output terminal.
  • the first terminal of the first transistor is electrically connected to the first terminal and the output terminal of the third transistor, and the second terminal of the third transistor is electrically connected to the first terminal of the second transistor.
  • the first terminal of the fourth transistor is electrically connected to the gate of the second transistor and the first terminal of the first capacitance, and the second terminal of the first capacitance is electrically connected to the input terminal.
  • the first potential may be input to the input terminal.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor may each have the same polarity.
  • the first potential is input to the input terminal
  • the second potential is input to the second terminal of the first transistor
  • the second potential of the second transistor is input.
  • the first transistor precharges the output terminal to the second potential when the first transistor is on.
  • the second transistor has a function of turning on or off according to the first potential input to the input terminal when the fourth transistor is in the off state.
  • the potential of the output terminal is changed to the second potential or the second potential by turning on the third transistor after the second potential is precharged to the output terminal and the first transistor is turned off. It is preferable to have a function of setting three potentials.
  • one aspect of the present invention may be a semiconductor device having a second capacity in the configuration of (1) or (4) above.
  • the first terminal of the second capacitance is electrically connected to the first terminal of the first transistor, the first terminal of the second transistor, and the output terminal.
  • each of the first transistor to the fourth transistor has a metal oxide or silicon in the channel forming region. May be good.
  • the first capacitance may include a fifth transistor.
  • the fifth transistor has a metal oxide or silicon in the channel forming region. Further, the gate of the fifth transistor functions as one of the first terminal or the second terminal of the first capacitance, and the first terminal and the second terminal of the fifth transistor are the first terminal or the second terminal of the first capacitance. Acts as the other of.
  • one aspect of the present invention is an imaging device including the semiconductor device according to any one of (1) to (7) above and a photoelectric conversion element. Further, the photoelectric conversion element is preferably located above the first transistor to the fourth transistor.
  • the semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics.
  • a semiconductor element transistor, diode, photodiode, etc.
  • the storage device, the display device, the light emitting device, the lighting device, the electronic device, and the like are themselves semiconductor devices, and may have the semiconductor device.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display
  • One or more devices, light emitting devices, loads, etc. can be connected between X and Y.
  • the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows.
  • a circuit that enables functional connection between X and Y for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion, etc.) Circuits (digital-analog conversion circuit, analog-to-digital conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the signal potential level, etc.), voltage source, current source , Switching circuit, amplification circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplification circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc.) It is possible to connect one or more to and from. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. do.
  • X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element between X and Y). Or when they are connected with another circuit in between) and when X and Y are directly connected (that is, they are connected without sandwiching another element or another circuit between X and Y). If there is) and.
  • X and Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and the X, the source (or the second terminal, etc.) of the transistor are connected to each other. (1 terminal, etc.), the drain of the transistor (or the 2nd terminal, etc.), and Y are electrically connected in this order.
  • the source of the transistor (or the first terminal, etc.) is electrically connected to X
  • the drain of the transistor (or the second terminal, etc.) is electrically connected to Y
  • the X, the source of the transistor (such as the second terminal).
  • the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order.
  • X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor. (Terminals, etc.), transistor drains (or second terminals, etc.), and Y are provided in this connection order.
  • the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be separated. Separately, the technical scope can be determined. Note that these expression methods are examples, and are not limited to these expression methods.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • circuit diagram shows that the independent components are electrically connected to each other, one component has the functions of a plurality of components.
  • one component has the functions of a plurality of components.
  • the term "electrically connected” as used herein includes the case where one conductive film has the functions of a plurality of components in combination.
  • the “resistance element” can be, for example, a circuit element having a resistance value higher than 0 ⁇ , wiring, or the like. Therefore, in the present specification and the like, the “resistive element” includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, a coil, and the like. Therefore, the term “resistance element” can be paraphrased into terms such as “resistance”, “load”, and “region having a resistance value”, and conversely, “resistance", “load”, and “region having a resistance value”. Can be rephrased as a term such as “resistive element”.
  • the resistance value can be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, and further preferably 10 m ⁇ or more and 1 ⁇ or less. Further, for example, it may be 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
  • the “capacitance element” means, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value, a parasitic capacitance, a transistor gate capacitance, and the like. Can be. Therefore, in the present specification and the like, the “capacitive element” is not only a circuit element containing a pair of electrodes and a dielectric contained between the electrodes, but also a parasitic capacitance appearing between the wirings. , The gate capacitance that appears between the gate and one of the source or drain of the transistor.
  • capacitor element means “capacitive element” and “parasitic”. It can be paraphrased into terms such as “capacity” and “gate capacitance”.
  • the term “pair of electrodes” in “capacity” can be rephrased as “pair of conductors", “pair of conductive regions”, “pair of regions” and the like.
  • the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be 1 pF or more and 10 ⁇ F or less.
  • the transistor has three terminals called a gate, a source, and a drain.
  • the gate is a control terminal that controls the conduction state of the transistor.
  • the two terminals that function as sources or drains are the input and output terminals of the transistor.
  • One of the two input / output terminals becomes a source and the other becomes a drain depending on the high and low potentials given to the conductive type (n-channel type, p-channel type) of the transistor and the three terminals of the transistor. Therefore, in the present specification and the like, the terms source and drain can be paraphrased.
  • the transistor when explaining the connection relationship of transistors, "one of the source or drain” (or the first electrode or the first terminal), “the other of the source or drain” (or the second electrode, or The notation (second terminal) is used.
  • it may have a back gate in addition to the above-mentioned three terminals.
  • one of the gate or the back gate of the transistor may be referred to as a first gate
  • the other of the gate or the back gate of the transistor may be referred to as a second gate.
  • the terms “gate” and “backgate” may be interchangeable.
  • the respective gates When the transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, and the like in the present specification and the like.
  • a node can be paraphrased as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on a circuit configuration, a device structure, and the like.
  • terminals, wiring, etc. can be paraphrased as nodes.
  • ground potential ground potential
  • the potentials are relative, and when the reference potential changes, the potential given to the wiring, the potential applied to the circuit or the like, the potential output from the circuit or the like also changes.
  • the terms “high level potential” and “low level potential” do not mean a specific potential.
  • both of the two wires “function as a wire that supplies a high level potential”
  • the high level potentials provided by both wires do not have to be equal to each other.
  • both of the two wires are described as “functioning as a wire that supplies a low level potential”
  • the low level potentials given by both wires do not have to be equal to each other. ..
  • the "current” is a charge transfer phenomenon (electrical conduction).
  • the description “electrical conduction of a positively charged body is occurring” means “electrical conduction of a negatively charged body in the opposite direction”. Is happening. " Therefore, in the present specification and the like, “current” refers to a charge transfer phenomenon (electrical conduction) accompanying the movement of carriers, unless otherwise specified.
  • the carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system in which the current flows (for example, semiconductor, metal, electrolyte, vacuum, etc.).
  • the "current direction” in the wiring or the like shall be the direction in which the positive carrier moves, and shall be described as a positive current amount.
  • the direction in which the negative carrier moves is opposite to the direction of the current, and is expressed by the amount of negative current. Therefore, in the present specification and the like, if there is no notice about the positive or negative of the current (or the direction of the current), the description such as “current flows from element A to element B” means “current flows from element B to element A” or the like. It can be paraphrased as. Further, the description such as “a current is input to the element A” can be rephrased as "a current is output from the element A” or the like.
  • the ordinal numbers “first”, “second”, and “third” are added to avoid confusion of the components. Therefore, the number of components is not limited. Moreover, the order of the components is not limited. For example, the component referred to in “first” in one of the embodiments of the present specification and the like may be the component referred to in “second” in another embodiment or in the claims. There can also be. Further, for example, the component mentioned in “first” in one of the embodiments of the present specification and the like may be omitted in another embodiment or in the claims.
  • the terms “upper” and “lower” do not limit the positional relationship of the components directly above or below and in direct contact with each other.
  • the electrode B on the insulating layer A it is not necessary that the electrode B is formed in direct contact with the insulating layer A, and another configuration is formed between the insulating layer A and the electrode B. Do not exclude those that contain elements.
  • membrane and layer can be interchanged with each other depending on the situation.
  • the terms “insulating layer” and “insulating film” may be changed to the term "insulator”.
  • Electrode may be used as part of a “wiring” and vice versa.
  • the term “electrode” or “wiring” also includes a case where a plurality of “electrodes” or “wiring” are integrally formed.
  • a “terminal” may be used as part of a “wiring” or “electrode” and vice versa.
  • the term “terminal” includes a case where a plurality of "electrodes", “wiring”, “terminals” and the like are integrally formed.
  • the "electrode” can be a part of the “wiring” or the “terminal”, and for example, the “terminal” can be a part of the “wiring” or the “electrode”.
  • terms such as “electrode”, “wiring”, and “terminal” may be replaced with terms such as "area” in some cases.
  • terms such as “wiring”, “signal line”, and “power supply line” can be interchanged with each other in some cases or depending on the situation.
  • the reverse is also true, and it may be possible to change terms such as “signal line” and “power supply line” to the term “wiring”.
  • a term such as “power line” may be changed to a term such as "signal line”.
  • terms such as “signal line” may be changed to terms such as "power line”.
  • the term “potential” applied to the wiring may be changed to a term such as “signal” in some cases or depending on the situation.
  • the reverse is also true, and terms such as “signal” may be changed to the term “potential”.
  • semiconductor impurities refer to, for example, other than the main components constituting the semiconductor layer.
  • an element having a concentration of less than 0.1 atomic% is an impurity.
  • the inclusion of impurities may cause, for example, a high defect level density in a semiconductor, a decrease in carrier mobility, a decrease in crystallinity, and the like.
  • the impurities that change the characteristics of the semiconductor include, for example, group 1 elements, group 2 elements, group 13 elements, group 14 elements, group 15 elements, and components other than the main components.
  • transition metals and the like and in particular, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, oxygen, and the like. There is.
  • the switch means a switch that is in a conductive state (on state) or a non-conducting state (off state) and has a function of controlling whether or not a current flows.
  • the switch means a switch having a function of selecting and switching a path through which a current flows.
  • an electric switch, a mechanical switch, or the like can be used. That is, the switch is not limited to a specific switch as long as it can control the current.
  • Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or logic circuits that combine these.
  • transistors for example, bipolar transistors, MOS transistors, etc.
  • diodes for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, and MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.
  • the "conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited.
  • the "non-conducting state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically cut off.
  • the polarity (conductive type) of the transistor is not particularly limited.
  • An example of a mechanical switch is a switch that uses MEMS (Micro Electro Mechanical System) technology.
  • the switch has an electrode that can be moved mechanically, and the movement of the electrode controls conduction and non-conduction.
  • parallel means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of ⁇ 5 ° or more and 5 ° or less is also included.
  • substantially parallel or approximately parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° or more and 30 ° or less.
  • vertical means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.
  • substantially vertical or “approximately vertical” means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • one aspect of the present invention it is possible to provide a semiconductor device having a function of shifting an input voltage to a lower voltage or a higher voltage.
  • one aspect of the present invention can provide a semiconductor device with reduced power consumption.
  • a novel semiconductor device can be provided by one aspect of the present invention.
  • an imaging device having the above semiconductor device can be provided.
  • the effect of one aspect of the present invention is not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are the effects not mentioned in this item, which are described below. Effects not mentioned in this item can be derived from those described in the description, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions.
  • one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.
  • FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a timing chart showing an operation example of the semiconductor device.
  • FIG. 3 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 4A is a circuit diagram showing a configuration example of capacitance
  • FIG. 4B is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 5 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 6 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • FIG. 7 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • 8A to 8C are schematic cross-sectional views showing a configuration example of a transistor.
  • FIG. 1 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a timing chart showing an operation example of the semiconductor device.
  • FIG. 3 is a circuit diagram showing a configuration example of a semiconductor device
  • FIG. 9 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • FIG. 10 is a schematic cross-sectional view showing a configuration example of the semiconductor device.
  • 11A and 11B are schematic cross-sectional views showing a configuration example of a transistor.
  • 12A and 12B are schematic cross-sectional views showing a configuration example of a transistor.
  • 13A is a top view showing a configuration example of the capacitance
  • FIGS. 13B and 13C are cross-sectional perspective views showing a configuration example of the capacitance.
  • 14A is a top view showing a configuration example of the capacitance
  • FIG. 14B is a cross-sectional view showing the configuration example of the capacitance
  • FIG. 14A is a top view showing a configuration example of the capacitance
  • FIG. 14B is a cross-sectional view showing the configuration example of the capacitance
  • FIG. 14C is a cross-sectional perspective view showing the configuration example of the capacitance.
  • FIG. 15 is a schematic cross-sectional view showing a configuration example of the imaging device.
  • FIG. 16 is a schematic cross-sectional view showing a configuration example of the imaging device.
  • FIG. 17A is a diagram for explaining the classification of the crystal structure of IGZO
  • FIG. 17B is a diagram for explaining the XRD spectrum of crystalline IGZO
  • FIG. 17C is a diagram for explaining the microelectron diffraction pattern of crystalline IGZO.
  • .. 18A is a perspective view showing an example of a semiconductor wafer
  • FIG. 18B is a perspective view showing an example of a chip
  • FIGS. 18C and 18D are perspective views showing an example of an electronic component.
  • 19A to 19F are perspective views of a package and a module containing an imaging device.
  • FIG. 20 is a perspective view showing an example of an electronic device.
  • a metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel forming region of a transistor having at least one of an amplification action, a rectifying action, and a switching action, the metal oxide is referred to as a metal oxide semiconductor. be able to. Further, when the term OSFET or OS transistor is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.
  • the configuration shown in each embodiment can be appropriately combined with the configuration shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.
  • the content (may be a part of the content) described in one embodiment is the other content (may be a part of the content) described in the embodiment and one or more other implementations. It is possible to apply, combine, or replace at least one content with the content described in the form of (may be a part of the content).
  • figure (which may be a part) described in one embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more other figures.
  • the figure (which may be a part) described in the embodiment is different from another part of the figure, another figure (which may be a part) described in the embodiment, and one or more other figures.
  • more figures can be formed.
  • the level shifter in the present specification and the like is a potential level conversion circuit that converts an input voltage level into another voltage level. At this time, the other voltage may be lower or higher than the input voltage. Depending on the input voltage, the same voltage as the input voltage may be output without performing level shift.
  • the level shifter in the present specification and the like may have a function of level-shifting the input high level potential to the first potential and level-shifting the input low level potential to the second potential.
  • the first potential may be a potential higher than the high level potential, a high level potential, or a potential lower than the high level potential
  • the second potential may be a potential higher than the low level potential, a low level potential, or a low level potential.
  • the potential may be lower than.
  • one of the input high level potential or the low level potential is level-shifted to a potential higher than the high level potential, and the other of the input high level potential or the low level potential is used. May have a function of level-shifting to a potential lower than the low-level potential.
  • the level shifter which is a semiconductor device according to one aspect of the present invention, is a circuit using the architecture of a dynamic logic circuit.
  • a dynamic logic circuit is, for example, a circuit in which a circuit is driven by an operation including temporarily holding data, precharging an electric potential, evaluating, and the like.
  • FIG. 1 shows a configuration example of the level shifter.
  • the level shifter 100 has a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a capacitance C1, and a capacitance CL.
  • the transistors Tr1 to Tr4 are preferably OS transistors as an example.
  • the channel forming region of the transistors Tr1 to Tr4 is more preferably an oxide containing at least one of indium, gallium, and zinc.
  • indium and element M element M includes, for example, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, etc.
  • oxides containing at least one of zinc may be used. It is more preferable that the transistors Tr1 to Tr4 have the transistor structure described in the second embodiment.
  • the transistors Tr1 to Tr4 may be, as an example, a transistor having silicon in the channel forming region (referred to as a Si transistor in the present specification).
  • a Si transistor in the present specification.
  • the silicon for example, amorphous silicon (sometimes referred to as hydride amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon and the like can be used.
  • transistors Tr1 to Tr4 other than the OS transistor and the Si transistor, for example, a transistor in which Ge or the like is included in the channel forming region, or a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe forms a channel.
  • Transistors included in the region, transistors in which carbon nanotubes are contained in the channel forming region, transistors in which organic semiconductors are contained in the channel forming region, and the like can be used.
  • Each of the transistors Tr1 to Tr4 has the same structure and material as each other (for example, materials such as a semiconductor, an insulator, and a conductor included in the channel forming region), so that the transistors Tr1 to Tr4 are the same. Since the production can be performed by a process, the production process of the level shifter 100 can be shortened.
  • the semiconductor device according to one aspect of the present invention is not limited to this, and may be, for example, a transistor in which a part of the transistors Tr1 to Tr4 has a different structure and material.
  • the transistor Tr1, the transistor Tr3, and the transistor Tr4 may be an OS transistor
  • the transistor Tr2 may be a Si transistor.
  • a back gate is shown for the transistors Tr1 to Tr4, and the connection configuration of the back gate is not shown, but the electrical connection destination of the back gate is determined at the design stage. be able to.
  • the gate and the back gate may be electrically connected in order to increase the on-current of the transistor. That is, for example, the gate of the transistor Tr1 and the back gate may be electrically connected, the gate of the transistor Tr2 and the back gate may be electrically connected, and the gate and the back of the transistor Tr3 may be electrically connected.
  • the gate may be electrically connected, or the gate of the transistor Tr4 and the back gate may be electrically connected.
  • the back gate of the transistor and an external circuit are electrically connected in order to fluctuate the threshold voltage of the transistor or to reduce the off current of the transistor.
  • a wiring for connection may be provided, and a potential may be applied to the back gate of the transistor by the external circuit or the like.
  • the threshold voltages of the transistors Tr1 to Tr4 are V TH1 , V TH2 , V TH3 , and V TH4 , respectively. Further, in the present specification and the like, unless otherwise specified, each of V TH1 to V TH4 is a real number larger than 0.
  • the transistors Tr1 to Tr4 shown in FIG. 1 have a back gate, but the semiconductor device according to one aspect of the present invention is not limited to this.
  • the transistors Tr1 to Tr4 shown in FIG. 1 may have a configuration that does not have a back gate, that is, a transistor having a single gate structure. Further, some transistors may have a back gate, and some other transistors may not have a back gate.
  • the transistors Tr1 to Tr4 shown in FIG. 1 are n-channel transistors, but the semiconductor device according to one aspect of the present invention is not limited thereto.
  • a part or all of the transistors Tr1 to Tr4 may be replaced with p-channel transistors.
  • the above-mentioned examples of changes regarding the structure and polarity of the transistor are not limited to the transistors Tr1 and Tr4.
  • the structure and polarity of the transistors may be changed in the same manner as described above.
  • the transistors Tr1 to Tr4 may operate in the saturation region when they are in the ON state. That is, when the transistors Tr1 to Tr4 are in the ON state, the gate voltage, source voltage, and drain voltage of the transistors Tr1 to Tr4 may be appropriately biased to the voltage within the operating range in the saturation region. And.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring VDHE
  • the second terminal of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr2 and the wiring BOTE
  • the gate of the transistor Tr1 is It is electrically connected to the wiring PRCE.
  • the second terminal of the transistor Tr2 is electrically connected to the first terminal of the transistor Tr3, and the gate of the transistor Tr2 is electrically connected to the first terminal of the transistor Tr4 and the first terminal of the capacitance C1.
  • the second terminal of the transistor Tr3 is electrically connected to the wiring VLSE, and the gate of the transistor Tr3 is electrically connected to the wiring EVE.
  • the second terminal of the transistor Tr4 is electrically connected to the wiring VLSE, and the gate of the transistor Tr4 is electrically connected to the wiring CLPE. Further, the second terminal of the capacitance C1 is electrically connected to the wiring INE. Further, the first terminal of the capacitance CL is electrically connected to the wiring BOTE, and the second terminal of the capacitance CL is electrically connected to the wiring VLSE.
  • the level shifter 100 has a storage unit AM as an example.
  • the storage unit AM has a transistor Tr4 and a capacitance C1 as an example.
  • the electrical connection point between the gate of the transistor Tr2, the first terminal of the capacitance C1 and the first terminal of the transistor Tr4 is referred to as a node FN.
  • the storage unit AM has a function of holding an electric potential in the node FN. Specifically, for example, in the storage unit AM, when a high level potential is input to the wiring CLPE and the transistor Tr4 is turned on, the node FN and the wiring VLSE are in a conductive state, and the potential of the node FN is changed. It becomes the potential given by the wiring VLSE.
  • the storage unit AM can hold the potential given by the wiring VLSE to the node FN.
  • the capacitance CL is provided to stabilize the output signal from the wiring BOTE. Specifically, for example, when a voltage is output to the wiring BOTE and the transistor Tr1 and the transistor Tr2 are in the off state, the voltage can be held by the capacitance CL. On the other hand, when the capacitance CL is not provided, the voltage of the wiring BOTE may fluctuate due to the leakage current from the transistor Tr1, the transistor Tr2, and the like. Therefore, it is preferable that the level shifter 100 is provided with a capacitance CL. If the output signal from the wiring BOTE does not change unfavorably due to parasitic capacitance or the like, the level shifter 100 may not be provided with a capacitance CL.
  • Wiring VDHE functions as wiring that gives a constant voltage, for example.
  • the constant voltage is the power supply voltage on the high level side of the level shifter 100.
  • the power supply voltage is referred to as VDDH.
  • Wiring VLSE functions as wiring that gives a constant voltage, for example.
  • the constant voltage is the power supply voltage on the low level side of the level shifter 100.
  • the power supply voltage is referred to as VSSL.
  • VSSL has a voltage lower than VDDH.
  • the wiring INE is electrically connected to the input terminal of the level shifter 100, and the wiring INE functions as a wiring for applying an input voltage to the input terminal.
  • the input voltage can be a voltage output from a logic circuit or the like that is electrically connected to the level shifter 100 via the wiring INE.
  • the input voltage (output voltage of the logic circuit) can be, for example, a high level potential or a low level potential.
  • the high level potential is referred to as VDD
  • VSS the low level potential
  • VDD has a voltage higher than VSS and a voltage lower than VDDH.
  • VSS has a voltage higher than VSSL.
  • the wiring PRCE functions as a wiring for controlling the presence or absence of a potential charge from the wiring VDHE to the wiring BOTE.
  • the wiring PRCE may be a wire that gives the VDDH + V TH1 or VSS.
  • VTH1 is the threshold voltage of the transistor Tr1.
  • the high level potential wiring PRCE gives may be VDDH not VDDH + V TH1, or a potential of more than VDDH + V TH1.
  • the wiring EVE functions as a wiring that gives an evaluation signal, for example.
  • the wiring EVE can be wiring that gives VDDH + VTH3 or VSS.
  • the V TH3 is the threshold voltage of the transistor Tr3.
  • the high level potential wiring EVE gives may be VDDH not VDDH + V TH3, or a potential of more than VDDH + V TH3.
  • the high level potential wiring EVE gives may be a potential below higher VDDH than V TH3.
  • the wiring CLPE functions as wiring for controlling switching between the ON state and the OFF state of the transistor Tr4.
  • the wiring CLPE can be a wiring that gives VDD or VSSL.
  • the high level potential given by the wiring CLPE may be VDD + V TH4 instead of VDD, or may be a potential exceeding VDD + V TH4.
  • the V TH4 is the threshold voltage of the transistor Tr4.
  • the wiring BOTE is electrically connected to the input terminal of the level shifter 100, and the wiring BOTE functions as a wiring for outputting the output voltage of the level shifter 100.
  • the level shifter 100 shifts VDD to VDDH, inverts the logic, and outputs VSSL to the wiring BOTE.
  • VSS is input to the wiring INE
  • the level shifter 100 shifts the level of VSS to VSSL and inverts the logic, and outputs VDDH to the wiring BOTE.
  • FIG. 2 is a timing chart showing changes in the voltages of the wiring CLPE, the wiring PRCE, the wiring EVE, the wiring INE, the node FN, and the wiring BOT in and around the time T1 to the time T9.
  • VSS is input to the wiring INE
  • VSSL is input to the wiring CLPE
  • VSSL is input to the wiring PRCE
  • VSSL is input to the wiring EVE at a time before the time T1.
  • VSSL or VSS is held in the node FN of the storage unit AM, and VDDH or VSSL is output to the wiring BOTE.
  • VDD is input to the wiring CLPE as a high level potential between the time T1 and the time T2.
  • VDD is input to the gate of the transistor Tr4, so that the gate-source voltage of the transistor Tr4 becomes VDD-VSSL.
  • V TH4 so that VDD-VSSL> V TH4
  • VSSL is input to the wiring CLPE as a low level potential.
  • the VSSL is input to the gate of the transistor Tr4, so that the gate-source voltage of the transistor Tr4 becomes 0.
  • the transistor Tr4 is turned off.
  • VSSL is input to the wiring PRCE as a low level potential.
  • data is input to the level shifter 100 between the time T3 and the time T4.
  • VDD is input to the wiring INE as a high level potential between the time T3 and the time T4.
  • the potential of the node FN fluctuates due to the capacitive coupling in the capacitance C1.
  • the potential of the node FN becomes VSSL + ⁇ (VDD-VSS) due to the capacitive coupling in the capacitance C1.
  • ⁇ is a capacitance coupling coefficient determined by the circuit configuration around the node FN and the like.
  • the timing of data input to the level shifter 100 is preferably between time T3 and time T4, preferably while VDDH is input to the wiring PRCE. That is, it is preferable that the VDD input to the wiring INE is performed while the VDDH is precharged in the wiring BOTE.
  • Non-overlap period (1) The period from time T4 to time T5 is a non-overlapping period.
  • the non-overlap period is a period provided so that the precharge period between the time T3 and the time T4 described above and the evaluation period between the time T5 and the time T6 described later do not overlap. .. If the precharge period and the evaluation period do not overlap, the non-overlap period may not be provided.
  • the second terminal of the transistor Tr2 and the wiring VLSE are in a conductive state, and the potential VSSL given by the wiring VLSE is input to the second terminal of the transistor Tr2.
  • V EVE having a potential higher than V TH3 and lower than VDDH may be input to the wiring EVE as a high level potential.
  • V TH2 satisfies ⁇ (VDD-VSS)> V TH2 , the transistor Tr2 is turned on.
  • the VSSL is input to the wiring EVE as a low level potential.
  • VSSL is input to the gate of the transistor Tr3.
  • Precharge period (2), data entry period (2) Between the time T6 and the time T7, the electric potential is precharged to the wiring BOTE. Specifically, the operation from time T3 to time T4 is similarly performed between time T6 and time T7. Therefore, the wiring PRCE is, VDDH + V TH1 is input as a high level potential, the potential of the wiring BOTE becomes VDDH.
  • VSSL is input to the wiring PRCE as a low level potential.
  • VSS is input to the wiring INE as a low level potential between the time T6 and the time T7.
  • the potential of the node FN fluctuates due to the capacitive coupling in the capacitance C1.
  • the potential of the wiring INE is VSS
  • the potential of the node FN returns to the potential of the node FN between the time T2 and the time T3. That is, the potential of the node FN between the time T6 and the time T7 is VSSL.
  • the timing of data input to the level shifter 100 is preferably between time T6 and time T7, preferably while VDDH is input to the wiring PRCE. That is, it is preferable that the VSS input to the wiring INE is performed while the wiring BOTE is precharged with VDDH.
  • Non-overlap period (2) The period from time T7 to time T8 is the same non-overlapping period as the period from time T4 to time T5. Therefore, for the non-overlapping period, the description of the operation between the time T4 and the time T5 will be taken into consideration.
  • VDDH After the output of VDDH is performed from the wiring BOTE, VSSL is input to the wiring EVE as a low level potential. As a result, the transistor Tr3 is turned off.
  • the input VDD can be level-shifted to VSS lower than VSS, or the input VSS can be level-shifted to VDDH higher than VDD.
  • the semiconductor device according to one aspect of the present invention is not limited to the configuration shown in FIG.
  • the semiconductor device according to one aspect of the present invention may have a circuit configuration of the level shifter 100 shown in FIG. 1 changed depending on the situation.
  • the level shifter 100 shown in FIG. 1 may be changed to the circuit configuration of the level shifter 100A shown in FIG.
  • the level shifter 100A has a configuration in which the transistor Tr2 and the transistor Tr3 are replaced in the level shifter 100.
  • the circuit configuration of the level shifter 100A of FIG. 3 will be described only in terms of differences from the level shifter 100 of FIG.
  • the first terminal of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr3
  • the second terminal of the transistor Tr3 is electrically connected to the first terminal of the transistor Tr2
  • the second terminal of the transistor Tr2 is. It is electrically connected to the wiring VLSE.
  • level shifter 100A of FIG. 3 As an operation example of the level shifter 100A of FIG. 3, for example, the same as the timing chart of FIG. 2 which is an operation example of the level shifter 100 of FIG. 1 can be used.
  • the level shifter 100 shown in FIG. 1 may have a configuration in which each of the capacitance C1 and the capacitance CL has a transistor.
  • the capacitance C1 (capacity CL) includes the transistor Tc1 (transistor TcL).
  • the first terminal and the second terminal of the transistor Tc1 are set as one of the first terminal or the second terminal of the capacitance C1 (capacity CL)
  • the gate of the transistor Tc1 (transistor TcL) is set as the capacitance. It is the other of the first terminal or the second terminal of C1 (capacity CL).
  • the level shifter 100B shown in FIG. 4B has a configuration in which the capacitance C1 and the capacitance CL are replaced with transistors Tc1 and transistors TcL, respectively.
  • the threshold voltage of the transistor Tc1 (transistor TcL) is preferably lower than the voltage between the gate of the transistor Tc1 (transistor TcL) and the source or drain of the transistor Tc1 (transistor TcL). Further, in the level shifter 100B shown in FIG.
  • the transistor Tc1 (transistor TcL) can be manufactured as the capacitance C1 (transistor CL) in the step of forming the transistor. It can be omitted. That is, the time required for producing the level shifter 100B can be shortened.
  • the level shifter 100 shown in FIG. 1 may have a configuration in which the second terminal of the capacitance CL is electrically connected to another wiring instead of the wiring VLSE.
  • the configuration of the level shifter 100C shown in FIG. 5 can be used.
  • the level shifter 100C is different from the level shifter 100 in that the second terminal of the capacitance CL is electrically connected to the wiring VAL.
  • the wiring VAL functions as a wiring that applies a constant voltage, similarly to the wiring VLSE.
  • the constant voltage may be VSS, ground potential (GND), or the like, instead of VSS provided by the wiring VLSE.
  • the wiring VAL may be wiring that applies a voltage such as VDD or VDDH.
  • the wiring VAL may be electrically connected to the wiring VDHE.
  • the semiconductor device shown in FIG. 6 includes a transistor 300, a transistor 500, and a capacitive element 600.
  • 8A is a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 8B is a cross-sectional view of the transistor 500 in the channel width direction
  • FIG. 8C is a cross-sectional view of the transistor 300 in the channel width direction.
  • the transistor 500 is a transistor (OS transistor) having a metal oxide in the channel forming region.
  • the transistor 500 has a characteristic that the off-current is small and the field effect mobility does not change even at a high temperature.
  • a semiconductor device for example, a transistor included in the level shifter 100, the level shifter 100A, the level shifter 100B, the level shifter 100C, etc. described in the above embodiment, it is possible to realize a semiconductor device whose operating ability does not decrease even at high temperatures. ..
  • the transistor 500 to the transistor Tr4 by utilizing the characteristic that the off-current is small, the potential written to the node FN of the storage unit AM can be held for a long time.
  • the transistor 500 is provided above the transistor 300, for example, and the capacitive element 600 is provided above the transistor 300 and the transistor 500, for example.
  • the capacitance element 600 can be a capacitance included in the level shifter 100, the level shifter 100A, the level shifter 100B, the level shifter 100C, and the like described in the above embodiment. Depending on the circuit configuration, the capacitive element 600 shown in FIG. 6 may not necessarily be provided.
  • the transistor 300 is provided on the substrate 311 and has a semiconductor region 313 composed of a conductor 316, an insulator 315, and a part of the substrate 311, a low resistance region 314a functioning as a source region or a drain region, and a low resistance region 314b. ..
  • the transistor 300 can be applied to, for example, the transistors included in the level shifter 100, the level shifter 100A, the level shifter 100B, the level shifter 100C, and the like described in the above embodiment.
  • the transistor Tr2 included in the level shifter 100 of FIG. 1 can be used.
  • FIG. 6 shows a configuration in which the gate of the transistor 300 is electrically connected to one of the source and drain of the transistor 500 via one of the pair of electrodes of the capacitive element 600, the level shifter 100 Depending on the configuration of the level shifter 100A, the level shifter 100B, the level shifter 100C, etc., one of the source or drain of the transistor 300 electrically connects to one of the source or drain of the transistor 500 via one of the pair of electrodes of the capacitive element 600.
  • the configuration may be such that one of the source or drain of the transistor 300 is electrically connected to the gate of the transistor 500 via one of the pair of electrodes of the capacitive element 600.
  • each terminal of the transistor 300 may be configured not to be electrically connected to each terminal of the transistor 500 and each terminal of the capacitance element 600.
  • a semiconductor substrate for example, a single crystal substrate or a silicon substrate
  • the substrate 311 it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 311.
  • the transistor 300 is covered with the conductor 316 on the upper surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315.
  • the on-characteristics of the transistor 300 can be improved by increasing the effective channel width. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristic of the transistor 300 can be improved.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • a semiconductor such as a silicon-based semiconductor in a region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a low resistance region 314a serving as a source region or a drain region, a low resistance region 314b, and the like.
  • It preferably contains crystalline silicon.
  • it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like.
  • a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used.
  • the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs or the like.
  • an element that imparts n-type conductivity such as arsenic and phosphorus, or a p-type conductivity such as boron is imparted.
  • the conductor 316 that functions as a gate electrode is a semiconductor material such as silicon, a metal material, or an alloy that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.
  • a material or a conductive material such as a metal oxide material can be used.
  • the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.
  • the transistor 300 shown in FIG. 6 is an example, and the transistor 300 is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration, driving method, and the like.
  • the configuration of the transistor 300 may be the same as that of the transistor 500 using an oxide semiconductor, as shown in FIG. The details of the transistor 500 will be described later.
  • the transistor 300 is provided on the substrate 312.
  • a semiconductor substrate may be used in the same manner as the substrate 311 of the semiconductor device of FIG.
  • the substrate 312 includes, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel still foil, a tungsten substrate, and a tungsten foil.
  • a substrate, a flexible substrate, a laminated film, a paper containing a fibrous material, a base film, or the like can be used.
  • glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass.
  • Examples of the flexible substrate, the laminated film, the base film and the like are as follows.
  • plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyether sulfone
  • PTFE polytetrafluoroethylene
  • acrylic examples include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, and the like.
  • An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order so as to cover the transistor 300.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, aluminum nitride and the like can be used. Just do it.
  • silicon oxide refers to a material having a higher oxygen content than nitrogen as its composition
  • silicon nitride as its composition means a material having a higher nitrogen content than oxygen as its composition. Is shown.
  • aluminum nitride refers to a material whose composition has a higher oxygen content than nitrogen
  • aluminum nitride refers to a material whose composition has a higher nitrogen content than oxygen. Is shown.
  • the insulator 322 may have a function as a flattening film for flattening a step generated by a transistor 300 or the like provided below the insulator 322.
  • the upper surface of the insulator 322 may be flattened by a flattening treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness.
  • CMP chemical mechanical polishing
  • the insulator 324 it is preferable to use a film having a barrier property such that hydrogen, impurities, etc. do not diffuse in the region where the transistor 500 is provided from the substrate 311 or the transistor 300.
  • a film having a barrier property against hydrogen for example, silicon nitride formed by the CVD method can be used.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • the amount of hydrogen desorbed can be analyzed using, for example, a heated desorption gas analysis method (TDS).
  • TDS heated desorption gas analysis method
  • the amount of hydrogen desorbed from the insulator 324 is such that the amount desorbed in terms of hydrogen atoms is converted per area of the insulator 324 when the surface temperature of the film is in the range of 50 ° C. to 500 ° C. It may be 10 ⁇ 10 15 atoms / cm 2 or less, preferably 5 ⁇ 10 15 atoms / cm 2 or less.
  • the insulator 326 preferably has a lower dielectric constant than the insulator 324.
  • the relative permittivity of the insulator 326 is preferably less than 4, more preferably less than 3.
  • the relative permittivity of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative permittivity of the insulator 324.
  • the insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a capacitance element 600, a conductor 328 connected to the transistor 500, a conductor 330, and the like.
  • the conductor 328 and the conductor 330 have a function as a plug or wiring.
  • a conductor having a function as a plug or wiring may collectively give a plurality of structures the same reference numerals.
  • the wiring and the plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • each plug and wiring As the material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or laminated. be able to. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low resistance conductive material.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are laminated in this order.
  • a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 has a function as a plug or wiring for connecting to the transistor 300.
  • the conductor 356 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 350 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 356 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen.
  • the conductor having a barrier property against hydrogen for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining the conductivity as wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen has a structure in contact with the insulator 350 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 354 and the conductor 356.
  • the insulator 360, the insulator 362, and the insulator 364 are laminated in this order.
  • a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364.
  • the conductor 366 has a function as a plug or wiring.
  • the conductor 366 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 360 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 366 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 364 and the conductor 366.
  • the insulator 370, the insulator 372, and the insulator 374 are laminated in this order.
  • a conductor 376 is formed on the insulator 370, the insulator 372, and the insulator 374.
  • the conductor 376 has a function as a plug or wiring.
  • the conductor 376 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 370 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 376 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen.
  • a wiring layer may be provided on the insulator 374 and the conductor 376.
  • the insulator 380, the insulator 382, and the insulator 384 are laminated in this order.
  • a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384.
  • the conductor 386 has a function as a plug or wiring.
  • the conductor 386 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the insulator 380 it is preferable to use an insulator having a barrier property against hydrogen, similarly to the insulator 324.
  • the conductor 386 preferably contains a conductor having a barrier property against hydrogen.
  • a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen.
  • the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment has been described. It is not limited to this.
  • the number of wiring layers similar to the wiring layer containing the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.
  • Insulator 510, insulator 512, insulator 514, and insulator 516 are laminated in this order on the insulator 384.
  • any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 it is preferable to use a substance having a barrier property against oxygen and hydrogen.
  • a film having a barrier property such that hydrogen, impurities, etc. do not diffuse from the region where the substrate 311 or the transistor 300 is provided to the region where the transistor 500 is provided is used. Is preferable. Therefore, the same material as the insulator 324 can be used.
  • Silicon nitride formed by the CVD method can be used as an example of a film having a barrier property against hydrogen.
  • hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as a transistor 500, so that the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300.
  • the membrane that suppresses the diffusion of hydrogen is a membrane that desorbs a small amount of hydrogen.
  • metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • the same material as the insulator 320 can be used for the insulator 512 and the insulator 516. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 512 and the insulator 516.
  • the insulator 510, the insulator 512, the insulator 514, and the insulator 516 are embedded with a conductor 518, a conductor (for example, a conductor 503) constituting the transistor 500, and the like.
  • the conductor 518 has a function as a plug or wiring for connecting to the capacitance element 600 or the transistor 300.
  • the conductor 518 can be provided by using the same material as the conductor 328 and the conductor 330.
  • the conductor 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having a barrier property against oxygen, hydrogen, and water.
  • the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.
  • a transistor 500 is provided above the insulator 516.
  • the transistor 500 includes a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, and an insulator arranged on the insulator 516 and the insulator 503.
  • 520 insulator 522 placed on insulator 520
  • insulator 524 placed on insulator 522
  • oxide 530a placed on insulator 524
  • oxide 530a placed on oxide 530a
  • the oxide 530b arranged on the oxide 530b, the conductor 542a and the conductor 542b arranged apart from each other on the oxide 530b, and the conductor 542a and the conductor 542b arranged on the conductor 542a and the conductor 542b.
  • the oxide 530c arranged on the bottom surface and the side surface of the opening, the insulator 550 arranged on the forming surface of the oxide 530c, and the forming surface of the insulator 550. It has an arranged conductor 560 and. In this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor 542.
  • the insulator 544 is arranged between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b, and the insulator 580.
  • the conductor 560 includes a conductor 560a provided inside the insulator 550, a conductor 560b provided so as to be embedded inside the conductor 560a, and the conductor 560b. It is preferable to have.
  • the insulator 574 is arranged on the insulator 580, the conductor 560, and the insulator 550.
  • oxide 530a, oxide 530b, and oxide 530c may be collectively referred to as oxide 530.
  • the transistor 500 shows a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are laminated in a region where a channel is formed and in the vicinity thereof.
  • One aspect of the present invention is this. It is not limited to.
  • a single layer of oxide 530b, a two-layer structure of oxide 530b and oxide 530a, a two-layer structure of oxide 530b and oxide 530c, or a laminated structure of four or more layers may be provided.
  • the conductor 560 is shown as a two-layer laminated structure, but one aspect of the present invention is not limited to this.
  • the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.
  • the transistor 500 shown in FIGS. 6, 8A, and 8B is an example, and the transistor 500 is not limited to the structure thereof, and an appropriate transistor may be used depending on the circuit configuration, driving method, and the like.
  • the conductor 560 functions as a gate electrode of the transistor, and the conductor 542a and the conductor 542b function as a source electrode or a drain electrode, respectively.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the arrangement of the conductor 560, the conductor 542a and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing the alignment margin, the occupied area of the transistor 500 can be reduced. As a result, the semiconductor device can be miniaturized and highly integrated.
  • the conductor 560 is formed in a region between the conductor 542a and the conductor 542b in a self-aligned manner, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved and a high frequency characteristic can be provided.
  • the conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode.
  • the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560 without interlocking with the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made larger than 0 V, and the off-current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when it is not applied.
  • the conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. As a result, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected to cover the channel forming region formed in the oxide 530. Can be done.
  • the structure of the transistor that electrically surrounds the channel formation region by the electric fields of the first gate electrode and the second gate electrode is referred to as a surroundd channel (S-channel) structure.
  • the conductor 503 has the same configuration as the conductor 518, and the conductor 503a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside.
  • the transistor 500 shows a configuration in which the conductor 503a and the conductor 503b are laminated, one aspect of the present invention is not limited to this.
  • the conductor 503 may be provided as a single layer or a laminated structure having three or more layers.
  • a conductive material for the conductor 503a which has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate).
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one oxygen atom, oxygen molecule, etc.
  • the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.
  • the conductor 503a since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 503b from being oxidized and the conductivity from being lowered.
  • the conductor 503 also functions as a wiring
  • the conductor 503a does not necessarily have to be provided.
  • the conductor 503b is shown as a single layer, it may have a laminated structure, for example, titanium or titanium nitride may be laminated with the conductive material.
  • the insulator 520, the insulator 522, and the insulator 524 have a function as a second gate insulating film.
  • the insulator 524 in contact with the oxide 530 it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition. That is, it is preferable that the insulator 524 is formed with an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen deficiency in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.
  • the insulator having an excess oxygen region it is preferable to use an oxide material in which a part of oxygen is desorbed by heating.
  • Oxides that desorb oxygen by heating are those in which the amount of oxygen desorbed in terms of oxygen atoms is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 1 in TDS (Thermal Desorption Spectrum) analysis.
  • the surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 400 ° C. or lower.
  • the insulator having the excess oxygen region and the oxide 530 may be brought into contact with each other to perform one or more of heat treatment, microwave treatment, or RF treatment.
  • heat treatment microwave treatment, or RF treatment.
  • water or hydrogen in the oxide 530 can be removed.
  • reactions occur which bonds VoH is disconnected, when other words happening reaction of "V O H ⁇ V O + H", can be dehydrogenated.
  • the hydrogen generated as oxygen combines with H 2 O, it may be removed from the oxide 530 or oxide 530 near the insulator.
  • a part of hydrogen may be diffused or captured (also referred to as gettering) in the conductor 542a and the conductor 542b.
  • the microwave processing for example, it is preferable to use an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side.
  • an apparatus having a power source for generating high-density plasma for example, by using a gas containing oxygen and using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be generated.
  • the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more.
  • oxygen and argon are used as the gas to be introduced into the apparatus for performing microwave treatment, and the oxygen flow rate ratio (O 2 / (O 2 + Ar)) is 50% or less, preferably 10% or more and 30. It is better to do it at% or less.
  • the heat treatment may be performed, for example, at 100 ° C. or higher and 450 ° C. or lower, more preferably 350 ° C. or higher and 400 ° C. or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment is preferably performed in an oxygen atmosphere.
  • oxygen can be supplied to the oxide 530 to reduce oxygen deficiency (VO ).
  • the heat treatment may be performed in a reduced pressure state.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas. good.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of the oxidizing gas, and then the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.
  • the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atom, oxygen molecule, etc.) (the oxygen is difficult to permeate).
  • oxygen for example, oxygen atom, oxygen molecule, etc.
  • the oxygen contained in the oxide 530 does not diffuse to the insulator 520 side, which is preferable. Further, it is possible to prevent the conductor 503 from reacting with oxygen contained in the insulator 524, the oxide 530 and the like.
  • the insulator 522 may be, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconate oxide, lead zirconate titanate (PZT), strontium titanate (SrTIO 3 ), or It is preferable to use an insulator containing a so-called high-k material such as (Ba, Sr) TiO 3 (BST) in a single layer or in a laminated state. As transistors become finer and more integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as a gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.
  • a so-called high-k material such as (Ba, Sr) TiO 3 (BST)
  • an insulator containing oxides of one or both of aluminum and hafnium which are insulating materials having a function of suppressing diffusion of impurities and oxygen (the above oxygen is difficult to permeate).
  • the insulator containing one or both oxides of aluminum and hafnium it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate) and the like.
  • the insulator 522 is a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530. Functions as.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated on the above insulator.
  • the insulator 520 is thermally stable.
  • silicon oxide and silicon nitride nitride are suitable because they are thermally stable.
  • an insulator made of high-k material and silicon oxide or silicon oxide nitride an insulator 520 having a laminated structure that is thermally stable and has a high relative permittivity can be obtained.
  • the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer laminated structure.
  • the gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers.
  • the laminated structure is not limited to the same material, and may be a laminated structure made of different materials.
  • oxide 530 a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel forming region.
  • oxide 530 In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium).
  • Hafnium, tantalum, tungsten, magnesium, etc. (one or more) and the like may be used.
  • the In-M-Zn oxide that can be applied as the oxide 530 is preferably CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) and CAC-OS (Cloud-Aligned Compound Oxide Semiconductor).
  • CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
  • CAC-OS Cloud-Aligned Compound Oxide Semiconductor
  • In—Ga oxide, In—Zn oxide, In oxide and the like may be used as the oxide 530.
  • a metal oxide having a low carrier concentration for the transistor 500 it is preferable to use a metal oxide having a low carrier concentration for the transistor 500.
  • the impurity concentration in the metal oxide may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • impurities in the metal oxide include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon and the like.
  • hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the metal oxide.
  • oxygen vacancies and hydrogen combine to form a V O H.
  • V O H acts as a donor, sometimes electrons serving as carriers are generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have a normally-on characteristic.
  • the metal oxide since hydrogen in the metal oxide is easily moved by stress such as heat and electric field, if the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • the highly purified intrinsic or substantially highly purified intrinsic it is preferable that the highly purified intrinsic or substantially highly purified intrinsic.
  • the impurities such as hydrogen (dehydration, may be described as dehydrogenation.) It is important to supply oxygen to the metal oxide to compensate for the oxygen deficiency (sometimes referred to as dehydrogenation treatment).
  • the metal oxide impurities is sufficiently reduced such V O H By using the channel formation region of the transistor, it is possible to have stable electrical characteristics.
  • a defect containing hydrogen in an oxygen deficiency can function as a donor of a metal oxide.
  • the carrier concentration may be evaluated instead of the donor concentration. Therefore, in the present specification and the like, as a parameter of the metal oxide, a carrier concentration assuming a state in which an electric field is not applied may be used instead of the donor concentration. That is, the "carrier concentration" described in the present specification and the like may be paraphrased as the "donor concentration".
  • the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm. It is less than 3, more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the metal oxide is a semiconductor having a high band gap and is intrinsic (also referred to as type I) or substantially intrinsic, and has a channel forming region.
  • the carrier concentration of the metal oxide is preferably less than 1 ⁇ 10 18 cm -3 , more preferably less than 1 ⁇ 10 17 cm -3 , and further preferably less than 1 ⁇ 10 16 cm -3. It is preferably less than 1 ⁇ 10 13 cm -3 , even more preferably less than 1 ⁇ 10 12 cm -3.
  • the lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but may be, for example, 1 ⁇ 10 -9 cm -3 .
  • the oxygen in the oxide 530 diffuses to the conductor 542a and the conductor 542b due to the contact between the conductor 542a and the conductor 542b and the oxide 530, and the conductor The 542a and the conductor 542b may be oxidized. It is highly probable that the conductivity of the conductor 542a and the conductor 542b will decrease due to the oxidation of the conductor 542a and the conductor 542b.
  • the diffusion of oxygen in the oxide 530 to the conductor 542a and the conductor 542b can be rephrased as the conductor 542a and the conductor 542b absorbing the oxygen in the oxide 530.
  • the three-layer structure of the conductor 542a or the conductor 542b, the different layer, and the oxide 530b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and MIS (Metal-Insulator-). It may be referred to as a Semiconductor) structure, or it may be referred to as a diode junction structure mainly composed of a MIS structure.
  • the different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b.
  • the different layer is formed between the conductor 542a and the conductor 542b and the oxide 530c. In some cases, it is formed between the conductor 542a and the conductor 542b and the oxide 530b, and between the conductor 542a and the conductor 542b and the oxide 530c.
  • the metal oxide that functions as a channel forming region in the oxide 530 preferably has a bandgap of 2 eV or more, preferably 2.5 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.
  • the oxide 530 can suppress the diffusion of impurities into the oxide 530b from the structure formed below the oxide 530a. Further, by having the oxide 530c on the oxide 530b, it is possible to suppress the diffusion of impurities into the oxide 530b from the structure formed above the oxide 530c.
  • the oxide 530 preferably has a laminated structure due to a plurality of oxide layers having different atomic number ratios of each metal atom.
  • the atomic number ratio of the element M in the constituent elements is larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used in the oxide 530b. Is preferable.
  • the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b.
  • the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a.
  • the oxide 530c a metal oxide that can be used for the oxide 530a or the oxide 530b can be used.
  • the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a is smaller than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530b
  • In-Ga-Zn oxide having a composition of 3 or its vicinity can be used.
  • a metal oxide having a composition in the vicinity of any one can be used.
  • oxides 530a, oxides 530b, and oxides 530c so as to satisfy the above-mentioned atomic number ratio relationship.
  • the above composition indicates the atomic number ratio in the oxide formed on the substrate or the atomic number ratio in the sputtering target.
  • the composition of the oxide 530b by increasing the ratio of In, the on-current of the transistor, the mobility of the field effect, and the like can be increased, which is preferable.
  • the energy at the lower end of the conduction band of the oxide 530a and the oxide 530c is higher than the energy at the lower end of the conduction band of the oxide 530b.
  • the electron affinity of the oxide 530a and the oxide 530c is smaller than the electron affinity of the oxide 530b.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c is continuously changed or continuously bonded.
  • the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, so that a mixed layer having a low defect level density is formed.
  • a common element (main component) other than oxygen so that a mixed layer having a low defect level density is formed.
  • the oxide 530b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide or the like may be used as the oxide 530a and the oxide 530c.
  • the main path of the carrier is oxide 530b.
  • the defect level density at the interface between the oxide 530a and the oxide 530b and the interface between the oxide 530b and the oxide 530c can be lowered. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.
  • a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided on the oxide 530b.
  • the conductors 542a and 542b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium.
  • Iridium, strontium, lanthanum, or an alloy containing the above-mentioned metal element as a component, or an alloy in which the above-mentioned metal element is combined is preferably used.
  • tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferable.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.
  • the conductor 542a and the conductor 542b are shown as a single-layer structure, but a laminated structure of two or more layers may be used.
  • a tantalum nitride film and a tungsten film may be laminated.
  • the titanium film and the aluminum film may be laminated.
  • a two-layer structure in which an aluminum film is laminated on a tungsten film a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a tungsten film. It may have a two-layer structure in which copper films are laminated.
  • a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed on the aluminum film or the copper film.
  • a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
  • a region 543a and a region 543b may be formed as a low resistance region at the interface of the oxide 530 with the conductor 542a (conductor 542b) and its vicinity.
  • the region 543a functions as one of the source region or the drain region
  • the region 543b functions as the other of the source region or the drain region.
  • a channel forming region is formed in a region sandwiched between the region 543a and the region 543b.
  • the oxygen concentration in the region 543a (region 543b) may be reduced. Further, in the region 543a (region 543b), a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the component of the oxide 530 may be formed. In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.
  • the insulator 544 is provided so as to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided so as to cover each side surface of the oxide 530 and the insulator 524 so as to be in contact with the insulator 522.
  • insulator 544 a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium and the like. Can be used. Further, as the insulator 544, silicon nitride oxide, silicon nitride or the like can also be used.
  • the insulator 544 it is preferable to use aluminum, or an oxide containing one or both oxides of aluminum or hafnium, such as aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate). ..
  • hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent step.
  • the conductors 542a and 542b are made of a material having oxidation resistance, or if the conductivity does not significantly decrease even if oxygen is absorbed, the insulator 544 is not an indispensable configuration. It may be appropriately designed according to the desired transistor characteristics.
  • the insulator 544 By having the insulator 544, it is possible to prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b via the oxide 530c and the insulator 550. Further, it is possible to suppress the oxidation of the conductor 560 due to the excess oxygen contained in the insulator 580.
  • the insulator 550 functions as a first gate insulating film.
  • the insulator 550 is preferably arranged in contact with the inside (upper surface and side surface) of the oxide 530c.
  • the insulator 550 is preferably formed by using an insulator that contains excess oxygen and releases oxygen by heating.
  • silicon oxide having excess oxygen silicon oxide, silicon nitride, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, silicon oxide to which nitrogen is added, and vacancies are used.
  • Silicon oxide having can be used.
  • silicon oxide and silicon nitride nitride are preferable because they are stable against heat.
  • oxygen is effectively applied from the insulator 550 through the oxide 530c to the channel forming region of the oxide 530b. Can be supplied. Further, similarly to the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced.
  • the film thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.
  • a metal oxide may be provided between the insulator 550 and the conductor 560.
  • the metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560.
  • the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to the oxide 530.
  • oxidation of the conductor 560 due to excess oxygen can be suppressed.
  • a material that can be used for the insulator 544 may be used.
  • the insulator 550 may have a laminated structure as in the case of the second gate insulating film.
  • an insulator that functions as a gate insulating film is made of a high-k material and heat.
  • the conductor 560 functioning as the first gate electrode is shown as a two-layer structure in FIGS. 8A and 8B, it may have a single-layer structure or a laminated structure of three or more layers.
  • Conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, nitric oxide molecule (N 2 O, NO, etc. NO 2), conductive having a function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one oxygen atom, oxygen molecule, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to prevent the conductor 560b from being oxidized by the oxygen contained in the insulator 550 and the conductivity from being lowered.
  • the conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide and the like are preferably used.
  • an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b into a film by a sputtering method, the electric resistance value of the conductor 560a can be lowered to form a conductor. This can be referred to as an OC (Oxide Conductor) electrode.
  • the conductor 560b it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 560b also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 560b may have a laminated structure, for example, titanium or a laminated structure of titanium nitride and the conductive material.
  • the insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544.
  • the insulator 580 preferably has an excess oxygen region.
  • silicon, resin, or the like silicon oxide and silicon oxide nitride are preferable because they are thermally stable.
  • silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later step.
  • the insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. It is preferable that the concentration of impurities such as water and hydrogen in the insulator 580 is reduced.
  • the opening of the insulator 580 is formed so as to overlap the region between the conductor 542a and the conductor 542b.
  • the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.
  • the conductor 560 When miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the film thickness of the conductor 560 is increased, the conductor 560 may have a shape having a high aspect ratio. In the present embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape having a high aspect ratio, the conductor 560 is formed without collapsing during the process. Can be done.
  • the insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550.
  • an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied into the oxide 530 from the excess oxygen region.
  • the insulator 574 use one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium and the like. Can be done.
  • aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide formed by the sputtering method can have a function as a barrier film for impurities such as hydrogen as well as an oxygen supply source.
  • the insulator 581 that functions as an interlayer film on the insulator 574.
  • the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.
  • the conductor 540a and the conductor 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544.
  • the conductor 540a and the conductor 540b are provided so as to face each other with the conductor 560 interposed therebetween.
  • the conductor 540a and the conductor 540b have the same configuration as the conductor 546 and the conductor 548 described later.
  • An insulator 582 is provided on the insulator 581.
  • the insulator 582 it is preferable to use a substance having a barrier property against oxygen, hydrogen and the like. Therefore, the same material as the insulator 514 can be used for the insulator 582.
  • a metal oxide such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.
  • aluminum oxide has a high blocking effect that does not allow the membrane to permeate both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from being mixed into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.
  • an insulator 586 is provided on the insulator 582.
  • the same material as the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, it is possible to reduce the parasitic capacitance generated between the wirings.
  • a silicon oxide film, a silicon nitride film, or the like can be used as the insulator 586.
  • the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator 574, the insulator 581, the insulator 582, and the insulator 586 include the conductor 546 and the conductor 548. Is embedded.
  • the conductor 546 and the conductor 548 have a function as a plug or wiring for connecting to the capacitance element 600, the transistor 500, or the transistor 300.
  • the conductor 546 and the conductor 548 can be provided by using the same material as the conductor 328 and the conductor 330.
  • an opening may be formed so as to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening.
  • an insulator having a high barrier property against hydrogen or water By wrapping the transistor 500 with the above-mentioned insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside.
  • a plurality of transistors 500 may be put together and wrapped with an insulator having a high barrier property against hydrogen or water.
  • an opening is formed so as to surround the transistor 500, for example, an opening reaching the insulator 514 or the insulator 522 is formed, and the above-mentioned insulator having a high barrier property is provided so as to be in contact with the insulator 514 or the insulator 522.
  • the insulator having a high barrier property to hydrogen or water for example, the same material as the insulator 522 may be used.
  • the capacitive element 600 has a conductor 610, a conductor 620, and an insulator 630.
  • the conductor 612 may be provided on the conductor 546 and the conductor 548.
  • the conductor 612 has a function as a plug or wiring for connecting to the transistor 500.
  • the conductor 610 has a function as an electrode of the capacitive element 600.
  • the conductor 612 and the conductor 610 can be formed at the same time.
  • the conductor 612 and the conductor 610 include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned elements as components.
  • a metal nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film and the like can be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. It is also possible to apply a conductive material such as indium tin oxide.
  • the conductor 612 and the conductor 610 have a single-layer structure, but the structure is not limited to this, and a laminated structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having a high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • the conductor 620 is provided so as to overlap with the conductor 610 via the insulator 630.
  • a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten.
  • tungsten When it is formed at the same time as another structure such as a conductor, Cu (copper), Al (aluminum), or the like, which are low resistance metal materials, may be used.
  • An insulator 650 is provided on the conductor 620 and the insulator 630.
  • the insulator 650 can be provided by using the same material as the insulator 320. Further, the insulator 650 may function as a flattening film that covers the uneven shape below the insulator 650.
  • the semiconductor device according to one aspect of the present invention may have a configuration in which, for example, another semiconductor substrate having a circuit is bonded below the substrate 311 on which the transistor 300 is formed.
  • FIG. 9 shows a configuration in which a layer SA, which is a part of the semiconductor device of FIG. 6, and a layer SB having a circuit formed on another semiconductor substrate are bonded together.
  • the semiconductor device shown in FIG. 9 has a configuration in which a substrate 211 including a circuit or the like included in the layer SB is bonded below the substrate 311 included in the layer SA. There is.
  • the conductor, the insulator, and the like above the insulator 360 are omitted in the layer SA.
  • the substrate 211 for example, a substrate applicable to the substrate 311 of the semiconductor device shown in FIG. 6 can be used.
  • an insulator 220, an insulator 222, an insulator 224, an insulator 226, and an insulator 230 are sequentially provided on the substrate 211 so as to cover the transistor 200, similarly to the transistor 300 on the substrate 311. ing.
  • the insulator 220, the insulator 222, the insulator 224, the insulator 226, the insulator 230, and the insulator 231 include, for example, the insulator 320, the insulator 322, the insulator 324, the insulator 326, and the insulator 230.
  • a material applicable to the above can be used.
  • the insulator 220, the insulator 222, the insulator 224, the insulator 226, the insulator 230, and the insulator 231 include, for example, the insulator 320, the insulator 322, the insulator 324, the insulator 326, and the insulator 350. It can be formed by the same process as the above.
  • a conductor 228, a conductor 229, and the like are embedded in the insulator 220, the insulator 222, the insulator 224, and the insulator 226.
  • the conductor 228 and the conductor 229 have a function as a plug or a wiring like the conductor 328 and the conductor 330. Further, as the conductor 228 and the conductor 229, materials applicable to the conductor 328 and the conductor 330 can be used.
  • the insulator 232 functions as a bonding layer for the insulator 341 provided below the substrate 311 described later. Further, a conductor 233 is embedded in the insulator 231 and the insulator 232 so as to be electrically connected to a part of the conductor 229, and the conductor 233 also functions as a part of the bonding layer. ..
  • silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, titanium nitride and the like can be used as the insulator 232.
  • the conductor 233 for example, copper, aluminum, tin, zinc, tungsten, silver, platinum, gold or the like can be used. Copper, aluminum, tungsten, or gold is preferably used because of the ease of bonding with the conductor 342, which will be described later.
  • the conductor 233 may have a multi-layer structure including a plurality of layers.
  • a first conductor is formed on the side wall of the opening of the insulator 231 and the insulator 232, and then a second conductor is formed so as to fill the opening of the insulator 231 and the insulator 232. May be good.
  • the first conductor for example, a conductor having a barrier property against hydrogen such as tantalum nitride can be used, and as the second conductor, for example, tungsten having high conductivity can be used.
  • an insulator 341 is formed below the substrate 311.
  • the insulator 341 functions as a bonding layer for the insulator 232 on the substrate 211.
  • the insulator 34 for example, a material applicable to the insulator 232 can be used.
  • the insulator 232 and the insulator 341 are composed of the same components.
  • the insulator 341, the substrate 311 and the insulator 320, and the insulator 322 are embedded with the conductor 342 so as to be electrically connected to a part of the conductor 330, and the conductor 342 is also embedded. Acts as part of the laminating layer.
  • a material applicable to the conductor 233 can be used.
  • the conductor 342 may have a multi-layer structure including a plurality of layers.
  • a first conductor is formed on the side wall of the opening of the insulator 341, the substrate 311 and the insulator 320, and the insulator 322, and then the opening of the insulator 341, the substrate 311 and the insulator 320, and the insulator 322.
  • a second conductor may be formed so as to fill the portion.
  • the first conductor for example, a conductor having a barrier property against hydrogen such as tantalum nitride can be used, and as the second conductor, for example, tungsten having high conductivity can be used.
  • the surfaces of the insulator 232 and the conductor 233 are flattened in the layer SB so that their heights match.
  • the surfaces of the insulator 341 and the conductor 342 are flattened so that their heights match.
  • the oxide film on the surface and the adsorption layer of impurities are removed by a sputtering treatment or the like to clean and activate the surface.
  • a surface-activated bonding method in which they are brought into contact with each other and bonded can be used.
  • a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonding at the atomic level occurs, so that excellent bonding can be obtained not only electrically but also mechanically.
  • the conductor 342 contained in the layer SA can be electrically connected to the conductor 233 contained in the layer SB. Further, it is possible to obtain a connection having mechanical strength between the insulator 341 contained in the layer SA and the insulator 232 contained in the layer SB.
  • an insulating layer and a metal layer are mixed on each bonding surface, so for example, a surface activation bonding method and a hydrophilic bonding method may be combined.
  • a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the metal layer.
  • the surface of the metal layer may be made of a refractory metal such as gold and subjected to hydrophilic treatment.
  • a joining method other than the above-mentioned method may be used.
  • the bonding process described above it is possible to add more circuits to the semiconductor device. Therefore, it is possible to suppress an increase in the circuit area of the semiconductor device. Further, by the bonding process, another semiconductor device (for example, a logic circuit, a signal conversion circuit, a potential level conversion circuit, a current source, a voltage source, a switching circuit, an amplifier circuit, a photoelectric conversion circuit, an operation) is used for the semiconductor device. Circuits, etc.) can be electrically connected. Therefore, a new semiconductor device can be configured.
  • another semiconductor device for example, a logic circuit, a signal conversion circuit, a potential level conversion circuit, a current source, a voltage source, a switching circuit, an amplifier circuit, a photoelectric conversion circuit, an operation
  • a transistor 200 is formed on the substrate 211 included in the layer SB.
  • the transistor 200 is shown as having the same structure as the transistor 300, but the transistor 200 may have a structure different from that of the transistor 300.
  • the transistor 200 may have the structure of the transistor 500 shown in FIGS. 6, 7, 8A, and 8B as the OS transistor.
  • the substrate 212 shown in FIG. 10 for example, a substrate applicable to the substrate 312 of the semiconductor device shown in FIG. 7 can be used.
  • FIGS. 11A and 11B are modifications of the transistor 500 shown in FIGS. 8A and 8B.
  • FIG. 11A is a cross-sectional view of the transistor 500 in the channel length direction
  • FIG. 11B is a channel width direction of the transistor 500. It is a cross-sectional view of.
  • the configurations shown in FIGS. 11A and 11B can also be applied to other transistors included in the semiconductor device of one aspect of the present invention, such as the transistor 300.
  • the transistor 500 having the configuration shown in FIGS. 11A and 11B is different from the transistor 500 having the configuration shown in FIGS. 8A and 8B in that it has an insulator 402 and an insulator 404. Further, it is different from the transistor 500 having the configuration shown in FIGS. 8A and 8B in that the insulator 552 is provided in contact with the side surface of the conductor 540a and the insulator 552 is provided in contact with the side surface of the conductor 540b. Further, it is different from the transistor 500 having the configuration shown in FIGS. 8A and 8B in that it does not have the insulator 520.
  • an insulator 402 is provided on the insulator 512. Further, the insulator 404 is provided on the insulator 574 and the insulator 402.
  • an insulator 514, an insulator 516, an insulator 522, an insulator 524, an insulator 544, an insulator 580, and an insulator 574 are provided, and the insulator is provided.
  • the structure is such that 404 covers them. That is, the insulator 404 includes an upper surface of the insulator 574, a side surface of the insulator 574, a side surface of the insulator 580, a side surface of the insulator 544, a side surface of the insulator 524, a side surface of the insulator 522, a side surface of the insulator 516, and an insulator. It is in contact with the side surface of the body 514 and the upper surface of the insulator 402, respectively. As a result, the oxide 530 and the like are isolated from the outside by the insulator 404 and the insulator 402.
  • the insulator 402 and the insulator 404 have a high function of suppressing the diffusion of hydrogen (for example, at least one hydrogen atom, hydrogen molecule, etc.) or water molecule.
  • hydrogen for example, at least one hydrogen atom, hydrogen molecule, etc.
  • the insulator 402 and the insulator 404 it is preferable to use silicon nitride or silicon nitride oxide, which is a material having a high hydrogen barrier property.
  • silicon nitride or silicon nitride oxide which is a material having a high hydrogen barrier property.
  • the insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544.
  • the insulator 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules.
  • an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide, which is a material having a high hydrogen barrier property.
  • silicon nitride is a material having a high hydrogen barrier property, it is suitable to be used as an insulator 552.
  • the insulator 552 By using a material having a high hydrogen barrier property as the insulator 552, it is possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductor 540a and the conductor 540b. Further, it is possible to prevent the oxygen contained in the insulator 580 from being absorbed by the conductor 540a and the conductor 540b. As described above, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.
  • the transistor 500 shown in FIGS. 11A and 11B may have a transistor configuration changed depending on the situation.
  • the transistor 500 of FIGS. 11A and 11B can be the transistor shown in FIGS. 12A and 12B as a modification.
  • FIG. 12A is a cross-sectional view of the transistor in the channel length direction
  • FIG. 12B is a cross-sectional view of the transistor in the channel width direction.
  • the transistors shown in FIGS. 12A and 12B differ from the transistors shown in FIGS. 11A and 11B in that the oxide 530c has a two-layer structure of an oxide 530c1 and an oxide 530c2.
  • the oxide 530c1 is in contact with the upper surface of the insulator 524, the side surface of the oxide 530a, the upper surface and the side surface of the oxide 530b, the side surface of the conductor 542a and the conductor 542b, the side surface of the insulator 544, and the side surface of the insulator 580.
  • the oxide 530c2 is in contact with the insulator 550.
  • In-Zn oxide can be used as the oxide 530c1.
  • the same material as the material that can be used for the oxide 530c when the oxide 530c has a one-layer structure can be used.
  • Metal oxides can be used.
  • the oxide 530c By having the oxide 530c have a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-current of the transistor can be increased as compared with the case where the oxide 530c has a one-layer structure. Therefore, the transistor can be applied as, for example, a power MOS transistor.
  • the oxide 530c of the transistors having the configurations shown in FIGS. 8A and 8B can also have a two-layer structure of oxide 530c1 and oxide 530c2.
  • the transistors having the configurations shown in FIGS. 12A and 12B can be applied to, for example, the transistors 300 shown in FIGS. 6 and 7. Further, for example, as described above, the transistor 300 is applied to the semiconductor device described in the above embodiment, for example, the transistor included in the level shifter 100, the level shifter 100A, the level shifter 100B, and the level shifter 100C described in the above embodiment. be able to.
  • the transistors shown in FIGS. 12A and 12B can also be applied to transistors other than the transistor 300 and the transistor 500 included in the semiconductor device of one aspect of the present invention.
  • FIG. 13 shows the capacitance element 600A as an example of the capacitance element 600 applicable to the semiconductor device shown in FIGS. 6 and 7.
  • 13A is a top view of the capacitive element 600A
  • FIG. 13B is a perspective view showing a cross section of the capacitive element 600A at the alternate long and short dash line L3-L4
  • FIG. 13C shows a cross section of the capacitive element 600A at the alternate long and short dash line W3-L4. It is a perspective view.
  • the conductor 610 functions as one of the pair of electrodes of the capacitance element 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitance element 600A. Further, the insulator 630 functions as a dielectric material sandwiched between the pair of electrodes.
  • Examples of the insulator 630 include silicon oxide, silicon nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, hafnium oxide, hafnium oxide, hafnium nitride, and hafnium nitride. Zirconium oxide or the like may be used, and it can be provided in a laminated or single layer.
  • the capacitance element 600A can secure a sufficient capacitance by having an insulator having a high dielectric constant (high-k), and by having an insulator having a large dielectric strength, the dielectric strength is improved and the capacitance is improved.
  • the electrostatic breakdown of the element 600A can be suppressed.
  • the insulator of the high dielectric constant (high-k) material material having a high specific dielectric constant
  • the insulator 630 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr) TiO 3 (BST).
  • Insulators containing high-k material may be used in single layers or in layers. For example, when the insulator 630 is laminated, a three-layer laminate in which zirconium oxide, aluminum oxide, and zirconium oxide are formed in this order, or zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are formed. A four-layer laminate or the like formed in order may be used.
  • the insulator 630 a compound containing hafnium and zirconium may be used.
  • problems such as leakage currents in transistors and / or capacitive elements may occur due to the thinning of the gate insulator and the dielectric used in the capacitive element.
  • a high-k material for the gate insulator and the insulator that functions as a dielectric used for the capacitive element it is possible to reduce the gate potential during transistor operation and secure the capacitance of the capacitive element while maintaining the physical film thickness. It will be possible.
  • the capacitive element 600 is electrically connected to the conductor 546 and the conductor 548 at the lower part of the conductor 610.
  • the conductor 546 and the conductor 548 function as a plug or wiring for connecting to another circuit element. Further, in FIGS. 13A to 13C, the conductor 546 and the conductor 548 are collectively referred to as the conductor 540.
  • the insulator 586 in which the conductor 546 and the conductor 548 are embedded and the insulator 650 covering the conductor 620 and the insulator 630 are omitted. ing.
  • the capacitive element 600 shown in FIGS. 6, 7, 13A, 13B, and 13C is a planar type, but the shape of the capacitive element is not limited to this.
  • the capacitance element 600 may be the cylinder type capacitance element 600B shown in FIGS. 14A to 14C.
  • FIG. 14A is a top view of the capacitive element 600B
  • FIG. 14B is a cross-sectional view taken along the alternate long and short dash line L3-L4 of the capacitive element 600B
  • FIG. 14C is a perspective view showing a sectional view taken along the alternate long and short dash line W3-L4 of the capacitive element 600B. be.
  • the capacitive element 600B includes a pair of an insulator 631 on an insulator 586 in which a conductor 540 is embedded, an insulator 651 having an opening, and a conductor 610 that functions as one of a pair of electrodes. It has a conductor 620 that functions as the other of the electrodes of the above.
  • the insulator 586, the insulator 650, and the insulator 651 are omitted in order to clearly show the figure.
  • the same material as the insulator 586 can be used.
  • the conductor 611 is embedded so as to be electrically connected to the conductor 540.
  • the conductor 611 for example, the same material as the conductor 330 and the conductor 518 can be used.
  • the same material as the insulator 586 can be used.
  • the insulator 651 has an opening, and the opening is superimposed on the conductor 611.
  • the conductor 610 is formed on the bottom portion and the side surface of the opening. That is, the conductor 610 is superposed on the conductor 611 and is electrically connected to the conductor 611.
  • an opening is formed in the insulator 651 by an etching method or the like, and then the conductor 610 is formed by a sputtering method, an ALD method or the like. After that, the conductor 610 formed on the insulator 651 may be removed by leaving the conductor 610 formed in the opening by a CMP (Chemical Mechanical Polishing) method or the like.
  • CMP Chemical Mechanical Polishing
  • the insulator 630 is located on the insulator 651 and on the forming surface of the conductor 610.
  • the insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitive element.
  • the conductor 620 is formed on the insulator 630 so as to fill the opening of the insulator 651.
  • the insulator 650 is formed so as to cover the insulator 630 and the conductor 620.
  • the cylinder-type capacitive element 600B shown in FIG. 14 can have a higher capacitance value than the planar type capacitive element 600A.
  • a photoelectric conversion element may be provided above the capacitance element 600 of the semiconductor device shown in FIGS. 6 and 7. That is, as one aspect of the present invention, an imaging device including the level shifter described in the above embodiment may be used.
  • the image pickup apparatus converts the current induced by the photoelectric conversion element into a digital signal by a current-voltage conversion circuit, an analog-digital conversion circuit, or the like, and the digital signal is level-shifted by providing a level shifter in the image pickup apparatus. be able to.
  • FIG. 15 shows a configuration example of an imaging device in which the photoelectric conversion element 700 is provided above the capacitance element 600 in the semiconductor device shown in FIG. 7.
  • the photoelectric conversion element 700 may be provided below the transistor 300, not above the capacitance element 600.
  • the photoelectric conversion element 700 has, for example, a layer 767a, a layer 767b, a layer 767c, a layer 767d, and a layer 767e.
  • the photoelectric conversion element 700 shown in FIG. 15 is an example of an organic photoconductive film.
  • Layer 767a is a lower electrode
  • layer 767e is a translucent upper electrode
  • layers 767b, 767c, and 767d are photoelectric conversion units.
  • a pn junction type photodiode, an avalanche photodiode, or the like may be used.
  • the layer 767a which is the lower electrode, can be one of the anode and the cathode
  • the layer 767b which is the upper electrode, can be the other of the anode and the cathode.
  • the layer 767a is used as a cathode
  • the layer 767b is used as an anode.
  • the layer 767a is preferably a low resistance metal layer, for example.
  • a low resistance metal layer for example.
  • the layer 767a for example, aluminum, titanium, tungsten, tantalum, silver or a laminate thereof can be used.
  • the layer 767e for example, it is preferable to use a conductive layer having high translucency with respect to visible light.
  • a conductive layer having high translucency with respect to visible light.
  • indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like is used. Can be done.
  • the layer 767e may be omitted.
  • One of the layers 767b and 767d of the photoelectric conversion unit can be a hole transport layer and the other can be an electron transport layer. Further, the layer 767c can be a photoelectric conversion layer.
  • the hole transport layer for example, molybdenum oxide or the like can be used.
  • the electron transport layer for example, fullerenes such as C 60 and C 70 , or derivatives thereof and the like can be used.
  • a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used.
  • the insulator 751 is provided on the insulator 650, and the layer 767a is provided on the insulator 751. Further, the insulator 752 is provided on the insulator 751 and on the layer 767a. The layer 767b is provided on the insulator 752 and on the layer 767a.
  • a layer 767c, a layer 767d, a layer 767e, and an insulator 753 are laminated in this order.
  • the insulator 751 functions as an interlayer insulating film as an example.
  • the insulator 752 functions as an element separation layer as an example. Although not shown, the insulator 752 is provided to prevent a short circuit with another photoelectric conversion element located adjacent to the insulator 752. As the insulator 752, for example, it is preferable to use an organic insulator or the like.
  • the insulator 753 functions as a translucent flattening film as an example.
  • a material such as silicon oxide, silicon oxide nitride, silicon nitride oxide, or silicon nitride can be used.
  • a light-shielding layer 771 As an example, a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773 are provided.
  • the light-shielding layer 771 provided on the insulator 753 can suppress the inflow of light to adjacent pixels.
  • a metal layer such as aluminum or tungsten can be used for the light-shielding layer 771. Further, the metal layer and a dielectric film having a function as an antireflection film may be laminated.
  • a color filter can be used for the optical conversion layer 772 provided on the insulator 753 and the light shielding layer 771.
  • a color image can be obtained by assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filter for each pixel.
  • a wavelength cut filter is used for the optical conversion layer 772, it can be used as an image pickup device that can obtain images in various wavelength regions.
  • the optical conversion layer 772 uses a filter that blocks light below the wavelength of visible light, it can be used as an infrared imaging device. Further, if the optical conversion layer 772 uses a filter that blocks light having a wavelength of near infrared rays or less, a far infrared ray imaging device can be obtained. Further, if the optical conversion layer 772 uses a filter that blocks light having a wavelength equal to or higher than that of visible light, it can be used as an ultraviolet imaging device.
  • a scintillator is used for the optical conversion layer 772, it can be used as an imaging device for obtaining an image that visualizes the intensity of radiation used in an X-ray imaging device or the like.
  • radiation such as X-rays transmitted through a subject
  • a scintillator it is converted into light (fluorescence) such as visible light and ultraviolet light by a photoluminescence phenomenon.
  • the image data is acquired by detecting the light with the photoelectric conversion element 700.
  • an image pickup device having the above configuration may be used as a radiation detector or the like.
  • the scintillator contains a substance that absorbs the energy of radiation such as X-rays and gamma rays and emits visible light or ultraviolet light.
  • a substance that absorbs the energy of radiation such as X-rays and gamma rays and emits visible light or ultraviolet light.
  • Gd 2 O 2 S Tb
  • Gd 2 O 2 S Pr
  • Gd 2 O 2 S Eu
  • BaFCl Eu
  • NaI, CsI, CaF 2 , BaF 2 , CeF 3 LiF, LiI, ZnO, etc.
  • Those dispersed in resin, ceramics, etc. can be used.
  • a microlens array 773 is provided on the light-shielding layer 771 and on the optical conversion layer 772. Light passing through the individual lenses of the microlens array 773 passes through the optical conversion layer 772 directly below and is irradiated to the photoelectric conversion element 700. By providing the microlens array 773, the focused light can be incident on the photoelectric conversion element 700, so that photoelectric conversion can be performed efficiently.
  • the microlens array 773 is preferably formed of a resin or glass having high translucency with respect to visible light.
  • FIG. 15 shows the configuration of an image pickup apparatus in which a transistor 300 and a photoelectric conversion element 700 using an organic photoconductive film are provided above the transistor 500.
  • the imaging device according to one aspect of the present invention may be configured to provide a back-illuminated pn junction type photoelectric conversion element instead of the photoelectric conversion element 700.
  • FIG. 16 shows a configuration example of an image pickup apparatus in which a back-illuminated pn junction type photoelectric conversion element 700A is provided above the transistor 300 and the transistor 500.
  • the image pickup apparatus shown in FIG. 16 has a configuration in which a structure SC having a photoelectric conversion element 700A is bonded above a substrate 312 provided with a transistor 300, a transistor 500, and a capacitance element 600.
  • the structure SC includes a light-shielding layer 771, an optical conversion layer 772, and a microlens array 773, and the above description is taken into consideration for these explanations.
  • the photoelectric conversion element 700A is a pn junction type photodiode formed on a silicon substrate, and has a layer 765b corresponding to a p-type region and a layer 765a corresponding to an n-type region.
  • the photoelectric conversion element 700A is an embedded photodiode, and a thin p-type region (a part of the layer 765b) provided on the surface side (current extraction side) of the layer 765a can suppress dark current and reduce noise. can.
  • the insulator 701, the conductor 741, and the conductor 742 have a function as a bonding layer.
  • the insulator 754 has a function as an interlayer insulating film and a flattening film.
  • the insulator 755 has a function as an element separation layer.
  • the insulator 756 has a function of suppressing the outflow of carriers.
  • the silicon substrate is provided with a groove for separating pixels, and the insulator 756 is provided on the upper surface of the silicon substrate and the groove.
  • the insulator 756 By providing the insulator 756, it is possible to prevent the carriers generated in the photoelectric conversion element 700A from flowing out to the adjacent pixels.
  • the insulator 756 also has a function of suppressing the intrusion of stray light. Therefore, the insulator 756 can suppress color mixing.
  • An antireflection film may be provided between the upper surface of the silicon substrate and the insulator 756.
  • the element separation layer can be formed by using the LOCOS (LOCOxidation of Silicon) method. Alternatively, it may be formed by using an STI (Shallow Trench Isolation) method or the like.
  • LOCOS LOCxidation of Silicon
  • STI Shallow Trench Isolation
  • an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic can be used.
  • the insulator 756 may have a multi-layer structure.
  • the layer 765a (n-type region, corresponding to the cathode) of the photoelectric conversion element 700A is electrically connected to the conductor 741.
  • the layer 765b (p-type region, corresponding to the anode) is electrically connected to the conductor 742.
  • the conductor 741 and the conductor 742 have a region embedded in the insulator 701. Further, the surfaces of the insulator 701, the conductor 741, and the conductor 742 are flattened so that their heights match.
  • Insulator 691 and insulator 692 are laminated in this order above the insulator 650. Further, for example, in FIG. 16, the insulator 692 is provided with an opening, and the conductor 743 is formed so as to fill the opening.
  • insulator 691 for example, a material applicable to the insulator 751 can be used.
  • insulator 692 for example, a material applicable to the insulator 650 can be used.
  • Each of the insulator 693 and the insulator 701 functions as a part of the bonding layer. Further, each of the conductor 741, the conductor 742, and the conductor 743 also functions as a part of the bonding layer.
  • the insulator 693 and the insulator 701 for example, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, titanium nitride and the like can be used.
  • the insulator 693 and the insulator 701 are composed of the same components.
  • the conductor 741, the conductor 742, and the conductor 743 for example, copper, aluminum, tin, zinc, tungsten, silver, platinum, gold, or the like can be used.
  • copper, aluminum, tungsten, or gold is preferably used in order to facilitate bonding between the conductor 741 and the conductor 743, and the conductor 742 and the conductor 743.
  • the conductor 741, the conductor 742, and the conductor 743 may have a multi-layer structure including a plurality of layers.
  • the first conductor may be formed on the side surface of the opening provided with the conductor 741, the conductor 742, or the conductor 743, and then the second conductor may be formed so as to fill the opening. ..
  • a conductor having a barrier property against hydrogen such as tantalum nitride can be used
  • the second conductor for example, tungsten having high conductivity can be used.
  • the heights of the surfaces of the insulator 693 and the conductor 743 are the same on the substrate 312 side. Flattening is done. Similarly, on the structure SC side, the surfaces of the insulator 701, the conductor 741, and the conductor 742 are flattened so that their heights match.
  • the surfaces treated with oxygen plasma or the like are brought into contact with each other after being given high flatness by polishing or the like. It is possible to use a hydrophilic bonding method or the like in which temporary bonding is performed by performing temporary bonding, and main bonding is performed by dehydration by heat treatment. Since the hydrophilic bonding method also causes bonding at the atomic level, it is possible to obtain mechanically excellent bonding.
  • the oxide film on the surface and the adsorption layer of impurities are subjected to sputtering treatment.
  • a surface-activated bonding method can be used in which the surfaces are removed by contact with each other, cleaned and activated, and then bonded to each other.
  • a diffusion bonding method or the like in which surfaces are bonded to each other by using both temperature and pressure can be used. In both cases, bonding at the atomic level occurs, so that excellent bonding can be obtained not only electrically but also mechanically.
  • the conductor 743 on the substrate 312 side can be electrically connected to the conductor 741 and the conductor 742 on the structure SC side. Further, it is possible to obtain a connection having mechanical strength between the insulator 693 on the substrate 312 side and the insulator 701 on the structure SC side.
  • an insulating layer and a metal layer are mixed on each bonding surface, so for example, a surface activation bonding method and a hydrophilic bonding method may be combined.
  • a method can be used in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an antioxidant treatment, and then a hydrophilic treatment is performed to join the metal layer.
  • the surface of the metal layer may be made of a refractory metal such as gold and subjected to hydrophilic treatment.
  • a joining method other than the above-mentioned method may be used.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to them, it is preferable that aluminum, gallium, yttrium, tin and the like are contained. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and the like. ..
  • FIG. 17A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxides containing In, Ga, and Zn).
  • IGZO metal oxides containing In, Ga, and Zn
  • oxide semiconductors are roughly classified into “Amorphous”, “Crystalline”, and “Crystal”.
  • Amorphous includes complete amorphous.
  • the “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-LinkedComposite) (extracting single cycle).
  • single crystal, poly crystal, and single crystal amorphous are excluded from the classification of "Crystalline”.
  • “Crystal” includes single crystal and poly crystal.
  • the structure in the thick frame shown in FIG. 17A is an intermediate state between "Amorphous” and “Crystal", and belongs to a new boundary region (New crystal line phase). .. That is, the structure can be rephrased as a structure completely different from the energetically unstable "Amorphous” and "Crystal".
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum.
  • XRD X-ray diffraction
  • FIG. 17B the XRD spectrum obtained by GIXD (Glazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" is shown in FIG. 17B (horizontal axis is 2 ⁇ [deg.], And vertical axis is intensity. (Intensity) is expressed in an arbitrary unit (au)).
  • the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method.
  • the XRD spectrum obtained by the GIXD measurement shown in FIG. 17B will be simply referred to as an XRD spectrum.
  • a peak showing clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film.
  • the crystal structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a microelectron diffraction pattern) observed by a micro electron diffraction method (NBED: Nano Beam Electron Diffraction).
  • the diffraction pattern of the CAAC-IGZO film is shown in FIG. 17C.
  • FIG. 17C is a diffraction pattern observed by the NBED in which the electron beam is incident parallel to the substrate.
  • electron diffraction is performed with the probe diameter set to 1 nm.
  • oxide semiconductors may be classified differently from FIG. 17A.
  • oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • the non-single crystal oxide semiconductor include the above-mentioned CAAC-OS and nc-OS.
  • the non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.
  • CAAC-OS CAAC-OS
  • nc-OS nc-OS
  • a-like OS the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.
  • CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions are oriented in a specific direction on the c-axis.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface to be formed of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film.
  • the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region in which the lattice arrangement is aligned. Further, the CAAC-OS has a region in which a plurality of crystal regions are connected in the ab plane direction, and the region may have distortion.
  • the strain refers to a region in which a plurality of crystal regions are connected in which the orientation of the lattice arrangement changes between a region in which the lattice arrangement is aligned and a region in which another grid arrangement is aligned. That is, CAAC-OS is an oxide semiconductor that is c-axis oriented and not clearly oriented in the ab plane direction.
  • Each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the size of the crystal region may be about several tens of nm.
  • CAAC-OS has indium (In) and oxygen. It tends to have a layered crystal structure (also referred to as a layered structure) in which a layer (hereinafter, In layer) and a layer having elements M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are laminated. There is. Indium and element M can be replaced with each other. Therefore, the (M, Zn) layer may contain indium. In addition, the In layer may contain the element M. The In layer may contain Zn.
  • the layered structure is observed as a lattice image in, for example, a high-resolution TEM image.
  • the position of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.
  • a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film.
  • a certain spot and another spot are observed at point-symmetrical positions with the spot of the incident electron beam passing through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit lattice is not limited to a regular hexagon and may be a non-regular hexagon. Further, in the above strain, it may have a lattice arrangement such as a pentagon or a hex.
  • a clear grain boundary cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal atoms. It is thought that this is the reason.
  • CAAC-OS for which no clear crystal grain boundary is confirmed, is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor.
  • a configuration having Zn is preferable.
  • In-Zn oxide and In-Ga-Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor that has high crystallinity and no clear grain boundary is confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries. Further, since the crystallinity of the oxide semiconductor may be lowered due to the mixing of impurities and / or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and / or defects (oxygen deficiency, etc.). .. Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. CAAC-OS is also stable against high temperatures (so-called thermal budgets) in the manufacturing process. Therefore, when CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • nc-OS has tiny crystals. Since the size of the minute crystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystal is also referred to as a nanocrystal.
  • nc-OS does not show regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film.
  • the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method. For example, when a structural analysis is performed on an nc-OS film using an XRD apparatus, a peak indicating crystallinity is not detected in the Out-of-plane XRD measurement using a ⁇ / 2 ⁇ scan. Further, when electron beam diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter larger than that of nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is performed. Is observed.
  • electron beam diffraction also referred to as selected area electron diffraction
  • nanocrystals for example, 50 nm or more
  • electron diffraction also referred to as nanobeam electron diffraction
  • an electron beam having a probe diameter for example, 1 nm or more and 30 nm or less
  • An electron diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be acquired.
  • the a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a void or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, a-like OS has a higher hydrogen concentration in the membrane than nc-OS and CAAC-OS.
  • CAC-OS relates to the material composition.
  • CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size close thereto.
  • the mixed state is also called a mosaic shape or a patch shape.
  • CAC-OS has a structure in which the material is separated into a first region and a second region to form a mosaic shape, and the first region is distributed in the membrane (hereinafter, also referred to as a cloud shape). It says.). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.
  • the atomic number ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region in which [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region in which [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • the first region is a region in which [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.
  • the first region is a region in which indium oxide, indium zinc oxide, or the like is the main component.
  • the second region is a region in which gallium oxide, gallium zinc oxide, or the like is the main component. That is, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
  • a region containing In as a main component (No. 1) by EDX mapping acquired by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region (1 region) and the region containing Ga as a main component (second region) have a structure in which they are unevenly distributed and mixed.
  • EDX Energy Dispersive X-ray spectroscopy
  • CAC-OS When CAC-OS is used for a transistor, the conductivity caused by the first region and the insulating property caused by the second region act in a complementary manner to switch the switching function (On / Off function). Can be added to the CAC-OS. That is, the CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS as a transistor, high on-current ( Ion ), high field-effect mobility ( ⁇ ), and good switching operation can be realized.
  • Ion on-current
  • ⁇ high field-effect mobility
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one aspect of the present invention has two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS. You may.
  • the oxide semiconductor as a transistor, a transistor with high field effect mobility can be realized. Moreover, a highly reliable transistor can be realized.
  • the carrier concentration of the oxide semiconductor is 1 ⁇ 10 17 cm -3 or less, preferably 1 ⁇ 10 15 cm -3 or less, more preferably 1 ⁇ 10 13 cm -3 or less, more preferably 1 ⁇ 10 11 cm ⁇ . It is 3 or less, more preferably less than 1 ⁇ 10 10 cm -3 , and more than 1 ⁇ 10 -9 cm -3.
  • the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • a low impurity concentration and a low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • An oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • the charge captured at the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the concentration of silicon, carbon, etc. in the oxide semiconductor and the concentration of silicon, carbon, etc. near the interface with the oxide semiconductor are determined. 2, 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the oxide semiconductor contains an alkali metal or an alkaline earth metal
  • a defect level may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5 ⁇ 10 19 atoms / cm 3 , preferably 5 ⁇ 10 18 atoms / cm 3 or less, and more preferably 1 ⁇ 10 18 atoms / cm 3 or less. , More preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency.
  • oxygen deficiency When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated.
  • a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , and more preferably 5 ⁇ 10 18 atoms / cm. Less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • This embodiment shows an example of a semiconductor wafer on which the semiconductor device and the like shown in the above embodiment are formed, and an electronic component in which the semiconductor device is incorporated.
  • the semiconductor wafer 4800 shown in FIG. 18A has a wafer 4801 and a plurality of circuit units 4802 provided on the upper surface of the wafer 4801.
  • the portion without the circuit portion 4802 is the spacing 4803, which is a dicing region.
  • the semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 by the previous process. Further, after that, the surface on the opposite side on which the plurality of circuit portions 4802 of the wafer 4801 are formed may be ground to reduce the thickness of the wafer 4801. By this step, the warp of the wafer 4801 can be reduced and the size of the wafer can be reduced.
  • a dicing process is performed. Dicing is performed along the scribing line SCL1 and the scribing line SCL2 (sometimes referred to as a dicing line or a cutting line) indicated by an alternate long and short dash line.
  • the spacing 4803 is provided so that a plurality of scribe lines SCL1 are parallel to each other and a plurality of scribe lines SCL2 are parallel to each other in order to facilitate the dicing process. It is preferable to provide them so as to be vertical.
  • the chip 4800a as shown in FIG. 18B can be cut out from the semiconductor wafer 4800.
  • the chip 4800a has a wafer 4801a, a circuit unit 4802, and a spacing 4803a.
  • the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between the adjacent circuit units 4802 may be substantially the same as the cutting margin of the scribe line SCL1 or the cutting margin of the scribe line SCL2.
  • the shape of the element substrate of one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in FIG. 18A.
  • the shape of the element substrate can be appropriately changed depending on the process of manufacturing the device and the device for manufacturing the device.
  • FIG. 18C shows a perspective view of a substrate (mounting substrate 4704) on which the electronic component 4700 and the electronic component 4700 are mounted.
  • the electronic component 4700 shown in FIG. 18C has a chip 4800a in the mold 4711. As shown in FIG. 18C, the chip 4800a may have a configuration in which circuit units 4802 are laminated. In FIG. 18C, a part is omitted in order to show the inside of the electronic component 4700.
  • the electronic component 4700 has a land 4712 on the outside of the mold 4711. The land 4712 is electrically connected to the electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714.
  • the electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board 4702 to complete the mounting board 4704.
  • FIG. 18D shows a perspective view of the electronic component 4730.
  • the electronic component 4730 is an example of SiP (System in Package) or MCM (Multi Chip Module).
  • an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.
  • the electronic component 4730 has a semiconductor device 4710.
  • the semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, a wideband memory (HBM: High Bandwidth Memory), or the like.
  • HBM High Bandwidth Memory
  • an integrated circuit semiconductor device such as a CPU, GPU, FPGA, or storage device can be used.
  • the package substrate 4732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 4731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or multiple layers.
  • the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 to the electrode provided on the package substrate 4732.
  • the interposer may be referred to as a "rewiring board” or an "intermediate board”.
  • a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 4731 It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide an active element in the silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult with a resin interposer.
  • the interposer on which the HBM is mounted is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer on which the HBM is mounted.
  • the reliability is unlikely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. Further, since the surface of the silicon interposer is high, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is unlikely to occur. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer, it is preferable to use a silicon interposer.
  • a heat sink heat dissipation plate
  • the heights of the integrated circuits provided on the interposer 4731 are the same.
  • the heights of the semiconductor device 4710 and the semiconductor device 4735 are the same.
  • an electrode 4733 may be provided on the bottom of the package substrate 4732.
  • FIG. 18D shows an example in which the electrode 4733 is formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 4733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 4730 can be mounted on another substrate by using various mounting methods, not limited to BGA and PGA.
  • BGA Band-GPU
  • PGA Stimble Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded package
  • QFN QuadFNeged
  • FIG. 19A is an external perspective view of the upper surface side of the package containing the image sensor chip.
  • the package has a package substrate 4510 for fixing the image sensor chip 4550 (see FIG. 19C), a cover glass 4520, an adhesive 4530 for adhering the two, and the like.
  • FIG. 19B is an external perspective view of the lower surface side of the package.
  • BGA Ball Grid Array
  • solder balls are bumps 4540.
  • LGA Land Grid Array
  • PGA Peripheral Component Interconnect Express
  • FIG. 19C is a perspective view of the package shown by omitting a part of the cover glass 4520 and the adhesive 4530.
  • An electrode pad 4560 is formed on the package substrate 4510, and the electrode pad 4560 and the bump 4540 are electrically connected via a through hole.
  • the electrode pad 4560 is electrically connected to the image sensor chip 4550 by a wire 4570.
  • FIG. 19D is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package.
  • the camera module includes a package substrate 4511 for fixing the image sensor chip 4551 (FIG. 19F), a lens cover 4521, a lens 4535, and the like.
  • an IC chip 4590 (FIG. 19F) having functions such as a drive circuit for an image pickup device and a signal conversion circuit is also provided between the package substrate 4511 and the image sensor chip 4551, and is configured as a SiP (System in Package). have.
  • FIG. 19E is an external perspective view of the lower surface side of the camera module.
  • the package substrate 4511 has a QFN (Quad Flat No-lead package) configuration in which a land 4541 for mounting is provided on the lower surface and the side surface thereof.
  • QFN Quad Flat No-lead package
  • the configuration is an example, and QFP (Quad Flat Package), the above-mentioned BGA, and the like may be provided.
  • FIG. 19F is a perspective view of the module shown by omitting a part of the lens cover 4521 and the lens 4535.
  • the land 4541 is electrically connected to the electrode pad 4651, and the electrode pad 4651 is electrically connected to the image sensor chip 4551 or the IC chip 4590 by a wire 4571.
  • the image sensor chip By housing the image sensor chip in the above-mentioned package, it becomes easy to mount it on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.
  • FIG. 20 illustrates how the electronic component 4700 having the semiconductor device is included in each electronic device.
  • the information terminal 5500 shown in FIG. 20 is a mobile phone (smartphone) which is a kind of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511, and as an input interface, a touch panel is provided in the display unit 5511 and buttons are provided in the housing 5510.
  • the information terminal 5500 has a semiconductor device such as a storage device and an image pickup device.
  • the information terminal 5500 can reduce the power consumption of the storage device, the image pickup device, the display unit 5511, and the like by applying the semiconductor device described in the above embodiment. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • FIG. 20 shows a wristwatch-type information terminal 5900 as an example of a wearable terminal.
  • the information terminal 5900 has a housing 5901, a display unit 5902, an operation button 5903, an operator 5904, a band 5905, and the like.
  • the wearable terminal can be a semiconductor device such as a storage device, an image pickup device, and a display unit 5902 included in the wearable terminal by applying the semiconductor device described in the above embodiment. Power consumption can be reduced.
  • FIG. 20 shows a desktop information terminal 5300.
  • the desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can reduce the power consumption of the semiconductor device provided in the desktop information terminal 5300 by applying the semiconductor device described in the above embodiment.
  • smartphones, desktop information terminals, and wearable terminals are taken as examples of electronic devices, respectively, as shown in FIG. 20, but information terminals other than smartphones, desktop information terminals, and wearable terminals can be applied.
  • Examples of information terminals other than smartphones, desktop information terminals, and wearable terminals include PDAs (Personal Digital Assistants), notebook-type information terminals, and workstations.
  • FIG. 20 shows an electric freezer / refrigerator 5800 as an example of an electric appliance.
  • the electric freezer / refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the power consumption of the electric freezer / refrigerator 5800 can be reduced.
  • an electric refrigerator / freezer has been described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH (Induction Heating) cooker, a water server, and an air conditioner.
  • air conditioners including air conditioners, washing machines, dryers, and audiovisual equipment.
  • FIG. 20 shows a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 has a housing 5201, a display unit 5202, a button 5203, and the like.
  • FIG. 20 shows a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can be provided with a display unit for displaying a game image, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a slide type knob, and the like.
  • the controller 7522 is not limited to the shape shown in FIG. 20, and the shape of the controller 7522 may be variously changed according to the genre of the game.
  • a controller shaped like a gun can be used by using a trigger as a button.
  • a controller having a shape imitating a musical instrument, a music device, or the like can be used.
  • the stationary game machine may be in a form in which a controller is not used, and instead, a camera, a depth sensor, a microphone, and the like are provided and operated by the gesture and / or voice of the game player.
  • the above-mentioned video of the game machine can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • a display device such as a television device, a personal computer display, a game display, or a head-mounted display.
  • the semiconductor device described in the above embodiment By applying the semiconductor device described in the above embodiment to the portable game machine 5200, it is possible to realize the portable game machine 5200 with low power consumption. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • FIG. 20 illustrates a portable game machine as an example of a game machine, but the electronic device of one aspect of the present invention is not limited to this.
  • Examples of the electronic device of one aspect of the present invention include a stationary game machine for home use, an arcade game machine installed in an entertainment facility (game center, amusement park, etc.), and a pitching machine for batting practice installed in a sports facility. Machines and the like.
  • the semiconductor device described in the above embodiment can be applied to an automobile which is a moving body and around the driver's seat of the automobile.
  • FIG. 20 shows an automobile 5700 which is an example of a moving body.
  • an instrument panel that can display speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, etc. Further, a display device for displaying such information may be provided around the driver's seat.
  • the semiconductor device described in the above embodiment can be applied to the above-mentioned instrument panel, image pickup device, and the like. Therefore, it is possible to reduce the power consumption of the instrument panel, the image pickup device, and the like provided in the automobile 5700. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • the automobile is described as an example of the moving body, but the moving body is not limited to the automobile.
  • examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the semiconductor device of one aspect of the present invention is applied to these moving objects. Therefore, the power consumption can be reduced.
  • FIG. 20 shows a digital camera 6240, which is an example of an imaging device.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation button 6243, a shutter button 6244, and the like, and a removable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 has a configuration in which the lens 6246 can be removed from the housing 6241 and replaced here, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured so that a strobe device, a viewfinder, and the like can be separately attached.
  • a low power consumption digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment to the image pickup apparatus included in the digital camera 6240. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • Video camera The semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 20 shows a video camera 6300, which is an example of an imaging device.
  • the video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation key 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation key 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by a connecting portion 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connecting portion 6306. be.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 on the connecting unit 6306.
  • the video camera 6300 has an imaging device like the digital camera 6240. Therefore, the low power consumption video camera 6300 can be realized by applying the semiconductor device described in the above embodiment to the image pickup device included in the video camera 6300. Further, since the heat generation from the circuit can be reduced due to the low power consumption, the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be reduced.
  • AM Storage unit

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Thin Film Transistor (AREA)
  • Amplifiers (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/IB2021/050568 2020-02-07 2021-01-26 半導体装置、及び撮像装置 Ceased WO2021156700A1 (ja)

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CN202180013110.XA CN115053514A (zh) 2020-02-07 2021-01-26 半导体装置及摄像装置
US17/796,916 US12363991B2 (en) 2020-02-07 2021-01-26 Semiconductor device and imaging device
KR1020227029933A KR102959950B1 (ko) 2020-02-07 2021-01-26 반도체 장치 및 촬상 장치
JP2021575094A JP7693562B2 (ja) 2020-02-07 2021-01-26 半導体装置、及び撮像装置
JP2025093865A JP2025126183A (ja) 2020-02-07 2025-06-05 トランジスタ
US19/259,822 US20260013205A1 (en) 2020-02-07 2025-07-03 Semiconductor Device and Imaging Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12525576B2 (en) 2020-03-13 2026-01-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12362732B2 (en) 2019-11-29 2025-07-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
JP7801325B2 (ja) 2021-05-27 2026-01-16 株式会社半導体エネルギー研究所 半導体装置、表示装置、及び電子機器
US12598985B2 (en) * 2023-01-04 2026-04-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and forming method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013009311A (ja) * 2011-05-20 2013-01-10 Semiconductor Energy Lab Co Ltd 半導体装置
JP2016140054A (ja) * 2014-08-29 2016-08-04 株式会社半導体エネルギー研究所 撮像装置および電子機器
JP2016208515A (ja) * 2015-04-22 2016-12-08 株式会社半導体エネルギー研究所 撮像装置、撮像装置の駆動方法および電子機器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1331627B1 (en) * 2002-01-24 2012-04-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving the semiconductor device
JP5820336B2 (ja) 2011-05-20 2015-11-24 株式会社半導体エネルギー研究所 半導体装置
US9246476B2 (en) 2013-05-10 2016-01-26 Semiconductor Energy Laboratory Co., Ltd. Driver circuit
KR102211966B1 (ko) * 2013-10-14 2021-02-15 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이를 포함하는 유기 발광 표시 장치
US9537478B2 (en) 2014-03-06 2017-01-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10332446B2 (en) * 2015-12-03 2019-06-25 Innolux Corporation Driving circuit of active-matrix organic light-emitting diode with hybrid transistors
US11887537B2 (en) * 2015-12-03 2024-01-30 Innolux Corporation Driving circuit of active-matrix organic light-emitting diode with hybrid transistors
KR102305442B1 (ko) * 2017-03-30 2021-09-28 삼성디스플레이 주식회사 화소 및 이를 포함하는 유기 발광 표시 장치
US10490128B1 (en) * 2018-06-05 2019-11-26 Apple Inc. Electronic devices having low refresh rate display pixels with reduced sensitivity to oxide transistor threshold voltage
US11296701B2 (en) 2018-10-25 2022-04-05 Semiconductor Energy Laboratory Co., Ltd. Single-polarity level shifter circuit and semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013009311A (ja) * 2011-05-20 2013-01-10 Semiconductor Energy Lab Co Ltd 半導体装置
JP2016140054A (ja) * 2014-08-29 2016-08-04 株式会社半導体エネルギー研究所 撮像装置および電子機器
JP2016208515A (ja) * 2015-04-22 2016-12-08 株式会社半導体エネルギー研究所 撮像装置、撮像装置の駆動方法および電子機器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12525576B2 (en) 2020-03-13 2026-01-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device

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