WO2021156378A1 - Procédé de fabrication d'un dispositif électronique comportant au moins une zone supraconductrice et dispositif associé - Google Patents
Procédé de fabrication d'un dispositif électronique comportant au moins une zone supraconductrice et dispositif associé Download PDFInfo
- Publication number
- WO2021156378A1 WO2021156378A1 PCT/EP2021/052684 EP2021052684W WO2021156378A1 WO 2021156378 A1 WO2021156378 A1 WO 2021156378A1 EP 2021052684 W EP2021052684 W EP 2021052684W WO 2021156378 A1 WO2021156378 A1 WO 2021156378A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- zone
- layer
- substrate
- superconducting
- sublayer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 20
- 230000008021 deposition Effects 0.000 claims description 14
- 229910021521 yttrium barium copper oxide Inorganic materials 0.000 claims description 10
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 8
- 229910052729 chemical element Inorganic materials 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 20
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- -1 oxygen ions Chemical class 0.000 description 4
- 229910052788 barium Inorganic materials 0.000 description 3
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052727 yttrium Inorganic materials 0.000 description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 125000002091 cationic group Chemical group 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910002076 stabilized zirconia Inorganic materials 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/80—Constructional details
- H10N60/81—Containers; Mountings
- H10N60/815—Containers; Mountings for Josephson-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0268—Manufacture or treatment of devices comprising copper oxide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0268—Manufacture or treatment of devices comprising copper oxide
- H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
- H10N60/0688—Etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
Definitions
- the present invention relates to a method of manufacturing an electronic device, the electronic device comprising at least one superconducting zone and at least one insulating zone according to a predefined arrangement.
- the present invention also relates to an electronic device capable of being obtained by such a method.
- a superconducting material exhibits zero resistance under certain temperature conditions.
- An electronic device made with components having layers made of such a material therefore exhibits particularly advantageous electrical performance.
- the development of electronic devices involves different types of etching, in particular to obtain tracks or electrodes.
- the engravings are in particular chemical or ionic.
- the devices obtained by this technique exhibit reduced performance when these devices are exposed to temperatures greater than or equal to 80 ° C.
- the present description relates to a method of manufacturing an electronic device, the electronic device comprising at least one superconducting zone and at least one insulating zone according to a predefined arrangement, the method comprising at least minus the steps of depositing a first layer on at least part of a substrate, the first layer being a buffer layer, of etching the first layer according to the predefined arrangement to obtain at least a first zone and at least one second area, each first area being an area in which the substrate is covered by the first layer and each first area being intended to form a respective superconducting area, each second area being an area in which the substrate is exposed and each second area being intended in forming a respective insulating zone, and depositing a second layer on the whole of the substrate part, the second layer being made of a superconductive material, in which the first layer is produced in the form of at least two sublayers superimposed.
- the manufacturing process comprises one or more of the following characteristics, taken in isolation or according to all the technically possible combinations:
- the substrate is made of a material, the superconducting material comprising a plurality of chemical elements, the material of the substrate being a material in which at least one chemical element of the superconducting material diffuses into the material of the substrate when the two materials are in contact and brought to a temperature greater than or equal to 200 ° C., the material of the substrate being in particular Si or GaAs.
- the superconducting material is a cuprate, preferably a material chosen from the list consisting of YBCO, NdBaCuO, GdBaCuO, BiSrCaCuO and TICaBaCuO.
- each sub-layer of the first layer is made of a material chosen from the list consisting of YSZ, Ce0 2 , zirconia, MgAI 2 04, BaTiOs, MgO, AI2O3, AIN and SrTi0 3 .
- the material of the substrate is Si
- the material of the first sublayer is YSZ
- the material of the second sublayer is Ce0 2
- the superconducting material is a cuprate.
- the material of the substrate is Si
- the material of the first sublayer is SrTi0 3
- the material of the second sublayer is Ce0 2
- the superconducting material is a cuprate.
- the material of the substrate is GaAs
- the material of the first sublayer is MgO
- the material of the second sublayer is CeO 2
- the superconducting material is a cuprate.
- the electronic device is a Josephson junction, the predefined arrangement comprising two superconducting zones and an insulating zone intended to form a barrier zone having a maximum dimension along a direction connecting the two superconducting zones less than or equal to 60 nanometers.
- the first layer has a thickness between 10 nanometers and 80 nanometers.
- the thickness of the second layer is between 3 nanometers and 50 nanometers.
- each superconducting zone is a track.
- This description relates to an electronic device that can be obtained by the manufacturing process as described above.
- FIG. 3 a schematic perspective representation of a cross section of an example of an assembly obtained at the end of the implementation of the second step of the manufacturing process of the first example of an electronic device
- the manufacturing process aims to obtain an electronic device comprising at least one superconducting zone and at least one insulating zone according to a predefined arrangement.
- the layout is the spatial organization of each of the zones.
- it is desired to obtain a first electronic device comprising two parallel superconducting tracks separated by an insulating zone.
- the arrangement is an arrangement in the form of five contiguous bands.
- the five bands are successively a first insulating zone, a first superconducting zone forming a track, a second insulating zone, a second superconducting zone forming another track and a third insulating zone.
- the manufacturing process comprises three steps which are a step of depositing a first layer E1, a step of etching E2 and a step of depositing a second layer E3.
- the substrate 10 is made of silicon (Si).
- a first layer 12 is deposited on at least part of the substrate 10.
- the step of depositing a first layer E1 makes it possible to obtain the whole of the substrate. figure 2.
- the portion of the substrate 10 is a portion having a sufficiently large extent to enable the predefined arrangement to be made within the portion of the substrate 10.
- the first layer 12 is a buffer layer.
- buffer layer it is understood that the first layer 12 is made to allow insulation between the substrate 12 and a superconducting material, the buffer layer preventing contact between the two materials.
- the first layer 12 is produced in the form of two superimposed sublayers, a first sublayer 14 and a second sublayer 16.
- the first sublayer 14 is arranged between the substrate 10 and the second sublayer 16.
- the first sublayer 14 is in YSZ and the second sublayer 16 in CeC> 2.
- YSZ is yttrium stabilized zirconia.
- the first layer 12 has a thickness of between 10 nanometers (nm) and 80 nm.
- the thickness of a layer is measured in a direction corresponding to the direction of stacking of the layers.
- Other embodiments can however be envisaged for obtaining a first layer 12 forming a buffer layer.
- the first layer 12 is formed of a single sub-layer.
- each sub-layer 14 or 16 of the first layer 12 may be different from the aforementioned materials.
- each sublayer 14 or 16 is chosen from MgO or SrTiC> 3 .
- each sublayer 14 or 16 forming the first layer 12 is made of a material chosen from the list consisting of YSZ, CeC> 2 , zirconia, MgAI 2 C> 4, BaTiC> 3 , MgO, AIN and SrTi0 3 .
- the etching step E2 is then implemented.
- the etching step E2 is an etching step of the first layer 12 according to the predefined arrangement in the substrate part 10.
- Etching is, for example, chemical etching.
- the engraving is an ionic engraving.
- the predefined arrangement is then an engraving pattern.
- Such an etching step E2 makes it possible to obtain at least a first zone Z1 and at least a second zone Z2.
- Each first zone Z1 is a non-etched zone.
- each first zone Z1 is an area in which the substrate 10 is covered by the whole of the first layer 12.
- Each first zone Z1 is intended to form a respective superconducting zone.
- Each second zone Z2 is an engraved zone.
- Each second zone Z2 is a zone in which the substrate 10 is visible.
- Each second zone Z2 is a zone intended to form a respective insulating zone.
- the engraving pattern is a set of bands. More precisely, the engraving pattern is a set of three bands to be engraved. The first band and the second band delimits a band not to be burned (first track) and the second band and the third band delimit another band not to be burned (second track).
- the bands not to be etched are thus delimited by walls extending perpendicularly to the plane of the substrate 10. Such walls are called vertical walls hereinafter.
- an assembly is thus obtained comprising successively a second zone Z2, a first zone Z1, a second zone Z2, a first zone Z1 and a second zone Z2.
- the second layer E3 deposition step or second E3 deposition step is then implemented.
- the deposition of the second layer E3 is carried out by a pulsed laser ablation technique or by a sputtering technique.
- the second layer 18 is deposited over the entire substrate portion 10.
- the second deposition step E3 is thus a full wafer deposition step.
- the second layer 18 deposited is made of a superconductive material.
- the superconducting material is a high critical temperature superconducting material, that is, a superconducting material with a critical temperature greater than or equal to 40K.
- the superconducting material is YBa2Cu307- x .
- YBa 2 Cu 3 C> 7-x denotes a mixed oxide of barium, copper and yttrium.
- the terms “YBaCuO” and “YBCO” are also used to designate such an oxide.
- YBCO exhibits a critical temperature of 90K when the cationic and oxygen content are optimal.
- the superconducting material chosen is NdBaCuO, GdBaCuO, BiSrCaCuO or TICaBaCuO.
- the superconducting material is a cuprate.
- a cuprate is a chemical compound in which copper forms an anion or a complex whose overall charge is negative.
- the thickness of the second layer 18 deposited is between 3 nm and 50 nm.
- each first zone Z1 the superconducting material is in contact with the material of the second sublayer 16, in this case CeC> 2. No reaction takes place between the two materials.
- each first zone Z1 becomes a superconducting zone 20 corresponding to one of the tracks desired for the device to be manufactured.
- the YBCO deposited on the CeC> 2 will be superconducting at high temperatures (that is to say a temperature of the order of 90K in particular if the oxygen content is optimal as explained previously for the case of l 'YBCO)
- the superconducting material is also deposited on the vertical walls.
- the superconducting material loses its superconducting properties during deposition.
- At least one chemical element of the superconducting material diffuses into the material of the substrate 10 when the two materials are in contact.
- the barium diffuses into the substrate 10.
- the compound Ba2SiC> 4 which is an insulator is then formed while the YBCO will see its barium content decrease until the YBCO becomes an insulator.
- Each second zone Z2 thus becomes an insulating zone 22 corresponding to an insulating zone for the device to be manufactured.
- the desired electronic device is thus obtained, namely two isolated superconducting tracks.
- a resistivity of 69 Ohm.m was measured in the insulating zone 22 between the two superconducting zones 20. Such a value is 10,000 times greater than the resistivity in one of the superconducting zones 20.
- the method is relatively simple to implement insofar as the deposition of the second layer 18 results in self-functionalization of the second layer 18.
- the superconducting zones 20 separated by the insulating zones 22 are, in fact, formed without carrying out any etching of the second layer 18 which is a superconducting layer.
- the manufacturing process guarantees good insulation between the different superconducting zones 20 made on the functionalized substrate 10 over the entire temperature range, and excellent performance of the superconducting zones 20, since the superconducting regions are not modified by etching. ionic.
- the performance of devices manufactured by the method is thus increased.
- the process is robust at high temperature.
- the described method is a method of manufacturing an electronic device having superconductive regions which is more robust to heating.
- the method can also be used to form numerous devices based on superconductors.
- the method makes it possible to manufacture a Josephson junction based on YBCO on a silicon substrate 10.
- the predefined arrangement comprises two superconducting zones R1, R2 (also called reservoir) and an insulating zone R3 intended to form a barrier zone between the two superconducting zones R1 and R2.
- Such an arrangement also corresponds to a superconducting track formed of the two superconducting zones R1 and R2 interrupted at a slot corresponding to the insulating zone R3.
- the insulating zone R3 has a maximum dimension along a direction connecting the two superconducting zones less than or equal to 60 nm.
- the minimum distance between the two superconducting zones R1 and R2 (defined as the minimum distance between two points of these two zones) is less than or equal to 60 nm.
- the slit between the two superconducting zones R1 and R2 has a size of between 10 nm and 30 nm (in the broad sense, the terminals being included).
- the method involves the etching of the desired pattern, sizes less than or equal to 60 nm being accessible to the aforementioned etching techniques.
- the first areas R1 and R2 are in the form of a mesa. Then, the superconducting layer 18 is deposited.
- the insulating zone R3 is formed by the reaction of the superconducting layer 18 with the substrate 10.
- the manufacturing process thus allows the realization of Josephson junctions which are not altered by a posterior annealing of the devices, allowing an operational range of temperatures higher than that of the junctions produced by irradiation with oxygen ions.
- the property of reaction between the material of the substrate 10 and the superconducting material is advantageously used.
- the manufacturing process makes it possible in each case to be robust against heating the devices to temperatures above 80 ° C, unlike techniques involving irradiation with oxygen ions.
- the method can be used for any substrate material 10 in which at least one chemical element of the superconducting material diffuses into the material of the substrate when the two materials are in contact and brought to a temperature greater than or equal to 200 ° C.
- the material of the substrate can also be gallium arsenide (GaAs).
- the material of the substrate 10 is Si
- the material of the first sublayer 14 is YSZ
- the material of the second sublayer. 16 is CeC> 2
- the superconducting material is cuprate.
- the material of the substrate 10 is Si
- the material of the first sublayer 14 is of SrTiC> 3
- the material of the second sublayer 16 is CeC> 2
- the superconducting material is a cuprate.
- the material of the second sublayer 16 is MgAI 2 C> 4 , GAIN, MgO, BaTiC> 3, zirconia or GAI2O 3.
- the manufacturing process is a manufacturing process in which the material of the substrate 10 is GaAs, the material of the first sublayer 14 is MgO, the material of the second sublayer 16 is CeO 2 and the superconducting material is a cuprate.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2021217549A AU2021217549A1 (en) | 2020-02-05 | 2021-02-04 | Method for manufacturing an electronic device comprising at least one superconductive zone and associated device |
EP21702682.2A EP4101011A1 (fr) | 2020-02-05 | 2021-02-04 | Procédé de fabrication d'un dispositif électronique comportant au moins une zone supraconductrice et dispositif associé |
US17/797,794 US20230051835A1 (en) | 2020-02-05 | 2021-02-04 | Method for manufacturing an electronic device comprising at least one superconductive zone and associated device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2001126A FR3106935B1 (fr) | 2020-02-05 | 2020-02-05 | Procede de fabrication d'un dispositif electronique comportant au moins une zone supraconductrice et dispositif associe |
FRFR2001126 | 2020-02-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2021156378A1 true WO2021156378A1 (fr) | 2021-08-12 |
Family
ID=71994562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2021/052684 WO2021156378A1 (fr) | 2020-02-05 | 2021-02-04 | Procédé de fabrication d'un dispositif électronique comportant au moins une zone supraconductrice et dispositif associé |
Country Status (5)
Country | Link |
---|---|
US (1) | US20230051835A1 (fr) |
EP (1) | EP4101011A1 (fr) |
AU (1) | AU2021217549A1 (fr) |
FR (1) | FR3106935B1 (fr) |
WO (1) | WO2021156378A1 (fr) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090131262A1 (en) * | 2006-07-14 | 2009-05-21 | Xun Zhang | Method of forming a multifilament ac tolerant conductor with striated stabilizer, articles related to the same, and devices incorporating the same |
US20160163424A1 (en) * | 2013-11-12 | 2016-06-09 | Varian Semiconductor Equipment Associated, Inc. | Integrated superconductor device and method of fabrication |
-
2020
- 2020-02-05 FR FR2001126A patent/FR3106935B1/fr active Active
-
2021
- 2021-02-04 WO PCT/EP2021/052684 patent/WO2021156378A1/fr unknown
- 2021-02-04 EP EP21702682.2A patent/EP4101011A1/fr active Pending
- 2021-02-04 US US17/797,794 patent/US20230051835A1/en active Pending
- 2021-02-04 AU AU2021217549A patent/AU2021217549A1/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090131262A1 (en) * | 2006-07-14 | 2009-05-21 | Xun Zhang | Method of forming a multifilament ac tolerant conductor with striated stabilizer, articles related to the same, and devices incorporating the same |
US20160163424A1 (en) * | 2013-11-12 | 2016-06-09 | Varian Semiconductor Equipment Associated, Inc. | Integrated superconductor device and method of fabrication |
Also Published As
Publication number | Publication date |
---|---|
FR3106935B1 (fr) | 2022-01-14 |
AU2021217549A1 (en) | 2022-09-15 |
US20230051835A1 (en) | 2023-02-16 |
EP4101011A1 (fr) | 2022-12-14 |
FR3106935A1 (fr) | 2021-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0170544A1 (fr) | Procédé d'autopositionnement d'une ligne d'interconnexion sur un trou de contact électrique d'un circuit intégré | |
FR2566179A1 (fr) | Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement | |
FR2633101A1 (fr) | Photodiode et matrice de photodiodes sur hgcdte et leurs procedes de fabrication | |
EP0159931B1 (fr) | Procédé de fabrication de zones d'isolation électrique des composants d'un circuit intégré | |
EP3127142B1 (fr) | Procédé de fabrication d'une plaque de semi-conducteur adaptée pour la fabrication d'un substrat soi, et plaque de substrat soi ainsi obtenue | |
WO2013149964A1 (fr) | Structure semiconductrice optoelectronique a nanofils et procede de fabrication d'une telle structure | |
FR2910456A1 (fr) | Procede de realisation de microfils et/ou de nanofils | |
EP3531444A1 (fr) | Circuit intégré comprenant un substrat équipé d'une région riche en pièges, et procédé de fabrication | |
FR2675951A1 (fr) | Structure de jonction josephson. | |
EP1483793B1 (fr) | Diode schottky de puissance a substrat sicoi, et procede de realisation d'une telle diode | |
FR2625613A1 (fr) | ||
EP0577498B1 (fr) | Transistor JFET vertical à mode de fonctionnement bipolaire optimisé et procédé de fabrication correspondant | |
FR2625612A1 (fr) | Procede de realisation d'un dispositif semiconducteur du type transistor bipolaire a heterojonction | |
WO2021156378A1 (fr) | Procédé de fabrication d'un dispositif électronique comportant au moins une zone supraconductrice et dispositif associé | |
EP0913002B1 (fr) | Detecteur infrarouge bicolore a coherence spatio-temporelle planaire | |
EP0206929B1 (fr) | Procédé de fabrication d'un circuit intégré et notamment d'une mémoire eprom comportant deux composants distincts isolés électriquement | |
EP2432033A2 (fr) | Détecteur bispectral multicouche à photodiodes | |
EP1433206B1 (fr) | Transistor a un electron et a canal vertical, et procedes de realisation d'un tel transistor | |
EP0675544B1 (fr) | Procédé de fabrication d'un transistor à effet de champ à grille isolée de longueur de canal réduite, et transistor correspondant | |
EP0420322B1 (fr) | Procédé de réalisation d'un circuit semiconducteur intégré incluant un transistor bipolaire à hétérojonction et/ou des résistances enterrées | |
EP0951067A1 (fr) | Circuit intégré avec couche d'arrêt et procédé de fabrication associé | |
JPH104223A (ja) | 酸化物超電導体ジョセフソン素子 | |
FR2805924A1 (fr) | Procede de gravure d'une couche de silicium polycristallin et son application a la realisation d'un emetteur auto- aligne avec la base extrinseque d'un transistor bipolaire simple ou double polysilicium | |
EP4006997B1 (fr) | Procédé de réalisation d'un dispositif quantique | |
FR2687012A1 (fr) | Dispositif josephson et son procede de fabrication. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21702682 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 2021702682 Country of ref document: EP Effective date: 20220905 |
|
ENP | Entry into the national phase |
Ref document number: 2021217549 Country of ref document: AU Date of ref document: 20210204 Kind code of ref document: A |