WO2021147082A1 - Substrat d'affichage et son procédé de préparation - Google Patents

Substrat d'affichage et son procédé de préparation Download PDF

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Publication number
WO2021147082A1
WO2021147082A1 PCT/CN2020/073995 CN2020073995W WO2021147082A1 WO 2021147082 A1 WO2021147082 A1 WO 2021147082A1 CN 2020073995 W CN2020073995 W CN 2020073995W WO 2021147082 A1 WO2021147082 A1 WO 2021147082A1
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WO
WIPO (PCT)
Prior art keywords
layer
display area
light
electrode
display
Prior art date
Application number
PCT/CN2020/073995
Other languages
English (en)
Chinese (zh)
Inventor
黄炜赟
邱远游
肖星亮
黄耀
刘聪
王彬艳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/073995 priority Critical patent/WO2021147082A1/fr
Priority to CN202080000249.6A priority patent/CN113439338A/zh
Priority to CN202010130251.7A priority patent/CN111326560B/zh
Priority to EP20891410.1A priority patent/EP4095921A4/fr
Priority to KR1020217038802A priority patent/KR20220129999A/ko
Priority to CN202080000311.1A priority patent/CN113508466A/zh
Priority to PCT/CN2020/080182 priority patent/WO2021147160A1/fr
Priority to JP2022502521A priority patent/JP2023520267A/ja
Priority to US17/297,641 priority patent/US11968865B2/en
Priority to PCT/CN2021/073243 priority patent/WO2021147987A1/fr
Priority to US17/428,847 priority patent/US11980071B2/en
Publication of WO2021147082A1 publication Critical patent/WO2021147082A1/fr
Priority to US18/390,381 priority patent/US20240172497A1/en
Priority to US18/396,840 priority patent/US20240138214A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a preparation method thereof.
  • display screens used in electronic devices are developing towards larger screens and full screens, so as to enable users to have a better visual experience.
  • these electronic devices need to incorporate components such as cameras and light sensors, and these components usually occupy the display area of the display screen, which makes it difficult to realize a full-screen design for the display screen.
  • At least one embodiment of the present disclosure provides a display substrate including a first side for display and a second side opposite to the first side, the display substrate including: a display area, wherein the The display area includes a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side to be at least partially transmitted to the second side;
  • the display substrate further includes at least one first connection trace in the first display area and the second display area, wherein the first connection trace includes a first portion located in the first display area that is electrically connected to each other And a second portion located in the second display area, the first portion including a first light-transmitting wiring layer; wherein, the first display area includes a plurality of first sub-pixels arranged in an array, each of the first sub-pixels It includes a first light emitting device, the first light emitting device includes a first electrode structure, a second electrode structure, and a first light emitting layer between the first electrode structure and the second electrode structure, the first electrode The structure includes a
  • the at least one first connection trace includes a plurality of first connection traces;
  • the second display area includes a plurality of first pixel circuits, and the plurality of The first pixel circuit is respectively electrically connected to the first electrode structures of the plurality of first light-emitting devices through the plurality of first connecting wires, so as to drive the plurality of first light-emitting devices.
  • the second portion includes a second light-transmitting wiring layer, and the second light-transmitting wiring layer is provided in the same layer as the first light-transmitting wiring layer And one-piece connection.
  • the display substrate includes a base substrate, the second light-transmitting wiring layer and the first electrode sublayer are located on the base substrate, and the The second part further includes a first metal wiring layer located on a side of the second light-transmitting wiring layer away from the base substrate, and the first electrode structure further includes a first electrode sublayer located away from the first metal wiring layer.
  • the second electrode sublayer on one side of the base substrate, the second electrode sublayer and the first metal wiring layer are arranged in the same layer.
  • the second part further includes an anti-oxidation protection layer on the side of the first metal wiring layer away from the base substrate, and the first electrode structure It also includes a third electrode sublayer located on a side of the second electrode sublayer away from the base substrate, and the third electrode sublayer is provided in the same layer as the anti-oxidation protection layer.
  • the first electrode structure is a first anode structure
  • the second electrode structure is a first cathode structure
  • the material of the first electrode sublayer includes indium oxide.
  • Tin, the material of the second electrode sublayer includes silver or silver alloy, and the material of the third electrode sublayer includes indium tin oxide.
  • the second portion includes a second metal wiring layer, and the second metal wiring layer and the first light-transmitting wiring layer are arranged in different layers and pass through Via electrical connection.
  • the second display area further includes a plurality of second sub-pixels, and each second sub-pixel includes a second light-emitting device and is electrically connected to the second light-emitting device.
  • the second pixel circuit is configured to drive the second light-emitting device, and in the second display area, the plurality of second pixel circuits are arranged in a first array.
  • the plurality of first pixel circuits are dispersedly arranged in the first array and are connected to the plurality of second pixels.
  • the circuit is arranged in a second array.
  • the second light emitting device includes a second anode structure, a second cathode structure, and a second light emitting device between the second anode structure and the second cathode structure.
  • Layer, the second anode structure is electrically connected to the second pixel circuit through a via hole.
  • the display area further includes a third display area at least partially surrounding the second display area, and the third display area includes a plurality of third display areas arranged in an array.
  • each third sub-pixel includes a third light-emitting device and a third pixel circuit electrically connected to the third light-emitting device, the third pixel circuit is configured to drive the third light-emitting device, the third The light emitting device includes a third anode structure, a third cathode structure, and a third light emitting layer between the third anode structure and the third cathode structure, and the third anode structure is connected to the third pixel circuit through a via hole. Electric connection.
  • the display substrate includes a base substrate, the first display area further includes a transparent support layer on the base substrate, and the first light-emitting device is located The side of the transparent support layer away from the base substrate.
  • the first pixel circuit includes a thin film transistor and a storage capacitor, and the thin film transistor includes an active layer, a gate, and a source and drain electrode;
  • the storage capacitor includes a first A capacitor plate and a second capacitor plate, the active layer is arranged on the base substrate, a first gate insulating layer is arranged on the side of the active layer away from the base substrate, and the gate
  • the electrode and the first capacitor plate are arranged in the same layer on the side of the first gate insulating layer away from the base substrate, and the gate and the first capacitor plate are away from the base substrate
  • a second gate insulation layer is provided on one side of the second gate insulation layer, the second capacitor plate is provided on the side of the second gate insulation layer away from the base substrate, and the second capacitor plate is away from the liner
  • An interlayer insulating layer is provided on one side of the base substrate, and the source and drain electrodes are provided on the side of the interlayer insulating layer away from the base substrate and pass through the first gate
  • the gate insulating layer and the vias in the interlayer insulating layer are electrically connected to the active layer, and the source and drain electrodes are provided with a planarization layer on the side away from the base substrate; the transparent support layer is connected to At least one of the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the planarization layer is provided in the same layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a sensor, wherein the sensor is disposed on the second side of the display substrate, and the orthographic projection of the sensor on the base substrate is consistent with the first A display area at least partially overlaps and is configured to receive light from the first side.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, the display substrate having a first side for display and a second side opposite to the first side, and the preparation method includes: forming a display area, The display area includes a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side to be at least partially transmitted to the second side; At least one first connection trace is formed in the first display area and the second display area, wherein the first connection trace includes a first portion located in the first display area and a second portion located in the second display area that are electrically connected to each other.
  • a second part of the display area where the first part includes a first light-transmitting wiring layer; a plurality of first sub-pixels arranged in an array are formed in the first display area, and each first sub-pixel includes a first light-emitting device ,
  • the first light emitting device includes a first electrode structure, a second electrode structure, and a first light emitting layer between the first electrode structure and the second electrode structure, and the first electrode structure includes a first electrode A sub-layer, the first electrode sub-layer and the first light-transmitting wiring layer are formed in the same layer and electrically connected.
  • the at least one first connection trace includes a plurality of first connection traces; the preparation method further includes: forming a substrate in the second display area.
  • a plurality of first pixel circuits, and the plurality of first pixel circuits are respectively electrically connected to the first electrode structures of the plurality of first light-emitting devices through the plurality of first connecting wires, so as to drive the plurality of first pixel circuits.
  • Light emitting device is not limited to the first electrode structures of the plurality of first light-emitting devices.
  • forming the second part of the first connection trace includes: forming a second light-transmitting wiring layer, and the second light-transmitting wiring layer is connected to the The first light-transmitting wiring layer is formed in the same layer and connected integrally.
  • the method for preparing a display substrate further includes: providing a base substrate, wherein the second light-transmitting wiring layer and the first electrode sublayer are formed on the base substrate , Forming the second part of the first connection trace further includes: forming a first metal trace layer on a side of the second light-transmitting trace layer away from the base substrate, and forming a first metal trace layer on the first electrode A second electrode sublayer is formed on the side of the layer away from the base substrate, and the second electrode sublayer is formed in the same layer as the first metal wiring layer.
  • forming the second part of the first connection trace further includes: on the side of the first metal trace layer away from the base substrate An anti-oxidation protection layer is formed, a third electrode sub-layer is formed on the side of the second electrode sub-layer away from the base substrate, and the third electrode sub-layer is formed in the same layer as the anti-oxidation protection layer.
  • forming the first connection trace and the first electrode structure includes: using a mask in the first display area and the second display area.
  • the first electrode material layer, the second electrode material layer, and the third electrode material layer are sequentially deposited in the display area; at least part of the third electrode material layer and part of the second electrode located in the first display area are etched away using the first wet etching process Material layer; using a second wet etching process to etch away the remaining second electrode material layer located in the part of the first display area.
  • forming the first pixel circuit includes forming a thin film transistor and a storage capacitor, and the thin film transistor includes an active layer, a gate, and a source and drain electrode;
  • the storage capacitor includes a first capacitor plate and a second capacitor plate, wherein the active layer is formed on a base substrate, and a first gate insulation is formed on the side of the active layer away from the base substrate.
  • the same layer of the gate and the first capacitor plate is formed on the side of the first gate insulating layer away from the base substrate, and is formed on the side of the gate and the first capacitor plate.
  • a second gate insulating layer is formed on the side away from the base substrate, and the second capacitor plate is formed on the side of the second gate insulating layer away from the base substrate.
  • An interlayer insulating layer is formed on the side of the board away from the base substrate, and the source and drain electrodes are formed on the side of the interlayer insulating layer away from the base substrate and pass through the first gate insulating layer.
  • the via holes in the second gate insulating layer and the interlayer insulating layer are electrically connected to the active layer, and a planarization layer is formed on the side of the source and drain electrodes away from the base substrate; forming The first display area further includes: forming a transparent support layer between the base substrate and the first light-emitting device, wherein the transparent support layer is connected to the first gate insulating layer and the second gate At least one of the insulating layer, the interlayer insulating layer, and the planarization layer is formed in the same layer.
  • the method for preparing a display substrate further includes: providing a sensor, and combining the sensor on the second side of the display substrate, wherein the sensor is on the base substrate.
  • the orthographic projection at least partially overlaps the first display area, and is configured to receive the light from the first side.
  • Fig. 1A is a schematic plan view of a display substrate
  • Fig. 1B is a partial enlarged schematic diagram of a display substrate
  • FIG. 2 is a schematic cross-sectional view of the display substrate in FIG. 1B along the line A-A;
  • FIG. 3 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional view of the display substrate in FIG. 3 along the line B-B;
  • FIG. 5 is a schematic plan view of a first display area and a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • Fig. 6 is another schematic cross-sectional view of the display substrate in Fig. 3 along the line B-B;
  • FIG. 7 is another schematic cross-sectional view of the display substrate in FIG. 3 along the line B-B;
  • FIG. 8 is another schematic plan view of a first display area and a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 9 is a schematic plan view of the arrangement of sub-pixels in a display area of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic plan view of a wiring arrangement in a display area of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 11 is another schematic plan view of wiring arrangement in a display area of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 12 is still another schematic plan view of the first display area and the second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 13 is a schematic cross-sectional view of a second display area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 14 is a schematic cross-sectional view of a third display area in a display substrate provided by at least one embodiment of the present disclosure
  • 15A-15B are schematic cross-sectional views of a display substrate provided by at least one embodiment of the present disclosure during the manufacturing process;
  • FIG. 16 is a schematic cross-sectional view of another display substrate in the manufacturing process provided by at least one embodiment of the present disclosure.
  • FIG. 17 is another schematic plan view of the first display area and the second display area in a display substrate provided by at least one embodiment of the present disclosure.
  • part of the display area used to install the sensor (such as image sensor, infrared sensor) and other components can be designed as a light-transmitting display area, so the light-transmitting display area can be While realizing the display function, it also facilitates the installation of sensors and other components.
  • FIG. 1A shows a schematic plan view of a display substrate
  • FIG. 1B is a partial enlarged schematic view of the display substrate shown in FIG. 1A
  • FIG. 2 shows a schematic cross-sectional view of the display substrate in FIG. 1B along the line A-A.
  • the display area of the display substrate includes a light-transmitting display area 1, a peripheral display area 2 and a main body display area 3.
  • the main display area 3 is the main display area and has a higher resolution (PPI, Pixel Per Inch), that is, the main display area 3 is arranged with sub-pixels with higher density for display.
  • Each sub-pixel includes a light-emitting device and a pixel circuit that drives the light-emitting device.
  • the light-transmitting display area 1 may allow light incident from the display side of the display substrate to pass through the display substrate to reach the back side of the display substrate, so as to be used for normal operation of components such as sensors located on the back side of the display substrate.
  • the light-transmitting display area 1 and the peripheral display area 2 also include a plurality of sub-pixels for display.
  • the pixel circuit of the sub-pixel usually does not transmit light
  • the sub-pixels in the light-transmitting display area 1 (for example, shown in the box in the light-transmitting display area 1 in FIG. 1B)
  • the pixel circuit can be set in the peripheral display area 2, as shown by the gray box in the peripheral display area 2, so it occupies part of the space of the peripheral display area 2, and the remaining space of the peripheral display area 2 is used to set the peripheral display area 2.
  • each white box in the peripheral display area 2 represents a sub-pixel.
  • the sub-pixels in the peripheral display area 2 (white boxes in FIG.
  • the resolution of the transparent display area 1 and the peripheral display area 2 is lower than the resolution of the main display area 3. That is, the density of the sub-pixels arranged in the transparent display area 1 and the peripheral display area 2 for display is less than Sub-pixel density of the main display area 3.
  • the light-emitting device 4 of one sub-pixel in the light-transmitting display area 1 includes an anode 4A, a cathode 4C, and a light-emitting layer 4B between the anode 4A and the cathode 4C.
  • the anode 4A is connected to the peripheral display area by a conductive wire. 2 in the pixel circuit 5.
  • the conductive lead may be a metal lead, for example, it may be the same material as the source and drain electrode metal in the pixel circuit of the sub-pixel, or it may be a transparent wiring (such as an ITO wiring) 6 electrically connected to the peripheral display area 2
  • the pixel circuit 5, and thus the pixel circuit 5 located in the peripheral display area 2 can be used to drive the light emitting device 4 located in the light-transmitting display area 1. Since the transparent wiring 6 has high light transmittance, it can be ensured that the light transmitting display area 1 also has high light transmittance.
  • components such as the sensor 7 provided on the back side of the display substrate can receive the light transmitted from the display side of the display substrate through the light-transmitting display area 1 to perform normal operation.
  • the transparent wiring 6 needs to extend from the pixel circuit 5 in the peripheral display area 2 to the light-emitting device 4 in the light-transmitting display area 1. Therefore, at least part of the transparent wiring 6 has a longer length, for example, its length will be too long.
  • the distance between the two sub-pixel regions on the other hand, compared to the source and drain electrode materials, such as Ti/Al/Ti, or either one or a combination of the two; or other electrode materials, such as copper, molybdenum, magnesium, Silver or a combination of at least two materials, etc.
  • the material used for the transparent wiring 6 has a relatively high resistance, and its preparation process is prone to deviations, which makes the overall resistance of the transparent wiring 6 relatively large, so the pixel circuit 5 transmits electrical signals to the sub-pixels in the light-transmitting display area 1.
  • the speed is slow, causing the sub-pixels in the light-transmitting display area 1 to be driven out of sync with the sub-pixels in the peripheral display area 2 and the main display area 3, which affects the display effect of the display area.
  • a patterning process is usually used to form the transparent wiring 6, and then a patterning process is used to form the insulating layer 6A on the transparent wiring 6, and the insulating layer 6A is formed with via holes.
  • an anode 4A is formed on the insulating layer 6A, and the anode 4A is electrically connected to the transparent wiring 6 through the via hole in the insulating layer 6A.
  • This preparation process requires multiple patterning processes to form structures such as the transparent wiring 6 and the anode 4A, which complicates the preparation process.
  • At least one embodiment of the present disclosure provides a display substrate having a first side for display and a second side opposite to the first side, the display substrate including a display area, the display area including a first display area and at least The second display area partially surrounding the first display area, the first display area allows light from the first side to be at least partially transmitted to the second side; the display substrate further includes at least one of the first display area and the second display area A connecting trace, the first connecting trace includes a first portion located in the first display area and a second portion located in the second display area that are electrically connected to each other, the first portion includes a first light-transmitting wiring layer; the first display area includes A plurality of first sub-pixels arranged in an array, each of the first sub-pixels includes a first light-emitting device, the first light-emitting device includes a first electrode structure, a second electrode structure, and between the first electrode structure and the second electrode structure The first light-emitting layer, the first electrode structure includes a first electrode sub-layer, the first electrode sub-
  • At least one embodiment of the present disclosure provides a display substrate and a preparation method thereof.
  • the display substrate has a first side for display and a second side opposite to the first side.
  • the display substrate includes a display area, and the display area includes a first display. Area and a second display area at least partially surrounding the first display area, the first display area allows light from the first side to be at least partially transmitted to the second side;
  • the display substrate further includes At least one first connection trace, the first connection trace includes a first portion located in the first display area and a second portion located in the second display area that are electrically connected to each other, the first portion includes a first light-transmitting wiring layer, and the second Part includes metal wiring layer.
  • the first connection wiring in the display substrate has a relatively low resistance.
  • FIG. 3 shows a schematic plan view of the display substrate
  • FIG. 4 shows a schematic cross-sectional view of the display substrate along the line BB in FIG. 3
  • the display substrate has a first side for display (shown as the upper side of the display substrate in FIG. 4, that is, the display side of the display substrate) and a second side opposite to the first side. Side (shown as the lower side of the display substrate in FIG. 4).
  • the display substrate includes a display area, the display area includes a first display area 10 and a second display area 20 at least partially surrounding the first display area 10, and the first display area 10 allows light from the first side to be at least partially transmitted to the second display area.
  • the side, that is, the first display area 10 is at least partially light-transmissive, so as to facilitate the installation of image sensors, infrared sensors and other components.
  • the display substrate further includes at least one first connecting wire 15 in the first display area 10 and the second display area 20, and the first connecting wire 15 includes electrically connected to each other located in the first display area 10.
  • the material of the first light-transmitting wiring layer may be a transparent conductive material, such as transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO), and the material of the metal wiring layer may include silver (Ag), Metal materials such as aluminum (Al), molybdenum (Mo) or titanium (Ti) or their alloy materials. Since the resistance of the metal wiring layer is relatively low, the first connection wiring 15 may have a lower resistance than a wiring including only a light-transmitting wiring layer.
  • transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO)
  • the material of the metal wiring layer may include silver (Ag), Metal materials such as aluminum (Al), molybdenum (Mo) or titanium (Ti) or their alloy materials. Since the resistance of the metal wiring layer is relatively low, the first connection wiring 15 may have a lower resistance than a wiring including only a light-transmitting wiring layer.
  • the first display area 10 includes a plurality of first sub-pixels arranged in an array, each of the first sub-pixels includes a first light-emitting device 11, and the first light-emitting device 11 includes a first electrode.
  • the first electrode structure 111 includes a first electrode sublayer 111A, and the first electrode sublayer 111A is connected to the
  • the first light-transmitting wiring layer of the first part 15A is arranged in the same layer and electrically connected, for example, integrally connected, that is, the first electrode sublayer 111A and the first light-transmitting wiring layer of the first part 15A are arranged in the same layer and are in direct contact, thereby forming One-piece structure.
  • “same-layer arrangement” means that two functional layers or structural layers are formed in the same layer and with the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers
  • the layer or the structure layer can be formed of the same material layer, and the required pattern and structure can be formed through the same patterning process.
  • One patterning process includes, for example, photoresist formation, exposure, development, and etching.
  • the first electrode sub-layer 111A and the first light-transmitting wiring layer of the first portion 15A can be formed by using the same material layer and using the same patterning process, thereby simplifying the preparation of the display substrate. Craft.
  • the first display area 10 includes a plurality of first sub-pixels arranged in an array, each first sub-pixel includes a first light-emitting device 11, and the display area includes a plurality of first sub-pixels.
  • a connecting wire 15, the second display area 20 includes a plurality of first pixel circuits D, and the plurality of first pixel circuits D are respectively electrically connected to the first light-emitting devices of the plurality of first sub-pixels through the plurality of first connecting wires 15 11 to drive a first light emitting device 11 of a plurality of first sub-pixels.
  • the plurality of first pixel circuits D correspond to the first light-emitting devices 11 of the plurality of first sub-pixels one-to-one and are electrically connected by the first connecting wires 15.
  • one The first pixel circuit D is used to drive the first light emitting device 11 of a first sub-pixel.
  • one first pixel circuit D may be electrically connected to the first light-emitting devices 11 of the first sub-pixels through a plurality of first connection wires 15 respectively.
  • a first pixel circuit D The pixel circuit D can be used to drive the first light emitting devices 11 of a plurality of first sub-pixels.
  • the embodiment of the present disclosure does not specifically limit the correspondence between the first pixel circuit D and the first light-emitting device 11 of the first sub-pixel.
  • the second portion 15B of the first connection trace 15 includes a second light-transmitting wiring layer, and the second light-transmitting wiring layer (that is, the portion indicated by the mark 15B) is connected to the first light-transmitting wiring layer.
  • the layers that is, the part indicated by the mark 15A
  • the first electrode structure 111 is the first anode structure of the first light emitting device 11
  • the second electrode structure 113 is the first cathode structure of the first light emitting device 11.
  • the first light-emitting layer 112 between the first anode structure and the first cathode structure can emit light.
  • the orthographic projection of the first light-emitting layer 112 on the first anode structure is located inside the first anode structure
  • the orthographic projection of the first light-emitting layer 112 on the first cathode structure is located inside the first cathode structure, thus the first anode The structure and the first cathode structure can sufficiently drive the first light-emitting layer 112 to emit light.
  • the first cathode structure may be a structure formed on the entire surface of the display substrate.
  • the first cathode structure may include lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc. metallic material. Since the first cathode structure can be formed as a very thin layer, the first cathode structure 113 has good light transmittance.
  • the first anode structure may include a multi-layer stack structure.
  • the first anode structure may also include a second electrode sublayer 111B and a third electrode sublayer 111C laminated with the first electrode sublayer 111A, so that the first anode structure has Three-layer laminated structure.
  • the first anode structure may also be a single-layer structure, a double-layer structure, etc. The embodiments of the present disclosure do not limit the specific form of the first anode structure.
  • the first electrode sublayer 111A, the second electrode sublayer 111B, and the third electrode sublayer 111C are all surface electrodes, and the plane shapes of the first electrode sublayer 111A, the second electrode sublayer 111B, and the third electrode sublayer 111C are And the size is basically the same (that is, the orthographic projection shape and size of the first electrode sublayer 111A, the second electrode sublayer 111B, and the third electrode sublayer 111C on the base substrate 14 are basically the same), and any two adjacent electrodes Direct and complete contact between the sub-layers.
  • the orthographic projection of the first light-emitting layer 112 on any one of the electrode sublayers in the first anode structure is located inside the electrode sublayer.
  • the material of the first electrode sublayer 111A may include indium tin oxide (ITO)
  • the material of the second electrode sublayer 111B may include silver (Ag) or a silver alloy
  • the material of the third electrode sublayer 111C may include The material may include indium tin oxide (ITO).
  • ITO indium tin oxide
  • the first anode structure has an ITO/Ag/ITO three-layer laminated structure.
  • the display substrate includes a base substrate 14, and the first light-transmitting wiring layer, the second light-transmitting wiring layer, and the first electrode sub-layer 111A are located on the base substrate 14.
  • the second portion 15B of the first connection trace 15 may only include the second light-transmitting trace layer.
  • the second portion 15B of the first connection trace 15 may further include a first metal trace located on the side of the second light-transmitting trace layer away from the base substrate 14.
  • Layer 16 The arrangement of the metal wiring layer 16 can reduce the resistance of the first connecting wiring 15.
  • the material of the metal wiring layer 16 may include metal materials such as silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti), or alloy materials thereof. Therefore, the metal wiring layer 16 has higher conductivity, which can significantly reduce the resistance of the first connecting wiring 15.
  • the second electrode sub-layer 111B is located on the side of the first electrode sub-layer 111A away from the base substrate 14, and the second electrode sub-layer 111B is provided in the same layer as the first metal wiring layer 16. Therefore, the second electrode sub-layer 111B and the first metal wiring layer 16 can be formed using the same material layer and through the same patterning process, so as to simplify the manufacturing process of the display substrate.
  • the second portion 15B may further include an anti-oxidation protection layer 17 on the side of the first metal wiring layer 16 away from the base substrate 14.
  • the anti-oxidation protection layer 17 can prevent the metal wiring layer 16 from being oxidized.
  • the anti-oxidation protection layer 17 can also enhance the adhesion between the metal wiring layer 16 and the insulating layer 146 (also the pixel defining layer, which will be described later) formed thereon To prevent poor connection between the metal wiring layer 16 and the insulating layer 145.
  • the anti-oxidation protective layer 17 can be made of transparent oxide materials, such as ITO, IZO, and other transparent conductive oxide materials, thereby further reducing the resistance of the first connecting trace 15.
  • the third electrode sub-layer 111C is located on the side of the second electrode sub-layer 111B away from the base substrate 14, and the third electrode sub-layer 111C and the anti-oxidation protection layer 17 are provided in the same layer.
  • the third electrode sub-layer 111C and the anti-oxidation protection layer 17 may be formed of the same material layer and formed by the same patterning process, so as to simplify the manufacturing process of the display substrate.
  • the second portion 15B of the first connecting wire 15 is formed as a three-layered conductive structure, which can significantly reduce the resistance of the first connecting wire 15 .
  • the above-mentioned design of the first connecting wires 15 can also improve the uniformity of the current flowing through the plurality of first connecting wires 15 And improve the display effect of the display substrate.
  • the three-layer laminate structure of the second portion 15B can be formed in the same layer as the three-layer laminate structure of the first anode structure, thereby simplifying the preparation process of the display substrate.
  • the second portion 15B of the first connection trace 15 may further include an oxidation protection layer 17 laminated with the metal wiring layer 16, and the oxidation protection layer 17 may prevent
  • the metal wiring layer 16 is oxidized to ensure that the metal wiring layer 16 maintains high conductivity; in addition, the anti-oxidation protection layer 17 can also enhance the adhesion between the metal wiring layer 16 and the insulating layer 145 formed thereon to prevent The metal wiring layer 16 and the insulating layer 145 are poorly connected.
  • the anti-oxidation protective layer 17 can be made of transparent oxide materials, such as ITO, IZO, and other transparent conductive oxide materials, thereby further reducing the resistance of the first connecting trace 15.
  • the first light-emitting device 11 includes a first anode structure 111, a first cathode structure 113, and a gap between the first anode structure 111 and the first cathode structure 113.
  • the first light-emitting layer 112 and the first portion 15A of the first connection trace 15 are electrically connected to the first anode structure 111 through a via hole.
  • an insulating layer 145 is provided on the first connection trace 15.
  • the insulation layer 145 has a via 145A in the first display area 10, and the first portion 15A of the first connection trace 15 passes through the via 145A in the insulation layer 145 and
  • the first anode structure 111 is electrically connected.
  • the first anode structure 111 includes multiple anode sublayers, for example, three anode sublayers are shown in the figure.
  • the three-layer anode sub-layer has an ITO/Ag/ITO three-layer laminated structure.
  • the first cathode structure 113 may be a structure formed on the entire surface of the display substrate.
  • the first cathode structure 113 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag). Since the first cathode structure 113 can be formed as a very thin layer, the first cathode structure 113 has good light transmittance.
  • the second part 15B of the first connecting wire 15 may also adopt a structure different from the embodiment of FIG. 4 and FIG. 6.
  • the second portion 15B of the first connecting wiring 15 may not include the second light-transmitting wiring layer, but only the metal wiring layer.
  • the second portion 15B includes a second metal wiring layer.
  • the second metal wiring layer and the first light-transmitting wiring layer of the first portion 15A are arranged in different layers and pass through Hole electrical connection.
  • an insulating layer 145 is provided above the second metal wiring layer, and the insulating layer 145 has a via 145A.
  • the second metal wiring layer and the first light-transmitting wiring layer of the first portion 15A are electrically connected through the via 145A of the insulating layer 145. connect.
  • FIG. 8 shows a plan view of the first display area 10 and the second display area 20 in the above situation.
  • the second display area 20 has a via area (area framed by a dashed line) at a position close to the first display area 10, and the first portion 15A and the second portion 15A of the multiple first connecting wires 15
  • the part 15B may be electrically connected through a plurality of via holes 145A provided in the via hole area, respectively.
  • the second metal trace layer of the second portion 15B may include metal materials such as silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti). Or its alloy material, so it has higher conductivity, and can also significantly reduce the resistance of the first connecting wire 15.
  • metal materials such as silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti). Or its alloy material, so it has higher conductivity, and can also significantly reduce the resistance of the first connecting wire 15.
  • FIG. 9 shows a pattern of the first sub-pixel arrangement in the first display area.
  • the second sub-pixels in the second display area 20 also have the arrangement regularity of sub-pixels as shown in FIG. 9.
  • every four sub-pixels constitute a pixel unit, and each sub-pixel has a different shape.
  • the anode structure of the light-emitting device of each sub-pixel also has a different shape.
  • the first anode structure 111 of the first light-emitting device of each first sub-pixel has a different shape, and performs as shown in FIG. Arrangement.
  • FIG. 10 shows the connection mode of the data line D when the first sub-pixel in the first display area 10 and the second sub-pixel in the second display area 20 are arranged in the above-mentioned sub-pixel arrangement.
  • the data line D is arranged around the border of the second display area 20 close to the first display area 10, and in the first display area 10 and the second display area 20, the sub-lines in the same column
  • the pixel circuits of the pixels are electrically connected to the same data line D.
  • FIG. 10 shows the connection mode of the data line D when the first sub-pixel in the first display area 10 and the second sub-pixel in the second display area 20 are arranged in the above-mentioned sub-pixel arrangement.
  • the first pixel circuit located in the second display area 20 shown by a gray square is electrically connected to the first pixel circuit located on the left side of the first display area 10 through the first connecting wire 15
  • a light-emitting device of a first sub-pixel, through the winding of the data line D, can connect the sub-pixels in the same column as the first first sub-pixel on the left side (whether it is the first sub-pixel or the second sub-pixel)
  • the pixel circuits are all electrically connected, so that the pixel circuits of the sub-pixels in the same column are electrically connected to the same data line.
  • a part DA of the data line D (shown in the figure as a thick line extending horizontally on the upper side of the data line D) can be set by means of jumpers, that is, a part DA of the data line D can be set with other parts of the data line D In different layers.
  • the use of jumper design can reduce the arrangement space of the data lines, which is more conducive to the arrangement of the wires.
  • FIG. 10 only shows the connection traces and data lines of a first sub-pixel in the first display area 10, and other first sub-pixels in the first display area 10 also have a similar connection relationship.
  • the area occupied by the gray box may have first pixel circuits of four first sub-pixels of one pixel unit.
  • the four first pixel circuits may be electrically connected by four first connecting wires 15 respectively.
  • the data line D may be wound on one side of the second display area 20, for example, FIG. 10 shows a situation where the data line D is wound on the upper side of the second display area 20.
  • the data line D can also be wound on the upper and lower sides of the second display area 20 at the same time.
  • the pixel circuits of the first column of sub-pixels on the left in the first display area 10 and the second display area 20 use the same data line D3 (the data on the left in the figure)
  • the pixel circuits of the second column of sub-pixels on the left are electrically connected by the same data line D4 (the data line on the right in the figure).
  • the data lines are simultaneously wound on the upper and lower sides of the second display area 20 , So as to electrically connect the pixel circuits of the sub-pixels located in the same column, so that the light-emitting devices of the sub-pixels located in the same column can be driven by the same data line.
  • a part DA of the data line D3 and the data line D4 can also be designed with jumpers.
  • the data lines are arranged densely, so a jumper design can be adopted for part of the data lines wound around the edge to save space and simplify the circuit arrangement.
  • FIG. 11 only shows the connection traces and data lines of the four first sub-pixels in the first display area 10, and other first sub-pixels in the first display area 10 also have similar connection relationships.
  • Middle 11 is not shown.
  • the area occupied by the gray box may have first pixel circuits of four first sub-pixels of one pixel unit.
  • the four first pixel circuits may be electrically connected by four first connecting wires 15 respectively.
  • the first sub-pixels located in the third column on the left side of the first display area 10 and the second column of second sub-pixels P in the second display area 20 above the first display area 10 are located in the same column.
  • the first sub-pixel in the third column on the left side of the first display area 10 is driven by the first pixel circuit D in the first column in the second display area 20 above the first display area 10.
  • the data line D can be routed in the first column of the first pixel circuit D and the second column of the second sub-pixel P in the second display area 20 to electrically connect the pixel circuits of the sub-pixels in the same column to the same data line Therefore, the light-emitting devices of the sub-pixels located in the same column can be driven by the same data line.
  • the pixel circuits of the sub-pixels located in the same row can be electrically connected to the same scan line, so that the light-emitting devices of the sub-pixels located in the same row can be driven by the same scan line.
  • the first light-emitting device 11 located in the first first sub-pixel in the first row of the first display area 10 and a second display area 20 located on the left side of the first display area 10 A pixel circuit D is electrically connected, the light-emitting device 11 of the second first sub-pixel in the first row in the first display area 10 and a first pixel circuit in the second display area 20 located on the upper side of the first display area 10 D is electrically connected.
  • the first pixel circuit D of the two first sub-pixels in the same row can be electrically connected through the winding of the scan line G1 (the scan line on the left in the figure).
  • the first light-emitting device 11 located in the first first sub-pixel of the third row in the first display area 10 is electrically connected to a first pixel circuit D located in the second display area 20 on the left side of the first display area 10.
  • the light emitting device 11 of the second first sub-pixel located in the third row in the first display area 10 is electrically connected to a first pixel circuit D in the second display area 20 located on the upper side of the first display area 10, through
  • the winding of the scan line G2 (the scan line on the right in the figure) can electrically connect the first pixel circuits D of the two first sub-pixels in the same row (the third row in the figure).
  • the light-emitting devices of the sub-pixels located in the same row can be driven by the same scan line.
  • the pixel circuits of the sub-pixels located in the same column can be electrically connected to the same data line, and the pixel circuits of the sub-pixels located in the same row can be electrically connected The same scan line to simplify the drive control of each sub-pixel in the display panel.
  • the wires of different lines are arranged in different wire layers, that is, the wires of different lines are arranged in different layers.
  • the first connection trace 15 with the darkest color and the thickest line, the data line D with darker color but thinner lines, and the scan line G with the lightest color and thinner lines are arranged in different layers, so in preparation Different material layers are used in the process.
  • the second display area 20 further includes a plurality of second sub-pixels P, and each second sub-pixel P includes A second light-emitting device and a second pixel circuit electrically connected to the second light-emitting device, the second pixel circuit is configured to drive the second light-emitting device; in the second display area 20, a plurality of second pixel circuits are arranged in a first array , Which is the array arranged by the gray squares in Figure 5 and Figure 8. For example, in the direction perpendicular to the display substrate, the first connection wiring 15 and the second sub-pixel P do not overlap.
  • a plurality of first pixel circuits D are dispersedly arranged in a first array, and are arranged in a second array with a plurality of second pixel circuits D, as shown in FIG. 5 It is an array arranged together with the gray squares and white squares in Figure 8.
  • the first pixel circuit D for driving the first light-emitting device 11 includes a thin film transistor 12 and a storage capacitor 13.
  • the thin film transistor 12 includes an active layer 121, a gate 122, and source and drain electrodes (ie, source and drain).
  • the electrode 123 and the drain electrode 124), and the storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132.
  • the active layer 121 is provided on the base substrate 14, the side of the active layer 121 away from the base substrate 14 is provided with a first gate insulating layer 141, and the gate 122 and the first capacitor plate 131 are provided in the same layer.
  • the side of the first gate insulating layer 141 away from the base substrate 14 and the side of the gate 122 and the first capacitor plate 131 away from the base substrate 14 are provided with a second gate insulating layer 142, and the second capacitor plate 132 It is arranged on the side of the second gate insulating layer away from the base substrate 14, the side of the second capacitor plate 132 away from the base substrate 14 is provided with an interlayer insulating layer 143, and the source and drain electrodes are arranged on the interlayer insulating layer 143
  • the side away from the base substrate 14 is electrically connected to the active layer 121 through the via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143, and the source and drain electrodes are
  • FIG. 13 shows a schematic cross-sectional view of a second display area 20.
  • the second display area 20 includes a second light-emitting device 21 and a second pixel circuit that drives the second light-emitting device 21.
  • the second pixel circuit includes structures such as a thin film transistor 22 and a storage capacitor 23.
  • the second light emitting device 21 includes a second anode structure 211, a second cathode structure 213, and a second light emitting layer 212 between the second anode structure 211 and the second cathode structure 213.
  • the second anode structure 211 is connected to the second pixel through the via hole.
  • the circuit is electrically connected.
  • the second anode structure 211 may include a plurality of anode sub-layers, such as a three-layer structure of ITO/Ag/ITO (not shown in the figure), etc.
  • the specific form of the second anode structure 211 is not described in the embodiment of the present disclosure. limited.
  • the thin film transistor 22 includes structures such as an active layer 221, a gate 222, and source and drain electrodes (ie, a source 223 and a drain 224), and the storage capacitor 23 includes a first capacitor plate 231 and a second capacitor plate 232.
  • the active layer 221 is provided on the base substrate 14, the side of the active layer 221 away from the base substrate 14 is provided with a first gate insulating layer 141, and the gate 222 and the first capacitor plate 231 are provided in the same layer.
  • the side of the first gate insulating layer 141 away from the base substrate 14 and the side of the gate 222 and the first capacitor plate 231 away from the base substrate 14 are provided with a second gate insulating layer 142, and the second capacitor plate 232 It is arranged on the side of the second gate insulating layer 142 away from the base substrate 14, and the side of the second capacitor plate 232 away from the base substrate 14 is provided with an interlayer insulating layer 143, and the source and drain electrodes are arranged on the interlayer insulating layer.
  • the side of the 143 away from the base substrate 14 is electrically connected to the active layer 221 through the via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143.
  • the source and drain electrodes are away from the liner.
  • a planarization layer 144 is provided on one side of the base substrate 14 to planarize the second pixel circuit.
  • the planarization layer 144 has a via 144A, and the second anode structure 211 is electrically connected to the source 223 of the thin film transistor 22 through the via 144A in the planarization layer 144.
  • the transition layer may be provided in the same layer as the first connection trace 15.
  • the display area further includes a third display area 30 at least partially surrounding the second display area 20, and the third display area 30 includes a plurality of third sub-pixels arranged in an array.
  • FIG. 14 shows a schematic cross-sectional view of a third display area 30.
  • each third sub-pixel includes a third light-emitting device 31 and a third pixel circuit electrically connected to the third light-emitting device.
  • the third pixel circuit is configured to drive the third light emitting device 31.
  • the third light emitting device 31 includes a third anode structure 311, a third cathode structure 313, and a third light emitting layer 312 between the third anode structure 311 and the third cathode structure 313.
  • the third anode structure 311 is connected to the third pixel through the via hole.
  • the circuit is electrically connected.
  • the third anode structure 311 may include a plurality of anode sub-layers, such as a three-layer structure of ITO/Ag/ITO (not shown in the figure), etc.
  • the specific form of the third anode structure 311 is not described in the embodiment of the present disclosure. limited.
  • the third pixel circuit includes structures such as a thin film transistor 32 and a storage capacitor 33.
  • the thin film transistor 32 includes an active layer 331, a gate 332, and source and drain electrodes (ie, a source 233 and a drain 234)
  • the storage capacitor 33 includes a first capacitor plate 331 and a second capacitor plate 332.
  • the active layer 321 is provided on the base substrate 14, the side of the active layer 321 away from the base substrate 14 is provided with a first gate insulating layer 141, and the gate 322 and the first capacitor plate 331 are provided in the same layer.
  • the side of the first gate insulating layer 141 away from the base substrate 14 and the side of the gate 322 and the first capacitor plate 331 away from the base substrate 14 are provided with a second gate insulating layer 142, and the second capacitor plate 332 It is arranged on the side of the second gate insulating layer 142 away from the base substrate 14, and the side of the second capacitor plate 332 away from the base substrate 14 is provided with an interlayer insulating layer 143, and the source and drain electrodes are arranged on the interlayer insulating layer.
  • the side of the 143 away from the base substrate 14 is electrically connected to the active layer 321 through the via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143.
  • the source and drain electrodes are away from the liner.
  • a planarization layer 144 is provided on one side of the base substrate 14 to planarize the third pixel circuit.
  • the planarization layer 144 has a via hole 144B, and the third anode structure 311 is electrically connected to the source electrode 323 of the thin film transistor 32 through the via hole 144B in the insulating layer 145.
  • transition layer there may be a transition layer (not shown in the figure) between the source electrode 323 and the second anode structure 311, and the transition layer may be provided in the same layer as the first connection trace 15.
  • the first pixel circuit and the second pixel circuit in the second display area 20 are arranged in the same layer as the third pixel circuit in the third display area 30, so the same patterning process can be used in the manufacturing process.
  • the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144 are arranged in the same layer in the second display area 20 and the third display area 30. In some embodiments It is still integrally connected, so the same reference numerals are used in the drawings.
  • the first display area 10 further includes a transparent support layer 18 on the base substrate 14, and the first light emitting device 11 is located on the transparent support layer 18.
  • the transparent support layer 18 is provided in the same layer as at least one of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144.
  • the transparent support layer 18 is disposed in the same layer as the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144, so that the first light emitting device 11 in the first display area 10 It is substantially the same height as the second light emitting device 21 in the second display area 20 and the third light emitting device 31 in the third display area 30, and the manufacturing process of the display substrate is simplified.
  • the display substrate further includes a pixel defining layer 146, an encapsulation layer 147 and other structures.
  • the pixel defining layer 146 is disposed on the first anode structure and includes a plurality of openings, and the first light-emitting layer is formed on the pixel defining layer.
  • the encapsulation layer 147 may include a single-layer or multi-layer encapsulation structure, for example, the multilayer encapsulation structure includes a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect on the display substrate.
  • the pixel defining layer 146 and the encapsulation layer 147 are arranged in the same layer, and in some embodiments, they are integrally connected. The same label is used in.
  • the base substrate 14 may be a glass substrate, a quartz substrate, a metal substrate, a resin substrate, or the like.
  • the embodiments of the present disclosure do not limit this.
  • the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143 and the planarization layer 144, the insulating layer 145, the pixel defining layer 146, the encapsulation layer 147, and the insulating layer 148 may include silicon oxide, Inorganic insulating materials such as silicon nitride and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin.
  • the embodiments of the present disclosure do not specifically limit the materials of the above-mentioned functional layers.
  • the material of the active layer may include semiconductor materials such as polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the part of the active layer 121/221/321 may be conductive through a conductive process such as doping, so as to have higher conductivity.
  • the materials of the grid, the first capacitor plate, and the second capacitor plate may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the material of the source and drain electrodes may include metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer, such as titanium, aluminum, Titanium three-layer metal laminate (Ti/Al/Ti), etc.
  • the display substrate provided by the embodiment of the present disclosure may be a display substrate such as an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the embodiment of the present disclosure does not limit the specific type of the display substrate.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the light-emitting layer 111/211/311 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may emit red light or green light. Light, blue light, or white light, etc.
  • the light-emitting layer 111/211/311 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer 111/211/311 may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots Dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the first display area 10 may have various shapes such as a circle (the situation shown in FIG. 3), a rectangle, a triangle, etc.
  • the shape of the first display area 10 in the embodiment of the present disclosure is different. Make a limit.
  • the display substrate may further include a sensor 19, such as an image sensor, an infrared sensor, a distance sensor, etc.
  • the sensor 19 may be implemented in the form of a chip, for example.
  • the sensor 19 is arranged on the second side of the display substrate, for example, the sensor 19 is arranged on the second side of the display panel by means of double-sided tape, and the orthographic projection of the sensor 19 on the base substrate 14 is at least the same as that of the first display area 10. Partially overlapped and configured to receive light from the first side. Therefore, the first display area 10 provides convenience for the setting of the sensor 19 while realizing display.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate having a first side for display and a second side opposite to the first side.
  • the preparation method includes: forming a display area, the display area including a first side A display area and a second display area at least partially surrounding the first display area, the first display area allows light from the first side to be at least partially transmitted to the second side; at least one of the first display area and the second display area is formed
  • the first connection trace includes a first portion located in the first display area and a second portion located in the second display area that are electrically connected to each other.
  • the first portion includes a first light-transmitting wiring layer;
  • the region forms a plurality of first sub-pixels arranged in an array, each of the first sub-pixels includes a first light-emitting device, the first light-emitting device includes a first electrode structure, a second electrode structure, and the first electrode structure and the second electrode structure
  • the first electrode structure includes a first electrode sublayer, and the first electrode sublayer and the first light-transmitting wiring layer are formed in the same layer and electrically connected, for example, integrally connected.
  • the at least one first connection trace includes a plurality of first connection traces; the preparation method of the display substrate further includes: forming a plurality of first pixel circuits in the second display area, and a plurality of first pixels The circuits are respectively electrically connected to the first electrode structures of the plurality of first light-emitting devices through a plurality of first connecting wires, so as to drive the plurality of first light-emitting devices.
  • forming the second part of the first connection trace includes: forming a second light-transmitting wiring layer, the second light-transmitting wiring layer and the first light-transmitting wiring layer are formed in the same layer and integrally connected .
  • the method for preparing the display substrate further includes: providing a base substrate, and the second light-transmitting wiring layer and the first electrode sublayer are formed on the base substrate to form the second connecting wiring.
  • the part also includes: forming a first metal wiring layer on the side of the second light-transmitting wiring layer away from the base substrate, and forming a second electrode sublayer on the side of the first electrode sublayer away from the base substrate, and the second electrode The sub-layer is formed in the same layer as the first metal wiring layer.
  • forming the second part of the first connection trace further includes: forming an anti-oxidation protection layer on the side of the first metal trace layer away from the base substrate, and forming the second electrode sublayer away from the A third electrode sublayer is formed on one side of the base substrate, and the third electrode sublayer is formed in the same layer as the anti-oxidation protection layer.
  • a patterning process is used on the base substrate 14 to simultaneously form pixel circuits in the second display area 20 and the third display area 30 (including the first pixel circuit, the second pixel circuit, and the third pixel circuit). ), and at the same time form a transparent support layer 18.
  • forming the first pixel circuit includes forming a thin film transistor 12 and a storage capacitor 13.
  • the thin film transistor 12 includes an active layer 121, a gate 122, and source and drain electrodes 123 and 124.
  • the storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132.
  • the active layer 121 is formed on the base substrate 14, a first gate insulating layer 141 is formed on the side of the active layer 121 away from the base substrate 14, and the same layer is formed on the first gate insulating layer 141.
  • the gate 122 and the first capacitor plate 131 are formed.
  • a second gate insulating layer 142 is formed on the side of the gate 122 and the first capacitor plate 131 away from the base substrate 14, and the second gate insulating layer 142 is away from the liner.
  • a second capacitor plate 132 is formed on one side of the base substrate 14, an interlayer insulating layer 143 is formed on the side of the second capacitor plate 132 away from the base substrate 14, and on the side of the interlayer insulating layer 143 away from the base substrate 14
  • Source and drain electrodes 123 and 124 are formed on one side, and the source and drain electrodes 123 and 124 are electrically connected to the active layer 121 through vias in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143, and then
  • a planarization layer 144 is formed on the side of the source and drain electrodes 123 and 124 away from the base substrate 14. For example, via holes exposing the source and drain are formed in the planarization layer 144.
  • the transparent support layer 18 is formed in the same layer as at least one of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144.
  • the transparent support layer 18 is formed in the same layer as the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144.
  • each of the above-mentioned functional layers is formed by a patterning process.
  • One patterning process includes, for example, photoresist formation, exposure, development, and etching.
  • a buffer layer (not shown in the figure) may also be formed on the base substrate 14.
  • the buffer layer serves as a transition layer to prevent harmful substances in the base substrate 14 from intruding into the display.
  • the inside of the substrate can also increase the adhesion of the film layer in the display substrate on the base substrate 14.
  • the material of the buffer layer may include a single-layer or multi-layer structure formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the first connection wiring 15 and the first electrode structure 111 are formed in the first display area 10 and the second display area 20.
  • a first electrode material layer 151, a second electrode material layer 161, and a third electrode material layer 171 are sequentially deposited on the first display area 10 and the second display area 20 through the mask 40.
  • the mask plate 40 has a hollow part (ie, the white part in the figure), so that the material passes through the hollow part to form a certain pattern.
  • the first electrode material layer 151, the second electrode material layer 161, and the third electrode material layer 171 deposited through the mask 40 have substantially the same pattern.
  • the first wet etching process is used to etch away the parts located in the second display area 20 and part of the first display area 10 (that is, the part of the area where the first portion 15A of the first connection trace 15 will be formed).
  • the third electrode material layer 171 and part of the second electrode material layer 161 that is, the first wet etching process completely etches the third electrode material layer 171 in the second display area 20 and part of the first display area 10, but the etching
  • the thickness of the second electrode material layer 161 is less than the formation thickness of the second electrode material layer 161); then a second wet etching process is used to etch away the remaining second display area 20 and the above-mentioned part of the first display area 10.
  • the electrode material layer is used to completely remove the second electrode material layer 161 located in the second display region 20 and the above-mentioned part of the first display region 10 through two wet etching processes, thereby forming the first electrode material layer in the above-mentioned part of the first display region 10. Connect the first portion 15A of the trace 15. At this time, the unetched second electrode material layer 161 and the third electrode material layer 171 in the first display area 10 respectively form the second electrode sublayer 111B of the first electrode structure 111 And the third electrode sublayer 111C.
  • the etching thickness of the material layer can be accurately controlled by the wet etching twice to avoid over-etching; and, when the material of the second electrode material layer 161 is Ag, the wet etching twice can effectively suppress the etching The phenomenon of Ag precipitation in the process, so as to ensure the accuracy of etching.
  • basically the same method can also be used to form the display substrate as shown in FIGS. 6 and 7.
  • the first electrode material layer 151, the second electrode material layer 161, and the third electrode material are sequentially deposited on the first display area 10 and the second display area 20 through the mask 40 After the layer 171, as shown in FIG.
  • a first wet etching process can be used to etch away the third electrode located in a part of the first display area 10 (that is, a part of the area where the first portion 15A of the first connection trace 15 will be formed) Material layer 171 and part of the second electrode material layer 161; then the remaining second electrode material layer 161 located in the part of the first display area 10 is etched away using a second wet etching process, so as to be completely removed by two wet etching processes The second electrode material layer 161 is located in the above-mentioned part of the first display area 10, thereby forming the first part 15A of the first connection wiring 15 in the above-mentioned part of the first display area 10.
  • the first display area 10 is not
  • the etched second electrode material layer 161 and the third electrode material layer 171 respectively form the second electrode sublayer 111B and the third electrode sublayer 111C of the first electrode structure, and the unetched second electrode sublayer 111C in the second display area 20
  • the electrode material layer 161 and the third electrode material layer 171 respectively form the metal wiring layer 16 and the oxidation protection layer 17 of the second portion 15B of the first connection wiring 15.
  • a patterning process may be used to first form the metal wiring layer of the second portion 15B, and then form an insulating layer 145 on the metal wiring layer, and form vias in the insulating layer 145 .
  • a patterning process is used to form the first light-transmitting wiring layer of the first portion 15A and the first electrode sublayer of the first anode structure in the same layer on the insulating layer 145.
  • the first light-transmitting wiring layer passes through the insulating layer 148.
  • the via hole formed in is electrically connected to the second portion 15B, thereby forming a first connection trace 15 including the first portion 15A and the second portion 15B.
  • the preparation method of the display substrate further includes forming a pixel defining layer, a light emitting device, and an encapsulation layer on the first connection trace 15.
  • a pixel defining layer for example, a pixel defining layer, a light emitting device, and an encapsulation layer on the first connection trace 15.
  • the preparation method of the display substrate may further include: providing a sensor and bonding the sensor to the second side of the display substrate. At this time, the orthographic projection of the sensor on the base substrate at least partially overlaps the first display area, so that the light from the first side can be received through the first display area.
  • FIG. 17 shows another plan view of the first display area 10 and the second display area 20.
  • the first connection trace 15 may cross the second sub-pixel P in the second display area 20 to electrically connect the first light emitting device 11 (for example, It includes an anode, a light-emitting layer, and a cathode) and a first pixel circuit D (for example, including a driving transistor, a storage capacitor, etc.) located in the second display area 20 for driving the first light-emitting device 11.
  • the first light emitting device 11 for example, It includes an anode, a light-emitting layer, and a cathode
  • a first pixel circuit D for example, including a driving transistor, a storage capacitor, etc.
  • the first connection trace 15 may be linearly electrically connected to the first light emitting device 11 located in the first display area 10 and the first light emitting device 11 located in the second display area 20 for driving the first
  • the data lines D (for example, D1, D2) used to drive the first sub-pixels in the first display area 10 may be arranged around the boundary of the second display area 20 close to the first display area 10.
  • the pixel circuits of the sub-pixels located in the same column can be electrically connected to the same data line, so that the light-emitting devices of the sub-pixels located in the same column can be driven by the same data line.
  • the data line D1 on the left is electrically connected to the pixel circuits of the first column of sub-pixels on the left in the first display area 10 through windings
  • the data line D2 on the right is electrically connected to the first display.
  • other columns of sub-pixels in the first display area 10 are also respectively connected to a data line, which is not shown in the figure.
  • the column direction refers to the vertical direction in the figure
  • the row direction refers to the horizontal direction in the figure.
  • the column direction and the row direction can be interchanged. The embodiments of the present disclosure do not limit this.
  • the wiring dense area Jumper wire design can be used, that is, the wires are arranged in different wire layers.
  • the first display area has a relatively high light transmittance, so it can be used as the sensor’s Set up to provide convenience.
  • the first connecting wires in the first display area can be formed in the same layer as the first electrode structure of the first light-emitting device, which can also simplify the manufacturing process of the display substrate.

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un substrat d'affichage et son procédé de préparation. Le substrat d'affichage présente un premier côté pour l'affichage et un second côté opposé au premier côté. Une zone d'affichage du substrat d'affichage comprend une première zone d'affichage (10) et une seconde zone d'affichage (20) entourant au moins partiellement la première zone d'affichage (10). Le substrat d'affichage comprend en outre au moins un premier câblage de connexion (15), le premier câblage de connexion (15) comprenant une première partie (15A) située dans la première zone d'affichage (10) et une seconde partie (15B) située dans la seconde zone d'affichage (20) qui sont électriquement connectées l'une à l'autre, la première partie (15A) comprenant une première couche de câblage transmettant la lumière; la première zone d'affichage (10) comprenant une pluralité de premiers sous-pixels agencés en une matrice, chacun des premiers sous-pixels comprenant un premier dispositif électroluminescent, et une première sous-couche d'électrode (111A) d'une première structure d'électrode (111) comprise dans le premier dispositif électroluminescent et la première couche de câblage transmettant la lumière étant disposées sur la même couche et étant électriquement connectées l'une à l'autre, de sorte qu'un processus de préparation du substrat d'affichage peut être simplifié.
PCT/CN2020/073995 2020-01-23 2020-01-23 Substrat d'affichage et son procédé de préparation WO2021147082A1 (fr)

Priority Applications (13)

Application Number Priority Date Filing Date Title
PCT/CN2020/073995 WO2021147082A1 (fr) 2020-01-23 2020-01-23 Substrat d'affichage et son procédé de préparation
CN202080000249.6A CN113439338A (zh) 2020-01-23 2020-01-23 显示基板及其制备方法
CN202010130251.7A CN111326560B (zh) 2020-01-23 2020-02-28 显示基板和显示装置
CN202080000311.1A CN113508466A (zh) 2020-01-23 2020-03-19 显示基板和显示装置
KR1020217038802A KR20220129999A (ko) 2020-01-23 2020-03-19 디스플레이 기판 및 디스플레이 디바이스
EP20891410.1A EP4095921A4 (fr) 2020-01-23 2020-03-19 Substrat d'affichage et dispositif d'affichage
PCT/CN2020/080182 WO2021147160A1 (fr) 2020-01-23 2020-03-19 Substrat d'affichage et dispositif d'affichage
JP2022502521A JP2023520267A (ja) 2020-01-23 2020-03-19 表示基板および表示装置
US17/297,641 US11968865B2 (en) 2020-01-23 2020-03-19 Display substrate and display device
PCT/CN2021/073243 WO2021147987A1 (fr) 2020-01-23 2021-01-22 Substrat et dispositif d'affichage
US17/428,847 US11980071B2 (en) 2020-01-23 2021-01-22 Display substrate and display device
US18/390,381 US20240172497A1 (en) 2020-01-23 2023-12-20 Display substrate and display device
US18/396,840 US20240138214A1 (en) 2020-01-23 2023-12-27 Display substrate and display device

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Application Number Priority Date Filing Date Title
PCT/CN2020/073995 WO2021147082A1 (fr) 2020-01-23 2020-01-23 Substrat d'affichage et son procédé de préparation

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CN114283701A (zh) * 2021-12-31 2022-04-05 厦门天马微电子有限公司 显示面板和显示装置
CN114464757A (zh) * 2022-02-09 2022-05-10 武汉天马微电子有限公司 一种显示面板和显示装置
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CN113644107A (zh) * 2021-08-12 2021-11-12 昆山国显光电有限公司 阵列基板、显示面板及显示设备
CN113644107B (zh) * 2021-08-12 2023-12-26 昆山国显光电有限公司 阵列基板、显示面板及显示设备
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CN114464757A (zh) * 2022-02-09 2022-05-10 武汉天马微电子有限公司 一种显示面板和显示装置
CN114464757B (zh) * 2022-02-09 2024-03-26 武汉天马微电子有限公司 一种显示面板和显示装置
CN115032836A (zh) * 2022-06-09 2022-09-09 京东方科技集团股份有限公司 显示基板和显示装置
CN115032836B (zh) * 2022-06-09 2023-10-17 京东方科技集团股份有限公司 显示基板和显示装置
WO2024000891A1 (fr) * 2022-06-30 2024-01-04 昆山国显光电有限公司 Panneau d'affichage, dispositif d'affichage, et procédé de préparation de panneau d'affichage

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