WO2021146942A1 - Shift register circuit, gate driver circuit, device, and driving and collection methods - Google Patents

Abstract

Disclosed are a shift register circuit, a gate driver circuit and a driving method therefor, an electronic device and a driving method therefor, and a method for texture collection by using electronic device. The shift register unit (110) comprises an input end (IN), an output end (OUT), and a global reset end (RST2), and is configured to receive an input control signal at the input end (IN), output a scanning signal at the output end (OUT), and receive a global reset control signal at the global reset end (RST2) so as to be reset. A scanning node setting unit (120) comprises a node setting circuit (121), a node starting circuit (122), and an auxiliary node setting circuit (123). The shift register circuit and the gate driver circuit have the function of starting and stopping any of nodes, and also have two modes of driving all and any of the nodes. When applied to texture collection, the circuits can significantly reduce the texture scanning time, increase the texture recognition response speed, improve the GOA resource utilization rate, and effectively reduce the equipment power consumption.

Description

Shift register circuit, gate drive circuit, device, drive and acquisition method Technical field

Various embodiments of the present disclosure relate to a shift register circuit, a gate driving circuit and a driving method thereof, an electronic device and a driving method thereof, and a method of using the electronic device for pattern collection.

Background technique

In the field of display technology, for example, a pixel array of a liquid crystal display usually includes multiple rows of gate lines and multiple columns of data lines interlaced therewith. The gate line can be driven by an attached integrated drive circuit. With the continuous improvement of amorphous silicon thin film technology in recent years, it is also possible to directly integrate the gate line driver circuit on the thin film transistor array substrate to form a GOA (Gate Driver On Array) to drive the gate line.

For example, a GOA composed of multiple cascaded shift register units can be used to provide switch-state voltage signals for multiple rows of gate lines of the pixel array, thereby controlling the multiple rows of gate lines to turn on sequentially, and the data lines correspond to the pixel array. The pixel units of the rows provide data signals to form the gray-scale voltages required by each gray-scale of the displayed image, and then display each frame of image.

Summary of the invention

At least one embodiment of the present disclosure provides a shift register circuit including: a shift register unit and a scan node setting unit. The shift register unit includes an input terminal, an output terminal, and a global reset terminal, and is configured to receive an input control signal at the input terminal, output a scan signal at the output terminal, and receive a global reset control at the global reset terminal Signal to be reset. The scanning node setting unit includes a node setting circuit, a node starting circuit, and a node auxiliary setting circuit. The control terminal of the node setting circuit and the first terminal of the node auxiliary setting circuit are connected to each other and both are configured to receive a scan input signal, and the first terminal of the node setting circuit is configured to receive a node setting signal, The second terminal of the node setting circuit is connected to the first node. The first terminal of the node activation circuit is configured to receive a node activation control signal, the second terminal of the node activation circuit is connected to the input terminal of the shift register unit, and the control terminal of the node activation circuit is connected to the The first node, the node activation circuit is configured to be turned on under the control of the level of the first node to transmit the node activation control signal to the input terminal of the shift register unit as the shift The input control signal of the register unit. The second end of the node auxiliary setting circuit is connected to the second end of the node starting circuit and the input end of the shift register unit, and the control end of the node auxiliary setting circuit is configured to receive node auxiliary setting Signal.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the node setting circuit includes a first transistor. The gate of the first transistor is connected to the scan input signal input terminal to receive the scan input signal, and the first pole of the first transistor is connected to the node setting signal input terminal to receive the node setting signal, so The second electrode of the first transistor is connected to the first node.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the node startup circuit includes a second transistor and a first capacitor. The gate of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the node activation control signal input terminal to receive the node activation control signal, and the second transistor of the second transistor is connected to the node activation control signal input terminal. The pole is connected to the input terminal of the shift register unit. The first electrode of the first capacitor is connected to the first node, and the second electrode of the first capacitor is connected to the input terminal of the shift register unit and the second electrode of the second transistor.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the node auxiliary setting circuit includes a third transistor. The gate of the third transistor is connected to the node auxiliary setting signal input terminal to receive the node auxiliary setting signal, and the first electrode of the third transistor and the gate of the first transistor are connected to each other and connected to The scan input signal input terminal is to receive the scan input signal, and the second electrode of the third transistor is connected to the second electrode of the second transistor and the input terminal of the shift register unit.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the scan node setting unit further includes a node reset circuit. The control terminal of the node reset circuit is configured to receive a node reset signal, the first terminal of the node reset circuit is connected to the first node, and the second terminal of the node reset circuit is configured to receive a first voltage.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the node reset circuit includes a fourth transistor. The gate of the fourth transistor is connected to the node reset signal input terminal to receive the node reset signal, the first electrode of the fourth transistor is connected to the first node, and the second electrode of the fourth transistor is connected to the The first voltage terminal is connected to receive the first voltage.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the shift register unit further includes an input circuit. The input circuit is connected to the second node and the input terminal, and is configured to control the level of the second node in response to the input control signal received by the input terminal.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the input circuit includes a fifth transistor. The gate of the fifth transistor is connected to the input terminal to receive the input control signal, the first electrode of the fifth transistor is connected to the first control signal terminal to receive the first control signal, and the fifth transistor The second pole is connected to the second node.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the shift register unit further includes an output circuit. The output circuit is connected to the second node, the first clock signal terminal, and the output terminal, and is configured to output the first clock signal of the first clock signal terminal under the control of the level of the second node To the output terminal as the scan signal.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the output circuit includes a sixth transistor and a second capacitor. The gate of the sixth transistor is connected to the second node, the first pole of the sixth transistor is connected to the first clock signal terminal to receive the first clock signal, and the first pole of the sixth transistor is connected to the first clock signal terminal. The two poles are connected to the output terminal. The first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the second electrode of the sixth transistor.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the shift register unit further includes a first control circuit. The first control circuit is connected to the second node and the third node, and is configured to control the level of the third node in response to the level of the second node.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the first control circuit includes: a seventh transistor, an eighth transistor, a ninth transistor, and a third capacitor. The gate of the seventh transistor is connected to the first electrode and connected to the second clock signal terminal to receive the second clock signal, and the second electrode of the seventh transistor is connected to the third node. The gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the third node, and the second electrode of the eighth transistor is connected to the second voltage terminal to receive The second voltage. The gate of the ninth transistor is connected to the output terminal, the first electrode of the ninth transistor is connected to the third node, and the second electrode of the ninth transistor is connected to the second voltage terminal to Receiving the second voltage. The first pole of the third capacitor is connected to the third node, and the second pole of the third capacitor is connected to the second voltage terminal.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the shift register unit further includes a noise reduction circuit. The noise reduction circuit is connected to the third node and the output terminal, and is configured to reduce noise on the output terminal under the control of the level of the third node.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the noise reduction circuit includes a tenth transistor. The gate of the tenth transistor is connected to the third node, the first electrode of the tenth transistor is connected to the output terminal, and the second electrode of the tenth transistor is connected to the second voltage terminal to receive the third node. Two voltages.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the shift register unit further includes a second control circuit. The second control circuit is connected to the second node and the third node, and is configured to control the level of the second node in response to the level of the third node.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the second control circuit includes an eleventh transistor. The gate of the eleventh transistor is connected to the third node, the first electrode of the eleventh transistor is connected to the second node, and the second electrode of the eleventh transistor is connected to the second voltage terminal Connect to receive the second voltage.

For example, in the shift register circuit provided by at least one embodiment of the present disclosure, the shift register unit further includes a first reset circuit and a second reset circuit. The first reset circuit is connected to the second node and the first reset terminal, and is configured to reset the second node in response to the first reset control signal of the first reset terminal. The second reset circuit is connected to the second node and the second reset terminal, and is configured to reset the second node in response to a second reset control signal of the second reset terminal. The first reset circuit includes a twelfth transistor, the gate of the twelfth transistor is connected to the first reset terminal to receive the first reset control signal, and the first electrode of the twelfth transistor is connected to To the second node, the second electrode of the twelfth transistor is connected to the second control signal terminal to receive the second control signal. The second reset circuit includes a thirteenth transistor, the gate of the thirteenth transistor is connected to the second reset terminal to receive the second reset control signal, and the first pole of the thirteenth transistor is connected to the second reset terminal. The second node is connected, and the second electrode of the thirteenth transistor is connected to the second voltage terminal to receive the second voltage. The first reset terminal is the current reset terminal of the shift register unit, the second reset terminal is the global reset terminal of the shift register unit, and the second reset control signal serves as the global reset control Signal.

At least one embodiment of the present disclosure further provides a gate driving circuit, including a plurality of cascaded shift register circuits in any of the above embodiments. The scan input signal input terminal of the n-th stage shift register circuit is connected to the output terminal of the n-1 stage shift register circuit, and the first reset terminal of the n-th stage shift register circuit and the n+1 stage shift register circuit are connected The output terminal of is connected, and n is an integer greater than 1.

At least one embodiment of the present disclosure further provides an electronic device, including the gate drive circuit and the array circuit in any of the above embodiments. The array circuit includes a multi-stripe scan line, and the multi-stripe scan line is correspondingly connected to a plurality of output terminals of a plurality of shift register circuits in the gate driving circuit.

For example, in the electronic device provided by at least one embodiment of the present disclosure, the array circuit is a pattern collection array circuit.

For example, the electronic device provided by at least one embodiment of the present disclosure further includes a touch circuit. The touch circuit is configured to perform touch detection on a touch area, and the pattern collection array circuit is located in the touch area detected by the touch circuit.

At least one embodiment of the present disclosure further provides a method for driving the gate driving circuit in any of the above embodiments. The method includes: in the first stage, a node setting circuit in the first shift register circuit sets the node The bit signal is transmitted to the first node, thereby controlling the level of the first node. In the second stage, the node in the first shift register circuit initiates the control of the level of the first node by the node in the first shift register circuit. Next, the node start control signal is transmitted to the input end of the shift register unit in the first shift register circuit as the input control signal. In the third stage, the first shift register circuit The shift register unit of, in response to the input control signal received by the input terminal, outputs the scan signal at the output terminal. The first shift register circuit is any one stage shift register circuit in the gate drive circuit.

At least one embodiment of the present disclosure further provides a driving method of the gate driving circuit in any of the above embodiments, including: the node auxiliary setting circuit transmits the scan input signal to the input terminal of the shift register unit As the input control signal, the shift register unit outputs the scan signal at the output terminal in response to the input control signal received by the input terminal.

At least one embodiment of the present disclosure further provides a method for driving an electronic device in any of the foregoing embodiments, including: according to the timing of the node setting signal, the node activation control signal, and the node auxiliary setting signal, The gate drive circuit outputs the scan signal to the array circuit.

For example, in the driving method of the electronic device provided by at least one embodiment of the present disclosure, in the case that the electronic device further includes a touch circuit, the driving method further includes: determining the touch circuit according to the detection result of the touch circuit. The timing of the node set signal, the node start control signal, and the node auxiliary set signal.

At least one embodiment of the present disclosure also provides a method for the electronic device in any of the foregoing embodiments to perform pattern collection, including: determining a target collection area based on a detection result of a touch circuit; and driving the gate drive circuit corresponding to all The shift register circuit of the target acquisition area sequentially outputs the scanning signal to clear the charge in the array circuit in the target acquisition area; the array circuit in the target acquisition area accumulates the charge; and drives the gate again The shift register circuit in the drive circuit corresponding to the target acquisition area sequentially outputs the scanning signals to read the charges accumulated in the array circuits in the target acquisition area. In the process of emptying the charges and reading During the process of the accumulated charges, the shift register circuit in the gate drive circuit that does not correspond to the target acquisition area does not output.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, rather than limit the present disclosure.

FIG. 1A is a schematic block diagram of a shift register circuit provided by at least one embodiment of the present disclosure;

FIG. 1B is an example structure diagram of a scanning node setting unit included in the shift register circuit in FIG. 1A;

2A is a schematic block diagram of another shift register circuit provided by at least one embodiment of the present disclosure;

2B is an example structure diagram of a scanning node setting unit included in the shift register circuit in FIG. 2A;

3A is a schematic block diagram of a shift register unit of a shift register circuit provided by at least one embodiment of the present disclosure;

FIG. 3B is an example structure diagram of the shift register unit in FIG. 3A;

4 is an example structure diagram of a shift register circuit provided by at least one embodiment of the present disclosure;

5A is a schematic block diagram of a gate driving circuit provided by at least one embodiment of the present disclosure;

5B is an example structure diagram of a gate driving circuit provided by at least one embodiment of the present disclosure;

6 is a signal timing diagram of a gate driving circuit provided by at least one embodiment of the present disclosure;

FIG. 7A is a schematic block diagram of a display device provided by at least one embodiment of the present disclosure;

FIG. 7B is a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure;

FIG. 8 is a flowchart of a driving method of a gate driving circuit provided by at least one embodiment of the present disclosure;

FIG. 9 is a flowchart of a driving method of an electronic device according to at least one embodiment of the present disclosure;

FIG. 10 is a flowchart of a method for using an electronic device to collect patterns according to at least one embodiment of the present disclosure; and

FIG. 11 is a schematic diagram of a comparison between a scheme of fingerprint collection using a gate drive circuit and a scheme of fingerprint collection using the gate drive circuit provided in an embodiment of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. Likewise, similar words such as "a", "one" or "the" do not mean a quantity limit, but mean that there is at least one. "Include" or "include" and other similar words mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, but do not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate the relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

With the development of display and pattern recognition equipment, users have gradually greater requirements for the size of pattern recognition equipment. Especially driven by full-screen display devices, users have increasingly strong demand for full-screen pattern recognition equipment. However, as the screen size of the pattern recognition device increases, the area that needs to be scanned and recognized by the pattern also becomes larger. Under normal circumstances, the pattern recognition device does not have the function of scanning the pattern only for a specific area, and can only scan the full screen from the beginning to the end, which inevitably leads to problems such as slow response speed and high power consumption of the pattern recognition device.

At least one embodiment of the present disclosure provides a shift register circuit including: a shift register unit and a scan node setting unit. The shift register unit includes an input terminal, an output terminal, and a global reset terminal, and is configured to receive an input control signal at the input terminal, output a scan signal at the output terminal, and receive a global reset control at the global reset terminal Signal to be reset. The scanning node setting unit includes a node setting circuit, a node starting circuit, and a node auxiliary setting circuit. The control terminal of the node setting circuit and the first terminal of the node auxiliary setting circuit are connected to each other and both are configured to receive a scan input signal, and the first terminal of the node setting circuit is configured to receive a node setting signal, The second terminal of the node setting circuit is connected to the first node. The first terminal of the node activation circuit is configured to receive a node activation control signal, the second terminal of the node activation circuit is connected to the input terminal of the shift register unit, and the control terminal of the node activation circuit is connected to the The first node, the node activation circuit is configured to be turned on under the control of the level of the first node to transmit the node activation control signal to the input terminal of the shift register unit as the shift The input control signal of the register unit. The second end of the node auxiliary setting circuit is connected to the second end of the node starting circuit and the input end of the shift register unit, and the control end of the node auxiliary setting circuit is configured to receive node auxiliary setting Signal.

At least one embodiment of the present disclosure also provides a gate driving circuit and a driving method thereof, an electronic device and a driving method thereof, and a method of using the electronic device for pattern collection. The shift register circuit provided by the embodiment of the present disclosure has the function of starting and stopping at any node, and has two modes of full drive and arbitrary node drive at the same time. In practical applications, it can be combined with touch coordinate positioning technology to provide users with an efficient pattern recognition solution that scans only specific areas (such as contact areas), thereby significantly reducing the time of pattern scanning, improving the response speed of pattern recognition, and at the same time greatly Reduce the waste of GOA resources and effectively reduce equipment power consumption.

The embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

It should be noted that in the embodiments of the present disclosure, for example, when each circuit is implemented as an N-type transistor, the term “pull up” means to charge a node or an electrode of a transistor, so that the node or the electrode The absolute value of the level is increased to realize the operation of the corresponding transistor (for example, turn-on); “pull-down” means to discharge a node or an electrode of a transistor to make the absolute value of the level of the node or the electrode Decrease, so as to achieve the operation of the corresponding transistor (such as turning off); the term "working potential" means that the node is at a high potential, so that when the gate of a transistor is connected to the node, the transistor is turned on; the term "non-operating potential" means The node is at a low potential, so that when the gate of a transistor is connected to the node, the transistor is turned off. For another example, when each circuit is implemented as a P-type transistor, the term "pull-up" means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor Operation (for example, turn on); "pull down" means to charge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (for example, turning off) ; The term "working potential" means that the node is at a low potential, so that when the gate of a transistor is connected to the node, the transistor is turned on; the term "non-operating potential" means that the node is at a high potential, so that when the gate of a transistor is When the pole is connected to this node, the transistor is turned off.

FIG. 1A is a schematic block diagram of a shift register circuit provided by at least one embodiment of the present disclosure, and FIG. 1B is an exemplary structure diagram of a scanning node setting unit included in the shift register circuit in FIG. 1A.

As shown in FIG. 1A, at least one embodiment of the present disclosure provides a shift register circuit 10. The shift register circuit 10 includes: a shift register unit 110 and a scan node setting unit 120.

For example, the shift register unit 110 includes an input terminal IN, an output terminal OUT, a first reset terminal RST1 and a second reset terminal RST2, and is configured to receive an input control signal at the input terminal IN and output a scan signal at the output terminal OUT. For example, the second reset terminal RST2 is a global reset terminal, and the shift register unit 110 is further configured to receive a global reset control signal at the second reset terminal RST2 to be reset.

For example, the scan node setting unit 120 includes a node setting circuit 121, a node starting circuit 122, and a node assisting setting circuit 123. For example, the control terminal of the node setting circuit 121 and the first terminal of the node auxiliary setting circuit 123 are connected to each other and both are configured to receive the scan input signal SIN, and the first terminal of the node setting circuit 121 is configured to receive the node setting signal set_1 , The second terminal of the node setting circuit 121 is connected to the first node N1. For example, the first terminal of the node activation circuit 122 is configured to receive the node activation control signal set_2, the second terminal of the node activation circuit 122 is connected to the input terminal IN of the shift register unit 110, and the control terminal of the node activation circuit 122 is connected to the first For node N1, the node activation circuit 122 is configured to be turned on under the control of the level of the first node N1 to transmit the node activation control signal set_2 to the input terminal IN of the shift register unit 110 as the input control of the shift register unit 110 Signal. For example, the second terminal of the node auxiliary setting circuit 123 is connected to the second terminal of the node starting circuit 122 and the input terminal IN of the shift register unit 110, and the control terminal of the node auxiliary setting circuit 123 is configured to receive the node auxiliary setting signal set_en.

The shift register circuit 10 provided by the embodiment of the present disclosure can transmit the node setting signal set_1 to the first node N1 through the node setting circuit 121, thereby controlling the level of the first node N1, and the node activation circuit 122 is at the first node. Under the control of the level of N1, the node start control signal set_2 is transmitted to the input terminal IN of the shift register unit 110 as an input control signal. The shift register unit 110 responds to the input control signal received by the input terminal IN, The output terminal OUT outputs a scan signal for scanning, so as to realize the function of starting at any node. By receiving the global reset control signal by the second reset terminal RST2 of the shift register 110, the shift register circuit can be turned off to stop output, thereby realizing the function of stopping at any node.

Therefore, the shift register circuit 10 provided by the embodiments of the present disclosure has the function of starting and stopping at any node, and at the same time has two modes of full drive and arbitrary node drive, which can improve the utilization of shift register circuit resources and effectively reduce the power consumption of the device. In the full drive mode, multiple cascaded shift register circuits 10 can sequentially output scan signals; in any node drive mode, a selected part of the shift register circuits 10 of the multiple cascaded shift register circuits 10 The scanning signals are sequentially output, and the remaining shift register circuits 10 may not output.

Hereinafter, in conjunction with FIG. 1B, the embodiments of the present disclosure are described by taking each transistor as an N-type transistor as an example, but this does not constitute a limitation to the embodiments of the present disclosure.

As shown in FIG. 1B, for example, in at least one embodiment, the node setting circuit 121 includes a first transistor T1. The gate of the first transistor T1 is connected to the scan input signal input terminal SIN to receive the scan input signal, and the first pole of the first transistor T1 is connected to the node setting signal input terminal set_1 to receive the node setting signal. The second pole is connected to the first node N1.

For example, the node startup circuit 122 includes a second transistor T2 and a first capacitor C1. The gate of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the node start control signal input terminal set_2 to receive the node start control signal, and the second electrode of the second transistor T2 is connected to the shift register The input terminal IN of the unit 110 is connected. The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode of the first capacitor C1 is connected to the input terminal IN of the shift register unit 110 and the second electrode of the second transistor T2.

For example, the node auxiliary setting circuit 123 includes a third transistor T3. The gate of the third transistor T3 is connected to the node auxiliary setting signal input terminal set_en to receive the node auxiliary setting signal, the first electrode of the third transistor T3 and the gate of the first transistor T1 are connected to each other and connected to the scan input signal input The terminal SIN is to receive the scan input signal, and the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2 and the input terminal IN of the shift register unit 110.

For example, when the scan input signal received by the scan input signal input terminal SIN is at a valid level (for example, a high level), the first transistor T1 is turned on, and the node setting signal set_1 is transmitted to the first node N1. When the set signal set_1 is raised (for example, from a low level to a high level), the first capacitor C1 is charged. When the charging of the first capacitor C1 is completed, it indicates that the first node N1 is successfully set. That is, the first node N1 is maintained at an operating potential (for example, a high level), and the second transistor T2 is maintained on. At this time, the node start control signal set_2 is transmitted to the input terminal IN of the shift register unit 110 through the turned-on second transistor T2 as an input control signal. The turn-off and turn-on of the third transistor T3 are controlled by the level of the node auxiliary set signal set_en.

It should be noted that, for the convenience and conciseness of description, in the various embodiments of the present disclosure, set_1 can represent both the node setting signal input terminal and the node setting signal provided by the node setting signal input terminal; set_2 can mean either The node start control signal input terminal also represents the node start control signal provided by the node start control signal input terminal; set_en can represent the node auxiliary set signal input terminal, and also the node auxiliary set signal provided by the node auxiliary set signal input terminal ; And SIN can represent both the scan input signal input terminal and the scan input signal provided by the scan input signal input terminal. CLKA can represent both the first clock signal terminal and the first clock signal provided by the first clock signal terminal; CLKB can represent both the second clock signal terminal and the second clock signal provided by the second clock signal terminal; RST1 is both It can represent the first reset terminal and the first reset control signal provided by the first reset terminal; RST2 can represent both the second reset terminal and the second reset control signal provided by the second reset terminal; and RSTN can both represent the node The reset signal input terminal also represents the node reset signal provided by the node reset signal input terminal.

2A is a schematic block diagram of another shift register circuit provided by at least one embodiment of the present disclosure, and FIG. 2B is an example structure diagram of a scan node setting unit included in the shift register circuit in FIG. 2A.

As shown in FIG. 2A, at least one embodiment of the present disclosure provides a shift register circuit 20. The shift register circuit 20 includes a shift register unit 210 and a scan node setting unit 220.

For example, the shift register unit 210 includes an input terminal IN, an output terminal OUT, a first reset terminal RST1 and a second reset terminal RST2. For example, the scanning node setting unit 220 includes a node setting circuit 221, a node starting circuit 222, and a node assisting setting circuit 223.

It should be noted that the detailed description of the node setting circuit 221, the node starting circuit 222, and the node auxiliary setting circuit 223 can refer to the node setting circuit 121, the node starting circuit 122, and the node auxiliary setting circuit 123 in the above embodiment. For a detailed description of the shift register unit 210, reference may be made to the detailed description of the shift register unit 110 in the foregoing embodiment, which will not be repeated here.

For example, as shown in FIG. 2A, in at least one embodiment, the scan node setting unit 220 in the shift register circuit 20 may further include a node reset circuit 224. For example, the control terminal of the node reset circuit 224 is configured to receive the node reset signal RSTN, the first terminal of the node reset circuit 224 is connected to the first node N1, and the second terminal of the node reset circuit 224 is configured to receive the first voltage V1 (for example, low Voltage).

For example, as shown in FIG. 2B, in conjunction with the related description of FIG. 1B, the embodiments of the present disclosure are described by taking each transistor as an N-type transistor as an example, but this does not constitute a limitation to the embodiments of the present disclosure.

In at least one embodiment, the node reset circuit 224 in the scan node setting unit 220 may include a fourth transistor T4. The gate of the fourth transistor T4 is connected to the node reset signal input terminal RSTN to receive the node reset signal, the first electrode of the fourth transistor T4 is connected to the first node N1, the second electrode of the fourth transistor T4 and the first voltage terminal V1 Connect to receive the first voltage (e.g., low voltage). For example, the first voltage terminal V1 may be configured to keep inputting a low-level direct current signal, and the first voltage terminal V1 is, for example, a ground terminal.

For example, when the node reset signal RSTN is at a high level, the fourth transistor T4 is turned on, and the first node N1 is electrically connected to the first voltage terminal V1, so that the first capacitor C1 is discharged. After the first capacitor C1 is discharged, the first node N1 is maintained at a non-operating potential (for example, a low level), so that the second transistor T2 is kept off.

FIG. 3A is a schematic block diagram of a shift register unit provided by at least one embodiment of the present disclosure, and FIG. 3B is an example structure diagram of the shift register unit in FIG. 3A.

As shown in FIG. 3A, for example, in at least one embodiment of the present disclosure, the shift register unit 310 includes an input circuit 311. The input circuit 311 is connected to the second node N2 and the input terminal IN, and the input circuit 311 is configured to control the level of the second node N2 (for example, a pull-up node) in response to the input control signal received by the input terminal IN.

For example, as shown in FIG. 3B, in some examples, the input circuit 311 includes a fifth transistor T5. The gate of the fifth transistor T5 is connected to the input terminal IN to receive the input control signal, the first electrode of the fifth transistor T5 is connected to the first control signal terminal CN to receive the first control signal, and the second electrode of the fifth transistor T5 is connected To the second node N2.

For example, when the input control signal provided by the input terminal IN is at an effective level (for example, a high level), the fifth transistor T5 is turned on, so that the first control signal terminal CN is electrically connected to the second node N2, so that the first control signal terminal CN is electrically connected to the second node N2. The first control signal provided by the control signal terminal CN is input to the second node N2. For example, if the first control signal is maintained at a high level, the potential of the second node N2 is pulled up to the working potential.

For example, in at least one embodiment of the present disclosure, the shift register unit 310 includes an output circuit 312. The output circuit 312 is connected to the second node N2, the first clock signal terminal CLKA, and the output terminal OUT, and the output circuit 312 is configured to, under the control of the level of the second node N2, connect the first clock signal terminal CLKA to the first The clock signal is output to the output terminal OUT as a scanning signal.

For example, as shown in FIG. 3B, in some examples, the output circuit 312 includes a sixth transistor T6 and a second capacitor C2. The gate of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first clock signal terminal CLKA to receive the first clock signal CLKA, the second electrode of the sixth transistor T6 and the output terminal OUT connect. The first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode of the second capacitor C2 is connected to the second electrode of the sixth transistor T6.

For example, when the second node N2 (ie, the pull-up node) is at a working potential (for example, a high level), the sixth transistor T6 is turned on, thereby outputting the first clock signal CLKA to the output terminal OUT. The second capacitor C2 is used to maintain the level of the second node N2 and achieve a bootstrap function when the output terminal OUT outputs a signal.

For example, in at least one embodiment of the present disclosure, the shift register unit 310 may further include a first control circuit 313. The first control circuit 313 is connected to the second node N2 and the third node N3 (for example, a pull-down node), and the first control circuit 313 is configured to control the level of the third node N3 in response to the level of the second node N2.

For example, as shown in FIG. 3B, the first control circuit 313 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a third capacitor C3. The gate of the seventh transistor T7 is connected to the first electrode and connected to the second clock signal terminal CLKB to receive the second clock signal, and the second electrode of the seventh transistor T7 is connected to the third node N3. The gate of the eighth transistor T8 is connected to the second node N2, the first electrode of the eighth transistor T8 is connected to the third node N3, and the second electrode of the eighth transistor T8 is connected to the second voltage terminal V2 (for example, the first The voltage terminal V1) is connected to receive the second voltage (for example, a low voltage). The gate of the ninth transistor T9 is connected to the output terminal OUT, the first electrode of the ninth transistor T9 is connected to the third node N3, and the second electrode of the ninth transistor T9 is connected to the second voltage terminal V2 to receive the second voltage (for example ,low voltage). The first pole of the third capacitor C3 is connected to the third node N3, and the second pole of the third capacitor C3 is connected to the second voltage terminal V2.

For example, in some examples, the second voltage terminal V2 is configured to maintain the input DC low-level signal, for example, to ground. For example, in some examples, the second voltage terminal V2 may be the same voltage terminal as the first voltage terminal V1 to provide the same low-level signal; in other examples, the second voltage terminal V2 may also be a separately provided voltage At the end, the embodiment of the present disclosure does not limit this.

For example, when the second node N2 is at an operating potential (for example, a high level), the eighth transistor T8 and the sixth transistor T6 are turned on. Through the turned-on eighth transistor T8, the third node N3 is electrically connected to the second voltage terminal V2 (for example, the low voltage terminal), thereby pulling down the potential of the third node N3. The signal provided by the first clock signal terminal CLKA is transmitted to the output terminal OUT through the turned-on sixth transistor T6. When the first clock signal CLKA is at an active level (for example, a high level), the ninth transistor T9 is turned on, and the The three node N3 is electrically connected to the second voltage terminal V2 (for example, a low voltage terminal), thereby further pulling down the potential of the third node N3, so that the third node N3 is at a non-operating potential (for example, a low level). When the third node N3 is at a non-operating potential (for example, a low level), the third capacitor C3 is discharged to maintain the low level of the third node N3. When the second node N2 is at a non-operating potential (for example, a low level), the eighth transistor T8, the sixth transistor T6, and the ninth transistor T9 are turned off, and when the second clock signal CLKB is at an active level (for example, a high level) When the seventh transistor T7 is turned on, the high-level signal provided by the second clock signal terminal CLKB is written into the third node N3 through the seventh transistor T7, so as to pull up the potential of the third node N3 to the working potential (for example , High level), when the third node N3 is at a working potential (for example, a high level), the third capacitor C3 is charged to maintain the high level of the third node N3.

For example, as shown in FIG. 3A, in at least one embodiment of the present disclosure, the shift register unit 310 may further include a noise reduction circuit 314. The noise reduction circuit 314 is connected to the third node N3 and the output terminal OUT, and is configured to reduce noise on the output terminal OUT under the control of the level of the third node N3.

For example, as shown in FIG. 3B, the noise reduction circuit 314 includes a tenth transistor T10. The gate of the tenth transistor T10 is connected to the third node N3, the first electrode of the tenth transistor T10 is connected to the output terminal OUT, and the second electrode of the tenth transistor T10 is connected to the second voltage terminal V2 to receive the second voltage (low Voltage).

For example, when the third node N3 is at a working potential (for example, a high level) and the tenth transistor T10 is turned on, the output terminal OUT is electrically connected to the second voltage terminal V2, thereby reducing noise on the output terminal OUT.

For example, as shown in FIG. 3A, in at least one embodiment, the shift register unit 310 further includes a second control circuit 315. The second control circuit 315 is connected to the second node N2 and the third node N3, and the second control circuit 315 is configured to control the level of the second node N2 in response to the level of the third node N3.

For example, as shown in FIG. 3B, the second control circuit 315 includes an eleventh transistor T11. The gate of the eleventh transistor T11 is connected to the third node N3, the first electrode of the eleventh transistor T11 is connected to the second node N2, and the second electrode of the eleventh transistor T11 is connected to the second voltage terminal V2 to receive the Two voltage (for example, low voltage).

For example, when the third node N3 is at a working potential (for example, a high level), the eleventh transistor T11 is turned on, and the second node N2 is electrically connected to the second voltage terminal V2, thereby writing a low voltage to the second node N2 to perform pull-down noise reduction on the second node N2.

For example, in at least one embodiment of the present disclosure, the shift register unit 310 further includes a first reset circuit 316 and a second reset circuit 317. The first reset circuit 316 is connected to the second node N2 and the first reset terminal RST1, and the first reset circuit 316 is configured to reset the second node N2 in response to the first reset control signal of the first reset terminal RST1. The second reset circuit 317 is connected to the second node N2 and the second reset terminal RST2, and the second reset circuit 317 is configured to reset the second node N2 in response to the second reset control signal of the second reset terminal RST2.

For example, as shown in FIG. 3B, the first reset circuit 316 includes a twelfth transistor T12. The gate of the twelfth transistor T12 is connected to the first reset terminal RST1 to receive the first reset control signal, the first electrode of the twelfth transistor T12 is connected to the second node N2, and the second electrode of the twelfth transistor T12 is connected to The second control signal terminal CNB is used to receive the second control signal.

For example, in some examples, the second reset circuit 317 includes a thirteenth transistor T13. The gate of the thirteenth transistor T13 is connected to the second reset terminal RST2 to receive the second reset control signal. The electrode is connected to the second node N2, and the second electrode of the thirteenth transistor T13 is connected to the second voltage terminal V2 to receive the second voltage (for example, a low voltage).

It should be noted that the first reset terminal RST1 is the local reset terminal of the shift register unit 310, the second reset terminal RST is the global reset terminal of the shift register unit 310, and the second reset control signal is, for example, a global reset control signal.

It should be noted that in the various embodiments of the present disclosure, the storage capacitors (for example, the first capacitor C1, the second capacitor C2, and the third capacitor C3 in FIGS. 1B, 2B, and 3B) may be capacitive devices manufactured through a process, For example, a capacitor device realized by manufacturing a special capacitor electrode, each electrode of the storage capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), and the like. The storage capacitance may also be a parasitic capacitance between transistors, which may be realized by the transistor itself and other devices and circuits, which is not specifically limited in the embodiments of the present disclosure.

It should be noted that the description of the specific circuit structure of the shift register circuit 10 in the embodiments of the present disclosure is exemplary rather than restrictive. For example, the shift register unit 110 may adopt a conventional structure. For example, it may be a structure including 9 transistors and 2 capacitors (ie 9T2C), or a structure including 4 transistors and 1 capacitor (ie 4T1C). The disclosed embodiments do not specifically limit this.

It should be noted that in the description of the various embodiments of the present disclosure, the first node N1, the second node N2, and the third node N3 do not represent actual components, but represent the junction of related electrical connections in the circuit diagram.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin film transistors are used as examples for description. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one pole is directly described as the first pole and the other pole is the second pole.

In addition, the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example. At this time, the first electrode of the transistor is the drain, and the second electrode is the source. It should be noted that the present disclosure includes but is not limited to this. For example, one or more transistors in the shift register circuit 10 provided by the embodiment of the present disclosure may also be P-type transistors. In this case, the first electrode of the transistor is the source and the second electrode is the drain. The poles of the transistors of a certain type are connected correspondingly with reference to the poles of the corresponding transistors in the embodiments of the present disclosure, and the corresponding voltage terminals provide the corresponding high voltage or low voltage. When N-type transistors are used, indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) can be used as the active layer of the thin film transistor. Compared with the use of low temperature polysilicon (LTPS) or amorphous silicon (such as hydrogenated amorphous silicon), As the active layer of thin film transistors, crystalline silicon can effectively reduce the size of the transistor and prevent leakage current.

FIG. 4 is an exemplary circuit structure diagram of a shift register circuit provided by at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a shift register circuit 40 including a shift register unit 410 and a scan node setting unit 420. As shown in FIG. 4, for example, the shift register circuit 40 includes first to thirteenth transistors T1-T13 and first to third capacitors C1-C3. Regarding the description of the structure of the shift register circuit 40, reference may be made to the relevant description of the foregoing embodiment, which will not be repeated here. For example, the circuit structure shown in FIG. 4 can be obtained by combining the scan node setting unit 220 in FIG. 2B and the shift register unit 310 in FIG. 3B.

The shift register circuit 40 has an arbitrary node start and stop function, and has two modes of full drive and arbitrary node drive at the same time. In practical applications, it can be combined with touch coordinate positioning technology to provide users with an efficient pattern recognition solution that scans only specific areas (such as contact areas), thereby significantly reducing the time of pattern scanning, improving the response speed of pattern recognition, and at the same time greatly Improve the utilization of the shift register circuit and effectively reduce the power consumption of the device.

At least one embodiment of the present disclosure further provides a gate drive circuit, which includes a plurality of cascaded shift register circuits provided by any embodiment of the present disclosure.

FIG. 5A is a schematic block diagram of a gate driving circuit provided by at least one embodiment of the present disclosure, and FIG. 5B is an exemplary structure diagram of a gate driving circuit provided by at least one embodiment of the present disclosure. As shown in FIGS. 5A and 5B, the gate driving circuit 50 includes a plurality of cascaded shift register circuits (for example, A1, A2, A3, etc.). The number of multiple shift register circuits is not limited and can be determined according to actual needs. For example, the shift register circuit adopts the shift register circuit 10 provided in any embodiment of the present disclosure. For example, in the gate driving circuit 50, part or all of the shift register circuits may adopt the shift register circuit 10 provided in any embodiment of the present disclosure. For example, the gate driving circuit 50 can be directly integrated on the array substrate of the display device using the same process as the thin film transistor to form a GOA, which can realize, for example, a progressive scan driving function and only target specific areas (such as contact areas). Perform scan drive function. For example, as shown in FIG. 5B, each shift register circuit may adopt the example circuit structure of the shift register circuit 40 shown in FIG. 4, and a plurality of shift register circuits (for example, A1, A2, A3) Make specific connections in the manner described in the text.

For example, in some examples, as shown in FIGS. 5A and 5B, each shift register circuit may have a scan input signal input terminal SIN, a first clock signal terminal CLKA, a second clock signal terminal CLKB, an output terminal OUT, and a node setting. The bit signal input terminal set_1, the node start control signal input terminal set_2, the node auxiliary set signal input terminal set_en, the first reset terminal RST1, the second reset terminal RST2, and the node reset signal input terminal RSTN.

For example, in the gate drive circuit 50 provided by an embodiment of the present disclosure, the scan input signal input terminal SIN of the nth stage shift register circuit is connected to the output terminal OUT of the n-1th stage shift register circuit, and the nth stage The first reset terminal RST1 of the shift register circuit is connected to the output terminal OUT of the n+1th stage shift register circuit, and n is an integer greater than 1.

For example, in some examples, as shown in FIGS. 5A and 5B, except for the shift register circuit of the last stage (for example, the third shift register circuit A3), the first reset terminals RST1 and RST1 of the shift register circuits of the remaining stages are The output terminal OUT of the shift register circuit of the next stage is connected. Except for the first stage shift register circuit (for example, the first shift register circuit A1), the scan input signal input terminals SIN of the shift register circuits of the other stages are connected to the output terminal OUT of the previous stage shift register circuit. For example, the scan input signal input terminal SIN of the first stage shift register circuit may be configured to receive the trigger signal STV, and the first reset terminal RST1 of the last stage shift register circuit may be configured to receive the reset signal RESET, and the trigger signal STV And the reset signal RESET is not shown in FIGS. 5A and 5B.

For example, the gate driving circuit 50 may also include a timing controller. For example, the timing controller T-CON is configured to communicate with the first clock signal line CLKA_L, the second clock signal line CLKB_L, the node setting signal line set_1_L, the node start control signal line set_2_L, the node auxiliary setting signal line set_en_L, and the second clock signal line CLKB_L. The reset signal line RST2_L and the node reset signal line RSTN_L are connected to provide respective corresponding signals to the shift register circuits of each stage. The timing controller T-CON may also be configured to provide the trigger signal STV and the reset signal RESET. It should be noted that the phase relationship between the multiple clock signals provided by the timing controller T-CON may be determined according to actual requirements.

It should be noted that in the embodiments of the present disclosure, the first clock signal CLKA and the second clock signal CLKB are triggered alternately, that is, the first clock signal CLKA and the second clock signal CLKB alternately provide high-level pulses.

FIG. 6 is a signal timing diagram of a gate driving circuit provided by at least one embodiment of the present disclosure. The working principle of the gate driving circuit 50 shown in FIGS. 5A and 5B will be described below in conjunction with the signal timing diagram shown in FIG. 6. It should be noted that the level of the potential in the signal timing diagram shown in FIG. 6 is only schematic, and does not represent the true potential value. In the embodiment shown in FIG. 6, it is assumed that the target scan area corresponds to the Nth to N+M stage shift register circuits in the gate driving circuit (that is, the Nth to N+Mth rows).

As shown in FIG. 6, first, in the entire signal timing diagram, both the first voltage V1 and the second voltage V2 are maintained at a low level, the first control signal CN is maintained at a high level, and the second control signal CNB is maintained at a low level. Level.

Before the P1 phase (node setting phase), there is an interval S1. In the S1 interval, the second reset control signal RST2 is at a high level, so that the entire gate driving circuit 50 is reset (that is, a global reset). The trigger signal STV, the node setting signal set_1, the node reset signal RSTN, the node start control signal set_2, the first clock signal CLKA, and the second clock signal CLKB are all low, and the node auxiliary setting signal set_en is high.

In the P1 phase (node setting phase), the second reset control signal RST2 changes from a high level to a low level, and the first-stage shift register circuit in the gate drive circuit 50 (for example, A1 in FIGS. 5A and 5B) The trigger signal STV received by the input terminal SIN of) changes to a high level to drive the first-stage shift register circuit to work, and then the first clock signal CLKA and the second clock signal CLKB start to trigger alternately (that is, alternate high-level pulses are provided ), the output terminal OUT_1 of the first-stage shift register circuit starts to output, and then OUT_1 is transmitted to the second-stage shift register circuit (for example, A2 in FIGS. 5A and 5B), as the scan input signal SIN to drive the second stage The shift register circuit, in the same way, sequentially drives the next stage shift register circuit for output. Until the N-1 stage shift register circuit outputs OUT_N-1, the node setting signal set_1 changes from a low level to a high level, and the node auxiliary setting signal set_en changes from a high level to a low level. At this time, the first capacitor C1 is charged. When the first capacitor C1 is fully charged, it indicates that the node is successfully set, and the second transistor T2 remains on, that is, the Nth row is set as the first row start of the next scan. At this time, STV keeps low level all the time, and the first-stage shift register circuit will not be driven.

In the S2 interval, the second reset control signal RST2 changes from a low level to a high level, and resets the entire gate driving circuit 50. The trigger signal STV, the node setting signal set_1, the node reset signal RSTN, the node start control signal set_2, the first clock signal CLKA, and the second clock signal CLKB are all low, and the node auxiliary setting signal set_en is high.

In the P2 phase (the first node activation phase), the second reset control signal RST2 changes from high to low, the node activation control signal set_2 changes from low to high, and the node auxiliary set signal set_en changes from high The level becomes low. At this time, through the turned-on second transistor T2, the effective level (high level) of the node start control signal set_2 is transmitted to the input end of the shift register unit to drive the Nth stage shift register circuit to work, and then the first clock The signal CLKA and the second clock signal CLKB start to trigger alternately, the Nth stage shift register circuit outputs OUT_N, and then the output signal OUT_N drives the N+1th stage shift register circuit to output, and proceed in sequence.

In the S3 interval, that is, after the N+M stage shift register circuit outputs OUT_N+M, the second reset control signal RST2 changes from a low level to a high level to reset the entire gate driving circuit 50. The trigger signal STV, the node setting signal set_1, the node reset signal RSTN, the node start control signal set_2, the first clock signal CLKA, and the second clock signal CLKB are all low, and the node auxiliary setting signal set_en is high.

In the P3 stage (the second node startup stage), when the target area needs to be scanned again, that is, when the N-th to N+M-stage shift register circuits are driven again, the second reset control signal RST2 changes from high level to low level , The node start control signal set_2 changes from low level to high level, and the node auxiliary set signal set_en changes from high level to low level, which directly drives the Nth stage shift register circuit to work, Nth to N+M stages The working process of the shift register circuit is basically the same as that of the P2 stage, and will not be repeated here.

In the S4 interval, that is, after the N+M stage shift register circuit outputs OUT_N+M, the second reset control signal RST2 changes from a low level to a high level to reset the entire gate driving circuit 50. The trigger signal STV, the node setting signal set_1, the node start control signal set_2, the first clock signal CLKA, and the second clock signal CLKB are all low, and the node auxiliary setting signal set_en is high. Assuming that the entire scanning operation on the target area ends at this time, the node reset signal RSTN changes from low level to high level, and the first capacitor C1 is discharged. After the first capacitor C1 is discharged, it indicates that the node reset is successful.

For example, in the full drive mode, the node setting operation in the P1 stage may not be performed, so that the gate drive circuit 50 can start scanning from the first row row by row, which is similar to a normal scanning method. In any node drive mode, according to actual needs, any row (for example, the Nth row) shift register circuit can be set in the P1 stage, so that the gate drive circuit 50 can be used in the P2 stage and the P3 stage. Scanning starts at the Nth row without starting from the first row, and by setting the timing of the second reset control signal RST2, the above scanning operation can be ended in any row (for example, the N+Mth row) shift register circuit.

It should be noted that in the embodiments of the present disclosure, the above-mentioned S1-S4 interval may be a blanking period between frames, or may be an interval set according to requirements. No restrictions.

It can be seen from the signal timing diagram of FIG. 6 that the gate drive circuit provided by the embodiment of the present disclosure has the function of starting and stopping at any node, and has two modes of full drive and arbitrary node drive at the same time. Compared with the traditional gate drive circuit Each frame scan starts from the first-stage shift register circuit and needs to be driven row by row from beginning to end. The gate drive circuit provided by the embodiment of the present disclosure can successfully set the node (for example, set the first row of the Nth row). After row start), each subsequent frame can be driven directly from the Nth row, thereby improving the resource utilization of the gate driving circuit, effectively reducing the power consumption of the device, and shortening the scanning time.

FIG. 7A is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure, and FIG. 7B is a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure. As shown in FIG. 7A, the electronic device 70 includes the gate driving circuit 701 and the array circuit 702 in any of the above embodiments. The array circuit 702 includes a multi-stripe scan line GL, and the multi-stripe scan line GL is correspondingly connected to a plurality of output terminals of a plurality of shift register circuits in the gate driving circuit 701.

For example, in some examples, the array circuit 702 is a pattern collection array circuit, and the pattern collection array circuit can be used to collect fingerprints, palm prints, and the like. For example, the gate driving circuit 701 may output a scan signal to the array circuit 702 to scan and drive all rows or any row of sub-circuits in the array circuit 702, so as to realize the pattern collection.

For example, in some examples, the electronic device 70 further includes a touch circuit 703. For example, the touch circuit 703 is configured to perform touch detection on the touch area, and the pattern collection array circuit is located in the touch area detected by the touch circuit 703.

For example, in some examples, as shown in FIG. 7B, the electronic device 70 includes a touch display panel, and the touch area of the touch circuit 703 is the display area 710. The display area 710 includes a pattern recognition area (for example, a fingerprint recognition area) 1112. The pattern recognition area 1112 may be part or all of the display area 710, thereby realizing a partial or full-screen pattern recognition function. The recognition area 1112 not only has a pattern recognition function, but also has a touch function and a display function. The user can put handprints (for example, fingerprints or palmprints) in the pattern recognition area 1112 or press the pattern recognition area 1112. When the light-emitting unit of the electronic device 70 emits light, the light emitted by the light-emitting unit is reflected back through the handprint. After the photosensitive imaging device is collected and imaged, the pattern image obtained by the photosensitive imaging device can be used for subsequent pattern recognition operations.

The touch circuit 703 can be of various types, such as a self-capacitance or mutual-capacitance type touch circuit, including an array composed of a plurality of touch electrodes (such as touch sensing electrodes and/or touch sensing driving electrodes), so that the user will When the handprint is placed in the touch area or the touch area is pressed, the array can not only determine whether it is touched or not, but also determine the current touch range in the touched area, by determining the leftmost electrode and the most touched area. The right electrode, the uppermost electrode, and the lowermost electrode, etc., obtain a touch range, such as a rectangular area determined by the aforementioned electrodes (see the dashed frame in the figure). As shown in Fig. 7B, when the scanning direction of the pattern recognition area is the upper and lower sides in the figure (for example, scanning progressively from the upper side to the lower side), the positions of the upper and lower sides of the rectangular area (for example, the number of rows) ) Can be used to determine the part of the pattern recognition area that needs to be scanned in the current pattern recognition process, that is, the part of the pattern recognition area that overlaps the aforementioned rectangular area in the height direction, so that it is not necessary to scan the pattern recognition area 1112 as a whole, This significantly shortens the pattern scanning time and improves the pattern recognition response speed.

FIG. 8 is a flowchart of a driving method 800 of a gate driving circuit provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 8, the driving method 800 of the gate driving circuit may include:

Step S801: In the first stage, the node setting circuit in the first shift register circuit transmits the node setting signal to the first node, thereby controlling the level of the first node;

Step S802: In the second stage, the node activation circuit in the first shift register circuit transmits the node activation control signal to the input of the shift register unit in the first shift register circuit under the control of the level of the first node The terminal is used as the input control signal;

Step S803: In the third stage, the shift register unit in the first shift register circuit outputs a scan signal at the output terminal in response to the input control signal received at the input terminal.

It should be noted that the first shift register circuit is any one stage shift register circuit in the gate drive circuit.

For example, in at least one embodiment, in the case of not adopting any node driving mode, that is, adopting the full driving mode, the driving method of the gate driving circuit may include: a node-assisted setting circuit transmits the scan input signal to the shift The input terminal of the register unit serves as an input control signal, and the shift register unit outputs a scan signal at the output terminal in response to the input control signal received by the input terminal. This method is not shown in the figure.

FIG. 9 is a flowchart of a driving method 900 of an electronic device provided by at least one embodiment of the present disclosure. For example, in some examples, the driving method 900 of the electronic device may include:

According to the timing of the node set signal, the node start control signal and the node auxiliary set signal, the scan signal is output to the array circuit through the gate drive circuit.

For example, in some examples, as shown in FIG. 9, when the electronic device further includes a touch circuit, the driving method 900 of the electronic device may include:

Step S901: Determine the timing of the node setting signal, the node starting control signal, and the node auxiliary setting signal according to the detection result of the touch circuit;

Step S902: According to the timing of the node setting signal, the node start control signal, and the node auxiliary setting signal, output a scan signal to the array circuit through the gate drive circuit.

For example, in this embodiment, the touch position can be obtained according to the detection result of the touch circuit. Therefore, in the case where the pattern collection is required, only the area near the touch position needs to be pattern collection, and there is no need to perform pattern collection. Full-screen texture collection. Therefore, the timing of the node set signal, node start control signal, and node auxiliary set signal can be determined, so that the shift register circuit corresponding to the area near the touch position outputs the scan signal, so that only the area near the touch position is performed. Grain collection operation.

For detailed descriptions and technical effects of the driving method provided by the embodiments of the present disclosure, reference may be made to the corresponding descriptions of the shift register circuit, the gate driving circuit, and the electronic device in the embodiments of the present disclosure, which will not be repeated here.

FIG. 10 is a flowchart of a method 1000 for collecting patterns of an electronic device according to at least one embodiment of the present disclosure. For example, as shown in FIG. 10, the method 1000 for collecting patterns of the electronic device may include the following operations:

Step S1001: Determine the target collection area based on the detection result of the touch circuit;

Step S1002: driving the shift register circuits in the gate driving circuit corresponding to the target acquisition area to sequentially output scanning signals to clear the charges in the array circuits in the target acquisition area;

Step S1003: the array circuit in the target collection area accumulates charges;

Step S1004: driving the shift register circuit in the gate driving circuit corresponding to the target acquisition area to sequentially output scanning signals to read the charges accumulated in the array circuit in the target acquisition area.

It should be noted that in the process of clearing the charge (step S1002) and the process of reading the accumulated charge (step S1004), that is, after the node is successfully set (the first row is successfully set), the gate drive circuit The shift register circuit that does not correspond to the target acquisition area may not output.

FIG. 11 is a schematic diagram of a comparison between a scheme of fingerprint collection using a gate drive circuit and a scheme of fingerprint collection using the gate drive circuit provided in an embodiment of the present disclosure. In conjunction with the method for collecting patterns of the electronic device shown in FIG. 10, a case where an under-screen optical device performs fingerprint collection is taken as an example for description. As shown in Figure 11, Scheme 1 is a traditional fingerprint collection scheme, that is, each frame scans the screen line by line from the beginning to the end. For example, the screen includes one fingerprint pressing area and two fingerprint-free areas (ie, areas above and below the fingerprint pressing area on the screen).

For example, in the embodiment of the present disclosure, based on the detection result of the touch circuit, the target acquisition area (for example, the area near the touch position) can be determined, and the shift register circuit corresponding to the target acquisition area can be obtained as the first in GOA. N to N+M row shift register circuit, so the timing of node setting signal, node start control signal, node auxiliary setting signal, reset signal, etc. can be set.

For example, in the fingerprint collection process of Scheme 1, it is assumed that the traditional gate driving circuit starts to scan the Xth frame to clear the charge. First, perform a quick scan on the first fingerprint-free area, and the required time is t1; then perform a normal scan on the fingerprint pressing area, and the required time is t2; then perform a quick scan on the second fingerprint-free area, and the required time is t3. Then the time to complete the X-th frame scan is t1+t2+t3. Then, between the Xth frame and the X+1th frame, exposure is performed to accumulate charge, and the required time is t4. Then start to scan the X+1th frame from the beginning to the end to read the charge, and the time to complete the X+1th frame scan is also t1+t2+t3. Therefore, in scheme 1, the fingerprint collection period is V1=2*(t1+t2+t3)+t4.

For example, solution 2 is to use the gate driving circuit and driving method provided by the embodiments of the present disclosure to perform pattern collection, and only scan the target collection area (ie, the area near the touch position or the fingerprint pressing area). For example, combined with the touch positioning technology, it is known that the gate drive circuit corresponding to the fingerprint pressing area is the Nth to N+Mth row (that is, the Nth to N+M stage shift register circuit), according to the above implementation of the present disclosure For the GOA driving method provided in the example, after completing the setting of the Nth row, only the Nth to N+Mth rows can be driven, and the shift register circuit corresponding to the fingerprint-free pressing area does not output.

For example, in the fingerprint collection process of Scheme 2, the time to complete the scanning of the Xth frame and the X+1th frame is t2, plus the exposure time t4. Therefore, in Scheme 2, the fingerprint collection cycle is V2=2* t2+t4.

Therefore, compared with the solution 1, the scheme 2 directly omits the ineffective scanning time of the fingerprint-free area, significantly shortens the fingerprint scanning time, improves the fingerprint recognition response speed, and greatly reduces the waste of GOA resources and effectively reduces the power consumption of the device. .

For this disclosure, the following points need to be explained:

(1) The drawings of the embodiments of the present disclosure only refer to the structures related to the embodiments of the present disclosure, and other structures can refer to the usual design.

(2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (26)

1. A shift register circuit includes a shift register unit and a scan node setting unit, wherein the shift register unit includes an input terminal, an output terminal, and a global reset terminal, and is configured to receive an input control signal at the input terminal , Output a scan signal at the output terminal, and receive a global reset control signal at the global reset terminal to be reset,

   The scanning node setting unit includes a node setting circuit, a node starting circuit, and a node auxiliary setting circuit,

   The control terminal of the node setting circuit and the first terminal of the node auxiliary setting circuit are connected to each other and both are configured to receive a scan input signal, and the first terminal of the node setting circuit is configured to receive a node setting signal, The second end of the node setting circuit is connected to the first node;

   The first terminal of the node activation circuit is configured to receive a node activation control signal, the second terminal of the node activation circuit is connected to the input terminal of the shift register unit, and the control terminal of the node activation circuit is connected to the The first node, the node activation circuit is configured to be turned on under the control of the level of the first node to transmit the node activation control signal to the input terminal of the shift register unit as the shift Input control signal of the register unit;

   The second end of the node auxiliary setting circuit is connected to the second end of the node starting circuit and the input end of the shift register unit, and the control end of the node auxiliary setting circuit is configured to receive node auxiliary setting Signal.
2. The shift register circuit according to claim 1, wherein the node setting circuit includes a first transistor,

   The gate of the first transistor is connected to the scan input signal input terminal to receive the scan input signal, and the first pole of the first transistor is connected to the node setting signal input terminal to receive the node setting signal, so The second electrode of the first transistor is connected to the first node.
3. The shift register circuit according to claim 2, wherein the node startup circuit includes a second transistor and a first capacitor,

   The gate of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the node activation control signal input terminal to receive the node activation control signal, and the second transistor of the second transistor is connected to the node activation control signal input terminal. Pole is connected to the input end of the shift register unit;

   The first electrode of the first capacitor is connected to the first node, and the second electrode of the first capacitor is connected to the input terminal of the shift register unit and the second electrode of the second transistor.
4. The shift register circuit according to claim 3, wherein the node auxiliary setting circuit includes a third transistor,

   The gate of the third transistor is connected to the node auxiliary setting signal input terminal to receive the node auxiliary setting signal, and the first electrode of the third transistor and the gate of the first transistor are connected to each other and connected to The scan input signal input terminal is to receive the scan input signal, and the second electrode of the third transistor is connected to the second electrode of the second transistor and the input terminal of the shift register unit.
5. The shift register circuit according to any one of claims 1 to 4, wherein the scanning node setting unit further comprises a node reset circuit,

   The control terminal of the node reset circuit is configured to receive a node reset signal, the first terminal of the node reset circuit is connected to the first node, and the second terminal of the node reset circuit is configured to receive a first voltage.
6. The shift register circuit according to claim 5, wherein the node reset circuit includes a fourth transistor,

   The gate of the fourth transistor is connected to the node reset signal input terminal to receive the node reset signal, the first electrode of the fourth transistor is connected to the first node, and the second electrode of the fourth transistor is connected to the The first voltage terminal is connected to receive the first voltage.
7. The shift register circuit according to any one of claims 1 to 4, wherein the shift register unit further comprises an input circuit,

   The input circuit is connected to the second node and the input terminal, and is configured to control the level of the second node in response to the input control signal received by the input terminal.
8. The shift register circuit according to claim 7, wherein the input circuit includes a fifth transistor,

   The gate of the fifth transistor is connected to the input terminal to receive the input control signal, the first electrode of the fifth transistor is connected to the first control signal terminal to receive the first control signal, and the fifth transistor The second pole is connected to the second node.
9. The shift register circuit according to any one of claims 1 to 4, wherein the shift register unit further comprises an output circuit,

   The output circuit is connected to the second node, the first clock signal terminal, and the output terminal, and is configured to output the first clock signal of the first clock signal terminal under the control of the level of the second node To the output terminal as the scan signal.
10. The shift register circuit according to claim 9, wherein the output circuit includes a sixth transistor and a second capacitor,

    The gate of the sixth transistor is connected to the second node, the first pole of the sixth transistor is connected to the first clock signal terminal to receive the first clock signal, and the first pole of the sixth transistor is connected to the first clock signal terminal. The two poles are connected to the output terminal;

    The first electrode of the second capacitor is connected to the second node, and the second electrode of the second capacitor is connected to the second electrode of the sixth transistor.
11. The shift register circuit according to any one of claims 1 to 4, wherein the shift register unit further comprises a first control circuit,

    The first control circuit is connected to the second node and the third node, and is configured to control the level of the third node in response to the level of the second node.
12. 11. The shift register circuit according to claim 11, wherein the first control circuit comprises: a seventh transistor, an eighth transistor, a ninth transistor, and a third capacitor;

    The gate of the seventh transistor is connected to the first electrode and connected to the second clock signal terminal to receive the second clock signal, and the second electrode of the seventh transistor is connected to the third node;

    The gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the third node, and the second electrode of the eighth transistor is connected to the second voltage terminal to receive Second voltage,

    The gate of the ninth transistor is connected to the output terminal, the first electrode of the ninth transistor is connected to the third node, and the second electrode of the ninth transistor is connected to the second voltage terminal to Receiving the second voltage,

    The first pole of the third capacitor is connected to the third node, and the second pole of the third capacitor is connected to the second voltage terminal.
13. The shift register circuit according to any one of claims 1 to 4, wherein the shift register unit further comprises a noise reduction circuit,

    The noise reduction circuit is connected to the third node and the output terminal, and is configured to reduce noise on the output terminal under the control of the level of the third node.
14. The shift register circuit according to claim 13, wherein the noise reduction circuit includes a tenth transistor,

    The gate of the tenth transistor is connected to the third node, the first electrode of the tenth transistor is connected to the output terminal, and the second electrode of the tenth transistor is connected to the second voltage terminal to receive the third node. Two voltages.
15. The shift register circuit according to any one of claims 1 to 4, wherein the shift register unit further comprises a second control circuit,

    The second control circuit is connected to the second node and the third node, and is configured to control the level of the second node in response to the level of the third node.
16. The shift register circuit according to claim 15, wherein the second control circuit includes an eleventh transistor,

    The gate of the eleventh transistor is connected to the third node, the first electrode of the eleventh transistor is connected to the second node, and the second electrode of the eleventh transistor is connected to the second voltage terminal Connect to receive the second voltage.
17. 4. The shift register circuit according to any one of claims 1 to 4, wherein the shift register unit further comprises a first reset circuit and a second reset circuit;

    The first reset circuit is connected to the second node and the first reset terminal, and is configured to reset the second node in response to the first reset control signal of the first reset terminal;

    The second reset circuit is connected to the second node and the second reset terminal, and is configured to reset the second node in response to a second reset control signal of the second reset terminal;

    The first reset circuit includes a twelfth transistor, the gate of the twelfth transistor is connected to the first reset terminal to receive the first reset control signal, and the first electrode of the twelfth transistor is connected to To the second node, the second electrode of the twelfth transistor is connected to a second control signal terminal to receive a second control signal;

    The second reset circuit includes a thirteenth transistor, the gate of the thirteenth transistor is connected to the second reset terminal to receive the second reset control signal, and the first pole of the thirteenth transistor is connected to the second reset terminal. The second node is connected, and the second electrode of the thirteenth transistor is connected to the second voltage terminal to receive the second voltage;

    Wherein, the first reset terminal is the current reset terminal of the shift register unit, the second reset terminal is the global reset terminal of the shift register unit, and the second reset control signal serves as the global reset terminal. Reset signal.
18. A gate drive circuit, comprising a plurality of cascaded shift register circuits according to any one of claims 1-17, wherein:

    The scan input signal input terminal of the n-th stage shift register circuit is connected to the output terminal of the n-1th stage shift register circuit;

    The first reset terminal of the n-th stage shift register circuit is connected to the output terminal of the n+1th stage shift register circuit;

    n is an integer greater than 1.
19. An electronic device, comprising the gate drive circuit and the array circuit according to claim 18, wherein the array circuit includes a multi-stripe scan line, and the multi-stripe scan line is more than the gate drive circuit. The multiple output terminals of each shift register circuit are connected correspondingly.
20. The electronic device according to claim 19, wherein the array circuit is a pattern collection array circuit.
21. The electronic device according to claim 20, further comprising a touch circuit, wherein the touch circuit is configured to perform touch detection on a touch area,

    The pattern collection array circuit is located in the touch area detected by the touch circuit.
22. A method for driving a gate driving circuit according to claim 18, comprising:

    In the first stage, the node setting circuit in the first shift register circuit transmits the node setting signal to the first node, thereby controlling the level of the first node;

    In the second stage, the node activation circuit in the first shift register circuit transmits the node activation control signal to the node activation control signal in the first shift register circuit under the control of the level of the first node. The input terminal of the shift register unit is used as the input control signal;

    In the third stage, the shift register unit in the first shift register circuit outputs the scan signal at the output terminal in response to the input control signal received by the input terminal;

    Wherein, the first shift register circuit is any one stage shift register circuit in the gate drive circuit.
23. A method for driving a gate driving circuit according to claim 18, comprising:

    The node-assisted setting circuit transmits the scan input signal to the input terminal of the shift register unit as the input control signal, and the shift register unit responds to the input terminal received Input a control signal, and output the scan signal at the output terminal.
24. A method for driving an electronic device according to any one of claims 19-21, comprising:

    According to the timings of the node setting signal, the node activation control signal, and the node auxiliary setting signal, the scan signal is output to the array circuit through the gate drive circuit.
25. The driving method of an electronic device according to claim 24, wherein, in the case that the electronic device further includes a touch circuit, the driving method further comprises:

    The timings of the node setting signal, the node activation control signal, and the node auxiliary setting signal are determined according to the detection result of the touch control circuit.
26. A method of using the electronic device as claimed in any one of claims 19-21 to collect patterns, comprising:

    Determine the target collection area based on the detection result of the touch circuit;

    Driving the shift register circuits in the gate driving circuit corresponding to the target acquisition area to sequentially output the scanning signals to clear the charges in the array circuits in the target acquisition area;

    The array circuit in the target collection area accumulates charges;

    Driving the shift register circuits in the gate driving circuit corresponding to the target acquisition area to sequentially output the scan signals to read the charges accumulated in the array circuits in the target acquisition area;

    Wherein, in the process of emptying the charge and reading the accumulated charge, the shift register circuit in the gate drive circuit that does not correspond to the target collection area does not output.

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