WO2021146912A1 - 通信接口与封装结构 - Google Patents

通信接口与封装结构 Download PDF

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Publication number
WO2021146912A1
WO2021146912A1 PCT/CN2020/073495 CN2020073495W WO2021146912A1 WO 2021146912 A1 WO2021146912 A1 WO 2021146912A1 CN 2020073495 W CN2020073495 W CN 2020073495W WO 2021146912 A1 WO2021146912 A1 WO 2021146912A1
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Prior art keywords
interface
unit
semiconductor unit
transmission channels
communication interface
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PCT/CN2020/073495
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English (en)
French (fr)
Inventor
周红星
邓秋荣
方骏
白颂荣
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2020/073495 priority Critical patent/WO2021146912A1/zh
Priority to CN202080001610.7A priority patent/CN112041830A/zh
Publication of WO2021146912A1 publication Critical patent/WO2021146912A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a communication interface and packaging structure.
  • the chip pin processing module (IO PAD) on the two chips is connected by wire bonding to realize the interconnection and communication between the two chips.
  • IO PAD chip pin processing module
  • corresponding IO PADs can be set for various signals to realize interconnection and communication between two chips.
  • the purpose of some of the embodiments of this application is to provide a communication interface and packaging structure to balance the multiplexing rate of the transmission channel while multiplexing the transmission channel, thereby reducing the requirement of the communication interface on the operating frequency, and thereby reducing ⁇ Power consumption.
  • An embodiment of the present application provides a communication interface, including: a first interface connected to a first semiconductor unit, and a second interface connected to the second semiconductor unit, the first interface and the second interface are matched and connected, and Multiple transmission channels are formed between the first semiconductor unit and the second semiconductor unit; in one clock cycle of the communication interface, M transmission channels of the multiple transmission channels are multiplexed between the first semiconductor unit and the second semiconductor unit Multiple types of interconnection signals are transmitted between, and M is an integer greater than 8.
  • An embodiment of the present application provides a package structure, including: the above-mentioned communication interface, a first semiconductor unit, and a second semiconductor unit.
  • the embodiments of the present application provide a communication interface.
  • the communication interface includes a first interface connected to a first semiconductor unit and a second interface connected to a second semiconductor unit.
  • the second interface is matched and connected, and multiple transmission channels are formed between the first semiconductor unit and the second semiconductor unit.
  • M transmission channels of the multiple transmission channels are multiplexed in Multiple types of interconnection signals are transmitted between the first semiconductor unit and the second semiconductor unit, and the number of multiplexed transmission channels M is set to be greater than 8, so as to balance the multiplexing rate of the transmission channels while multiplexing the transmission channels.
  • the first interface and the second interface have the same structure; each interface includes a logic control unit, a register unit, and a drive unit connected to each other; the drive unit of the first interface is connected to the drive unit of the second interface to form multiple transmission channels
  • the logic control unit is used to obtain the interconnection signal to be transmitted from the register unit, and output the interconnection signal to be transmitted through the drive unit; the logic control unit is also used to store the interconnection signal received through the drive unit in the register unit.
  • the register unit includes: input status register, input address register, input data register, output data register; the logic control unit is used to judge whether the interface belongs to the output state according to the flag bit in the input status register; the logic control unit is used to When it is determined that the interface to which it belongs is in the output state, the interconnection signal to be transmitted is obtained from the output data register, and the interconnection signal to be transmitted is output through the drive unit; the logic control unit is used to control the drive when it is determined that the interface to which it belongs is in the input state The unit is in the receiving state and receives the interconnection signal through the drive unit; the logic control unit is used to store the received interconnection signal in the input data register according to the address information in the input address register.
  • This embodiment provides a specific structure of the register unit.
  • each drive unit forms multiple pins on the interface to which it belongs; multiple pins of the first interface correspond to and connected to multiple pins of the second interface, forming multiple transmission channels; multiple pins It includes M data pins; the multiplexed transmission channel is the transmission channel formed between the data pin of the first interface and the data pin of the second interface.
  • This embodiment provides a specific implementation of the multiplexed transmission channel.
  • the first interface and the second interface use the same operating frequency, and the operating frequency is the internal clock frequency of the first semiconductor unit or the internal clock frequency of the second semiconductor unit.
  • the operating frequency is the internal clock frequency of the first semiconductor unit or the internal clock frequency of the second semiconductor unit.
  • M is greater than or equal to the bit width of any type of interconnection signal among multiple types of interconnection signals.
  • M is equal to the largest bit width among the bit widths of multiple types of interconnected signals.
  • the multiple transmission channels include transmission channels for transmitting power signals, and the transmission channels for transmitting power signals do not overlap with M transmission channels.
  • interconnection signals include: operation instructions, address signals, and data signals.
  • multiple types of interconnection signals also include: communication handshake signals.
  • the first semiconductor unit includes a first chip
  • the second semiconductor unit includes a second chip
  • the first chip and the second chip are respectively a master chip and a memory chip.
  • the parasitic capacitance between any two transmission channels is less than a preset capacitance threshold.
  • the power consumption is effectively reduced and the signal transmission speed is increased, and low-power high-speed transmission between the first semiconductor unit and the second semiconductor unit is realized.
  • the first interface and the second interface have the same structure; each interface includes a logic control unit, a register unit, and a drive unit connected to each other, and each drive unit forms multiple pins on the interface to which it belongs; Each pin corresponds to the multiple pins of the second interface and is connected to form multiple transmission channels; the multiple pins of the first interface and the multiple pins of the second interface are connected by flip-chip packaging to form multiple A transmission channel.
  • This embodiment provides a specific packaging method for making the parasitic capacitance between any two transmission channels smaller than the preset capacitance threshold.
  • the first semiconductor unit and the second semiconductor unit are both located on the third semiconductor unit, and the communication interface is located on the third semiconductor unit; the first interface and the second interface in the communication interface are connected by wires on the third semiconductor unit.
  • the first interface and the second interface are connected to each other through multiple wires on the third semiconductor unit, so that the first semiconductor unit and the second semiconductor unit are interconnected and communicated through multiple transmission channels formed by multiple wires.
  • the area of the internal wiring of the third semiconductor unit is reduced, and then the interference between the wiring is also reduced.
  • the third semiconductor unit is a chip
  • the first semiconductor unit and the second semiconductor unit are two different modules on the third semiconductor unit.
  • Fig. 1 is a schematic diagram of a communication interface according to the first embodiment of the present application.
  • each interface includes a logic control unit, a register unit, and a drive unit connected to each other;
  • Fig. 3 is a schematic diagram of a communication interface according to the second embodiment of the present application, in which the register unit includes an input status register, an input address register, an input data register, and an output data register;
  • Fig. 4 is a schematic diagram of a communication interface according to the second embodiment of the present application, in which multiple pins include: VDD pin, VCC pin, VSS pin, M data pins, CLK pin, TX pin, and RX pin;
  • FIG. 5 is a schematic diagram of a communication interface according to the second embodiment of the present application, where multiple pins include: VDD pin, VCC pin, VSS pin, M data pins, and CLK pin;
  • FIG. 6 is a timing diagram of data read and data written between the first semiconductor unit and the second semiconductor unit according to the second embodiment of the present application;
  • Fig. 7 is a schematic diagram of a package structure according to a fourth embodiment of the present application.
  • the first embodiment of the present application relates to a communication interface, which is used to connect a first semiconductor unit and a second semiconductor unit.
  • the communication interface includes: a first interface 11 connected to the first semiconductor unit 2, and a second interface 12 connected to the second semiconductor unit 3, the first interface 11 and the second interface 12 Match and connect, and form multiple transmission channels 4 between the first semiconductor unit 2 and the second semiconductor unit 3, that is, multiple connection lines between the first interface 11 and the second interface 12 form multiple transmission channels 4.
  • M transmission channels 4 of the multiple transmission channels 4 are multiplexed between the first semiconductor unit and the second semiconductor unit to transmit multiple types of interconnection signals, M It is an integer greater than 8; among them, the types of the multiplexed transmission channels are the same.
  • the first interface 11 and the second interface 12 use the same operating frequency, and the operating frequency is the internal clock frequency of the first semiconductor unit 2 or the internal clock frequency of the second semiconductor unit 3, that is, in the first semiconductor unit 2
  • the working frequency is the internal clock frequency of the first semiconductor unit 2
  • the working frequency is the internal clock frequency of the second semiconductor unit 3
  • the working frequency is the internal clock frequency of the second semiconductor unit 3, which can take into account the communication interface.
  • Transmission speed and power consumption realize low power consumption while realizing higher transmission speed.
  • the communication interface includes a first interface connected to a first semiconductor unit and a second interface connected to a second semiconductor unit.
  • the two interfaces are matched and connected, and multiple transmission channels are formed between the first semiconductor unit and the second semiconductor unit.
  • M transmission channels of the multiple transmission channels are multiplexed in the first
  • Multiple types of interconnected signals are transmitted between a semiconductor unit and a second semiconductor unit, and the number of multiplexed transmission channels M is set to be greater than 8, so as to balance the multiplexing rate of the transmission channels while multiplexing the transmission channels, thereby The requirements of the communication interface on the operating frequency are reduced, thereby reducing the power consumption.
  • the second embodiment of the present application relates to a communication interface. Compared with the first embodiment, the main difference of this embodiment is that a specific structure of the first interface 11 and the second interface 12 is provided.
  • each interface includes a logic control unit 111, a register unit 112, and a driving unit 113 connected to each other, and the driving unit of the first interface 11 113 is connected to the driving unit 113 of the second interface 12 to form a plurality of transmission channels 4.
  • the first interface 11 is an interface formed inside the first semiconductor unit 2
  • the second interface 12 is an interface formed inside the second semiconductor unit 3.
  • the logic control unit 111 is configured to obtain the interconnection signal to be transmitted from the register unit 112 and output the interconnection signal to be transmitted through the driving unit 113.
  • the logic control unit 111 is also used to store the interconnection signal received by the driving unit 113 in the register unit 112.
  • the register unit 112 includes: an input status register 1121, an input address register 1122, an input data register 1123, and an output data register 1124.
  • the input status register 1121, the input address register 1122, the input data register 1123, and the output data register 1124 can be at least partially multiplexed to reduce the area occupied by the register unit 112.
  • the logic control unit 111 is used for judging whether the belonging interface is in the output state according to the flag bit in the input state register 1121.
  • the logic control unit 111 is used to obtain the interconnection signal to be transmitted from the output data register 1124 when determining that the interface to which it belongs is in the output state, and output the interconnection signal to be transmitted through the driving unit 113.
  • the logic control unit 111 is used to control the driving unit 113 to be in the receiving state when it is determined that the interface to which it belongs is in the input state, and to receive the interconnection signal through the driving unit.
  • the logic control unit 11 is configured to store the received interconnection signal in the input data register 1123 according to the address information in the input address register 1122.
  • each driving unit 113 forms multiple pins on the interface to which it belongs, that is, each drive unit 113 forms multiple pins on the interface to which it belongs; the multiple pins of the first interface 11 and The multiple pins of the second interface 12 are in one-to-one correspondence and connected to form multiple transmission channels 4.
  • the driving unit 113 may include multiple buffers, each buffer corresponding to a transmission channel 4, each buffer buffer is used to complete the corresponding transmission channel 4 driving, and its working state includes outputting high level, Output low level and high impedance.
  • the type of each pin is defined in the first interface 11 and the second interface 12, and the type of the two connected pins determines the type of the transmission channel formed.
  • the multiple pins of each interface include VDD pin, VCC pin, VSS pin, M data pins, CLK pin, TX pin, and RX pin.
  • the transmission channel 4 formed by connecting the VDD pin of the first interface 11 and the VDD pin of the second interface is a VDD channel for transmitting VDD signals; the VCC pin of the first interface 11 is in phase with the VCC pin of the second interface
  • the transmission channel 4 formed by the connection is a VCC channel for transmitting VCC signals;
  • the transmission channel 4 formed by connecting the VSS pin of the first interface 11 and the VSS pin of the second interface is a VSS channel to achieve grounding;
  • the transmission channel 4 formed by connecting the data pin of 11 and the data pin of the second interface is a data channel for transmitting various types of interconnected signals; the CLK pin of the first interface 11 and the CLK pin of the second interface
  • the transmission channel 4 formed by the connection is the CLK channel, which is used to transmit clock signals; the transmission channel 4 formed by connecting the TX pin
  • VCC is the power supply voltage
  • VDD is the operating voltage (usually VCC>VDD)
  • VSS is the ground point
  • the VDD signal, VCC signal and VSS signal can be collectively referred to as the power signal
  • the VDD channel, VCC channel and VSS channel can be collectively referred to as The transmission channel used to transmit the power signal, it can be seen that there is no overlap between the transmission channel used to transmit the power signal and the data channel used to transmit multiple types of interconnected signals, that is, the data channel does not support the transmission of the power signal.
  • VCC supplies power to the logic control unit 101 and the register unit in the first interface 11, and at the same time supplies power to the logic control unit 101 and the register unit in the second interface 12 through the VCC interface, and VDD supplies power to the drive unit 113 in the first interface 11. At the same time, power is supplied to the driving unit 113 in the second module 12 through the VDD pin.
  • M data pins in the two interfaces are connected to form M data channels (data channel 1 to data channel M), and these M data channels are Multiplexed between the first semiconductor unit 2 and the second semiconductor unit 3 for time-sharing transmission of multiple types of interconnection signals, the multiple types of interconnection signals include operation commands, address signals, and data signals.
  • each interface includes a VDD pin, a VCC pin, a VSS pin, M data pins, and a CLK pin.
  • the connection mode of the pins in Fig. 3 and the signal type transmitted by the channel are the same as those in Fig. 2, which will not be repeated here.
  • the main difference is that in this embodiment, two interfaces (the first interface 11 and In the second interface 12), the RX pin dedicated to transmitting the input control signal (RX signal) and the TX pin used to transmit the output control signal (TX signal). At this time, two interfaces (the first interface 11 and the first interface 11) are used.
  • communication handshake signals can be added to the multiple types of interconnection signals.
  • the communication handshake signals include TX signals and RX signal, thereby further reducing the total number of pins in the communication interface, which can further reduce power consumption.
  • the first semiconductor unit 2 and the second semiconductor unit 3 can complete at least one read and write operation.
  • the reading of data in the unit 3 is described as an example.
  • FIG. 6 is a timing diagram of the first semiconductor unit 2 and the second semiconductor unit 3 for reading and writing data.
  • the TX signal is high and the RX signal is low
  • the first interface 11 of the first semiconductor unit 2 is in the sending state
  • the first semiconductor unit 2 sends to the second semiconductor unit 3 through M data channels
  • Read instructions and read addresses that is, the logic control unit 111 controls the buffers of each data pin to output high-level or low-level signals through the corresponding data channel according to the binary code of the read instruction and the read address; this
  • the second interface 12 of the second semiconductor unit 3 is in the receiving state, and the buffers of the logic data pins are in the high-impedance state, so that the read command and the read address can be received.
  • the TX signal is at low level and the RX signal is at high level.
  • the first interface The logic control unit 111 in 11 switches the buffer of each data pin to a high-impedance state to receive the data signal sent by the second semiconductor unit 3 through M data channels.
  • the second interface 12 of the first semiconductor unit 2 is in the sending state, and the logic control unit 111 of the second interface 12 controls the buffer of each data pin to output high voltage through the corresponding data channel according to the binary code of the data signal.
  • a level or low level signal to send data signals to the first semiconductor unit 2 through M data channels.
  • M is greater than or equal to the bit width of any type of interconnection signal.
  • M can be set to be equal to the largest bit width among the bit widths of multiple types of interconnection signals; specifically, multiple types
  • the interconnection signals include operation instructions, address signals, and data signals.
  • the bit width of the data signal is the largest, and the number of data channels can be set to be equal to the bit width of the data signal. For example, for a 32-bit data signal If each interface includes 32 data pins, 32 data channels can be formed between the first semiconductor unit 2 and the second semiconductor unit 3, which are multiplexed to transmit multiple types of interconnected signals.
  • first The semiconductor unit 2 and the second semiconductor unit 3 should also include pins for transmitting TX signals, RX signals, VDD signals, CLK signals, VCC signals, and VSS signals. At this time, the first semiconductor unit 2 and the second semiconductor unit 3 There are 38 transmission channels formed between.
  • this embodiment provides a specific structure of the first interface and the second interface.
  • the third embodiment of the present application relates to a package structure. Please refer to FIGS. 1 to 5.
  • the package structure includes the communication interface, the first semiconductor unit 2 and the second semiconductor unit 3 in the first embodiment or the second embodiment. .
  • the first semiconductor unit 2 includes a first chip
  • the second semiconductor unit 3 includes a second chip
  • the first interface 11 is located on the first semiconductor unit 2
  • the second interface 12 is located on the second semiconductor unit 3, namely
  • the first interface 11 and the second interface 12 are respectively located on two different chips to realize the communication and interconnection between the two chips, and multiplex the M transmission channels among the multiple transmission channels between the two chips to transmit multiple types of transmission channels. Interconnect signals.
  • the first semiconductor unit 2 may be a first chip
  • the second semiconductor unit 3 may be a second chip.
  • the first chip may be a micro-processing main control chip or a memory chip
  • the second chip may be a micro-processing main control chip or a memory chip.
  • the communication interface can be called MCU External memory physical interface (MCU External Memory Physical interface, referred to as MEMPHY interface).
  • the MEMPHY interface includes MEMPHYMaster (first interface) connected to the micro-processing main control chip and MEMPHYSlave (second interface) connected to the memory chip.
  • MEMPHYMaster first interface
  • MEMPHYSlave second interface
  • One of MEMPHYMaster and MEMPHYSlave There are multiple transmission channels formed between, that is, multiple connection lines between MEMPHYMaster and MEMPHYSlave form multiple transmission channels.
  • the second semiconductor unit 3 can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (FLASH ROM), static memory (SRAM) or dynamic memory (DRAM), etc.
  • ROM read-only memory
  • PROM programmable read-only memory
  • EPROM erasable programmable read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • FLASH ROM flash memory
  • SRAM static memory
  • DRAM dynamic memory
  • the first semiconductor unit 2 is the micro-processing main control chip and the second semiconductor unit 3 is the memory chip
  • data can be written to the micro-processing main control chip through the memory chip.
  • the process of adjusting the parameters of the micro-processing main control chip is called Trimming.
  • Trimming process through the configuration of the Trimming information in the storage chip and the timing configuration of the interconnection signal between the micro-processing main control chip and the storage chip, the interconnection of storage chips of different processes and the same micro-processing main control chip can be realized, or The same memory chip is interconnected with the micro-processing main control chip of different processes.
  • multiple types of interconnection signals include: operation instructions, address signals, and data signals. That is, for the M transmission channels multiplexed in the MEMPHY interface, these M transmission channels can be Used for time-sharing transmission of operating instructions, address signals, and data signals.
  • the power signal, operation instruction, address signal, data signal, clock signal, input control signal, and output control signal of the memory chip are all derived from the micro-processing main control chip (the first semiconductor unit). 2)
  • the micro-processing main control chip can realize the reading and writing, sleep and other test operations of the memory chip through the MEMPHY interface.
  • the clock signal can be selected from the clock frequency of the main clock in the micro-processing main control chip, and there is no need to set an additional clock source, which reduces the cost.
  • the multiplexing of the MEMPHY interface can be realized by selecting the same type of memory chip, that is, the micro-processing main control chip can be connected to multiple memory chips through one MEMPHY interface.
  • the parasitic capacitance between any two of the multiple transmission channels in the MEMPHY interface is less than a preset capacitance threshold. That is, the parasitic capacitance generated by any two of the multiple connections between the MEMPHYMaster and the MEMPHYSlave in the MEMPHY interface is less than the preset capacitance threshold.
  • the parasitic capacitance includes the capacitance of the connection to the ground and the adjacent wiring.
  • MEMPHYMaster and MEMPHYSlave have the same structure; each interface (MEMPHYMaster or MEMPHYSlave) includes a logic control unit, a register unit, and a drive unit connected to each other, and each drive unit forms multiple pins on its own interface; The multiple pins of one interface correspond to and connect to the multiple pins of the second interface one by one to form multiple transmission channels.
  • the first semiconductor unit 2 and the second semiconductor unit 3 can be flip-chip (FC) packaged by flip-chip technology to connect multiple pins of the MEMPHYMaster in the MEMPHY interface with multiple MEMPHYSlave
  • FC flip-chip
  • the pin effectively shortens the circuit connection path between MEMPHYMaster and MEMPHYSlave, so that the parasitic capacitance between any two transmission channels of MEMPHYMaster and MEMPHYSlave is smaller than the preset capacitance threshold.
  • the FC package except for the power supply signal (including VDD, VCC, VSS), the other signals may not be directly led to the package pins, thereby reducing the total number of package pins.
  • this embodiment provides a packaging structure applying the communication interface in the first or second embodiment; the number of transmission channels in the communication interface is reduced, thereby reducing the wiring of the packaging structure The area is conducive to reducing the size of the package structure and reducing the cost; and, low-power high-speed transmission between the first semiconductor unit and the second semiconductor unit is realized.
  • the fourth embodiment of the present application relates to a packaging structure. Compared with the first embodiment, the main difference between this embodiment and the first embodiment is that it provides a specific implementation method for interconnecting and communicating between modules of the same semiconductor unit. .
  • the first semiconductor unit 2 and the second semiconductor unit 3 are both located on the third semiconductor unit 4, and the communication interface is located on the third semiconductor unit 4; the first interface 11
  • the second interface 12 is connected to each other through a plurality of metal wires on the third semiconductor unit 4, and the plurality of metal wires form a plurality of transmission channels between the first interface 11 and the second interface 12.
  • the third semiconductor unit 4 includes a chip or a wafer (including multiple chips on the wafer). Taking the third semiconductor unit 4 as one chip as an example, the first semiconductor unit 2 and the second semiconductor unit 2
  • the semiconductor unit 3 is two modules in the chip.
  • the first semiconductor unit 2 is an analog signal module
  • the second semiconductor unit 3 is a digital signal module
  • the analog signal module is connected to the first interface 11 through a wiring in the chip.
  • the signal module is connected to the second interface 12 through the wiring in the chip, and the first interface 11 and the second interface 12 are connected to each other through multiple wiring in the chip, so that the two modules are transmitted by multiple wirings.
  • the channel realizes interconnection communication, reduces the area of the internal wiring of the chip, and then also reduces the interference between the wiring.
  • this embodiment provides a specific implementation method for realizing interconnection and communication between the modules of the same semiconductor unit; the wiring area in the third semiconductor unit is reduced, thereby reducing the first 3. Package volume of semiconductor unit.

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Abstract

本申请实施例提供了一种通信接口与封装结构，包括：连接于第一半导体单元（2）的第一接口（11），以及连接于第二半导体单元（3）的第二接口（12），所述第一接口（11）与所述第二接口（12）相匹配且连接，并在所述第一半导体单元（2）与所述第二半导体单元（3）之间形成多条传输通道（4）；在所述通信接口的一个时钟周期内，多条所述传输通道（4）中的M条所述传输通道（4）被复用在所述第一半导体单元（2）与所述第二半导体单元（3）之间传输多种类型的互联信号，M为大于8的整数。采用上述方案，在复用传输通道的同时，平衡了传输通道的复用率，从而减小了通信接口对工作频率的要求，进而减小了功耗。

Description

通信接口与封装结构 技术领域
本申请涉及半导体技术领域，特别涉及一种通信接口与封装结构。
背景技术
目前，在两颗芯片需要互联通信时，将两颗芯片上的芯片管脚处理模块(IO PAD)通过金属线打线连接，以实现两颗芯片之间的互联通信。对于多IO PAD的芯片互联，则可以针对各种信号设置对应的IO PAD来实现两颗芯片之间的互联通信。
发明内容
本申请部分实施例的目的在于提供一种通信接口与封装结构，以在复用传输通道的同时，平衡了传输通道的复用率，从而减小了通信接口对工作频率的要求，进而减小了功耗。
本申请实施例提供了一种通信接口，包括：连接于第一半导体单元的第一接口，以及连接于第二半导体单元的第二接口，第一接口与第二接口相匹配且连接，并在第一半导体单元与第二半导体单元之间形成多条传输通道；在通信接口的一个时钟周期内，多条传输通道中的M条传输通道被复用在第一半导体单元与第二半导体单元之间传输多种类型的互联信号，M为大于8的整数。
本申请实施例提供了一种封装结构，包括：上述的通信接口、第一半导体单元以及第二半导体单元。
本申请实施例现对于现有技术而言，提供了一种通信接口，该通信接口包括连接于第一半导体单元的第一接口，以及连接于第二半导体单元的第二接口，第一接口与第二接口相匹配且连接，并在第一半导体单元与第二半导体单元之间形成多条传输通道，在通信接口的一个时钟周期内，多条传输通道中的M条传输通道被复用在第一半导体单元与第二半导体单元之间传输多种类型的互联信号，设置被复用的传输通道的数量M大于8，以在复用传输通道的同时，平衡了传输通道的复用率，从而减小了通信接口对工作频率的要求，进而减小了功耗。
例如，第一接口与第二接口的结构相同；每个接口包括相互连接的逻辑控制单元、寄存器单元与驱动单元；第一接口的驱动单元连接于第二接口的驱动单元，形成多条传输通道；逻辑控制单元用于从寄存器单元中获取待传输的互联信号，并通过驱动单元输出待传输的互联信号；逻辑控制单元还用于将通过驱动单元接收到的互联信号存储到寄存器单元中。本实施例提供了第一接口与第二接口的一种具体结构。
例如，寄存器单元包括：输入状态寄存器、输入地址寄存器、输入数据寄存器、输出数据寄存器；逻辑控制单元用于根据输入状态寄存器中的标志位，判断所属的接口是否处于输出状态；逻辑控制单元用于在判定所属的接口处于输出状态时，从输出数据寄存器中获取待传输的互联信号，并通过驱动单元输出待传输的互联信号；逻辑控制单元用于在判定所属的接口处于输入状态时，控制驱动单元处于接收状态，并通过驱动单元接收互联信号；逻辑控制单元用 于根据输入地址寄存器中的地址信息，将接收到的互联信号存储到输入数据寄存器中。本实施例提供了寄存器单元的一种具体结构。
例如，每个驱动单元在所属的接口上形成多个引脚；第一接口的多个引脚与第二接口的多个引脚一一对应且连接，形成多条传输通道；多个引脚中包括M个数据引脚；被复用的传输通道为形成在第一接口的数据引脚与第二接口的数据引脚之间的传输通道。本实施例提供了被复用的传输通道的一种具体实现方式。
例如，第一接口与第二接口采用相同的工作频率，工作频率为第一半导体单元的内部时钟频率或第二半导体单元的内部时钟频率。本实施例中兼顾传输速度与功耗，在实现较高传输速度的同时，实现了低功耗。
例如，M大于或等于多种类型的互联信号中任一类型的互联信号的位宽。
例如，M等于多种类型的互联信号的位宽中最大的位宽。
例如，多条传输通道包括用于传输电源信号的传输通道，且用于传输电源信号的传输通道与M条传输通道不重叠。
例如，多种类型的互联信号包括：操作指令、地址信号以及数据信号。
例如，多种类型的互联信号还包括：通讯握手信号。
例如，第一半导体单元包括第一芯片，第二半导体单元包括第二芯片。
例如，第一芯片与第二芯片分别为主控芯片和存储芯片。
例如，任意两条传输通道之间的寄生电容小于预设的电容阈值。本实施例中，有效的降低功耗且提高信号传输速度，实现了第一半导体单元与第二半导体单元之间的低功耗的高速传输。
例如，第一接口与第二接口的结构相同；每个接口包括相互连接的逻辑 控制单元、寄存器单元与驱动单元，每个驱动单元在所属的接口上形成多个引脚；第一接口的多个引脚与第二接口的多个引脚一一对应且连接，形成多条传输通道；采用倒装封装方式连接第一接口的多个引脚与第二接口的多个引脚，形成多条传输通道。本实施例提供了使任意两条传输通道之间的寄生电容小于预设的电容阈值的一种具体封装方式。
例如，第一半导体单元与第二半导体单元均位于第三半导体单元上，通信接口位于第三半导体单元上；通信接口中的第一接口与第二接口通过第三半导体单元上的走线连接。本实施方式中，第一接口与第二接口通过第三半导体单元上的多条走线相互连接，使得第一半导体单元与第二半导体单元通过多条走线形成的多条传输通道实现互联通讯，减小了第三半导体单元内部走线的面积，继而也减小了走线之间的干扰。
例如，第三半导体单元为芯片，第一半导体单元与第二半导体单元为第三半导体单元上两个不同的模块。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例中的通信接口的示意图；
图2是根据本申请第二实施例中的通信接口的示意图，其中每个接口包括相互连接的逻辑控制单元、寄存器单元以及驱动单元；
图3是根据本申请第二实施例中的通信接口的示意图，其中寄存器单元 包括输入状态寄存器、输入地址寄存器、输入数据寄存器以及输出数据寄存器；
图4是根据本申请第二实施例中的通信接口的示意图，其中多个引脚包括：VDD引脚、VCC引脚、VSS引脚、M个数据引脚、CLK引脚、TX引脚以及RX引脚；
图5是根据本申请第二实施例中的通信接口的示意图，其中多个引脚包括：VDD引脚、VCC引脚、VSS引脚、M个数据引脚以及CLK引脚；
图6是根据本申请第二实施例中的第一半导体单元与第二半导体单元之间读取数据与写入数据的时序图；
图7是根据本申请第四实施例中的封装结构的示意图。
具体实施例
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
发明人发现现有技术至少存在以下问题：对于多IO PAD的芯片互联，由于IO PAD对地和IO PAD之间产生的寄生电容较高，导致功耗过高。
本申请第一实施例涉及一种通信接口，其用于连接第一半导体单元与第二半导体单元。本实施例中，请参考图1，通信接口包括：连接于第一半导体单元2的第一接口11，以及连接于第二半导体单元3的第二接口12，第一接口11与第二接口12相匹配且连接，并在第一半导体单元2与第二半导体单元3之间形成多条传输通道4，即第一接口11与第二接口12之间的多条连接线形成了多条传输通道4。
本实施例中，在通信接口的一个时钟周期内，多条传输通道4中的M条传输通道4被复用在第一半导体单元与第二半导体单元之间传输多种类型的互联信号，M为大于8的整数；其中，被复用的传输通道的类型相同。
在一个例子中，第一接口11与第二接口12采用相同的工作频率，该工作频率为第一半导体单元2的内部时钟频率或第二半导体单元3的内部时钟频率，即在第一半导体单元2为主设备时，工作频率为第一半导体单元2的内部时钟频率；在第二半导体单元3为主设备时，工作频率为第二半导体单元3的内部时钟频率，此时可以兼顾通信接口的传输速度与功耗，在实现较高传输速度的同时，实现了低功耗。
本实施例相对于现有技术而言，提供了一种通信接口，该通信接口包括连接于第一半导体单元的第一接口，以及连接于第二半导体单元的第二接口，第一接口与第二接口相匹配且连接，并在第一半导体单元与第二半导体单元之间形成多条传输通道，在通信接口的一个时钟周期内，多条传输通道中的M条传输通道被复用在第一半导体单元与第二半导体单元之间传输多种类型的互联信号，设置被复用的传输通道的数量M大于8，以在复用传输通道的同时，平衡了传输通道的复用率，从而减小了通信接口对工作频率的要求，进而减小了功耗。
本申请第二实施例涉及一种通信接口，本实施例相对于第一实施例而言，主要区别之处在于：提供了第一接口11与第二接口12的一种具体结构。
本实施例中，请参考图2，第一接口11与第二接口12的结构相同；每个接口包括相互连接的逻辑控制单元111、寄存器单元112与驱动单元113，第一接口11的驱动单元113连接于第二接口12的驱动单元113，形成多条传输 通道4。其中，第一接口11为形成在第一半导体单元2内部的接口、第二接口12为形成在第二半导体单元3内部的接口。
逻辑控制单元111用于从寄存器单元112中获取待传输的互联信号，并通过驱动单元113输出待传输的互联信号。
逻辑控制单元111还用于将通过驱动单元113接收到的互联信号存储到寄存器单元112中。
在一个例子中，请参考图3，寄存器单元112包括：输入状态寄存器1121、输入地址寄存器1122、输入数据寄存器1123、输出数据寄存器1124。其中，输入状态寄存器1121、输入地址寄存器1122、输入数据寄存器1123、输出数据寄存器1124可以至少部分复用，以减小寄存器单元112的面积占用。
逻辑控制单元111用于根据输入状态寄存器1121中的标志位，判断所属的接口是否处于输出状态。
逻辑控制单元111用于在判定所属的接口处于输出状态时，从输出数据寄存器1124中获取待传输的互联信号，并通过驱动单元113输出待传输的互联信号。
逻辑控制单元111用于在判定所属的接口处于输入状态时，控制驱动单元113处于接收状态，并通过驱动单元接收到互联信号。
逻辑控制单元11用于根据输入地址寄存器1122中的地址信息，将接收到的互联信号存储到输入数据寄存器1123中。
本实施例中，每个驱动单元113在所属的接口上形成多个引脚，即每个驱动单元113在其所属的接口上形成了多个引脚；第一接口11的多个引脚与第二接口12的多个引脚一一对应且连接，形成多条传输通道4。其中，驱动单元 113可以包括多个缓冲器buffer，每个缓冲器buffer对应于一条传输通道4，每个缓冲器buffer用于完成对应的传输通道4的驱动，其工作状态包括输出高电平、输出低电平以及高阻。
本实施例中，第一接口11与第二接口12中定义各引脚的类型，相连接的两个引脚的类型决定了所形成的传输通道的类型。
在一个例子中，请参考图4，每个接口的多个引脚中包括VDD引脚、VCC引脚、VSS引脚，M个数据引脚、CLK引脚、TX引脚以及RX引脚。第一接口11的VDD引脚与第二接口的VDD引脚相连接形成的传输通道4为VDD通道，用于传输VDD信号；第一接口11的VCC引脚与第二接口的VCC引脚相连接形成的传输通道4为VCC通道，用于传输VCC信号；第一接口11的VSS引脚与第二接口的VSS引脚相连接形成的传输通道4为VSS通道，以实现接地；第一接口11的数据引脚与第二接口的数据引脚相连接形成的传输通道4为数据通道，用于传输多种类型的互联信号；第一接口11的CLK引脚与第二接口的CLK引脚相连接形成的传输通道4为CLK通道，用于传输时钟信号；第一接口11的TX引脚与第二接口的TX引脚相连接形成的传输通道4为TX通道，用于传输输出控制信号(TX信号)；第一接口11的RX引脚与第二接口的RX引脚相连接形成的传输通道4为RX通道，用于传输输入控制信号(RX信号)。
其中，VCC是供电电压，VDD是工作电压(通常VCC>VDD)，VSS是接地点，VDD信号、VCC信号以及VSS信号可以统称为电源信号，由此VDD通道、VCC通道以及VSS通道可以统称为用于传输电源信号的传输通道，可见用于传输电源信号的传输通道与用于传输多种类型的互联信号的数据通道不 存在重叠，即数据通道不支持电源信号的传输。VCC给第一接口11中的逻辑控制单元101以及寄存器单元供电，同时通过VCC接口给第二接口12中的逻辑控制单元101以及寄存器单元供电，VDD给第一接口11中的驱动单元113供电，同时通过VDD引脚给第二模块12中的驱动单元113供电。
在图4中，两个接口(第一接口11与第二接口12)中的M个数据引脚分别连接形成了M条数据通道(数据通道1至数据通道M)，这M条数据通道被复用在第一半导体单元2和第二半导体单元3之间分时传输多种类型的互联信号，多种类型的互联信号包括操作指令、地址信号以及数据信号。
在一个例子中，请参考图5，每个接口的多个引脚中包括VDD引脚、VCC引脚、VSS引脚，M个数据引脚以及CLK引脚。其中，图3中引脚的连接方式以及通道传输的信号类型与图2中类型，在此不再赘述，主要不同之处在于：本实施例中，取消了两个接口(第一接口11与第二接口12)中专用于传输输入控制信号(RX信号)的RX引脚以及用来传输输出控制信号(TX信号)的TX引脚，此时在利用两个接口(第一接口11与第二接口12)中的M个数据引脚分别连接形成的M条数据通道分时传输多种类型的互联信号时，可以在多种类型的互联信号加入通讯握手信号，通讯握手信号包括TX信号与RX信号，从而进一步减少了通信接口中引脚的总数量，可以进一步减小功耗。
本实施例中，一个时钟周期内，第一半导体单元2与第二半导体单元3可以完成至少一次读写操作，下面以图4中所示的通信接口，且第一半导体单元2从第二半导体单元3中读取数据为例进行说明，图6为第一半导体单元2与第二半导体单元3读取数据与写入数据的时序图。
第一阶段中，TX信号为高电平、RX信号为低电平，第一半导体单元2 的第一接口11处于发送状态，第一半导体单元2通过M条数据通道向第二半导体单元3发送读取指令、读取地址，即逻辑控制单元111根据读取指令与读取地址的二进制编码，控制各数据引脚的缓冲器buffer通过对应的数据通道输出高电平或者低电平信号；此时，第二半导体单元3的第二接口12处于接收状态，逻辑各数据引脚的缓冲器buffer处于高阻状态，从而能够接收读取指令与读取地址。
第二阶段中，TX信号为低电平、RX信号为高电平，第一半导体单元2的通过M条数据通道发送读取指令、读取地址完毕后，需要切换为接收状态，第一接口11中的逻辑控制单元111将各数据引脚的缓冲器buffer切换为高阻状态，以通过M条数据通道接收第二半导体单元3发出的数据信号。此时，第一半导体单元2的第二接口12处于发送状态，第二接口12的逻辑控制单元111根据数据信号的二进制编码，控制各数据引脚的缓冲器buffer通过对应的数据通道输出高电平或者低电平信号，以通过M条数据通道向第一半导体单元2发送数据信号。
本实施例中，M大于或等于任一类型的互联信号的位宽，在一个例子中，可以设置M等于多种类型的互联信号的位宽中最大的位宽；具体的，以多种类型的互联信号包括操作指令、地址信号以及数据信号为例，这三种信号中，数据信号的位宽最大，则可以设定数据通道的数量与数据信号的位宽相等，例如对于32bit的数据信号，设置每个接口中包括32个数据引脚，则可以在第一半导体单元2与第二半导体单元3之间形成被复用于传输多种类型的互联信号的32条数据通道，此外第一半导体单元2与第二半导体单元3之间还应包括传输TX信号、RX信号、VDD信号、CLK信号、VCC信号和VSS信号的接脚，此 时第一半导体单元2与第二半导体单元3之间形成有38条传输通道。
本实施例相对于第一实施例而言，提供了第一接口与第二接口的一种具体结构。
本申请第三实施例涉及一种封装结构，请参考考图1至图5，封装结构包括第一实施例中或第二实施例中的通信接口、第一半导体单元2以及第二半导体单元3。
本实施例中，第一半导体单元2包括第一芯片，第二半导体单元3包括第二芯片；第一接口11位于第一半导体单元2上，第二接口12位于第二半导体单元3上，即第一接口11与第二接口12分别位于两颗不同的芯片上，实现两颗芯片之间的通信互联，复用两颗芯片之间的多条传输通道中M条传输通道传输多种类型的互联信号。
在另一个例子中，第一半导体单元2可以为第一芯片，第二半导体单元3可以为第二芯片。
示例的，第一芯片可以为微处理主控芯片或存储芯片，第二芯片可以为微处理主控芯片或存储芯片。
本实施例中，以第一半导体单元2为微处理主控芯片，第二半导体单元3为存储芯片为例，即以微处理主控芯片外挂存储芯片进行说明，此时通信接口可以称为MCU外部存储物理接口(MCU External Memory Physical interface，简称MEMPHY接口)，MEMPHY接口包括连接于微处理主控芯片的MEMPHYMaster(第一接口)与连接于存储芯片的MEMPHYSlave(第二接口)，MEMPHYMaster与MEMPHYSlave之间形成有多条传输通道，即MEMPHYMaster与MEMPHYSlave之间的多条连接线形成了多条传输通道。其 中第二半导体单元3可以为只读存储器(ROM)、可编程只读存储器(PROM)、可擦写可编程只读存储器(EPROM)、电可擦除可编程只读存储器(EEPROM)、闪存(FLASH ROM)、静态存储器(SRAM)或者动态存储器(DRAM)等。
需要说明的是，若第一半导体单元2为微处理主控芯片，第二半导体单元3为存储芯片，在二者封装在一起后，可以通过存储芯片向微处理主控芯片写入数据，来调整微处理主控芯片的参数，这个过程称为Trimming。在Trimming过程中，可以通过对存储芯片中Trimming信息的配置以及微处理主控芯片与存储芯片之间互联信号的时序配置，实现不同工艺的存储芯片与相同的微处理主控芯片的互联，或相同的存储芯片与不同工艺的微处理主控芯片的互联。
本实施例以及之后的实施例中均以多种类型的互联信号包括：操作指令、地址信号、数据信号，即对于MEMPHY接口中被复用的M条传输通道来说，这M条传输通道可以用于分时传输操作指令、地址信号、数据信号。
本实施例中，存储芯片(第二半导体单元3)的电源信号、操作指令、地址信号、数据信号、时钟信号、输入控制信号、输出控制信号均来源于微处理主控芯片(第一半导体单元2)，微处理主控芯片可以通过MEMPHY接口实现对存储芯片的读写、睡眠和其他测试操作。其中，时钟信号的可以选择微处理主控芯片中主时钟的时钟频率，无需额外设定时钟源，减小了成本。
需要说明的是，本实施例可以通过选定相同类型的存储芯片，实现MEMPHY接口的复用，即微处理主控芯片可以通过一个MEMPHY接口连接于多个存储芯片。
在一个例子中，MEMPHY接口中的多条传输通道中任意两条传输通道之间的寄生电容小于预设的电容阈值。亦即，MEMPHY接口中的 MEMPHYMaster与MEMPHYSlave之间的多条连线中任意两条连线所产生的寄生电容小于预设的电容阈值，该寄生电容包括连线对地以及相邻走线的电容，从而有效的降低功耗且提高信号传输速度，实现了两块芯片之间的低功耗的高速传输，使得外挂的存储的芯片实现嵌入式闪存(Embedded Flash)的性能，因而利用该封装结构可以替代嵌入式闪存晶圆的加工工艺，从而有利于降低成本，且针对不同容量的存储需求，封装结构的芯片设计方案更为灵活和标准化。
本实施例中，MEMPHYMaster与MEMPHYSlave的结构相同；每个接口(MEMPHYMaster或MEMPHYSlave)包括相互连接的逻辑控制单元、寄存器单元与驱动单元，每个驱动单元在所属的接口上形成多个引脚；第一接口的多个引脚与第二接口的多个引脚一一对应且连接，形成多条传输通道。
在一个例子中，可以通过倒装技术将第一半导体单元2与第二半导体单元3倒装(Flip Chip，简称FC)封装，以连接MEMPHY接口中的MEMPHYMaster的多个引脚与MEMPHYSlave的多个引脚，有效缩短了MEMPHYMaster与MEMPHYSlave之间的电路连接路径，使得MEMPHYMaster与MEMPHYSlave的任意两条传输通道之间的寄生电容小于预设的电容阈值。其中，采用FC封装后，除了电源信号(包括VDD、VCC、VSS)以外，其余信号可均不直接引出到封装的引脚，从而减小了封装引脚的总数量。
本实施例相对于第一实施例而言，提供了应用第一实施例或第二实施例中的通信接口的封装结构；通信接口中减少了传输通道的数量，从而减少了封装结构的走线面积，有利于减小封装结构的尺寸，降低成本；并且，实现了第一半导体单元与第二半导体单元之间的低功耗的高速传输。
本申请第四实施例涉及一种封装结构，本实施例相对于第一实施例而言， 主要区别之处在于：提供了在同个半导体单元的模块之间实现互联通讯的一种具体实现方式。
请参考图6(以图1中的通信接口为例)，第一半导体单元2与第二半导体单元3均位于第三半导体单元4上，通信接口位于第三半导体单元4上；第一接口11与第二接口12通过第三半导体单元4上的多条金属线相互连接，多条金属线形成了第一接口11与第二接口12之间的多条传输通道。
本实施例中，第三半导体单元4包括一颗芯片或者一片晶圆(晶圆上包括多颗芯片)，以第三半导体单元4为一颗芯片为例，则第一半导体单元2与第二半导体单元3为芯片内的两个模块，例如，第一半导体单元2为模拟信号模块、第二半导体单元3为数字信号模块，模拟信号模块通过芯片内的走线连接于第一接口11，数字信号模块通过芯片内的走线连接于第二接口12，第一接口11与第二接口12通过芯片内的多条走线相互连接，使得这两个模块通过多条走线形成的多条传输通道实现互联通讯，减小了芯片内部走线的面积，继而也减小了走线之间的干扰。
本实施例相对于第三实施例而言，提供了在同个半导体单元的模块之间实现互联通讯的一种具体实现方式；减小了第三半导体单元内的走线面积，从而减小第三半导体单元的封装体积。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (17)

  1. 一种通信接口，其特征在于，包括：连接于第一半导体单元的第一接口，以及连接于第二半导体单元的第二接口，所述第一接口与所述第二接口相匹配且连接，并在所述第一半导体单元与所述第二半导体单元之间形成多条传输通道；
    在所述通信接口的一个时钟周期内，多条所述传输通道中的M条所述传输通道被复用在所述第一半导体单元与所述第二半导体单元之间传输多种类型的互联信号，M为大于8的整数。
  2. 如权利要求1所述的通信接口，其特征在于，所述第一接口与所述第二接口的结构相同；每个所述接口包括相互连接的逻辑控制单元、寄存器单元与驱动单元；所述第一接口的所述驱动单元连接于所述第二接口的所述驱动单元，形成多条所述传输通道；
    所述逻辑控制单元用于从所述寄存器单元中获取待传输的所述互联信号，并通过所述驱动单元输出所述待传输的所述互联信号；
    所述逻辑控制单元还用于将通过所述驱动单元接收到的所述互联信号存储到所述寄存器单元中。
  3. 如权利要求2所述的通信接口，其特征在于，所述寄存器单元包括：输入状态寄存器、输入地址寄存器、输入数据寄存器、输出数据寄存器；
    所述逻辑控制单元用于根据所述输入状态寄存器中的标志位，判断所属的所述接口是否处于输出状态；
    所述逻辑控制单元用于在判定所属的所述接口处于输出状态时，从所述输出数据寄存器中获取待传输的所述互联信号，并通过所述驱动单元输出所述待传输的所述互联信号；
    所述逻辑控制单元用于在判定所属的所述接口处于输入状态时，控制所述驱动单元处于接收状态，并通过所述驱动单元接收所述互联信号；
    所述逻辑控制单元用于根据所述输入地址寄存器中的地址信息，将接收到的所述互联信号存储到所述输入数据寄存器中。
  4. 如权利要求2所述的通信接口，其特征在于，每个所述驱动单元在所属的所述接口上形成多个引脚；所述第一接口的多个所述引脚与所述第二接口的多个所述引脚一一对应且连接，形成多条所述传输通道；所述多个引脚中包括M个数据引脚；被复用的所述传输通道为形成在所述第一接口的所述数据引脚与所述第二接口的所述数据引脚之间的所述传输通道。
  5. 如权利要求1所述的通信接口，其特征在于，所述第一接口与所述第二接口采用相同的工作频率，所述工作频率为所述第一半导体单元的内部时钟频率或所述第二半导体单元的内部时钟频率。
  6. 如权利要求1所述的通信接口，其特征在于，M大于或等于所述多种类型的互联信号中任一类型的所述互联信号的位宽。
  7. 如权利要求1所述的通信接口，其特征在于，M等于多种类型的所述互联信号的位宽中最大的位宽。
  8. 如权利要求1所述的通信接口，其特征在于，多条所述传输通道包括用于用于传输电源信号的所述传输通道，且用于传输电源信号的所述传输通道与所述M条所述传输通道不重叠。
  9. 如权利要求1至8任意一项所述的通信接口，其特征在于，所述多种类型的互联信号包括：操作指令、地址信号以及数据信号。
  10. 如权利要求9所述的通信接口，其特征在于，所述多种类型的互联信号还包括：通讯握手信号。
  11. 一种封装结构，其特征在于，包括：权利要求1至1中任一项所述的通信接口、第一半导体单元以及第二半导体单元。
  12. 如权利要求11所述的封装结构，其特征在于，所述第一半导体单元包括第一芯片，所述第二半导体单元包括第二芯片。
  13. 如权利要求12所述的封装结构，其特征在于，所述第一芯片与所述第二芯片分别为主控芯片和存储芯片。
  14. 如权利要求11所述的封装结构，其特征在于，任意两条所述传输通道之间的寄生电容小于预设的电容阈值。
  15. 如权利要求14所述的封装结构，其特征在于，所述第一接口与所述第二接口的结构相同；每个所述接口包括相互连接的逻辑控制单元、寄存器单元与驱动单元，每个所述驱动单元在所属的所述接口上形成多个引脚；所述第一接口的多个所述引脚与所述第二接口的多个所述引脚一一对应且连接，形成多条所述传输通道；
    采用倒装封装方式连接所述第一接口的多个所述引脚与所述第二接口的多个所述引脚，形成多条所述传输通道。
  16. 如权利要求11所述的封装结构，其特征在于，所述第一半导体单元与所述第二半导体单元均位于第三半导体单元上，所述通信接口位于所述第三半导体单元上；
    所述通信接口中的所述第一接口与所述第二接口通过所述第三半导体单元上的走线连接。
  17. 如权利要求16所述的封装结构，其特征在于，所述第三半导体单元为芯片，所述第一半导体单元与所述第二半导体单元为所述第三半导体单元上两个不同的模块。
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