WO2021146909A1

WO2021146909A1 - Demodulation circuit for isolation drive circuit, pulse generation circuit, and isolation drive circuit

Info

Publication number: WO2021146909A1
Application number: PCT/CN2020/073486
Authority: WO
Inventors: 黄睿; 唐雨池; 李�根
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2020-01-21
Filing date: 2020-01-21
Publication date: 2021-07-29
Also published as: CN112514222A

Abstract

Provided are a demodulation circuit for an isolation drive circuit, a pulse generation circuit, and an isolation drive circuit. A demodulation circuit connected to a drive MOS transistor demodulates an input narrow pulse signal to obtain a gate drive voltage of the drive MOS transistor; when a first pulse skipping edge of the narrow pulse signal arrives, a first voltage is presented and maintained until a second pulse skipping edge of the narrow pulse signal arrives; and when the second pulse skipping edge of the narrow pulse signal arrives, a second voltage is presented and maintained until the first pulse skipping edge of the narrow pulse signal arrives. When a duty cycle of a gate drive signal of the drive MOS transistor is changed, only an interval between a positive pulse and a negative pulse of the narrow pulse signal needs to be changed, without affecting the volt-second balance. Therefore, when the duty cycle of the gate drive signal of the drive MOS transistor is changed to a large extent, abnormal pulse transmission cannot be caused.

Description

Demodulation circuit, pulse generation circuit, and isolation drive circuit for isolation drive circuit

Technical field

The present disclosure relates to the technical field of drive circuits, and in particular, to a demodulation circuit, a pulse generation circuit, and an isolation drive circuit used for an isolation drive circuit.

Background technique

The current isolated gate drive scheme based on the direct drive of the gate drive transformer generally includes a drive signal buffer, a pulse transformer and a gate spike suppression network. Due to the limitation of the volt-second capacity of the driving pulse transformer, when the duty cycle changes in a large range, it will cause abnormal pulse transmission, which makes it impossible to achieve a wide range of duty cycle driving.

Summary of the invention

In view of this, the embodiments of the present disclosure propose a demodulation circuit, a pulse generation circuit, and an isolation drive circuit for an isolation drive circuit to solve the technical problem of the related art that a dynamic response to a wide range of duty cycle changes cannot be achieved.

According to the first aspect of the embodiments of the present disclosure, a demodulation circuit for an isolation drive circuit is provided. The demodulation circuit is connected to a drive MOS tube for demodulating the input narrow pulse signal so that the drive The gate voltage of the MOS tube changes periodically in the following way:

When the first pulse jump edge of the narrow pulse signal arrives, the first voltage is presented and maintained until the second pulse jump edge of the narrow pulse signal arrives;

When the second pulse jump edge of the narrow pulse signal arrives, the second voltage is presented and maintained until the first pulse jump edge of the narrow pulse signal arrives.

According to a second aspect of the embodiments of the present disclosure, a pulse generating circuit is provided, the pulse generating circuit is used to generate a narrow pulse signal that modulates the gate voltage of the driving MOS tube; wherein, the gate of the driving MOS tube The voltage presents and remains as the first voltage when the first pulse edge of the narrow pulse signal arrives, and remains as the first voltage until the second pulse edge of the narrow pulse signal arrives, and when the second pulse edge of the narrow pulse signal arrives, When the transition edge arrives, the second voltage is presented and maintained until the first pulse transition edge of the narrow pulse signal arrives.

According to a third aspect of the embodiments of the present disclosure, an isolation driving circuit is provided, and the isolation driving circuit includes the demodulation circuit described in any of the embodiments.

Applying the solution of the embodiment of this specification, the input narrow pulse signal is demodulated by the demodulation circuit connected to the driving MOS tube to obtain the gate driving voltage for driving the MOS tube. At the first pulse transition edge of the narrow pulse signal When it arrives, it presents and maintains the first voltage until the second pulse edge of the narrow pulse signal arrives; it presents and maintains the second voltage when the second pulse edge of the narrow pulse signal arrives. The first pulse edge of the narrow pulse signal arrives. When changing the duty cycle of the gate drive signal that drives the MOS tube, only the interval between the positive pulse and the negative pulse of the narrow pulse signal needs to be changed, and the volt-second balance is not affected. Therefore, when the duty ratio of the gate driving signal of the driving MOS tube is changed in a wide range, it will not cause abnormal pulse transmission.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained from these drawings without creative labor.

FIG. 1A is a timing diagram of a narrow pulse signal and a gate voltage according to an embodiment of the present disclosure.

FIG. 1B is a timing diagram of a narrow pulse signal and a gate voltage according to another embodiment of the present disclosure.

FIG. 2A is a circuit diagram of a demodulation circuit for an isolation driving circuit according to an embodiment of the present disclosure.

FIG. 2B is a circuit diagram of a demodulation circuit for an isolation driving circuit according to another embodiment of the present disclosure.

FIG. 2C is a circuit diagram of a demodulation circuit for an isolation driving circuit according to still another embodiment of the present disclosure.

FIG. 2D is a circuit diagram of a demodulation circuit for an isolation driving circuit according to another embodiment of the present disclosure.

FIG. 3A is a circuit diagram of an isolated driving circuit according to an embodiment of the present disclosure.

FIG. 3B is a circuit diagram of an isolated driving circuit according to another embodiment of the present disclosure.

FIG. 3C is a circuit diagram of an isolated driving circuit according to still another embodiment of the present disclosure.

FIG. 3D is a circuit diagram of an isolated driving circuit according to another embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a movable platform according to an embodiment of the present disclosure.

Detailed ways

The exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this specification. Rather, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

The terms used in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the specification. The singular forms of "a", "said" and "the" used in this specification and appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determination".

The current isolated gate drive scheme based on the direct drive of the gate drive transformer generally includes a drive signal buffer, a pulse transformer, and a gate spike suppression network (usually including a resistor and a Zener diode). Limited by the volt-second capacity of the driving pulse transformer, a wide range of arbitrary duty cycle driving cannot be achieved. When the duty cycle deviates from 50%, the PWM (Pulse Width Modulation, pulse width modulation) driving signal output by the driving transformer will float up or sink, which is caused by the change of the DC component in the driving signal due to the change of the duty cycle. When the driving signal floats or sinks, the switch tube is not fully turned on or turns off more reliably (in high-power situations, the gate of the switch tube is usually required to have sufficient negative voltage to ensure the reliability of turn-off), which will cause the switch tube to be turned off. Increased loss and even damage. In addition, the gate drive transformer is generally larger in size in order to achieve a certain volt-second capacity in low-frequency drive situations.

The isolated gate drive technology based on optocouplers/new digital isolators usually includes optocouplers or digital isolators as the isolation link, as well as corresponding isolated power supplies and gate-side drive buffers. Although this scheme can be driven at any duty cycle, it must be used in conjunction with an isolated power supply, which increases the complexity and cost of the system. Moreover, the transmission delay of the optocoupler is usually relatively large and the speed is slow; the price of the new digital isolator is usually high. At the same time, the isolated power supply of this scheme must not only achieve DC isolation, but also achieve high-frequency AC isolation. Because the switch tube side usually has a very large du/dt (u represents voltage, t represents time), there are rich high-order harmonics. If a switching power supply is used, the parasitic capacitance between the primary winding and the secondary winding of the isolation transformer in the isolation power supply is required to be small; if a power-frequency transformer is used, the parasitic capacitance between the primary and the secondary of the power-frequency transformer itself is very large. Yes, it must cooperate with blocking elements to isolate high-frequency components. This is very detrimental to the complexity and cost optimization and reliability optimization of the system.

To sum up, the current isolated gate drive technology cannot take into account the dynamic response of a wide range of duty cycle changes and low cost.

Based on this, the embodiments of the present disclosure provide a demodulation circuit and an isolation drive circuit for an isolation drive circuit. In some embodiments, the present disclosure provides a demodulation circuit for isolating a driving circuit. The demodulation circuit is connected to a driving MOS tube for demodulating the input narrow pulse signal so that the driving MOS tube The gate voltage changes periodically in the following manner: when the first pulse edge of the narrow pulse signal arrives, it presents and remains as the first voltage until the second pulse edge of the narrow pulse signal arrives; When the second pulse jump edge of the narrow pulse signal arrives, the second voltage is presented and maintained until the first pulse jump edge of the narrow pulse signal arrives.

The narrow pulse signal is a signal with an extremely narrow pulse width. Compared with the previous method that uses a PWM signal as a gate drive signal, the pulse width of the narrow pulse signal is much smaller than the width of the PWM signal. In practical applications, this The pulse width of the narrow pulse signal may be in the same order of magnitude as the edge width of the driving signal used to drive the MOS tube. In some embodiments, the positive and negative pulse widths of the narrow pulse signal are equal.

In some embodiments, one of the first voltage and the second voltage is a high voltage, and the other is a low voltage, for example, the first voltage is a positive voltage, and the second voltage is a negative voltage; For another example, the first voltage is a positive voltage, and the second voltage is a zero voltage. Or for example, the first voltage is a negative voltage, and the second voltage is a positive voltage; for another example, the first voltage is a zero voltage, and the second voltage is a positive voltage. As shown in FIG. 1A and FIG. 1B, it is a timing diagram of a narrow pulse signal and a gate voltage signal according to an embodiment of the present disclosure. Among them, x(t) represents the narrow pulse signal, and y(t) represents the gate voltage of the driving MOS tube. As shown in FIG. 1A, the first voltage is a positive voltage and the second voltage is a negative voltage; as shown in FIG. 1B, the first voltage is a positive voltage, and the second voltage is a zero voltage. In some embodiments, the first pulse jumping edge may be the rising edge of a positive pulse, and the second pulse jumping edge may be the falling edge of a negative pulse.

Applying the solution of the embodiment of this specification, the input narrow pulse signal is demodulated by the demodulation circuit connected to the driving MOS tube, so as to obtain the driving signal for driving the gate voltage of the driving MOS tube. When the first pulse jump edge of the narrow pulse signal arrives, the drive signal makes the gate voltage of the driving MOS tube present and maintains the first voltage until the second pulse jump edge of the narrow pulse signal arrives; When the second pulse jumping edge of the narrow pulse signal arrives, the driving signal causes the gate voltage of the driving MOS tube to present and maintain the second voltage until the first pulse jumping edge of the narrow pulse signal arrives.

When changing the duty cycle of the driving signal, only the time interval between the positive pulse and the negative pulse of the narrow pulse signal needs to be changed, which does not affect the volt-second balance. Therefore, when the duty ratio of the driving signal changes in a wide range, it will not cause abnormal pulse transmission. For example, when the duty cycle needs to be increased, the time interval t1 between the positive pulse and the negative pulse of the narrow pulse signal can be increased and/or the time interval t2 between the negative pulse and the positive pulse of the narrow pulse signal can be reduced; Conversely, when the duty cycle needs to be reduced, t1 can be reduced and/or t2 can be increased.

The narrow pulse signal of the embodiment of the present disclosure can adopt a digital or analog method to transform the original PWM signal into a narrow pulse signal that flips at its edge. The pulse width of the narrow pulse signal can be on the order of nanoseconds (ns). In the application scenarios of, according to the power level of the power device (for example, MOS tube), and the speed level at which the power level is turned on and off can be reduced or increased. High-power application scenarios require lower switching speeds of MOS tubes, and the pulse width of narrow pulse signals can be on the order of hundreds of nanoseconds to several microseconds; low-power application scenarios require higher switching speeds of MOS tubes, narrow pulses The pulse width of the signal can be between several nanoseconds to tens of nanoseconds. In the case of digitally generating the narrow pulse signal, FPGA (Field Programmable Gate Array), DSP (Digital Signal Processing, digital signal processing) or MCU (Microcontroller Unit, micro control unit) can be used. ) The original PWM signal is modulated to obtain the narrow pulse signal. For some PWM control situations that are more composed of analog circuits, it is difficult to directly generate a narrow pulse signal, and the narrow pulse signal can be generated based on some circuits (for example, an RC differential circuit). The demodulation circuit demodulates the narrow pulse signal, thereby restoring the original PWM signal, so as to control the gate voltage of the driving MOS transistor.

In some embodiments, the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS tube; the demodulation circuit includes: a first switch unit connected between the driving MOS tube; When the positive pulse rising edge of the narrow pulse signal arrives, the first switch unit is turned on, so that the gate voltage of the driving MOS transistor is presented and maintained at the first voltage until the negative pulse signal is negative. The falling edge of the pulse arrives; when the falling edge of the negative pulse of the narrow pulse signal arrives, the first switch unit is turned off, and the gate of the driving MOS transistor presents and maintains the second voltage until the narrow pulse The positive pulse rising edge of the signal arrives. The isolated driving circuit is realized by using a pulse transformer, and the demodulation circuit of the embodiment of the present disclosure is used in the isolated driving circuit realized by the pulse transformer. On the one hand, the cost is lower, and on the other hand, it solves the problem that the pulse transformer cannot be realized in the traditional technology The problem of arbitrary duty cycle.

As shown in FIG. 2A, it is a circuit diagram of a demodulation circuit according to an embodiment of the present disclosure. In this embodiment, the first switch unit in the demodulation circuit includes: a first MOS transistor Q11; the source of the first MOS transistor Q11 is in phase with the positive tap of the secondary winding of the pulse transformer T1 Connected, the drain of the first MOS transistor Q11 is connected to the gate of the driving MOS transistor Q1, and the gate of the first MOS transistor Q11 is connected to the negative tap of the secondary winding of the pulse transformer T1 and the The source of the driving MOS transistor Q1 is connected.

Among them, the first MOS transistor Q11 may be a signal field effect transistor. Among them, the signal field effect tube is a field effect tube with a small working voltage. In the embodiments of the present disclosure, the body diode of the signal field effect tube is used as the gate charging diode, and the narrow pulse signal can be demodulated through a MOS tube, and the narrow pulse signal is restored to the PWM signal. For some low-voltage, medium- and small-power situations that do not require negative voltage shut-off, such as electric bicycle drivers, the solution of this embodiment can be used to implement gate driving. The first MOS transistor Q11 in this embodiment may be an N-channel MOS transistor or a P-channel MOS transistor. In the embodiment shown in FIG. 2A, the first MOS transistor Q11 is an N-channel MOS transistor.

At the rising edge of the positive pulse of the narrow pulse signal, the first MOS transistor Q11 is turned on, and the gate of the driving MOS transistor Q1 presents a positive voltage until the falling edge of the negative pulse of the narrow pulse signal arrives. At the negative pulse falling edge of the narrow pulse signal, the first MOS transistor Q11 is turned off, and the gate of the driving MOS transistor Q1 presents a zero voltage until the positive pulse rising edge of the narrow pulse signal arrives. So it goes round and round.

In practical applications, it is also possible to connect the source of the first MOS transistor Q11 to the negative tap of the secondary winding of the pulse transformer T1, and connect the drain of the first MOS transistor Q11 to the driving MOS transistor. The gate of Q1 is connected, and the gate of the first MOS transistor Q11 is connected to the positive tap of the secondary winding of the pulse transformer T1 and the source of the driving MOS transistor Q1, respectively. In this case, at the falling edge of the negative pulse of the narrow pulse signal, the first MOS transistor Q11 is turned on, and the gate of the driving MOS transistor Q1 presents a positive voltage until the positive pulse of the narrow pulse signal The rising edge of is coming. At the rising edge of the positive pulse of the narrow pulse signal, the first MOS transistor Q11 is turned off, and the gate of the driving MOS transistor Q1 presents a zero voltage until the falling edge of the negative pulse of the narrow pulse signal arrives. So it goes round and round.

In some embodiments, the demodulation circuit further includes a first voltage dividing unit connected to the first switch unit; the first voltage dividing unit is used to divide the voltage on the first switch unit Pressure. In the embodiment in which the first switch unit includes a first MOS transistor Q11, the first voltage divider unit is connected to the first MOS transistor Q11, and is used for performing voltage on the first MOS transistor Q11. Partial pressure.

Wherein, the first voltage dividing unit includes: a first resistor R11 and a second resistor R12; the first resistor R11 is connected between the gate and the source of the first MOS transistor Q11, and the second resistor R12 is connected between the gate of the first MOS transistor Q11 and the negative tap of the secondary winding of the pulse transformer T1.

In this embodiment, the gate voltage of the first MOS transistor Q11 can be denoted as:

Among them, r11 and r12 are the resistance of the first resistor R11 and the second resistor R12, respectively, U _g is the output voltage of the secondary winding of the pulse transformer T1, and U _T is the gate voltage of the first MOS transistor Q11. When the output voltage of the secondary winding of the pulse transformer T1 is greater than the working voltage of the first MOS transistor Q11, the first voltage dividing unit is used to divide the voltage on the first MOS transistor Q11, so as to avoid excessive voltage. This results in damage to the first MOS transistor Q11. Further, the first voltage dividing unit further includes: a first capacitor C11 connected in parallel with the second resistor R12.

The first voltage dividing unit of this embodiment can not only realize the function of dividing the voltage on the first MOS transistor Q11, but also can filter out the DC interference signal in the circuit through the first capacitor C11, and improve the anti-interference of the circuit. sex.

In some embodiments, the demodulation circuit includes: a first switch unit connected to the drive MOS tube; a second switch unit connected in parallel with the first switch unit, connected to the first switch unit and the drive MOS A first diode between the tubes, and a second diode connected between the second switch unit and the driving MOS tube, wherein the cathode of the first diode is connected to the first switch unit The anode of the second diode is connected to the second switch unit; when the first pulse edge of the narrow pulse signal arrives, the first switch unit is turned on, and the first switch unit is turned on. The second switch unit is turned off, and the gate capacitance of the driving MOS tube is charged through the first diode, thereby presenting and maintaining the first voltage; when the second pulse transition edge of the narrow pulse signal arrives, The first switch unit is turned off, the second switch unit is turned on, and the gate capacitance of the driving MOS transistor is discharged through the second diode, thereby presenting and maintaining the second voltage.

In this embodiment, the first switch unit may be a triode or a MOS tube, and the second switch unit may also be a triode or a MOS tube. In the following, two cases where the first switch unit and the second switch unit are both triodes, and the first switch unit and the second switch unit are both MOS transistors are respectively described as examples. In practical applications, it can also be the case where one of the first switch unit and the second switch unit is a MOS transistor, and the other is a triode. The working mode is similar to that of both being triodes or both being MOS transistors. , I won’t repeat it here.

As shown in FIG. 2B, it is a circuit diagram of a demodulation circuit according to another embodiment of the present disclosure. In this embodiment, the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS tube; the first switch unit in the demodulation circuit includes: a first triode Q21; The emitter of the first transistor Q21 is connected to the positive tap of the secondary winding of the pulse transformer T2, the collector is connected to the cathode of the first diode D11, and the base is connected to the pulse transformer respectively. The negative tap of the secondary winding of T2 and the source of the driving MOS transistor Q2 are connected. In this embodiment, the second switch unit in the demodulation circuit includes: a second triode Q22; the emitter of the second triode Q22 and the positive of the secondary winding of the pulse transformer T2 The taps are connected, the collector is connected with the anode of the second diode D22, and the bases are respectively connected with the negative tap of the secondary winding of the pulse transformer T2 and the source of the driving MOS transistor Q2.

Among them, the first transistor Q21 may be a PNP type transistor, and the second transistor Q22 may be an NPN type transistor. The embodiment of the present disclosure realizes the demodulation of the narrow pulse signal through two transistors and two diodes, and restores the narrow pulse signal to a PWM signal. The obtained PWM signal includes both a positive voltage and a negative voltage. For some high voltage and high power, it is required In the case of negative voltage shutdown, the solution of this embodiment can be used to realize gate drive.

At the rising edge of the positive pulse of the narrow pulse signal, the first transistor Q21 is turned on, and the second transistor Q22 is turned off. The first diode D21 causes the positive pulse to drive the MOS transistor Q2. The gate capacitance is charged, and the gate of the MOS transistor Q2 is driven to present a positive voltage until the negative pulse falling edge of the narrow pulse signal arrives. At the negative pulse falling edge of the narrow pulse signal, the second transistor Q22 is turned on, the first transistor Q21 is turned off, and the gate capacitance of the driving MOS transistor Q2 is driven by the second diode D22 Discharge, the gate of the driving MOS transistor Q2 presents a negative voltage until the positive pulse rising edge of the narrow pulse signal arrives. So it goes round and round.

In some embodiments, the demodulation circuit further includes: a second voltage dividing unit connected to the first transistor Q21, and/or a third voltage dividing unit connected to the second transistor Q22 The second voltage dividing unit is used to divide the voltage on the first transistor Q21, and the third voltage dividing unit is used to divide the voltage on the second transistor Q22. Partial pressure.

In some embodiments, the second voltage dividing unit includes: a third resistor R21 and a fourth resistor R22; the third resistor R21 is connected between the base and the emitter of the first transistor Q21, The fourth resistor R22 is connected between the base of the first transistor Q21 and the negative tap of the secondary winding of the pulse transformer T2. Further, the second voltage dividing unit further includes: a second capacitor C21 connected in parallel with the fourth resistor R22.

In other embodiments, the third voltage dividing unit includes: a fifth resistor R23 and a sixth resistor R24; the fifth resistor R23 is connected between the base and the emitter of the second transistor Q22 The sixth resistor R24 is connected between the base of the second transistor Q22 and the negative tap of the secondary winding of the pulse transformer T2. Further, the third voltage dividing unit further includes: a third capacitor C22 connected in parallel with the sixth resistor R24.

The voltage dividing mode of the second voltage dividing unit and the third voltage dividing unit is similar to the voltage dividing mode of the first voltage dividing unit, and will not be repeated here.

As shown in FIG. 2C, it is a circuit diagram of a demodulation circuit according to another embodiment of the present disclosure. In this embodiment, the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS tube; the first switch unit in the demodulation circuit includes: a second MOS tube Q31; The source of the second MOS transistor Q31 is connected to the positive tap of the secondary winding of the pulse transformer T3, the drain of the second MOS transistor Q31 is connected to the cathode of the first diode D31, and the second The gate of the MOS transistor Q31 is respectively connected to the negative tap of the secondary winding of the pulse transformer T3 and the source of the driving MOS transistor Q3. In this embodiment, the second switch unit in the demodulation circuit includes: a third MOS transistor Q32; the source of the third MOS transistor Q32 is in phase with the positive tap of the secondary winding of the pulse transformer T3 The drain of the third MOS transistor Q32 is connected to the anode of the second diode D32, and the gate of the third MOS transistor Q32 is connected to the negative tap of the secondary winding of the pulse transformer T3 and the The source of the driving MOS transistor Q3 is connected.

Among them, the second MOS transistor Q31 may be a P-channel MOS transistor, and the third MOS transistor Q32 may be an N-channel MOS transistor. The second MOS transistor Q31 and the third MOS transistor Q32 may be power field effect transistors, that is, field effect transistors with a relatively large working voltage. The embodiment of the present disclosure realizes the demodulation of the narrow pulse signal through two MOS tubes and two diodes, and restores the narrow pulse signal to a PWM signal. The obtained PWM signal includes both a positive voltage and a negative voltage. For some high voltage and high power, Where negative voltage shut-off is required, the solution of this embodiment can be used to realize gate drive.

At the rising edge of the positive pulse of the narrow pulse signal, the second MOS transistor Q31 is turned on, the third MOS transistor Q32 is turned off, and the positive pulse is driven to the gate of the MOS transistor Q3 through the first diode D31. The capacitor is charged to drive the gate of the MOS transistor Q3 to present a positive voltage until the negative pulse falling edge of the narrow pulse signal arrives. At the negative pulse falling edge of the narrow pulse signal, the second MOS transistor Q31 is turned off, the third MOS transistor Q32 is turned on, and the gate capacitance of the driving MOS transistor Q3 is discharged through the second diode D32, The gate of the driving MOS transistor Q3 presents a negative voltage until the positive pulse rising edge of the narrow pulse signal arrives. So it goes round and round.

In some embodiments, the demodulation circuit further includes: a fourth voltage dividing unit connected to the second MOS transistor Q31, and/or a fifth voltage dividing unit connected to the third MOS transistor Q32 The fourth voltage dividing unit is used to divide the voltage on the second MOS transistor Q31, and the fifth voltage dividing unit is used to divide the voltage on the third MOS transistor Q32.

In some embodiments, the fourth voltage dividing unit includes: a seventh resistor R31 and an eighth resistor R32; the seventh resistor R31 is connected between the gate and the source of the second MOS transistor Q31, so The eighth resistor R32 is connected between the gate of the second MOS transistor Q31 and the negative tap of the secondary winding of the pulse transformer T3. Further, the fourth voltage dividing unit further includes: a fourth capacitor C31 connected in parallel with the eighth resistor T32.

In other embodiments, the fifth voltage divider unit includes: a ninth resistor R33 and a tenth resistor R34; the ninth resistor R33 is connected between the gate and the source of the third MOS transistor Q32, The tenth resistor R34 is connected between the gate of the third MOS transistor Q32 and the negative tap of the secondary winding of the pulse transformer T3. Further, the fifth voltage dividing unit further includes: a fifth capacitor C32 connected in parallel with the tenth resistor R34.

The voltage dividing mode of the fourth voltage dividing unit and the fifth voltage dividing unit is similar to the voltage dividing mode of the first voltage dividing unit, and will not be repeated here.

As shown in FIG. 2D, it is a circuit diagram of a demodulation circuit according to another embodiment of the present disclosure. The demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS tube; the first switch unit includes: a third transistor Q41, an eleventh resistor R41 and a third diode D41; The anode of the third diode D41 is connected to the positive tap of the secondary winding of the pulse transformer T4, and the cathode is connected to the gate of the driving MOS transistor Q4; the collector of the third transistor Q41 Connected to the cathode of the third diode D41, the emitter is connected to the zero tap of the secondary winding of the pulse transformer T4 and the source of the driving MOS transistor Q4, and the base passes through the eleventh The resistor R41 is connected to the negative tap of the secondary winding of the pulse transformer T4; when the narrow pulse signal is at a positive level, the gate capacitance of the driving MOS transistor Q4 is charged through the third diode D41, so The gate voltage of the driving MOS transistor Q4 presents the first voltage; when the narrow pulse signal is at a negative level, the gate capacitance of the driving MOS transistor Q4 is discharged through the third transistor D41, and the driving The gate voltage of the MOS transistor Q4 presents the second voltage.

Wherein, the third transistor Q41 may be an NPN type transistor. This embodiment can be applied to occasions where negative pressure shut-off is not required. At the rising edge of the positive pulse of the narrow pulse signal, the third diode D41 and the third transistor Q41 are turned on, driving the gate of the MOS transistor Q4 to present a positive voltage until the negative of the narrow pulse signal The falling edge of the pulse arrives. At the negative pulse falling edge of the narrow pulse signal, the third diode D41 and the third transistor Q41 are turned off, and the gate of the driving MOS transistor Q4 presents a zero voltage until the positive pulse of the narrow pulse signal The rising edge is coming. So it goes round and round. The third transistor Q41 in this embodiment can also be replaced by an N-channel MOS tube, where the gate of the N-channel MOS tube passes through the eleventh resistor R41 and the secondary winding of the pulse transformer T4. The negative tap is connected, the drain is connected with the cathode of the third diode D41, and the source is respectively connected with the zero tap of the secondary winding of the pulse transformer T4 and the source of the driving MOS transistor Q4.

The embodiments of the present disclosure also provide a pulse generating circuit, which is used to generate a narrow pulse signal that modulates the gate voltage of the driving MOS tube; wherein, the gate voltage of the driving MOS tube is within the narrow When the first pulse jump edge of the pulse signal arrives, it presents and remains as the first voltage until the second pulse jump edge of the narrow pulse signal arrives, and when the second pulse jump edge of the narrow pulse signal arrives The second voltage is presented and maintained until the first pulse edge of the narrow pulse signal arrives.

In some embodiments, the pulse generating circuit generates the narrow pulse signal in an analog manner or a digital manner.

In some embodiments, when the pulse generation circuit generates the narrow pulse signal in an analog manner, the pulse generation circuit includes a modulation circuit that modulates a PWM signal to generate the narrow pulse signal. Wherein, the modulation circuit may be an RC differentiation circuit. In other embodiments, when the pulse generating circuit generates the narrow pulse signal in a digital manner, the pulse generating circuit includes a digital chip for generating the narrow pulse signal. Wherein, the digital chip may be FPGA, DSP or MCU.

In some embodiments, the first pulse jumping edge may be the rising edge of a positive pulse, and the second pulse jumping edge may be the falling edge of a negative pulse.

Embodiments of the present disclosure also provide an isolation drive circuit, which includes the demodulation circuit described in any of the above embodiments. In some embodiments, the isolation driving circuit further includes the pulse generating circuit described in any of the above embodiments. As shown in FIGS. 3A to 3D, they are respectively an isolated driving circuit including the demodulation circuit of any of the embodiments in FIGS. 2A to 2D. In some embodiments, the isolated driving circuit is used to drive a motor.

In some embodiments, as shown in FIG. 4, an embodiment of the present disclosure further provides a movable platform, including: a body 401; a motor 402, which is arranged in the body 401, and the motor 402 is used for The mobile platform provides power; and the isolated drive circuit 403 described in any embodiment is used to drive the motor 402 to rotate. For the embodiment of the isolation driving circuit 403 in the above-mentioned movable platform, please refer to the foregoing embodiment of the isolation driving circuit for details, which will not be repeated here.

In some embodiments, the movable platform may be a drone, an unmanned vehicle, a pan/tilt, or the like. Applications of the embodiments of the present disclosure include, but are not limited to, any of the following: In consumer electronics applications, it can be used to achieve high-reliability commercial desktop computer switching power supplies, higher-power laptop adapters, and higher-power fast-charging mobile phone chargers. High power, etc.; in industrial applications that require high voltage, high power and high reliability, it can be used to realize inverters, industrial UPS (Uninterrupted Power Supply, uninterrupted power supply), inverters, induction heating excitation power supplies, arc welding equipment power supplies , Ultrasonic welding machine, ultrasonic cleaning machine, CO ₂ (carbon dioxide) laser high-voltage drive power supply, Nd: YAG (yttrium aluminum garnet crystal) pulse laser pulse xenon lamp excitation power supply, etc.; in scientific research applications, it can be used to achieve work in harsh environments Meteorological radar system motor driver, radar system pulse power supply, etc.; in medical applications, it can be used to achieve high-reliability UPS systems for medical systems, X-ray tube drive power, etc.; in automotive applications, it can be used to achieve higher voltage electric vehicle motors Drivers, electric vehicle chargers, electric vehicle battery pack management systems, etc.

The various technical features in the above embodiments can be combined arbitrarily, as long as there is no conflict or contradiction between the combinations of features, but due to space limitations, they are not described one by one. Therefore, the various technical features in the above embodiments can be combined arbitrarily. It also belongs to the scope of the disclosure of this specification.

Those skilled in the art will easily think of other embodiments of the present disclosure after considering the specification and practicing the specification disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptive changes of the present disclosure. These variations, uses, or adaptive changes follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field that are not disclosed in the present disclosure. . The description and the embodiments are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are pointed out by the following claims.

It should be understood that the present disclosure is not limited to the precise structure that has been described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the present disclosure. Within the scope of protection.

Claims

A demodulation circuit for an isolation drive circuit, characterized in that the demodulation circuit is connected to a drive MOS tube for demodulating the input narrow pulse signal so that the gate voltage of the drive MOS tube is in accordance with Changes periodically in the following ways:

When the first pulse jump edge of the narrow pulse signal arrives, the first voltage is presented and maintained until the second pulse jump edge of the narrow pulse signal arrives;

When the second pulse jump edge of the narrow pulse signal arrives, the second voltage is presented and maintained until the first pulse jump edge of the narrow pulse signal arrives.
The demodulation circuit according to claim 1, wherein the demodulation circuit comprises:

A first switch unit connected to the driving MOS tube;

When the first pulse jumping edge of the narrow pulse signal arrives, the first switch unit is turned on, so that the gate voltage of the driving MOS transistor is presented and maintained at the first voltage until the narrow pulse The second pulse transition edge of the signal arrives;

When the second pulse jump edge of the narrow pulse signal arrives, the first switch unit is turned off, and the gate of the drive MOS transistor presents and maintains the second voltage until the first voltage of the narrow pulse signal is reached. A pulse edge is coming.
The demodulation circuit according to claim 2, wherein the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS tube; the first switch unit comprises:

The first MOS tube;

The source of the first MOS tube is connected to the positive tap of the secondary winding of the pulse transformer, the drain of the first MOS tube is connected to the gate of the driving MOS tube, and the first MOS tube The gates of are respectively connected with the negative tap of the secondary winding of the pulse transformer and the source of the driving MOS tube.
The demodulation circuit according to claim 3, wherein the demodulation circuit further comprises:

A first voltage divider unit connected to the first MOS tube;

The first voltage dividing unit is used to divide the voltage on the first MOS transistor.
The demodulation circuit according to claim 4, wherein the first voltage dividing unit comprises:

The first resistance and the second resistance;

The first resistor is connected between the gate and the source of the first MOS tube, and the second resistor is connected between the gate of the first MOS tube and the negative tap of the secondary winding of the pulse transformer. between.
The demodulation circuit according to claim 5, wherein the first voltage dividing unit further comprises:

A first capacitor connected in parallel with the second resistor.
The demodulation circuit according to any one of claims 2 to 6, wherein the first voltage is a positive voltage, and the second voltage is a zero voltage; and/or

The first pulse is a positive pulse, and the second pulse is a negative pulse.
8. The demodulation circuit according to claim 7, wherein the pulse width of the narrow pulse signal and the edge width of the driving signal used to drive the MOS transistor are in the same order; and/or

The positive and negative pulse widths of the pulse signal are equal.
8. The demodulation circuit according to claim 8, wherein the narrow pulse signal is generated by a digital chip or is obtained by modulating a PWM signal by an analog modulation circuit.
The demodulation circuit according to claim 9, wherein the digital chip is an FPGA, DSP or MCU; and/or

The analog modulation circuit is an RC differential circuit.
The demodulation circuit according to claim 2, wherein the demodulation circuit further comprises:

A second switch unit connected in parallel with the first switch unit, a first diode connected between the first switch unit and the driving MOS tube, and between the second switch unit and the driving MOS tube The second diode, wherein the cathode of the first diode is connected to the first switch unit, and the anode of the second diode is connected to the second switch unit;

When the first pulse transition edge of the narrow pulse signal arrives, the first switch unit is turned on, the second switch unit is turned off, and the gate capacitance of the driving MOS transistor passes through the first diode Charging, thereby presenting and maintaining the first voltage;

When the second pulse transition edge of the narrow pulse signal arrives, the first switch unit is turned off, the second switch unit is turned on, and the gate capacitance of the driving MOS transistor passes through the second diode Discharge, thereby presenting and maintaining the second voltage.
The demodulation circuit according to claim 11, wherein the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS tube; the first switch unit comprises:

First triode

The emitter of the first triode is connected to the positive tap of the secondary winding of the pulse transformer, the collector is connected to the cathode of the first diode, and the base is connected to the secondary winding of the pulse transformer. The negative tap of and the source of the driving MOS tube are connected;

and / or

The second switch unit includes:

Second triode

The emitter of the second triode is connected to the positive tap of the secondary winding of the pulse transformer, the collector is connected to the anode of the second diode, and the base is connected to the secondary winding of the pulse transformer. The negative tap of and the source of the driving MOS tube are connected.
The demodulation circuit according to claim 12, wherein the demodulation circuit further comprises:

A second voltage dividing unit connected to the first triode, and a third voltage dividing unit connected to the second triode;

The second voltage dividing unit is used to divide the voltage on the first triode, and the third voltage dividing unit is used to divide the voltage on the second triode.
The demodulation circuit according to claim 13, wherein the second voltage dividing unit comprises:

The third resistance and the fourth resistance;

The third resistor is connected between the base and emitter of the first triode, and the fourth resistor is connected between the base of the first triode and the negative of the secondary winding of the pulse transformer. Between taps

and / or

The third voltage dividing unit includes:

The fifth resistance and the sixth resistance;

The fifth resistor is connected between the base and emitter of the second triode, and the sixth resistor is connected between the base of the second triode and the negative of the secondary winding of the pulse transformer. Between the taps.
The demodulation circuit according to claim 14, wherein the second voltage dividing unit further comprises:

A second capacitor connected in parallel with the fourth resistor;

The third voltage dividing unit further includes:

A third capacitor connected in parallel with the sixth resistor.
The demodulation circuit according to claim 11, wherein the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS tube; the first switch unit comprises:

The second MOS tube;

The source of the second MOS tube is connected to the positive tap of the secondary winding of the pulse transformer, the drain of the second MOS tube is connected to the cathode of the first diode, and the second MOS tube is connected to the cathode of the first diode. The gate is respectively connected with the negative tap of the secondary winding of the pulse transformer and the source of the driving MOS tube;

and / or

The second switch unit includes:

The third MOS tube;

The source of the third MOS tube is connected to the positive tap of the secondary winding of the pulse transformer, the drain of the third MOS tube is connected to the anode of the second diode, and the third MOS tube is connected to the anode of the second diode. The gate of the tube is respectively connected with the negative tap of the secondary winding of the pulse transformer and the source of the driving MOS tube.
The demodulation circuit according to claim 16, wherein the demodulation circuit further comprises:

A fourth voltage dividing unit connected to the second MOS tube, and a fifth voltage dividing unit connected to the third MOS tube;

The fourth voltage dividing unit is used to divide the voltage on the second MOS transistor, and the fifth voltage dividing unit is used to divide the voltage on the third MOS transistor.
The demodulation circuit according to claim 17, wherein the fourth voltage dividing unit comprises:

The seventh resistor and the eighth resistor;

The seventh resistor is connected between the gate and the source of the second MOS tube, and the eighth resistor is connected between the gate of the second MOS tube and the negative tap of the secondary winding of the pulse transformer. between;

and / or

The fifth voltage dividing unit includes:

Ninth resistor and tenth resistor;

The ninth resistor is connected between the gate and the source of the third MOS transistor, and the tenth resistor is connected between the gate of the third MOS transistor and the negative tap of the secondary winding of the pulse transformer. between.
The demodulation circuit according to claim 18, wherein the fourth voltage dividing unit further comprises:

A fourth capacitor connected in parallel with the eighth resistor;

The fifth voltage dividing unit further includes:

A fifth capacitor connected in parallel with the tenth resistor.
The demodulation circuit according to claim 2, wherein the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS tube; the first switch unit comprises:

The third triode, the eleventh resistor and the third diode;

The anode of the third diode is connected to the positive tap of the secondary winding of the pulse transformer, and the cathode is connected to the gate of the driving MOS tube;

The collector of the third triode is connected with the cathode of the third diode, and the emitter is respectively connected with the zero tap of the secondary winding of the pulse transformer and the source of the driving MOS tube. The pole is connected to the negative tap of the secondary winding of the pulse transformer through the eleventh resistor;

When the narrow pulse signal is at a positive level, the gate capacitance of the driving MOS transistor is charged through the third diode, and the gate voltage of the driving MOS transistor presents the first voltage;

When the narrow pulse signal is at a negative level, the gate capacitance of the driving MOS transistor is discharged through the third triode, and the gate voltage of the driving MOS transistor presents the second voltage.
The demodulation circuit according to any one of claims 11 to 20, wherein the first voltage is a positive voltage, and the second voltage is a negative voltage; and/or

The first pulse is a positive pulse, and the second pulse is a negative pulse.
The demodulation circuit according to claim 21, wherein the pulse width of the narrow pulse signal is in the same order of magnitude as the edge width of the driving signal used to drive the MOS transistor; and/or

The positive and negative pulse widths of the pulse signal are equal.
The demodulation circuit according to claim 22, wherein the narrow pulse signal is generated by a digital chip, or is obtained by modulating a PWM signal by an analog modulation circuit.
The demodulation circuit according to claim 23, wherein the digital chip is an FPGA, DSP or MCU; and/or

The analog modulation circuit is an RC differential circuit.
A pulse generating circuit, characterized in that the pulse generating circuit is used to generate a narrow pulse signal that modulates the gate voltage of the driving MOS tube;

Wherein, the gate voltage of the driving MOS tube presents and maintains the first voltage when the first pulse edge of the narrow pulse signal arrives and remains until the second pulse edge of the narrow pulse signal arrives, and When the second pulse jump edge of the narrow pulse signal arrives, the second voltage is presented and maintained until the first pulse jump edge of the narrow pulse signal arrives.
The pulse generating circuit according to claim 25, wherein the pulse generating circuit generates the narrow pulse signal in an analog manner or a digital manner.
The pulse generating circuit according to claim 26, wherein when the pulse generating circuit generates the narrow pulse signal in an analog manner, the pulse generating circuit includes modulating a PWM signal to generate the A modulation circuit for narrow pulse signals; and/or

In the case where the pulse generating circuit generates the narrow pulse signal in a digital manner, the pulse generating circuit includes a digital chip for generating the narrow pulse signal.
The pulse generating circuit according to claim 27, wherein the modulation circuit is an RC differentiation circuit; and/or

The digital chip is FPGA, DSP or MCU.
An isolated drive circuit, characterized in that, the isolated drive circuit includes:

The demodulation circuit according to any one of claims 1 to 24.
The isolated drive circuit of claim 29, wherein the isolated drive circuit further comprises:

The pulse generating circuit according to any one of claims 25 to 28.
The isolated drive circuit according to claim 29 or 30, wherein the isolated drive circuit is used to drive a motor.
A movable platform, characterized in that it comprises:

Body

An electric motor, arranged in the body, and the electric motor is used to provide power for the movable platform; and

The isolated drive circuit according to any one of claims 29 to 31, which is used to drive the motor to rotate.