CN216625709U

CN216625709U - High-voltage driving circuit of high-power field effect transistor

Info

Publication number: CN216625709U
Application number: CN202123207419.9U
Authority: CN
Inventors: 王欢
Original assignee: Ruitao Electronic Technology Wuxi Co ltd
Current assignee: Ruitao Electronic Technology Wuxi Co ltd
Priority date: 2021-12-20
Filing date: 2021-12-20
Publication date: 2022-05-27
Anticipated expiration: 2031-12-20

Abstract

The utility model discloses a high-voltage driving circuit of a high-power field effect transistor, which forms an inverter structure by a thin gate NMOS (N-channel metal oxide semiconductor) tube and a thin gate PMOS (P-channel metal oxide semiconductor) tube, adopts a pulse-assisted rapid latch structure to drive the thin gate PMOS tube at high voltage, and drives the thin gate NMOS tube at low voltage by a cascade inverter, thereby ensuring the rapid driving capability of the high-voltage driving circuit, simultaneously avoiding the need of adopting a driving chip with large area and high price, ensuring that the high-voltage driving circuit does not generate larger static power consumption, simultaneously saving the cost of the whole circuit, and having the advantages of simple structure and easy realization.

Description

High-voltage driving circuit of high-power field effect transistor

Technical Field

The utility model relates to a field effect transistor driving circuit, in particular to a high-voltage driving circuit of a high-power field effect transistor.

Background

The driving circuit of the LED lamp generally comprises an NMOS tube and a PMOS tube to form a phase inverter, the driving voltage of the power tube generally reaches more than 10V, if the driving level phase inverter is directly supplied with power by adopting the high voltage of more than 10V, the grid electrode of the phase inverter tube needs to bear the high voltage of more than 10V, the driving level NMOS tube and the PMOS tube need to adopt high-voltage-resistant thick-grid devices, the on-resistance is large, and in addition, electronic chips reaching the same driving capability are adopted, the area of the electronic chips is large, the price is high, and the cost of the LED lamp and the size of an actual circuit are increased undoubtedly; if the thin gate device is directly used for driving, the thin gate NMOS and the thin gate PMOS of the driving stage can only be controlled separately, and an extra power supply is needed to provide voltage for the PMOS driving circuit, so that the problems of power supply stability, excessive filter capacitance and the like exist, the circuit is complex, the implementation cost is high, meanwhile, the static power consumption is large, and the driving speed is slow.

Disclosure of Invention

In order to overcome the defects of the prior art, the utility model provides a high-voltage driving circuit of a high-power field effect transistor.

The technical scheme adopted by the utility model for solving the technical problem is as follows:

a high-voltage driving circuit of a high-power field effect transistor comprises a voltage stabilizing diode D3, a voltage stabilizing diode D4, a PMOS (P-channel metal oxide semiconductor) transistor Q8, an NMOS (N-channel metal oxide semiconductor) transistor Q9, an NMOS (N-channel metal oxide semiconductor) transistor Q5, an NMOS (N-channel metal oxide semiconductor) transistor Q6, an NMOS transistor Q4, an NMOS transistor Q7, a PMOS transistor Q10, a PMOS transistor Q11, a current limiting resistor R5, a current limiting resistor R6, a current limiting resistor R7 and a current limiting resistor R8; the drain electrode of the PMOS tube Q8 is connected with the drain electrode of the NMOS tube Q9, the source electrode of the PMOS tube Q8 is divided into four paths, one path is connected with the negative electrode of the voltage stabilizing diode D4, the second path is connected with the source electrode of the PMOS tube Q11, the third path is connected with the source electrode of the PMOS tube Q10, and the fourth path is connected with the negative electrode of the voltage stabilizing diode D3; the grid electrode of the PMOS tube Q8 is divided into five paths, one path is connected with the anode of the voltage stabilizing diode D4, the second path is connected with the drain electrode of the PMOS tube Q11, the third path is connected with the grid electrode of the PMOS tube Q10, the fourth path is connected with the drain electrode of the NMOS tube Q7 through the current limiting resistor R8, and the fifth path is connected with the drain electrode of the PMOS tube Q6 through the current limiting resistor R7; the positive electrode of the voltage stabilizing diode D3 is divided into four paths, one path is connected with the grid electrode of the PMOS tube Q11, the second path is connected with the drain electrode of the PMOS tube Q10, the third path is connected with the drain electrode of the NMOS tube Q4 through the current limiting resistor R5, and the fourth path is connected with the drain electrode of the NMOS tube Q5 through the current limiting resistor R6; the source electrodes of the NMOS tube Q4, the NMOS tube Q5, the NMOS tube Q6 and the NMOS tube Q7 are all grounded, and the grid electrodes of the four are respectively connected with an input signal phi A, an input signal phi B, an input signal phi C and an input signal phi D.

The input signal phi C is an inverse signal of the input signal phi A; the input signal phi B and the input signal phi D are rising edge pulse signals of the input signal phi A and the input signal phi C respectively.

The resistance value of the current-limiting resistor R6 is smaller than that of the current-limiting resistor R5, and the resistance value of the current-limiting resistor R8 is smaller than that of the current-limiting resistor R7.

The high-voltage driving circuit comprises an inverter U1 and an inverter U2, wherein the input end of the inverter U1 is connected with an input signal φ A, and the output end of the inverter U1 is connected with the grid electrode of the NMOS tube Q9 through the inverter U2.

The utility model has the beneficial effects that: according to the utility model, the thin gate NMOS tube and the thin gate PMOS tube form an inverter structure, the thin gate PMOS tube is driven at high voltage by adopting a pulse-assisted rapid latch structure, and the thin gate NMOS tube is driven at low voltage by adopting a cascade inverter, so that the rapid driving capability of a high-voltage driving circuit is ensured, and meanwhile, a driving chip with large area and high price is not required, so that the high-voltage driving circuit is ensured not to generate large static power consumption, and the cost of the whole circuit is saved.

Drawings

The utility model is further illustrated with reference to the following figures and examples.

FIG. 1 is a circuit schematic of the present invention;

fig. 2 is a waveform diagram of an input signal.

Detailed Description

In the following, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by those skilled in the art without any inventive work based on the embodiments of the present invention belong to the protection scope of the present invention.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Referring to fig. 1 and 2, a high-voltage driving circuit of a high-power field effect transistor includes a zener diode D3, a zener diode D4, a PMOS transistor Q8, an NMOS transistor Q9, an NMOS transistor Q5, an NMOS transistor Q6, an NMOS transistor Q4, an NMOS transistor Q7, a PMOS transistor Q10, a PMOS transistor Q11, a current-limiting resistor R5, a current-limiting resistor R6, a current-limiting resistor R7, and a current-limiting resistor R8; the drain electrode of the PMOS tube Q8 is connected with the drain electrode of the NMOS tube Q9, the source electrode of the PMOS tube Q8 is divided into four paths, one path is connected with the negative electrode of the voltage stabilizing diode D4, the second path is connected with the source electrode of the PMOS tube Q11, the third path is connected with the source electrode of the PMOS tube Q10, and the fourth path is connected with the negative electrode of the voltage stabilizing diode D3; the grid electrode of the PMOS tube Q8 is divided into five paths, one path is connected with the anode of the voltage stabilizing diode D4, the second path is connected with the drain electrode of the PMOS tube Q11, the third path is connected with the grid electrode of the PMOS tube Q10, the fourth path is connected with the drain electrode of the NMOS tube Q7 through the current limiting resistor R8, and the fifth path is connected with the drain electrode of the PMOS tube Q6 through the current limiting resistor R7; the positive electrode of the voltage stabilizing diode D3 is divided into four paths, one path is connected with the grid electrode of the PMOS tube Q11, the second path is connected with the drain electrode of the PMOS tube Q10, the third path is connected with the drain electrode of the NMOS tube Q4 through the current limiting resistor R5, and the fourth path is connected with the drain electrode of the NMOS tube Q5 through the current limiting resistor R6; the sources of the NMOS tube Q4, the NMOS tube Q5, the NMOS tube Q6 and the NMOS tube Q7 are all grounded, the gates of the four are respectively connected with an input signal phi A, an input signal phi B, an input signal phi C and an input signal phi D, the VDDH in the figure 1 is a high-voltage power supply connected with the cathode of the zener diode D3, the voltage range of the power supply is 8-20V, the VDDL in the figure 1 is a low-voltage power supply, the voltage range of the power supply is 1.8-5.5V, and the OUT in the figure 1 is a node between the NMOS tube Q9 and the PMOS tube Q8 and is an output end point.

The high-voltage driving circuit comprises an inverter U1 and an inverter U2, wherein the input end of the inverter U1 is connected with an input signal phi A, and the output end of the inverter U1 is connected with the grid electrode of the NMOS tube Q9 through the inverter U2. The high-voltage driving circuit adopts an inverter structure, a preceding-stage circuit drives a thin-gate NMOS transistor Q9 and a thin-gate PMOS transistor Q8 separately, the driving is mainly pulse-assisted fast latch driving, and the structure diagram of the circuit is shown in figure 1. The NMOS tube Q9 and the PMOS tube Q8 are main driving devices, output drive follow-up power MOS tubes, the PMOS tube Q8 is a high-voltage-resistant thin-grid PMOS tube, the NMOS tube Q9 is a high-voltage-resistant thin-grid NMOS tube, and an inverter structure is formed, a traditional low-voltage inverter can be directly driven by a preceding-stage inverter, but the thin-grid device in a high-voltage power supply system is small in on-resistance, although the drain voltage resistance is high, the grid voltage resistance is generally not more than 6V, the voltage difference from the NMOS grid to the ground cannot exceed 6V, the grid of the high-voltage NMOS tube Q9 can be driven by the low-voltage inverter, and the low-voltage inverter is powered by a low-voltage power supply, such as 5V, therefore, in the high-voltage driving circuit, two different high-low voltage driving circuits are specially used for independently driving the PMOS tube Q8 and the NMOS tube Q9.

The NMOS transistors Q4-Q7, the PMOS transistor Q10 and the PMOS transistor Q11 form a latch structure, and the input signal phi C is an inverse signal of the input signal phi A; the input signal phi B and the input signal phi D are respectively rising edge pulse signals of the input signal phi A and the input signal phi C; when the gate input signal phia of the NMOS transistor Q4 rises from the level to the high level, the NMOS transistor Q4 is turned on, the gate of the NMOS transistor Q5 generates an input signal phib, and is turned on during the pulse, because the current-limiting resistor R6 is much smaller than the current-limiting resistor R5, the on current in the NMOS transistor Q5 is much larger than that in the NMOS transistor Q4, the NMOS transistor Q6 and the NMOS transistor Q7 are in the off state, so that the gate of the NMOS transistor Q11 is pulled down quickly, because of the limitation of the zener diode D3, the gate voltage of the NMOS transistor Q11, that is, the drain voltage of the PMOS transistor Q10 is pulled down to 5-6V lower than the power supply (the accessed high voltage power supply VDDH), and at the same time, the gate of the PMOS transistor Q10 is also pulled up quickly to the power supply, so the drive-stage PMOS transistor Q8 is turned off, the gate pulse signal of the NMOS transistor Q5 disappears, the transistor is turned off, the current in the zener diode D3 is the small NMOS transistor Q5, and maintains the on state of the NMOS transistor Q5842, the PMOS transistor 57342, the gate of the PMOS transistor Q8 is high, so that the PMOS transistor Q8 is maintained in an off state; similarly, when the gate input signal Φ C of the NMOS transistor Q6 rises from a high level to a high level, the NMOS transistor Q6 is turned on, the gate of the NMOS transistor Q7 generates an input signal Φ D, and is turned on during the pulse, since the current-limiting resistor R8 is much smaller than the current-limiting resistor R7, the on-current in the NMOS transistor Q7 is much larger than that of the NMOS transistor Q6, the NMOS transistor Q4 and the NMOS transistor Q5 are in an off state, so that the gate of the PMOS transistor Q10 is pulled down quickly, due to the limitation of the zener diode 10, the gate voltage of the PMOS transistor Q10, that is, the drain voltage of the NMOS transistor Q11 is pulled down 5 to 6V below the power supply, and meanwhile, the gate of the NMOS transistor Q11 is also pulled up quickly to the power supply, so the driver stage PMOS transistor Q8 is turned on, the gate pulse signal of the NMOS transistor Q7 disappears, the transistor is turned off, the current in the zener diode D4 is a small current in the NMOS transistor Q6, the PMOS transistor Q5 is maintained in an on state, the NMOS transistor Q11 is in an off state, the gate pulse signal of the PMOS transistor Q8 is in a low level, therefore, the PMOS tube Q8 is kept in a turn-off state, and the voltage stabilizing diode D3, the voltage stabilizing diode D4, the NMOS tube Q5, the NMOS tube Q6, the NMOS tube Q4, the NMOS tube Q7, the PMOS tube Q10, the PMOS tube Q11, the current limiting resistor R5, the current limiting resistor R6, the current limiting resistor R7 and the current limiting resistor R8 form a pulse auxiliary fast latch to drive the thin-gate PMOS tube Q8.

The above embodiments do not limit the scope of the present invention, and those skilled in the art can make equivalent modifications and variations without departing from the overall concept of the present invention.

Claims

1. A high-voltage driving circuit of a high-power field effect transistor is characterized by comprising a voltage stabilizing diode D3, a voltage stabilizing diode D4, a PMOS (P-channel metal oxide semiconductor) transistor Q8, an NMOS (N-channel metal oxide semiconductor) transistor Q9, an NMOS (N-channel metal oxide semiconductor) transistor Q5, an NMOS (N-channel metal oxide semiconductor) transistor Q6, an NMOS (N-channel metal oxide semiconductor) transistor Q4, an NMOS (N-channel metal oxide semiconductor) transistor Q7, a PMOS transistor Q10, a PMOS transistor Q11, a current limiting resistor R5, a current limiting resistor R6, a current limiting resistor R7 and a current limiting resistor R8; the drain electrode of the PMOS tube Q8 is connected with the drain electrode of the NMOS tube Q9, the source electrode of the PMOS tube Q8 is divided into four paths, one path is connected with the negative electrode of the voltage stabilizing diode D4, the second path is connected with the source electrode of the PMOS tube Q11, the third path is connected with the source electrode of the PMOS tube Q10, and the fourth path is connected with the negative electrode of the voltage stabilizing diode D3; the grid electrode of the PMOS tube Q8 is divided into five paths, one path is connected with the anode of the voltage stabilizing diode D4, the second path is connected with the drain electrode of the PMOS tube Q11, the third path is connected with the grid electrode of the PMOS tube Q10, the fourth path is connected with the drain electrode of the NMOS tube Q7 through the current limiting resistor R8, and the fifth path is connected with the drain electrode of the NMOS tube Q6 through the current limiting resistor R7; the positive electrode of the voltage stabilizing diode D3 is divided into four paths, one path is connected with the grid electrode of the PMOS tube Q11, the second path is connected with the drain electrode of the PMOS tube Q10, the third path is connected with the drain electrode of the NMOS tube Q4 through the current limiting resistor R5, and the fourth path is connected with the drain electrode of the NMOS tube Q5 through the current limiting resistor R6; the source electrodes of the NMOS tube Q4, the NMOS tube Q5, the NMOS tube Q6 and the NMOS tube Q7 are all grounded, and the grid electrodes of the four are respectively connected with an input signal phi A, an input signal phi B, an input signal phi C and an input signal phi D.

2. The high voltage driving circuit according to claim 1, wherein the input signal Φ C is an inverted signal of the input signal Φ a; the input signal phi B and the input signal phi D are rising edge pulse signals of the input signal phi A and the input signal phi C respectively.

3. The high voltage driving circuit as claimed in claim 1, wherein the resistance of the current limiting resistor R6 is smaller than the resistance of the current limiting resistor R5, and the resistance of the current limiting resistor R8 is smaller than the resistance of the current limiting resistor R7.

4. The high-voltage driving circuit as claimed in claim 1, comprising an inverter U1 and an inverter U2, wherein an input terminal of the inverter U1 receives the input signal Φ a, and an output terminal of the inverter U1 receives the gate of the NMOS transistor Q9 via the inverter U2.