CN112514222A - Demodulation circuit, pulse generation circuit and isolation drive circuit for isolation drive circuit - Google Patents
Demodulation circuit, pulse generation circuit and isolation drive circuit for isolation drive circuit Download PDFInfo
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- CN112514222A CN112514222A CN202080004337.3A CN202080004337A CN112514222A CN 112514222 A CN112514222 A CN 112514222A CN 202080004337 A CN202080004337 A CN 202080004337A CN 112514222 A CN112514222 A CN 112514222A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
- H03K9/08—Demodulating pulses which have been modulated with a continuously-variable signal of duration- or width-mudulated pulses or of duty-cycle modulated pulses
Abstract
The embodiment of the specification provides a demodulation circuit, a pulse generation circuit and an isolation drive circuit for an isolation drive circuit, wherein an input narrow pulse signal is demodulated through the demodulation circuit connected with a drive MOS (metal oxide semiconductor) tube to obtain a gate drive voltage of the drive MOS tube, and the gate drive voltage is presented and maintained as a first voltage when a first pulse jump edge of the narrow pulse signal arrives until a second pulse jump edge of the narrow pulse signal arrives; and presenting and maintaining the second voltage when the second pulse transition edge of the narrow pulse signal arrives until the first pulse transition edge of the narrow pulse signal arrives. When the duty ratio of a grid driving signal for driving the MOS tube is changed, only the interval between the positive pulse and the negative pulse of the narrow pulse signal needs to be changed, and the volt-second balance is not influenced. Therefore, when the duty ratio of the grid driving signal for driving the MOS tube is changed in a large range, pulse transmission abnormity can not be caused.
Description
Technical Field
The present disclosure relates to the field of driving circuit technology, and in particular, to a demodulation circuit, a pulse generation circuit, and an isolation driving circuit for an isolation driving circuit.
Background
At present, an isolation gate driving scheme based on direct drive of a gate driving transformer generally comprises a driving signal buffer, a pulse transformer and a gate spike suppression network. The duty ratio driving method is limited to the volt-second capacity of a driving pulse transformer, and when the duty ratio variation range is large, pulse transmission abnormality is caused, so that the duty ratio driving in a large range cannot be realized.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a demodulation circuit, a pulse generation circuit, and an isolation driving circuit for an isolation driving circuit, so as to solve the technical problem in the related art that a dynamic response with a large duty ratio variation cannot be achieved.
According to a first aspect of the embodiments of the present disclosure, a demodulation circuit for isolating a driving circuit is provided, where the demodulation circuit is connected to a driving MOS transistor and is configured to demodulate an input narrow pulse signal, so that a gate voltage of the driving MOS transistor periodically changes in the following manner:
presenting and maintaining a first voltage at an arrival of a first pulse transition edge of the narrow pulse signal until an arrival of a second pulse transition edge of the narrow pulse signal;
and presenting and maintaining the second voltage when the second pulse transition edge of the narrow pulse signal arrives until the first pulse transition edge of the narrow pulse signal arrives.
According to a second aspect of the embodiments of the present disclosure, a pulse generation circuit is provided, which is configured to generate a narrow pulse signal for modulating a gate voltage of a driving MOS transistor; the gate voltage of the driving MOS tube presents and keeps at the first voltage when a first pulse transition edge of the narrow pulse signal arrives until a second pulse transition edge of the narrow pulse signal arrives, and presents and keeps at the second voltage when the second pulse transition edge of the narrow pulse signal arrives until the first pulse transition edge of the narrow pulse signal arrives.
According to a third aspect of the embodiments of the present disclosure, an isolation driving circuit is provided, which includes the demodulation circuit of any of the embodiments.
By applying the scheme of the embodiment of the specification, an input narrow pulse signal is demodulated through a demodulation circuit connected with a drive MOS tube to obtain a gate drive voltage of the drive MOS tube, and the first voltage is presented and maintained when a first pulse jump edge of the narrow pulse signal arrives until a second pulse jump edge of the narrow pulse signal arrives; and presenting and maintaining the second voltage when the second pulse transition edge of the narrow pulse signal arrives until the first pulse transition edge of the narrow pulse signal arrives. When the duty ratio of a grid driving signal for driving the MOS tube is changed, only the interval between the positive pulse and the negative pulse of the narrow pulse signal needs to be changed, and the volt-second balance is not influenced. Therefore, when the duty ratio of the grid driving signal for driving the MOS tube is changed in a large range, the pulse transmission abnormality can not be caused.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1A is a timing diagram of a narrow pulse signal and a gate voltage according to an embodiment of the disclosure.
Fig. 1B is a timing diagram of a narrow pulse signal and a gate voltage according to another embodiment of the disclosure.
Fig. 2A is a circuit diagram of a demodulation circuit for isolating a driver circuit according to an embodiment of the disclosure.
Fig. 2B is a circuit diagram of a demodulation circuit for an isolated driver circuit according to another embodiment of the present disclosure.
Fig. 2C is a circuit diagram of a demodulation circuit for an isolated driver circuit according to yet another embodiment of the present disclosure.
Fig. 2D is a circuit diagram of a demodulation circuit for an isolated driver circuit according to yet another embodiment of the present disclosure.
Fig. 3A is a circuit diagram of an isolated driving circuit according to an embodiment of the disclosure.
Fig. 3B is a circuit diagram of an isolated drive circuit according to another embodiment of the present disclosure.
Fig. 3C is a circuit diagram of an isolated drive circuit according to yet another embodiment of the present disclosure.
Fig. 3D is a circuit diagram of an isolated drive circuit of yet another embodiment of the present disclosure.
Fig. 4 is a schematic view of a movable platform of an embodiment of the disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the specification, as detailed in the appended claims.
The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present specification. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
The current isolated gate drive scheme based on direct drive of a gate drive transformer generally comprises a drive signal buffer, a pulse transformer and a gate spike suppression network (generally comprising a resistor and a voltage stabilizing diode). The limitation of volt-second capacity of the drive pulse transformer does not allow for a wide range of arbitrary duty cycle drives. When the duty ratio deviates from 50%, a PWM (Pulse Width Modulation) driving signal output from the driving transformer may rise or fall due to a change in the dc component of the driving signal caused by a change in the duty ratio. When the driving signal floats up or sinks to cause the switch tube to be insufficiently conducted or more reliably turned off (the grid electrode of the switch tube is generally required to have enough negative pressure to ensure the reliability of turn-off in high-power occasions), the loss and even damage of the switch tube are caused. In addition, the gate drive transformer is generally large in size in order to achieve a certain volt-second capacity in the case of low-frequency driving.
The isolation grid driving technology based on the optical coupler/novel digital isolator generally comprises the optical coupler or the digital isolator which is used as an isolation link, a corresponding isolation power supply and a driving buffer on the grid side. Although this scheme can achieve any duty cycle drive, it must be used with an isolated power supply, adding to system complexity and cost. The transmission delay of the optical coupler is larger and the speed is slow; new digital isolators are typically very expensive. Meanwhile, the isolation power supply of the scheme not only needs to realize direct current isolation, but also needs to realize high-frequency alternating current isolation. Since the switching tube side usually has very large du/dt (u denotes voltage and t denotes time), the higher harmonics are rich. If a switching power supply is used, the parasitic capacitance between the primary winding and the secondary winding of an isolation transformer in the isolation power supply is required to be small; if a power frequency transformer is used, since the parasitic capacitance between the primary and secondary of the power frequency transformer itself is very large, a blocking element must be matched to isolate the high-frequency component. This is very disadvantageous for the complexity and cost optimization and reliability optimization of the system.
In summary, the existing isolated gate driving technology cannot consider both the dynamic response of the large-range duty ratio change and the low cost.
Based on this, the disclosed embodiments provide a demodulation circuit and an isolation drive circuit for an isolation drive circuit. In some embodiments, the present disclosure provides a demodulation circuit for isolating a driving circuit, where the demodulation circuit is connected to a driving MOS transistor and is configured to demodulate an input narrow pulse signal, so that a gate voltage of the driving MOS transistor periodically varies in the following manner: presenting and maintaining a first voltage at an arrival of a first pulse transition edge of the narrow pulse signal until an arrival of a second pulse transition edge of the narrow pulse signal; and presenting and maintaining the second voltage when the second pulse transition edge of the narrow pulse signal arrives until the first pulse transition edge of the narrow pulse signal arrives.
The narrow pulse signal is a signal with an extremely narrow pulse width, and compared with a conventional mode of adopting a PWM signal as a gate drive signal, the pulse width of the narrow pulse signal is much smaller than the width of the PWM signal. In some embodiments, the positive and negative pulse widths of the narrow pulse signal are equal.
In some embodiments, one of the first and second voltages is a high voltage and the other is a low voltage, e.g., the first voltage is a positive voltage and the second voltage is a negative voltage; for another example, the first voltage is a positive voltage and the second voltage is a zero voltage. Or for example, the first voltage is a negative voltage and the second voltage is a positive voltage; for another example, the first voltage is a zero voltage and the second voltage is a positive voltage. As shown in fig. 1A and 1B, are timing diagrams of the narrow pulse signal and the gate voltage signal of the embodiments of the present disclosure. Wherein, x (t) represents a narrow pulse signal, and y (t) represents a grid voltage of the driving MOS tube. As shown in fig. 1A, the first voltage is a positive voltage, and the second voltage is a negative voltage; as shown in fig. 1B, the first voltage is a positive voltage, and the second voltage is a zero voltage. In some embodiments, the first pulse transition edge may be a rising edge of a positive pulse and the second pulse transition edge may be a falling edge of a negative pulse.
By applying the scheme of the embodiment of the specification, the input narrow pulse signal is demodulated through the demodulation circuit connected with the driving MOS tube, so that the driving signal for driving the grid voltage of the driving MOS tube is obtained. When a first pulse transition edge of the narrow pulse signal arrives, the gate voltage of the driving MOS tube is presented and maintained as a first voltage by the driving signal until a second pulse transition edge of the narrow pulse signal arrives; when the second pulse transition edge of the narrow pulse signal arrives, the gate voltage of the driving MOS tube is presented and kept at the second voltage by the driving signal until the first pulse transition edge of the narrow pulse signal arrives.
When the duty ratio of the driving signal is changed, only the time interval between the positive pulse and the negative pulse of the narrow pulse signal needs to be changed, and the volt-second balance is not influenced. Therefore, when the duty ratio of the driving signal is changed in a large range, the pulse transmission abnormality is not caused. For example, when it is desired to increase the duty cycle, the time interval t1 between positive and negative pulses of the narrow pulse signal may be increased and/or the time interval t2 between negative and positive pulses of the narrow pulse signal may be decreased; conversely, when a decrease in duty cycle is desired, t1 may be decreased and/or t2 may be increased.
The narrow pulse signal of the embodiment of the present disclosure may convert an original PWM signal into a narrow pulse signal that is inverted at an edge thereof in a digital or analog manner, and a pulse width of the narrow pulse signal may be in the order of nanoseconds (ns), and in different application scenarios, the power level of a power device (e.g., a MOS transistor) and the speed level of turning on and off the power level may be reduced or increased. The requirement of a high-power application scene on the switching speed of the MOS tube is low, and the pulse width of the narrow pulse signal can be in the magnitude of hundreds of nanoseconds to microseconds; the switching speed of the MOS tube is high in the low-power application scene, and the pulse width of the narrow pulse signal can be between a few nanoseconds and a few tens of nanoseconds. In the case of generating the narrow pulse Signal in a Digital manner, an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processing), or an MCU (micro control Unit) may be used to modulate the original PWM Signal, so as to obtain the narrow pulse Signal. For some PWM control scenarios, which are more composed of analog circuits, it is difficult to directly generate the narrow pulse signal, which can be generated based on some circuits (e.g., RC differentiating circuit). And the demodulation circuit demodulates the narrow pulse signal so as to restore the original PWM signal to realize the control of the grid voltage of the driving MOS tube.
In some embodiments, the demodulation circuit is connected between a secondary winding of a pulse transformer and the drive MOS transistor; the demodulation circuit includes: the first switch unit is connected between the driving MOS tubes; when the positive pulse rising edge of the narrow pulse signal arrives, the first switch unit is conducted, so that the grid voltage of the driving MOS tube is presented and maintained as the first voltage until the negative pulse falling edge of the narrow pulse signal arrives; when the negative pulse falling edge of the narrow pulse signal comes, the first switch unit is turned off, and the grid of the driving MOS tube presents and keeps the second voltage until the positive pulse rising edge of the narrow pulse signal comes. The isolation driving circuit is realized by adopting the pulse transformer, and the demodulation circuit disclosed by the embodiment of the disclosure is used in the isolation driving circuit realized by the pulse transformer, so that on one hand, the cost is low, and on the other hand, the problem that any duty ratio cannot be realized by the pulse transformer in the traditional technology is solved.
Fig. 2A is a circuit diagram of a demodulation circuit according to an embodiment of the disclosure. In this embodiment, the first switching unit in the demodulation circuit includes: a first MOS transistor Q11; the source of the first MOS transistor Q11 is connected to the positive tap of the secondary winding of the pulse transformer T1, the drain of the first MOS transistor Q11 is connected to the gate of the driving MOS transistor Q1, and the gate of the first MOS transistor Q11 is connected to the negative tap of the secondary winding of the pulse transformer T1 and the source of the driving MOS transistor Q1, respectively.
The first MOS transistor Q11 may be a signal field effect transistor. Wherein, the signal field effect transistor is a field effect transistor with smaller working voltage. According to the embodiment of the disclosure, a body diode of a signal field effect transistor is used as a grid charging diode, and a narrow pulse signal can be demodulated through one MOS transistor and reduced into a PWM signal. For some low-voltage medium and small power occasions where negative voltage turn-off is not required, such as an electric bicycle driver, the scheme of the embodiment can be adopted to realize gate driving. The first MOS transistor Q11 of this embodiment may be an N-channel MOS transistor or a P-channel MOS transistor, and in the embodiment shown in fig. 2A, the first MOS transistor Q11 is an N-channel MOS transistor.
At the positive pulse rising edge of the narrow pulse signal, the first MOS transistor Q11 is turned on, and the gate of the driving MOS transistor Q1 presents a positive voltage until the negative pulse falling edge of the narrow pulse signal arrives. At the negative pulse falling edge of the narrow pulse signal, the first MOS transistor Q11 is turned off, and the gate of the driving MOS transistor Q1 assumes a zero voltage until the positive pulse rising edge of the narrow pulse signal arrives. This is repeated.
In practical applications, the source of the first MOS transistor Q11 may be connected to the negative tap of the secondary winding of the pulse transformer T1, the drain of the first MOS transistor Q11 may be connected to the gate of the driving MOS transistor Q1, and the gate of the first MOS transistor Q11 may be connected to the positive tap of the secondary winding of the pulse transformer T1 and the source of the driving MOS transistor Q1, respectively. In this case, at the falling edge of the negative pulse of the narrow pulse signal, the first MOS transistor Q11 is turned on, and the gate of the driving MOS transistor Q1 assumes a positive voltage until the rising edge of the positive pulse of the narrow pulse signal arrives. At the rising edge of the positive pulse of the narrow pulse signal, the first MOS transistor Q11 is turned off, and the gate of the driving MOS transistor Q1 assumes a zero voltage until the falling edge of the negative pulse of the narrow pulse signal arrives. This is repeated.
In some embodiments, the demodulation circuit further comprises a first voltage division unit connected to the first switching unit; the first voltage division unit is used for dividing the voltage on the first switch unit. In an embodiment where the first switch unit includes a first MOS transistor Q11, the first voltage dividing unit is connected to the first MOS transistor Q11, and is configured to divide the voltage across the first MOS transistor Q11.
Wherein the first voltage division unit includes: a first resistor R11 and a second resistor R12; the first resistor R11 is connected between the grid and the source of the first MOS transistor Q11, and the second resistor R12 is connected between the grid of the first MOS transistor Q11 and the negative tap of the secondary winding of the pulse transformer T1.
In this embodiment, the gate voltage of the first MOS transistor Q11 can be written as:
wherein R11 and R12 are the resistance of the first resistor R11 and the resistance of the second resistor R12, respectively, UgFor the output voltage of the secondary winding of the pulse transformer T1, UTIs the gate voltage of the first MOS transistor Q11. When the output voltage of the secondary winding of the pulse transformer T1 is greater than the working voltage of the first MOS tube Q11, the voltage on the first MOS tube Q11 is divided by the first voltage dividing unit, so that the first MOS tube Q11 is prevented from being damaged due to overlarge voltage. Further, the first voltage division unit further includes: and the first capacitor C11 is connected with the second resistor R12 in parallel.
The first voltage division unit of this embodiment can not only realize carrying out the effect of partial pressure to the voltage on the first MOS pipe Q11, can also filter the direct current interference signal in the circuit through first electric capacity C11, improves the interference immunity of circuit.
In some embodiments, the demodulation circuit comprises: the first switch unit is connected with the driving MOS tube; the second switch unit is connected with the first switch unit in parallel, a first diode is connected between the first switch unit and the driving MOS tube, and a second diode is connected between the second switch unit and the driving MOS tube, wherein the cathode of the first diode is connected with the first switch unit, and the anode of the second diode is connected with the second switch unit; when a first pulse transition edge of the narrow pulse signal arrives, the first switch unit is switched on, the second switch unit is switched off, and the gate capacitor of the driving MOS tube is charged through the first diode so as to present and maintain the first voltage; when a second pulse transition edge of the narrow pulse signal arrives, the first switch unit is turned off, the second switch unit is turned on, and the gate capacitor of the driving MOS tube discharges through the second diode, so that the second voltage is presented and maintained.
The first switch unit in this embodiment may be a transistor or an MOS transistor, and the second switch unit may also be a transistor or an MOS transistor. The following description will be made by taking two cases, i.e., the first switch unit and the second switch unit are both transistors, and the first switch unit and the second switch unit are both MOS transistors as examples. In practical applications, when one of the first switch unit and the second switch unit is an MOS transistor and the other is a triode, the operation mode is similar to that when both the first switch unit and the second switch unit are triodes or that when both the first switch unit and the second switch unit are MOS transistors, which is not described herein again.
Fig. 2B is a circuit diagram of a demodulation circuit according to another embodiment of the present disclosure. In this embodiment, the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS transistor; the first switching unit in the demodulation circuit includes: a first transistor Q21; the emitter of the first triode Q21 is connected with the positive tap of the secondary winding of the pulse transformer T2, the collector is connected with the cathode of the first diode D11, and the base is connected with the negative tap of the secondary winding of the pulse transformer T2 and the source of the driving MOS transistor Q2, respectively. In this embodiment, the second switching unit in the demodulation circuit includes: a second transistor Q22; an emitter of the second triode Q22 is connected with a positive tap of the secondary winding of the pulse transformer T2, a collector is connected with an anode of the second diode D22, and a base is respectively connected with a negative tap of the secondary winding of the pulse transformer T2 and a source of the driving MOS transistor Q2.
The first transistor Q21 may be a PNP transistor, and the second transistor Q22 may be an NPN transistor. The embodiment of the disclosure demodulates the narrow pulse signal through the two triodes and the two diodes, and reduces the narrow pulse signal into the PWM signal, and the obtained PWM signal includes both positive voltage and negative voltage.
At the positive pulse rising edge of the narrow pulse signal, the first transistor Q21 is turned on, the second transistor Q22 is turned off, the positive pulse charges the gate capacitor of the driving MOS transistor Q2 through the first diode D21, and the gate of the driving MOS transistor Q2 assumes a positive voltage until the negative pulse falling edge of the narrow pulse signal arrives. At the negative pulse falling edge of the narrow pulse signal, the second transistor Q22 is turned on, the first transistor Q21 is turned off, the gate capacitor of the driving MOS transistor Q2 is discharged through the second diode D22, and the gate of the driving MOS transistor Q2 assumes a negative voltage until the positive pulse rising edge of the narrow pulse signal arrives. This is repeated.
In some embodiments, the demodulation circuit further comprises: the second voltage division unit is connected with the first triode Q21, and/or the third voltage division unit is connected with the second triode Q22; the second voltage division unit is used for dividing the voltage on the first triode Q21, and the third voltage division unit is used for dividing the voltage on the second triode Q22.
In some embodiments, the second voltage division unit includes: a third resistor R21 and a fourth resistor R22; the third resistor R21 is connected between the base and emitter of the first transistor Q21, and the fourth resistor R22 is connected between the base of the first transistor Q21 and the negative tap of the secondary winding of the pulse transformer T2. Further, the second voltage division unit further includes: and the second capacitor C21 is connected with the fourth resistor R22 in parallel.
In other embodiments, the third partial pressure unit includes: a fifth resistor R23 and a sixth resistor R24; the fifth resistor R23 is connected between the base and emitter of the second transistor Q22, and the sixth resistor R24 is connected between the base of the second transistor Q22 and the negative tap of the secondary winding of the pulse transformer T2. Further, the third partial pressure unit further includes: and the third capacitor C22 is connected with the sixth resistor R24 in parallel.
The partial pressure mode of the second partial pressure unit and the third partial pressure unit is similar to the partial pressure mode of the first partial pressure unit, and the detailed description is omitted here.
Fig. 2C is a circuit diagram of a demodulation circuit according to still another embodiment of the present disclosure. In this embodiment, the demodulation circuit is connected between the secondary winding of the pulse transformer and the driving MOS transistor; the first switching unit in the demodulation circuit includes: a second MOS transistor Q31; the source of the second MOS transistor Q31 is connected to the positive tap of the secondary winding of the pulse transformer T3, the drain of the second MOS transistor Q31 is connected to the cathode of the first diode D31, and the gate of the second MOS transistor Q31 is connected to the negative tap of the secondary winding of the pulse transformer T3 and the source of the driving MOS transistor Q3, respectively. In this embodiment, the second switching unit in the demodulation circuit includes: a third MOS transistor Q32; the source of the third MOS transistor Q32 is connected to the positive tap of the secondary winding of the pulse transformer T3, the drain of the third MOS transistor Q32 is connected to the anode of the second diode D32, and the gate of the third MOS transistor Q32 is connected to the negative tap of the secondary winding of the pulse transformer T3 and the source of the driving MOS transistor Q3, respectively.
The second MOS transistor Q31 may be a P-channel MOS transistor, and the third MOS transistor Q32 may be an N-channel MOS transistor. The second MOS transistor Q31 and the third MOS transistor Q32 may be power fets, i.e., fets with a higher operating voltage. The embodiment of the disclosure demodulates the narrow pulse signal through the two MOS transistors and the two diodes, and reduces the narrow pulse signal into the PWM signal, and the obtained PWM signal includes both a positive voltage and a negative voltage.
At the positive pulse rising edge of the narrow pulse signal, the second MOS transistor Q31 is turned on, the third MOS transistor Q32 is turned off, the positive pulse charges the gate capacitor of the driving MOS transistor Q3 through the first diode D31, and the gate of the driving MOS transistor Q3 assumes a positive voltage until the negative pulse falling edge of the narrow pulse signal arrives. At the negative pulse falling edge of the narrow pulse signal, the second MOS transistor Q31 is turned off, the third MOS transistor Q32 is turned on, the gate capacitor of the driving MOS transistor Q3 is discharged through the second diode D32, and the gate of the driving MOS transistor Q3 assumes a negative voltage until the positive pulse rising edge of the narrow pulse signal arrives. This is repeated.
In some embodiments, the demodulation circuit further comprises: a fourth voltage division unit connected with the second MOS transistor Q31, and/or a fifth voltage division unit connected with the third MOS transistor Q32; the fourth voltage division unit is used for dividing the voltage on the second MOS tube Q31, and the fifth voltage division unit is used for dividing the voltage on the third MOS tube Q32.
In some embodiments, the fourth voltage dividing unit includes: a seventh resistor R31 and an eighth resistor R32; the seventh resistor R31 is connected between the gate and the source of the second MOS transistor Q31, and the eighth resistor R32 is connected between the gate of the second MOS transistor Q31 and the negative tap of the secondary winding of the pulse transformer T3. Further, the fourth voltage dividing unit further includes: and the fourth capacitor C31 is connected with the eighth resistor T32 in parallel.
In other embodiments, the fifth voltage division unit includes: a ninth resistor R33 and a tenth resistor R34; the ninth resistor R33 is connected between the gate and the source of the third MOS transistor Q32, and the tenth resistor R34 is connected between the gate of the third MOS transistor Q32 and the negative tap of the secondary winding of the pulse transformer T3. Further, the fifth voltage division unit further includes: a fifth capacitor C32 connected in parallel with the tenth resistor R34.
The partial pressure mode of fourth partial pressure unit and fifth partial pressure unit is similar with the partial pressure mode of first partial pressure unit, and the repeated description is omitted here.
Fig. 2D is a circuit diagram of a demodulation circuit according to another embodiment of the present disclosure. The demodulation circuit is connected between a secondary winding of the pulse transformer and the drive MOS tube; the first switching unit includes: a third triode Q41, an eleventh resistor R41 and a third diode D41; the anode of the third diode D41 is connected to the positive tap of the secondary winding of the pulse transformer T4, and the cathode is connected to the gate of the driving MOS transistor Q4; a collector of the third triode Q41 is connected with a cathode of the third diode D41, emitters are respectively connected with a zero tap of a secondary winding of the pulse transformer T4 and a source of the driving MOS transistor Q4, and a base is connected with a negative tap of a secondary winding of the pulse transformer T4 through the eleventh resistor R41; when the narrow pulse signal is at a positive level, the gate capacitance of the driving MOS transistor Q4 is charged through the third diode D41, and the gate voltage of the driving MOS transistor Q4 assumes the first voltage; when the narrow pulse signal is at a negative level, the gate capacitance of the driving MOS transistor Q4 is discharged through the third transistor D41, and the gate voltage of the driving MOS transistor Q4 exhibits the second voltage.
The third transistor Q41 may be an NPN transistor. The present embodiment may be applied to situations where negative pressure shut-off is not required. At the positive pulse rising edge of the narrow pulse signal, the third diode D41 and the third transistor Q41 are turned on, and the gate of the driving MOS transistor Q4 presents a positive voltage until the negative pulse falling edge of the narrow pulse signal arrives. At the negative pulse falling edge of the narrow pulse signal, the third diode D41 and the third transistor Q41 are turned off, and the gate of the driving MOS transistor Q4 presents zero voltage until the positive pulse rising edge of the narrow pulse signal arrives. This is repeated. The third transistor Q41 in this embodiment may also be replaced by an N-channel MOS transistor, wherein a gate of the N-channel MOS transistor is connected to the negative tap of the secondary winding of the pulse transformer T4 through the eleventh resistor R41, a drain of the N-channel MOS transistor is connected to the cathode of the third diode D41, and a source of the N-channel MOS transistor is connected to the zero tap of the secondary winding of the pulse transformer T4 and the source of the driving MOS transistor Q4, respectively.
The embodiment of the present disclosure further provides a pulse generating circuit, where the pulse generating circuit is configured to generate a narrow pulse signal for modulating a gate voltage of a driving MOS transistor; the gate voltage of the driving MOS tube presents and keeps at the first voltage when a first pulse transition edge of the narrow pulse signal arrives until a second pulse transition edge of the narrow pulse signal arrives, and presents and keeps at the second voltage when the second pulse transition edge of the narrow pulse signal arrives until the first pulse transition edge of the narrow pulse signal arrives.
In some embodiments, the pulse generation circuit generates the narrow pulse signal in an analog manner or a digital manner.
In some embodiments, where the pulse generation circuitry generates the narrow pulse signal in an analog manner, the pulse generation circuitry includes modulation circuitry that modulates a PWM signal to generate the narrow pulse signal. Wherein the modulation circuit may be an RC differentiation circuit. In other embodiments, where the pulse generation circuitry generates the narrow pulse signal digitally, the pulse generation circuitry includes a digital chip for generating the narrow pulse signal. The digital chip can be an FPGA, a DSP or an MCU.
In some embodiments, the first pulse transition edge may be a rising edge of a positive pulse and the second pulse transition edge may be a falling edge of a negative pulse.
The embodiment of the disclosure further provides an isolation driving circuit, which includes the demodulation circuit described in any of the above embodiments. In some embodiments, the isolation driving circuit further comprises the pulse generating circuit described in any of the above embodiments. As shown in fig. 3A to 3D, each of them is an isolation driving circuit including the demodulation circuit of any one of fig. 2A to 2D. In some embodiments, the isolated drive circuit is for driving a motor.
In some embodiments, as shown in fig. 4, embodiments of the present disclosure also provide a movable platform comprising: a body 401; the motor 402 is arranged in the machine body 401, and the motor 402 is used for providing power for the movable platform; and the isolation driving circuit 403 according to any embodiment, configured to drive the motor 402 to rotate. The embodiment of the isolation driving circuit 403 in the movable platform is described in detail in the foregoing embodiments, and will not be described herein again.
In some embodiments, the movable platform may be a drone, an unmanned vehicle, a pan-tilt, or the like. Applications of embodiments of the present disclosure include, but are not limited to, any of: in the application occasions of consumer electronics, the power supply can be used for realizing high power of a commercial desktop computer switching power supply with high reliability, a notebook computer adapter with higher power, a quick-charging mobile phone charger with higher power and the like; in the industrial application occasions requiring high voltage, high Power and high reliability, the device can be used for realizing a frequency converter, an industrial UPS (uninterruptible Power Supply), an inverter, an induction heating excitation Power Supply, an arc welding equipment Power Supply, an ultrasonic welding machine, an ultrasonic cleaning machine and CO2(carbon dioxide) laser high voltage driving power supply, Nd: YAG (yttrium aluminum garnet crystal) pulse laser pulse xenon lamp excitation power supply and the like; in scientific research application occasions, the device can be used for realizing a weather radar system motor driver, a radar system pulse power supply and the like working in severe environment; in medical application occasions, the device can be used for realizing a high-reliability UPS system of a medical system, an X-ray tube driving power supply and the like; in the application occasions of automobiles, the system can be used for realizing the occasions of electric automobile motor drivers, electric automobile chargers, electric automobile battery pack management systems and the like with higher voltage.
The various technical features in the above embodiments can be arbitrarily combined, so long as there is no conflict or contradiction between the combinations of the features, but the combination is limited by the space and is not described one by one, and therefore, any combination of the various technical features in the above embodiments also falls within the scope disclosed in the present specification.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
The above description is only exemplary of the present disclosure and should not be taken as limiting the disclosure, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (32)
1. The demodulation circuit for the isolation driving circuit is characterized in that the demodulation circuit is connected with a driving MOS tube and is used for demodulating an input narrow pulse signal so that the grid voltage of the driving MOS tube periodically changes according to the following modes:
presenting and maintaining a first voltage at an arrival of a first pulse transition edge of the narrow pulse signal until an arrival of a second pulse transition edge of the narrow pulse signal;
and presenting and maintaining the second voltage when the second pulse transition edge of the narrow pulse signal arrives until the first pulse transition edge of the narrow pulse signal arrives.
2. The demodulation circuit according to claim 1, wherein the demodulation circuit comprises:
the first switch unit is connected with the driving MOS tube;
when a first pulse transition edge of the narrow pulse signal arrives, the first switching unit is conducted, so that the grid voltage of the driving MOS tube is presented and maintained as the first voltage until a second pulse transition edge of the narrow pulse signal arrives;
when a second pulse transition edge of the narrow pulse signal arrives, the first switching unit is turned off, and the grid electrode of the driving MOS tube presents and keeps the second voltage until the first pulse transition edge of the narrow pulse signal arrives.
3. The demodulation circuit according to claim 2, wherein the demodulation circuit is connected between a secondary winding of a pulse transformer and the drive MOS transistor; the first switching unit includes:
a first MOS transistor;
the source electrode of the first MOS tube is connected with the positive tap of the secondary winding of the pulse transformer, the drain electrode of the first MOS tube is connected with the grid electrode of the driving MOS tube, and the grid electrode of the first MOS tube is respectively connected with the negative tap of the secondary winding of the pulse transformer and the source electrode of the driving MOS tube.
4. The demodulation circuit according to claim 3, wherein the demodulation circuit further comprises:
the first voltage division unit is connected with the first MOS tube;
the first voltage division unit is used for dividing the voltage on the first MOS tube.
5. The demodulation circuit according to claim 4, wherein the first voltage division unit includes:
a first resistor and a second resistor;
the first resistor is connected between the grid electrode and the source electrode of the first MOS tube, and the second resistor is connected between the grid electrode of the first MOS tube and the negative tap of the secondary winding of the pulse transformer.
6. The demodulation circuit according to claim 5, wherein the first voltage division unit further comprises:
and the first capacitor is connected with the second resistor in parallel.
7. The demodulation circuit according to any of claims 2 to 6, wherein the first voltage is a positive voltage, and the second voltage is a zero voltage; and/or
The first pulse is a positive pulse and the second pulse is a negative pulse.
8. The demodulation circuit according to claim 7, wherein the pulse width of the narrow pulse signal is in the same order of magnitude as the edge width of the driving signal for driving the driving MOS transistor; and/or
The positive and negative pulse widths of the pulse signal are equal.
9. The demodulation circuit of claim 8 wherein the narrow pulse signal is generated by a digital chip or modulated by an analog modulation circuit.
10. The demodulation circuit of claim 9 wherein the digital chip is an FPGA, a DSP, or an MCU; and/or
The analog modulation circuit is an RC differential circuit.
11. The demodulation circuit according to claim 2, wherein the demodulation circuit further comprises:
the second switch unit is connected with the first switch unit in parallel, a first diode is connected between the first switch unit and the driving MOS tube, and a second diode is connected between the second switch unit and the driving MOS tube, wherein the cathode of the first diode is connected with the first switch unit, and the anode of the second diode is connected with the second switch unit;
when a first pulse transition edge of the narrow pulse signal arrives, the first switch unit is switched on, the second switch unit is switched off, and the gate capacitor of the driving MOS tube is charged through the first diode so as to present and maintain the first voltage;
when a second pulse transition edge of the narrow pulse signal arrives, the first switch unit is turned off, the second switch unit is turned on, and the gate capacitor of the driving MOS tube discharges through the second diode, so that the second voltage is presented and maintained.
12. The demodulation circuit according to claim 11, wherein the demodulation circuit is connected between a secondary winding of a pulse transformer and the drive MOS transistor; the first switching unit includes:
a first triode;
an emitter of the first triode is connected with a positive tap of the secondary winding of the pulse transformer, a collector of the first triode is connected with a cathode of the first diode, and a base of the first triode is respectively connected with a negative tap of the secondary winding of the pulse transformer and a source of the driving MOS tube;
and/or
The second switching unit includes:
a second triode;
and the emitter of the second triode is connected with the positive tap of the secondary winding of the pulse transformer, the collector of the second triode is connected with the anode of the second diode, and the base of the second triode is respectively connected with the negative tap of the secondary winding of the pulse transformer and the source of the driving MOS tube.
13. The demodulation circuit of claim 12, wherein the demodulation circuit further comprises:
the second voltage division unit is connected with the first triode, and the third voltage division unit is connected with the second triode;
the second voltage division unit is used for dividing the voltage on the first triode, and the third voltage division unit is used for dividing the voltage on the second triode.
14. The demodulation circuit according to claim 13, wherein the second voltage division unit includes:
a third resistor and a fourth resistor;
the third resistor is connected between the base electrode and the emitting electrode of the first triode, and the fourth resistor is connected between the base electrode of the first triode and the negative tap of the secondary winding of the pulse transformer;
and/or
The third partial pressure unit includes:
a fifth resistor and a sixth resistor;
the fifth resistor is connected between the base electrode and the emitting electrode of the second triode, and the sixth resistor is connected between the base electrode of the second triode and the negative tap of the secondary winding of the pulse transformer.
15. The demodulation circuit according to claim 14, wherein the second voltage division unit further comprises:
a second capacitor connected in parallel with the fourth resistor;
the third voltage division unit further includes:
and the third capacitor is connected with the sixth resistor in parallel.
16. The demodulation circuit according to claim 11, wherein the demodulation circuit is connected between a secondary winding of a pulse transformer and the drive MOS transistor; the first switching unit includes:
a second MOS transistor;
the source electrode of the second MOS tube is connected with the positive tap of the secondary winding of the pulse transformer, the drain electrode of the second MOS tube is connected with the cathode of the first diode, and the grid electrode of the second MOS tube is respectively connected with the negative tap of the secondary winding of the pulse transformer and the source electrode of the driving MOS tube;
and/or
The second switching unit includes:
a third MOS transistor;
the source electrode of the third MOS tube is connected with the positive tap of the secondary winding of the pulse transformer, the drain electrode of the third MOS tube is connected with the anode of the second diode, and the grid electrode of the third MOS tube is respectively connected with the negative tap of the secondary winding of the pulse transformer and the source electrode of the driving MOS tube.
17. The demodulation circuit of claim 16, wherein the demodulation circuit further comprises:
the fourth voltage division unit is connected with the second MOS tube, and the fifth voltage division unit is connected with the third MOS tube;
the fourth voltage division unit is used for dividing the voltage on the second MOS tube, and the fifth voltage division unit is used for dividing the voltage on the third MOS tube.
18. The demodulation circuit according to claim 17, wherein the fourth voltage division unit comprises:
a seventh resistor and an eighth resistor;
the seventh resistor is connected between the grid electrode and the source electrode of the second MOS tube, and the eighth resistor is connected between the grid electrode of the second MOS tube and the negative tap of the secondary winding of the pulse transformer;
and/or
The fifth voltage division unit includes:
a ninth resistor and a tenth resistor;
the ninth resistor is connected between the grid electrode and the source electrode of the third MOS tube, and the tenth resistor is connected between the grid electrode of the third MOS tube and the negative tap of the secondary winding of the pulse transformer.
19. The demodulation circuit according to claim 18, wherein the fourth voltage division unit further comprises:
a fourth capacitor connected in parallel with the eighth resistor;
the fifth voltage division unit further includes:
a fifth capacitor connected in parallel with the tenth resistor.
20. The demodulation circuit according to claim 2, wherein the demodulation circuit is connected between a secondary winding of a pulse transformer and the drive MOS transistor; the first switching unit includes:
a third triode, an eleventh resistor and a third diode;
the anode of the third diode is connected with the positive tap of the secondary winding of the pulse transformer, and the cathode of the third diode is connected with the grid of the driving MOS tube;
a collector of the third triode is connected with a cathode of the third diode, an emitter of the third triode is respectively connected with a zero tap of the secondary winding of the pulse transformer and a source of the driving MOS tube, and a base of the third triode is connected with a negative tap of the secondary winding of the pulse transformer through the eleventh resistor;
when the narrow pulse signal is in a positive level, the gate capacitor of the driving MOS tube is charged through the third diode, and the gate voltage of the driving MOS tube is the first voltage;
when the narrow pulse signal is negative, the gate capacitor of the driving MOS tube discharges through the third triode, and the gate voltage of the driving MOS tube presents the second voltage.
21. The demodulation circuit according to any of claims 11 to 20, wherein the first voltage is a positive voltage and the second voltage is a negative voltage; and/or
The first pulse is a positive pulse and the second pulse is a negative pulse.
22. The demodulation circuit according to claim 21, wherein the pulse width of the narrow pulse signal is in the same order of magnitude as the edge width of the driving signal for driving the driving MOS transistor; and/or
The positive and negative pulse widths of the pulse signal are equal.
23. The demodulation circuit of claim 22 wherein the narrow pulse signal is generated by a digital chip or is modulated by an analog modulation circuit on a PWM signal.
24. The demodulation circuit of claim 23 wherein said digital chip is an FPGA, a DSP, or an MCU; and/or
The analog modulation circuit is an RC differential circuit.
25. The pulse generating circuit is characterized in that the pulse generating circuit is used for generating a narrow pulse signal for modulating a grid voltage of a driving MOS tube;
the gate voltage of the driving MOS tube presents and keeps at the first voltage when a first pulse transition edge of the narrow pulse signal arrives until a second pulse transition edge of the narrow pulse signal arrives, and presents and keeps at the second voltage when the second pulse transition edge of the narrow pulse signal arrives until the first pulse transition edge of the narrow pulse signal arrives.
26. The pulse generating circuit of claim 25, wherein the pulse generating circuit generates the narrow pulse signal in an analog manner or a digital manner.
27. The pulse generating circuit according to claim 26, wherein in a case where the pulse generating circuit generates the narrow pulse signal by an analog manner, the pulse generating circuit includes a modulating circuit that modulates a PWM signal to generate the narrow pulse signal; and/or
In a case where the pulse generation circuit generates the narrow pulse signal in a digital manner, the pulse generation circuit includes a digital chip for generating the narrow pulse signal.
28. The pulse generating circuit of claim 27 wherein the modulation circuit is an RC differentiating circuit; and/or
The digital chip is FPGA, DSP or MCU.
29. An isolated drive circuit, comprising:
a demodulation circuit as claimed in any one of claims 1 to 24.
30. The isolated driver circuit of claim 29, further comprising:
a pulse generating circuit as claimed in any one of claims 25 to 28.
31. An isolated drive circuit according to claim 29 or claim 30, wherein the isolated drive circuit is for driving a motor.
32. A movable platform, comprising:
a body;
the motor is arranged in the machine body and used for providing power for the movable platform; and
an isolated drive circuit as claimed in any one of claims 29 to 31, for driving rotation of said motor.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/073486 WO2021146909A1 (en) | 2020-01-21 | 2020-01-21 | Demodulation circuit for isolation drive circuit, pulse generation circuit, and isolation drive circuit |
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| Publication Number | Publication Date |
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| CN112514222A true CN112514222A (en) | 2021-03-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080004337.3A Pending CN112514222A (en) | 2020-01-21 | 2020-01-21 | Demodulation circuit, pulse generation circuit and isolation drive circuit for isolation drive circuit |
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| Country | Link |
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| CN (1) | CN112514222A (en) |
| WO (1) | WO2021146909A1 (en) |
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| WO2023016201A1 (en) * | 2021-08-13 | 2023-02-16 | 中兴通讯股份有限公司 | Driving apparatus and electronic device |
| CN116488624A (en) * | 2023-05-11 | 2023-07-25 | 天津大学 | All-solid-state nanosecond high-voltage pulse switch |
| EP4277101A1 (en) * | 2022-05-09 | 2023-11-15 | Hamilton Sundstrand Corporation | Multi-environmental circuit devices |
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| US5304863A (en) * | 1991-08-30 | 1994-04-19 | Hughes Aircraft Company | Transformer driver having unlimited duty cycle capability by inserting narrow pulses during unlimited duty cycles |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023016201A1 (en) * | 2021-08-13 | 2023-02-16 | 中兴通讯股份有限公司 | Driving apparatus and electronic device |
| CN114465459A (en) * | 2022-03-09 | 2022-05-10 | 湖南北顺源智能科技有限公司 | SiC/GaN MOSFET drive circuit and integrated circuit |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2021146909A1 (en) | 2021-07-29 |
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