WO2021143427A1 - 散热结构及其制造方法、芯片结构以及电子设备 - Google Patents

散热结构及其制造方法、芯片结构以及电子设备 Download PDF

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Publication number
WO2021143427A1
WO2021143427A1 PCT/CN2020/136462 CN2020136462W WO2021143427A1 WO 2021143427 A1 WO2021143427 A1 WO 2021143427A1 CN 2020136462 W CN2020136462 W CN 2020136462W WO 2021143427 A1 WO2021143427 A1 WO 2021143427A1
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chip
substrate
heat dissipation
heat sink
gallium
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PCT/CN2020/136462
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English (en)
French (fr)
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邓抄军
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华为技术有限公司
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Priority to EP20914393.2A priority Critical patent/EP4081008A4/en
Publication of WO2021143427A1 publication Critical patent/WO2021143427A1/zh
Priority to US17/862,540 priority patent/US20220344237A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/54—Providing fillings in containers, e.g. gas fillings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/22—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device liquid at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes
    • H01L23/4275—Cooling by change of state, e.g. use of heat pipes by melting or evaporation of solids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/427—Cooling by change of state, e.g. use of heat pipes

Definitions

  • This application relates to the technical field of electronic devices, and in particular to a heat dissipation structure and a manufacturing method thereof, a chip structure and an electronic device.
  • the embodiments of the present application provide a heat dissipation structure and a manufacturing method thereof, a chip structure, and an electronic device, which can solve the problem of chip heat dissipation.
  • the technical solutions are as follows:
  • a heat dissipation structure in one aspect, includes: a peripheral substrate, a chip substrate, a thermally conductive material, and a heat sink; wherein one end of the peripheral substrate is connected to the chip substrate along the periphery of the chip substrate, and the heat sink is connected to the peripheral substrate. The other end is connected; in addition, there is an accommodation space between the peripheral substrate, the radiator and the chip substrate, the thermal conductivity material is filled in the accommodation space, and the chip substrate is used to place the silicon wafer.
  • the heat generated by the chip can be diffused out only through the two heat conduction links of the silicon chip and the thermal conductive material, there are fewer heat conduction links, thereby reducing the thermal resistance between the heat conduction links.
  • the power consumption of the chip increases, and the heat generated by the chip can also be diffused through the silicon wafer and the thermally conductive material, which improves the efficiency of heat diffusion and improves the heat dissipation effect.
  • the heat sink includes a heat sink base plate and at least one heat dissipation fin, each heat dissipation fin is connected to one side of the heat sink base plate, and the other side of the heat sink base plate is connected to the other end of the peripheral substrate, and the heat sink There is an accommodating space between the film, the peripheral substrate and the chip substrate.
  • the heat sink further includes: a connecting portion, the upper surface of the connecting portion is connected with each heat dissipation fin, and the lower surface of the connecting portion is connected with the heat sink bottom sheet; a reference angle exists between the connecting portion and the heat sink bottom sheet.
  • the other side of the heat sink base is hermetically connected to the other end of the peripheral substrate.
  • one end of the peripheral substrate is hermetically connected to the chip substrate along the periphery of the chip substrate.
  • the thermally conductive material is liquid metal.
  • liquid metal By selecting liquid metal, on the one hand, the heat conduction links are reduced, and the heat dissipation efficiency of the chip can be improved.
  • the wear between the thermal conductive material 3 and the silicon wafer can be reduced, and the manufacturing cost of the chip can be reduced.
  • the liquid metal is gallium or a gallium alloy, where the gallium alloy may be any alloy containing gallium.
  • the gallium alloy is selected from at least one of gallium aluminum alloy, gallium bismuth alloy, gallium tin alloy, gallium indium alloy, gallium copper alloy, gallium gold alloy, and gallium silver alloy.
  • gallium aluminum alloy gallium bismuth alloy
  • gallium tin alloy gallium indium alloy
  • gallium copper alloy gallium copper alloy
  • gallium gold alloy gallium silver alloy.
  • gallium silver alloy As the state of gallium and gallium alloy is liquid when the chip is working, and the melting point of gallium and gallium alloy is very low, the boiling point is very high. Both gallium and gallium alloys can be well combined with silicon wafers, with a high degree of combination, which can reduce the thermal resistance of heat from silicon wafers to gallium or gallium alloys.
  • the surface of the silicon wafer in contact with the thermally conductive material is a smooth curved surface.
  • a chip structure is also provided.
  • the chip structure includes a chip body and a heat dissipation structure provided on the chip body.
  • the heat dissipation structure is the heat dissipation structure of any one of the above first aspects.
  • the electronic device includes a circuit board with the above-mentioned chip structure, and the chip structure includes any of the above heat dissipation structures.
  • the heat dissipation structure includes: a peripheral substrate, a chip substrate, a thermally conductive material, and a heat sink; the method includes: connecting one end of the peripheral substrate to the chip substrate along the periphery of the chip substrate, and placing on the chip substrate There is a silicon wafer; the heat-conducting material is filled in the accommodating space formed by the chip substrate and the peripheral substrate; the heat sink is connected to the other end of the peripheral substrate to close the accommodating space.
  • the heat sink includes: a heat sink base and at least one heat dissipation fin; connecting the heat sink to the other end of the peripheral substrate includes: connecting each heat dissipation fin to one side of the heat sink base, and The other side of the bottom plate of the heat sink is connected to the other end of the peripheral substrate.
  • the heat sink further includes: a connecting portion; the method further includes: connecting the upper surface of the connecting portion with each of the radiating fins, connecting the lower surface of the connecting portion with the bottom of the heat sink, and connecting the connecting portion and the bottom of the heat sink. There is a reference angle between.
  • Figure 1 is a schematic diagram of a heat dissipation structure provided by related technologies
  • Fig. 2 is a schematic diagram of a heat dissipation structure provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a heat sink provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a heat sink provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the structure of a circuit board provided by an embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the power consumption of the chip is increasing. Some chips have more than 200W power consumption. In the future, there will be more than 400W or even 500W chips. . However, as the power consumption of the chip continues to increase, a large amount of heat will be generated at the same time, so it is necessary to diffuse the large amount of heat generated by the chip.
  • the heat dissipation problem of high-power chips is difficult to solve, especially for chips that consume more than 250W. The greater the heating power, the more difficult it is to solve the heat dissipation problem. If it cannot be solved, the chip will not work, and all chips and chip-related systems will be invested. Will not be converted into application products.
  • the heat dissipation structure provided by the related technology as shown in Figure 1, the silicon chip is placed on the chip substrate, a first layer of thermally conductive material is arranged between the silicon chip and the chip cover, and a second layer is arranged between the chip cover and the heat sink. Layer of thermally conductive material.
  • the heat dissipation structure provided by related technologies can achieve the purpose of heat diffusion, the heat diffusion needs to pass through multiple heat conduction links. When the power consumption of the chip increases, the thermal resistance between the heat conduction links will increase, which will affect The diffusion of heat causes a serious rise in chip temperature and affects the normal operation of the device.
  • an embodiment of the present application provides a heat dissipation structure.
  • the heat dissipation structure includes: a peripheral substrate 1, a chip substrate 2, a thermal conductive material 3, and a heat sink 4.
  • peripheral substrate 1 One end of the peripheral substrate 1 is connected to the chip substrate 2 along the periphery of the chip substrate 2, and the heat sink 4 is connected to the other end of the peripheral substrate 1.
  • the thermally conductive material 3 is filled in the accommodating space, and the chip substrate 2 is used to place the silicon wafer 6.
  • the heat dissipation structure provided by the embodiment of the present application since the heat generated by the chip can be diffused out only through the two heat conduction links of the silicon wafer 6 and the thermal conductive material 3, there are fewer heat conduction links, thereby reducing the thermal resistance between the heat conduction links. Therefore, even if the power consumption of the chip increases, the heat generated by the chip can be diffused through the silicon wafer 6 and the thermally conductive material 3, which improves the efficiency of heat diffusion.
  • the heat dissipation structure provided by the embodiments of the present application can achieve good heat dissipation for chips with a power consumption of more than 600W.
  • the heat dissipation structure may also include solder balls, and the chip substrate 2 is connected to the circuit board 5 through the solder balls, so as to fix the chip on the circuit board 5.
  • the heat dissipation structure provided by the related technology includes a chip cover.
  • the chip cover can support the heat sink 4 and protect the silicon chip 6 placed on the chip substrate 2.
  • the heat conduction link will be increased. Increase the thermal resistance of the heat conduction link, thereby affecting the diffusion of heat.
  • the weight of the heat sink 4 can be supported, the heat sink 4 can prevent the silicon wafer 6 on the chip substrate 2 from being damaged, and the silicon wafer 6 can be protected from damage.
  • a closed accommodating space is formed by the peripheral substrate 1, the chip substrate 2 and the heat sink 4, and the silicon chip 6 is placed on the chip substrate 2.
  • the silicon chip 6 can be prevented from being exposed to the air, and the silicon chip 6 can be protected. Function; on the other hand, to prevent the heat-conducting material 3 filled in the containing space from leaking or reacting with outside air or other substances, thereby affecting the normal operation of the chip.
  • the shape of the peripheral substrate 1 may be determined according to the shape of the chip substrate 2 or the shape of the circuit board 5. Exemplarily, when the shape of the chip substrate 2 is a rectangle, the shape of the peripheral substrate 1 may be a rectangle; when the shape of the chip substrate 2 is a circle, the shape of the peripheral substrate 1 may be a circle.
  • the shape of the peripheral substrate 1 in the embodiment of the present application is not limited to this.
  • the width of the peripheral substrate 1 can be set according to the work requirements of forming the chip, which is not limited in the embodiment of the present application.
  • the size of the accommodating space formed between the peripheral substrate 1, the heat sink 4 and the chip substrate 2 can be determined according to the size of the chip substrate 2.
  • the size of the chip substrate 2 may be set to be larger.
  • the size of the accommodating space can also be determined according to the power consumption of the chip.
  • the power consumption of the chip is large, more heat will be generated.
  • the accommodating space can be larger to accommodate more thermally conductive materials 3 , Improve the rate of heat diffusion.
  • the power consumption of the chip is low, the heat generated by the chip will be less.
  • a smaller housing space can also achieve the purpose of heat diffusion. In this way, the cost of the heat dissipation structure can also be reduced.
  • the heat sink 4 includes: a heat sink base 41 and at least one heat dissipation fin 42, each heat dissipation fin 42 is fixedly connected to one side of the heat sink base 41, and the heat sink base 41 The other surface is connected to the other end of the peripheral substrate 1, and there is an accommodating space between the heat sink base 41, the peripheral substrate 1 and the chip substrate 2.
  • the heat sink base 41 can be connected to the other end of the peripheral substrate 1 to form a closed accommodating space to ensure that it is placed on the chip substrate 2.
  • the silicon wafer 6 is not exposed to the air.
  • each heat dissipation fin 42 may be integrally formed with the heat sink bottom sheet 41, or the heat dissipation fin 42 may be welded to the heat sink bottom sheet 41.
  • the embodiment of the present application does not limit the connection manner of the heat dissipation fin 42 and the heat sink bottom sheet 41.
  • the heat dissipation structure provided by the related technology also includes a chip cover, and a second layer of thermally conductive material is filled between the chip cover and the heat sink 4, and each layer of thermally conductive material filled has thermal resistance, so that the silicon wafer 6 and the heat sink 4 have thermal resistance.
  • the heat sink film 41 replaces the chip cover, that is, there is no need to provide a chip cover.
  • the heat dissipation structure provided by the embodiment of the present application reduces a layer of heat conduction link between the silicon wafer 6 and the heat sink 4, thereby reducing the thermal resistance between a layer of heat conduction link, and improving the efficiency of heat diffusion. .
  • the heat sink 4 further includes: a connecting portion 43, the upper surface of the connecting portion 43 is connected to each heat dissipation fin 42, and the lower surface of the connecting portion 43 is connected to the heat sink bottom sheet 41; There is a reference angle between the portion 43 and the bottom plate 41 of the heat sink.
  • the reference angle may be in the range of 180°-90°
  • each heat dissipation fin 42 is fixedly arranged on the upper surface of the connecting portion 43
  • the heat sink base 41 is fixedly arranged on the lower surface of the connecting portion 43.
  • the upper surface of each heat dissipation fin 42 and the connecting portion 43 may be integrally formed by stamping, or may be connected by welding.
  • the connecting portion 43 and the heat sink bottom sheet 41 may be integrally formed by stamping, or may be welded connection, which is not limited in the embodiment of the present application.
  • the other surface of the heat sink base plate 41 is hermetically connected to the other end of the peripheral substrate 1.
  • the other side of the heat sink base sheet 41 is sealed and connected to the other end of the peripheral substrate 1 to ensure the tightness of the accommodation space formed between the peripheral base plate 1, the heat sink base sheet 41 and the chip substrate 2 and avoid the thermal conductive material 3 when the chip is working. leakage.
  • the other surface of the heat sink base sheet 41 and the other end of the peripheral substrate 1 are fusion bonded.
  • one end of the peripheral substrate 1 is hermetically connected to the chip substrate 2 along the periphery of the chip substrate 2.
  • the peripheral substrate 1 since the heat-conducting material 3 needs to be contained in the containing space, the peripheral substrate 1 not only needs to ensure that the heat-conducting material 3 is not exposed to the air, but also to avoid squeezing the silicon wafer 6 by the heat sink 4, and to ensure that the temperature rises when the chip is working. When it is high, the thermally conductive material 3 does not leak from the gap between the peripheral substrate 1 and the chip substrate 2, and therefore, the end where the peripheral substrate 1 is provided is hermetically connected to the chip substrate 2.
  • one end of the peripheral substrate 1 is fusion bonded with the chip substrate 2 along the periphery of the chip substrate 2.
  • the materials of the heat sink bottom sheet 41, the peripheral substrate 1 and the chip substrate 2 are all plastics, it is necessary to achieve the airtightness between the peripheral substrate 1 and the chip substrate 2, as well as the peripheral substrate 1 and the heat sink.
  • the airtightness between the bottom sheet 41, between the heat sink bottom sheet 41 and the peripheral substrate 1, and between one end of the peripheral substrate 1 and the chip substrate 2 may be fusion bonding.
  • the heat sink bottom sheet 41 and the peripheral substrate 1 may be between one end of the peripheral substrate 1 and the chip substrate 2.
  • Use welding connection In this way, on the one hand, the airtightness between the heat sink base 41 and the peripheral substrate 1 and between one end of the peripheral substrate 1 and the chip substrate 2 can be ensured, and on the other hand, the stability and firmness of the heat dissipation structure can also be improved.
  • the heat sink base 41 and the peripheral substrate 1 and one end of the peripheral base 1 and the chip substrate 2 are connected by soldering, the heat sink base 41 can be welded to the peripheral base 1 through a solder layer.
  • One end of 1 can be soldered to the chip substrate 2 through a solder layer.
  • the solder in the solder may be tin. Since tin has a high thermal conductivity, it will not affect the thermal conductivity of the thermal conductive material 3 when used as a solder, and by setting the thickness of the solder layer of the solder tin within the reference range, the rate of heat dissipation of the chip can be further improved and a large amount of heat can be prevented Damage the chip.
  • the thickness of the solder layer may be set between 0.1 mm and 0.15 mm, such as 0.1 mm, 0.11 mm, 0.12 mm, 0.13 mm, 0.14 mm, or 0.15 mm. Further, in order to avoid as much as possible the thermal conductive material 3 dissolving the solder tin when the chip is working, the solder can be soldered from the outside, and the solder contacts the thermal conductive material 3 as much as possible.
  • the thermally conductive material 3 is liquid metal.
  • the thermally conductive material 3 provided by the embodiment of the present application is liquid metal, that is, the state of the thermally conductive material is liquid at least when the chip is working. It is understandable that some metals are liquid at room temperature, such as 25°C, and even if it is above 0°C, they are also liquid. The metal is in a liquid state when the chip is working. Or the chip does not work, but the metal is also liquid at room temperature.
  • the heat conduction links are reduced, and the heat dissipation efficiency of the chip can be improved.
  • the wear between the thermal conductive material 3 and the silicon wafer can be reduced, and the manufacturing cost of the chip can be reduced.
  • the liquid metal is gallium or a gallium alloy, where the gallium alloy may be any alloy containing gallium.
  • the liquid metal can diffuse the heat generated by the chip to the heat sink 4. Therefore, the choice of liquid metal is very important. It is necessary to select the metal that can be liquefied when the chip is working, that is, the metal in the liquid state, and the metal has a higher thermal conductivity, that is, it has a lower thermal resistance. It is highly combined with the silicon wafer 6 and diffuses heat efficiently. Metallic mercury has good thermal conductivity and low thermal resistance, but mercury is toxic, so it is not suitable to use mercury as a thermal conductive material3.
  • gallium and gallium alloy is liquid when the chip is working, and the melting point of gallium and gallium alloy is very low, and the boiling point is very high.
  • Both gallium and gallium alloy can be combined with the silicon wafer 6 well, and the combination degree is relatively high, which can reduce the thermal resistance of the heat from the silicon wafer 6 to the gallium or gallium alloy.
  • the silicon chip 6 due to the high degree of bonding between gallium and gallium alloy and silicon chip 6, when gallium or gallium alloy is filled in the containing space, the silicon chip 6 will not be damaged, and the efficiency of heat diffusion of the chip is also improved.
  • the liquid metal may be gallium alone, or a gallium alloy, or a mixture of gallium and gallium alloy.
  • the mixing ratio may be 1:1-2, for example, it may be 1:1 or 1:2.
  • the embodiment of the application does not limit the mixing ratio of gallium and gallium alloy mixture.
  • gallium or gallium alloy is filled in the accommodating space formed by the heat sink base plate 41, the chip substrate 2 and the peripheral substrate 1. On the one hand, it avoids setting a chip cover on the silicon wafer 6 and reduces the heat conduction link; On the one hand, it is also avoided to affect the heat diffusion efficiency due to the low thermal conductivity of the air between the chip cover and the heat sink 4.
  • the heat dissipation structure provided by the related technology requires a first layer of thermally conductive material to be added between the silicon chip 6 and the chip cover to improve the heat dissipation of the chip.
  • the first thermally conductive material provided by the related technology If the temperature is low, friction will occur with the silicon wafer 6, which will damage the silicon wafer 6 and increase the manufacturing cost of the heat dissipation structure.
  • the heat diffusion efficiency is low.
  • the heat dissipation structure provided by the embodiment of the present application not only reduces damage to the silicon wafer 6 by filling gallium or gallium alloy in the containing space, but also increases the rate of heat diffusion, thereby reducing the manufacturing cost of the heat dissipation structure.
  • the gallium alloy is selected from at least one of gallium aluminum alloy, gallium bismuth alloy, gallium tin alloy, gallium indium alloy, gallium copper alloy, gallium gold alloy, and gallium silver alloy.
  • the thermally conductive material 3 selected in the embodiment of the present application is liquid metal, that is, the thermally conductive material 3 needs to be liquid when the chip is working.
  • the gallium alloy mentioned above can be liquid at low temperatures, such as 0°C, and remain in a liquid state when the chip is working, and The above-mentioned gallium alloys have good thermal conductivity, low thermal resistance, and a high degree of bonding with the silicon wafer 6, which can significantly reduce the thermal resistance of heat diffusion with the silicon wafer 6.
  • the gallium alloy may be a single one of gallium aluminum alloy, gallium bismuth alloy, gallium tin alloy, gallium indium alloy, gallium copper alloy, gallium gold alloy, and gallium silver alloy, or a mixture of any two of the foregoing ,
  • a mixture of gallium-aluminum alloy and gallium-bismuth alloy, or a mixture of gallium-aluminum alloy and gallium-tin alloy, or a mixture of gallium-aluminum alloy and gallium-indium alloy, or a mixture of gallium-bismuth alloy and gallium-tin alloy, or gallium-tin alloy A mixture of gallium indium alloy and gallium indium alloy, or a mixture of gallium bismuth alloy and gallium indium alloy.
  • the mixing ratio can be 1:1 or 1:2.
  • the embodiment of the present application does not limit the mixing ratio of the two.
  • the gallium alloy can also be a mixture of any three of the above, for example, a mixture of gallium aluminum alloy, gallium bismuth alloy and gallium tin alloy, or a mixture of gallium bismuth alloy, gallium tin alloy and gallium indium alloy, or gallium aluminum
  • the mixing ratio can be 1:1:1 or 1:2:1.
  • the embodiment of the present application does not limit the mixing ratio of the three.
  • the gallium alloy may also be a mixture of any of the four above, for example, a mixture of gallium aluminum alloy, gallium bismuth alloy, gallium tin alloy, and gallium indium alloy, and the mixing ratio may be 1:1:2:1.
  • the embodiment of the present application does not limit the mixing ratio of the four.
  • the materials of the peripheral substrate 1 and the chip substrate 2 and the heat sink bottom sheet 41 may be pure iron material or plastic material.
  • alloys are the phenomenon of mutual dissolution between different metals. Generally, high temperature is required for forming alloys between metals. However, not all mutual dissolution between metals requires high temperature. Due to the low melting point of gallium, it becomes liquid at less than 30°C. Liquid gallium can form alloys with other metals, that is, it can dissolve other metals and corrode other metals. Therefore, gallium cannot be contained in a metal container.
  • the materials of the peripheral substrate 1 and the chip substrate 2 and the bottom plate 41 of the heat sink provided in the embodiments of the present application can be pure iron or other metal materials.
  • the selected metal material needs to be considered to avoid the formation of alloys with liquid metal. The problem.
  • the materials of the peripheral substrate 1 and the chip substrate 2 can also be selected from plastic materials.
  • the material of the heat sink bottom sheet 41 may also be a plastic material. Since the heat-conducting material 3 is in a liquid state during the working of the chip, the heat sink bottom sheet 41 may also contact the heat-conducting material 3. Therefore, the material of the heat sink bottom sheet 41 may also be a plastic material.
  • the plastic is polyimide, polyetheretherketone, polyamideimide, polybenzimidazole, polyetherimide, polyphenylene sulfide, polysulfone, polytetrafluoroethylene, or poly Vinylidene fluoride.
  • plastics provided in the embodiments of the present application are all high-temperature-resistant thermosetting plastics.
  • the use of high-temperature resistant plastics can make the peripheral substrate 1 not only resistant to the dissolution and corrosion of gallium or gallium alloys, but also at high temperatures. Will not deform or dissolve underneath.
  • the long-term working temperature of polybenzimidazole can reach 310°C, and the short-term working temperature can reach 500°C. Therefore, the selection of polybenzimidazole can meet the working state of the chip with high power consumption.
  • the long-term working temperature of polyimide can reach 290°C, the short-term working temperature can reach 480°C, and it can also work in the environment of -240°C.
  • Polyamide-imide is also a thermosetting plastic, with a long-term working temperature of 250°C, and has excellent wear resistance and impact resistance.
  • the long-term working temperature of polyether ether ketone can reach 160°C, and the short-term working temperature can reach 260°C. It has good high temperature resistance.
  • the long-term working temperature of polyetherimide can reach 170°C, and the short-term working temperature can reach 200°C.
  • the long-term working temperature of polyphenylene sulfide can reach 220°C, and the short-term working temperature can reach 260°C.
  • the long-term working temperature of polyvinylidene fluoride can reach 150°C, and the short-term working temperature can reach 160°C. At the same time, it has excellent corrosion resistance, and has high mechanical strength and rigidity.
  • the long-term working temperature of PTFE can reach 260°C, and the short-term working temperature is 280°C. It has excellent corrosion resistance and extremely low friction coefficient.
  • the long-term working temperature of polysulfone is 150°C, and the short-term working temperature can reach 180°C.
  • thermosetting plastics are all thermosetting plastics, and can work at high temperatures, and can also work in low-temperature environments, which can meet the working requirements of the chip under high power consumption.
  • the materials of the peripheral substrate 1 and the chip substrate 2 and the heat sink substrate 41 may also be metal.
  • the materials of the peripheral substrate 1 and the chip substrate 2 and the heat sink substrate 41 may be copper. It can also be steel.
  • the thermal conductive material 3 provided by the embodiment of the present application is liquid metal, and the liquid metal changes from solid to liquid when the chip is working, and the density of the liquid metal in the liquid state is greater than the density in the solid state. Therefore, when the chip is working, the heat-conducting material 3 will change from solid to liquid and its volume will decrease. When the chip is not working or in a low temperature environment, such as minus 30°C, the heat-conducting material 3 will become solid and increase in volume. . Therefore, by providing a reference gap between the heat-conducting material 3 and the heat sink 4, it is avoided that when the heat-conducting material 3 becomes a solid state, the volume of the containing space becomes smaller and the overall use function of the chip is avoided.
  • the thermally conductive material 3 is gallium or gallium alloy
  • the gallium or gallium alloy becomes liquid when the chip is working, and when the chip is not working or at a low temperature, for example, minus 30°C, the gallium or gallium alloy becomes solid. At this time, it is necessary to reserve space for gallium or gallium alloy to increase in volume.
  • gallium or gallium alloy is generally liquid above 30°C, it is also liquid at 0°C, that is, gallium or gallium alloy is also liquid when the chip is not working.
  • the embodiment of the present application sets a reference gap between the thermal conductive material 3 and the heat sink 4 , To avoid the occurrence of the above situation.
  • the reference gap between the thermal conductive material 3 and the heat sink 4 can not be too large. If the gap is too large, air will be trapped in the middle, which will affect the diffusion of heat. The gap should not be too small. The gap is too small. When the gallium or gallium alloy changes from a liquid state to a solid state, the gap is too small, which may cause squeeze on the peripheral substrate 1 or squeeze the silicon wafer 6 and damage the silicon wafer 6.
  • the reference gap may be 0.1 mm-0.15 mm. For example, 0.1 mm, 0.11 mm, 0.12 mm, 0.13 mm, 0.14 mm, or 0.15 mm.
  • the surface of the silicon wafer 6 in contact with the thermally conductive material 3 is a smooth curved surface.
  • the thermally conductive material 3 can prevent the silicon chip 6 from being worn or damaged, and on the other hand, the contact area between the silicon chip 6 and the thermally conductive material 3 is increased. The heat diffusion rate between the silicon wafer 6 and the thermal conductive material 3 is improved.
  • the thermally conductive material 3 is gallium or gallium alloy
  • the contact surface between the gallium or gallium alloy and the silicon wafer 6 can be further increased, and the silicon wafer 6 The degree of bonding with gallium or gallium alloy, thereby improving the diffusion of heat, and avoiding excess heat from damaging the chip.
  • the surface of the silicon wafer 6 in contact with the thermally conductive material 3 can also be set as an arc-shaped surface.
  • the shape of the contact surface of the silicon wafer 6 and the thermal conductive material 3 is not limited to this, as long as it can increase the contact area and improve the heat dissipation efficiency.
  • heat dissipation structure provided in the embodiments of the present application can not only be applied to chips with high power consumption above 250W, but also can be applied to chips with low power consumption, such as chips with power consumption less than 250W, or chips with low power consumption. Work in high-temperature environments, such as automotive electronics, wireless power amplifiers and other high-temperature working environments.
  • the embodiments of the present application also provide a chip structure, which includes a chip body and any one of the above heat dissipation structures provided on the chip body.
  • the chip body includes a silicon wafer 6.
  • the heat dissipation structure adopts the heat dissipation structure provided in the above-mentioned embodiment.
  • the structure and principle of the heat dissipation structure reference may be made to the above-mentioned embodiments, which will not be repeated here.
  • the heat dissipation structure provided by the above embodiments is provided on the silicon wafer 6 of the chip body. Since the heat generated by the chip only passes through the two heat conduction links of the silicon wafer 6 and the thermally conductive material 3, the heat conduction links are reduced, and the heat conduction is reduced. The thermal resistance between the links, even when the power consumption of the chip increases, the heat generated by the chip can be transferred through the silicon wafer 6 and the thermal conductive material 3, which improves the efficiency of heat dissipation.
  • the embodiment of the present application also provides a circuit board 5, as shown in FIG. 5, the circuit board 5 is provided with at least one heat dissipation structure as described above.
  • the circuit board 5 of the embodiment of the present application is provided with at least one chip structure of the above-mentioned embodiment.
  • the circuit board 5 is provided with at least one chip structure of the above-mentioned embodiment, and the chip structure is fixedly connected to the circuit board 5.
  • the chip structure can be soldered on the circuit board 5 or fixed on the circuit board 5 by bolts.
  • the position and number of chip structures on the circuit board 5 are not limited.
  • at least one chip structure may be provided on the upper surface of the circuit board 5; alternatively, at least one chip structure may be provided on the upper surface of the circuit board 5, and at least one chip structure may be provided on the lower surface of the circuit board 5.
  • the structure and principle of the chip structure can be referred to the above-mentioned embodiment, which will not be repeated here.
  • the circuit board 5 provided by the embodiment of the present application is provided with at least one chip structure of the above-mentioned embodiment on the circuit board 5. Since the heat generated by the chip only passes through the two heat conduction links of the silicon wafer 6 and the thermally conductive material 3, the heat conduction is reduced. The link further reduces the thermal resistance between the thermal conduction links. Even when the power consumption of the chip increases, the heat generated by the chip can be transferred through the silicon wafer 6 and the thermally conductive material 3, which improves the efficiency of heat diffusion.
  • an embodiment of the present application also provides an electronic device, in which at least one circuit board 5 described above is provided.
  • FIG. 6 is a schematic structural diagram of an electronic device provided in an embodiment of the application. As shown in FIG. 6, the electronic device provided in an embodiment of the application is provided with at least one circuit board 5 provided in the foregoing embodiment. The structure and principle of the circuit board 5 can be referred to the above-mentioned embodiments, which will not be repeated here.
  • the circuit boards 5 in the electronic device are connected in parallel with each other.
  • circuit boards 5 are provided in an electronic device, and the circuit boards 5 adopt the circuit boards 5 provided in the above-mentioned embodiments.
  • the structure and function of the circuit board 5 reference may be made to the introduction of the above-mentioned embodiment, which will not be repeated here.
  • multiple circuit boards 5 can be connected in parallel, and then the parallel circuit boards 5 are arranged in the electronic device.
  • the electronic device may be a server.
  • the connection mode of the circuit board 5 and the electronic device can be a fixed connection or a sliding connection.
  • one or more sliding grooves may be provided on the chassis of the electronic device, and then the circuit board 5 is arranged in the sliding groove, so that the circuit board 5 can slide on the sliding groove.
  • the structure of each circuit board 5 of the plurality of circuit boards 5 may be the same or different.
  • Each circuit board 5 is provided with at least one chip structure of the above-mentioned embodiment. Among them, the structure and principle of the chip structure can be referred to the above-mentioned embodiment, which will not be repeated here.
  • one or more circuit boards 5 provided in the foregoing embodiments are provided in the electronic device, and at least one chip structure of the foregoing embodiments is provided on each circuit board 5, and the chip structure
  • the silicon wafer 6 is provided with the heat dissipation structure provided in the above-mentioned embodiment. Since the heat generated by the chip only passes through the two heat conduction links of the silicon wafer 6 and the thermally conductive material 3, the heat conduction links are reduced, thereby reducing the thermal resistance between the heat conduction links, even if the power consumption of the chip increases, the heat generated by the chip can be The transfer is realized through the silicon wafer 6 and the thermally conductive material 3, which improves the efficiency of heat diffusion.
  • the embodiment of the present application provides a method for manufacturing a heat dissipation structure, wherein the heat dissipation structure includes: a peripheral substrate 1, a chip substrate 2, a thermally conductive material 3, and a heat sink 4; for the detailed description of the heat dissipation structure, please refer to the above The content of the embodiment will not be repeated here.
  • the manufacturing method of the heat dissipation structure includes the following steps:
  • Step 11 one end of the peripheral substrate 1 is connected to the chip substrate 2 along the periphery of the chip substrate 2, and a silicon wafer 6 is placed on the chip substrate 2.
  • one end of the peripheral substrate 1 is hermetically connected to the chip substrate 2 along the periphery of the chip substrate 2.
  • the silicon wafer 6 may be placed on the chip substrate 2 first.
  • the embodiment of the present application does not vary the order of the silicon chip 6 placement. Qualify.
  • Step 12 filling the heat-conducting material 3 in the accommodating space formed by the chip substrate 2 and the peripheral substrate 1.
  • Step 13 connect the heat sink 4 to the other end of the peripheral substrate 1 to close the containing space.
  • the heat sink 4 includes: a heat sink base plate 41 and at least one heat dissipation fin 42, therefore, connecting the heat sink 4 to the other end of the peripheral substrate 1 includes: connecting each heat dissipation fin 42 to the heat dissipation One side of the bottom plate 41 is connected, and the other side of the bottom plate 41 of the heat sink is connected to the other end of the peripheral substrate 1.
  • the other surface of the heat sink base plate 41 is hermetically connected to the other end of the peripheral substrate 1.
  • the heat sink 4 further includes a connecting portion 43
  • the method further includes: connecting the upper surface of the connecting portion 43 with each of the radiating fins 42, and connecting the lower surface of the connecting portion 43 with the heat sink bottom sheet 41 ; Among them, there is a reference angle between the connecting portion 43 and the bottom plate 41 of the radiator.
  • the heat generated by the chip since the heat generated by the chip only passes through the two heat conduction links of the silicon wafer and the heat-conducting material, the heat conduction link is reduced, and the thermal resistance between the heat conduction links is reduced, even when the power consumption of the chip increases. , The heat generated by the chip can also be transferred through the silicon wafer and the thermally conductive material, which improves the efficiency of heat dissipation.

Abstract

一种散热结构及其制造方法、芯片结构以及电子设备，属于电子设备技术领域。散热结构包括：外围基板（1）、芯片基板（2）、导热材料（3）与散热器（4）；其中，该外围基板（1）的一端沿芯片基板（2）的周边与芯片基板（2）连接，散热器（4）与外围基板（1）的另一端连接；此外，外围基板（1）、散热器（4）与芯片基板（2）之间具有容纳空间，导热材料（3）填充于容纳空间内，芯片基板（2）用于放置硅片（6）。由于芯片产生的热量只经过硅片（6）和导热材料（3）两个热传导环节即可被扩散出去，热量传导的环节较少，进而减少了热传导环节之间的热阻，即使芯片的功耗增大，芯片产生的热量也可以通过硅片（6）和导热材料（3）实现扩散，提高了热量扩散的效率，改善了散热效果。

Description

散热结构及其制造方法、芯片结构以及电子设备
本申请要求于2020年01月13日提交的申请号为202010032310.7、发明名称为“散热结构及其制造方法、芯片结构以及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子设备技术领域，特别涉及一种散热结构及其制造方法、芯片结构以及电子设备。
背景技术
随着芯片的使用越来越广泛，芯片中容纳的晶体管数量越来越多、晶体管运行速率越来越高，芯片的功耗也越来越大。芯片功耗不断增加会使芯片在运行过程中产生大量的热量，当这些热量导致芯片温度过高时，就会影响芯片的运行，进而使设备运行出现诸多问题。因此，有必要提供一种针对芯片的散热结构。
发明内容
本申请实施例提供了一种散热结构及其制造方法、芯片结构以及电子设备，可解决芯片散热的问题。技术方案如下：
一方面，提供了一种散热结构，该散热结构包括：外围基板、芯片基板、导热材料与散热器；其中，该外围基板的一端沿芯片基板的周边与芯片基板连接，散热器与外围基板的另一端连接；此外，外围基板、散热器与芯片基板之间具有容纳空间，导热材料填充于容纳空间内，芯片基板用于放置硅片。
本申请实施例提供的散热结构，由于芯片产生的热量只经过硅片和导热材料两个热传导环节即可被扩散出去，热量传导的环节较少，进而减少了热传导环节之间的热阻，即使芯片的功耗增大，芯片产生的热量也可以通过硅片和导热材料实现扩散，提高了热量扩散的效率，改善了散热效果。
在示例性实施例中，散热器包括：散热器底片和至少一个散热翅片，每一个散热翅片与散热器底片的一面连接，散热器底片的另一面与外围基板的另一端连接，散热器底片、外围基板与芯片基板之间具有容纳空间。
在示例性实施例中，散热器还包括：连接部，连接部上表面与每一个散热翅片连接，连接部下表面与散热器底片连接；连接部与散热器底片之间具有参考角度。通过设置连接部的一端与散热翅片连接，另一端与散热器底片连接，可以根据需要增加散热翅片的数量。
在示例性实施例中，散热器底片的另一面与外围基板的另一端密封连接。通过设置散热器底片与外围基板之间密封连接，避免导热材料外泄，或与空气接触发生反应。
在示例性实施例中，外围基板的一端沿芯片基板的周边与芯片基板密封连接。通过设置外围基板与芯片基板之间密封连接，避免导热材料外泄，或与空气接触发生反应。
在示例性实施例中，导热材料为液态金属。通过选用液态金属，一方面，减少了热传导环节，可以提高芯片的散热效率，另一方面还可以减少导热材料3与硅片之间的磨损，降低芯片的制备成本。
在示例性实施例中，液态金属为镓或镓合金，其中，镓合金可以是任意含有镓的合金。
在示例性实施例中，镓合金选自镓铝合金、镓铋合金、镓锡合金、镓铟合金、镓铜合金、镓金合金和镓银合金中的至少一种。由于镓与镓合金在芯片工作时的状态为液态，且镓与镓合金的熔点很低，沸点很高。镓与镓合金均可以与硅片很好的结合，结合度较高，可以减少热量由硅片到镓或镓合金的热阻。
在示例性实施例中，硅片与导热材料接触的面为光滑曲面。
还提供了一种芯片结构，该芯片结构包括芯片本体以及设置在芯片本体上的散热结构，该散热结构如上面第一方面任一的散热结构。
还提供了一种电子设备，该电子设备包括电路板，电路板上具有上述的芯片结构，芯片结构包括如上任一的散热结构。
还提供了一种散热结构制造方法，该散热结构包括：外围基板、芯片基板、导热材料与散热器；该方法包括：将外围基板的一端沿芯片基板的周边与芯片基板连接，芯片基板上放置有硅片；将导热材料填充于芯片基板与外围基板形成的容纳空间内；将散热器与外围基板的另一端连接，以封闭容纳空间。
在示例性实施例中，该散热器包括：散热器底片和至少一个散热翅片；将散热器与外围基板的另一端连接，包括：将每一个散热翅片与散热器底片的一面连接，将散热器底片的另一面与外围基板的另一端连接。
在示例性实施例中，散热器还包括：连接部；该方法还包括：将连接部上表面与每一个散热翅片连接，将连接部下表面与散热器底片连接，连接部与散热器底片之间具有参考角度。
附图说明
图1是相关技术提供的散热结构示意图；
图2是本申请实施例提供的散热结构示意图；
图3是本申请实施例提供的散热器的结构示意图；
图4是本申请实施例提供的散热器的结构示意图；
图5是本申请实施例提供的电路板的结构示意图；
图6是本申请实施例提供的电子设备的结构示意图。
具体实施方式
除非另有定义，本申请实施例所用的所有技术术语均具有与本领域技术人员通常理解的相同的含义。为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
随着芯片中容纳晶体管数量越来越多、晶体管运行速率越来越高，导致芯片功耗越来越大，有些芯片功耗已经超过200W，今后还会出现功耗超过400W甚至500W以上的芯片。但是，由于芯片功耗不断增加的同时会产生大量的热量，因此，就需要将芯片产生的大量的热量扩散出去。而大功率芯片的散热问题很难解决，特别是功耗超过250W的芯片，发热功率 越大，散热问题解决越困难，如果不能解决，将导致芯片无法工作，所有芯片和与芯片有关系统的投资将无法转化成应用产品。
相关技术提供的散热结构，如图1所示，硅片放置在芯片基板上，在硅片与芯片盖子之间设置有第一层导热材料，在芯片盖子与散热器之间又设置有第二层导热材料。热量扩散出去时，需要先经过硅片传递至填充在硅片与芯片盖子之间的第一层导热材料，然后依次经过芯片盖子、填充在芯片盖子与散热器之间的第二层导热材料最后到达散热器。相关技术提供的散热结构，虽然可以达到热量扩散的目的，但是热量的扩散需要经过多个热传导环节，而当芯片的功耗增大时，热传导环节之间的热阻则会增大，进而影响热量的扩散，导致芯片温度上升严重，影响设备的正常工作。
对此，本申请实施例提供了一种散热结构，如图2所示，散热结构包括：外围基板1、芯片基板2、导热材料3与散热器4。
外围基板1的一端沿芯片基板2的周边与芯片基板2连接，散热器4与外围基板1的另一端连接。
外围基板1、散热器4与芯片基板2之间具有容纳空间，导热材料3填充于容纳空间内，芯片基板2上用于放置硅片6。
本申请实施例提供的散热结构，由于芯片产生的热量只经过硅片6和导热材料3两个热传导环节即可被扩散出去，热量传导的环节较少，进而减少了热传导环节之间的热阻，即使芯片的功耗增大，芯片产生的热量也可以通过硅片6和导热材料3实现扩散，提高了热量扩散的效率。此外，本申请实施例提供的散热结构可以对功耗达到600W以上芯片实现很好的散热。
示例地，散热结构还可以包括焊球，芯片基板2通过焊球与电路板5连接，进而将芯片固定在电路板5上。
不难看出，相关技术提供的散热结构包括芯片盖子，芯片盖子可以起到支撑散热器4，保护芯片基板2上放置的硅片6的作用，但是当加上芯片盖子后，会增加热传导环节，增加热传导环节的热阻，进而影响热量的扩散。而本申请实施例通过设置外围基板1，可以支撑散热器4的重量，避免散热器4对芯片基板2上的硅片6造成破坏，可以保护硅片6不受破坏。
此外，通过外围基板1、芯片基板2以及散热器4形成封闭的容纳空间，硅片6放置在芯片基板2上，一方面，可以避免硅片6暴露在空气中，起到保护硅片6的作用；另一方面，避免填充在容纳空间的导热材料3外漏或与外界空气或其他物质发生反应，进而影响芯片的正常工作。
在示例性实施例中，该外围基板1的形状可以根据芯片基板2的形状或者电路板5的形状进行确定。示例性地，当芯片基板2的形状为矩形时，外围基板1的形状可以为矩形；当芯片基板2的形状为圆形时，外围基板1的形状可以为圆形。本申请实施例对外围基板1的形状不限于此。
示例性地，外围基板1的宽度可以根据形成芯片的工作需要进行设定，本申请实施例对此不做限定。
需要说明的是，外围基板1、散热器4与芯片基板2之间形成的容纳空间的大小可以根 据芯片基板2的大小进行确定。示例性地，当需要容纳空间较大时，可以设置芯片基板2的尺寸较大。示例性地，容纳空间的大小也可以根据芯片的功耗进行确定，当芯片的功耗较大时，产生的热量会较多，此时容纳空间可以较大，以便容纳更多的导热材料3，提高热量扩散的速率。当芯片的功耗较低时，芯片产生的热量会较少，此时容纳空间较小也可以达到热量扩散的目的，如此，也可以降低散热结构的成本。
在示例性实施例中，如图3所示，散热器4包括：散热器底片41和至少一个散热翅片42，每一个散热翅片42与散热器底片41的一面固定连接，散热器底片41的另一面与外围基板1的另一端连接，散热器底片41、外围基板1与芯片基板2之间具有容纳空间。
需要说明的是，本申请实施例提供的散热结构，在制作芯片时，即可将散热器底片41与外围基板1的另一端连接，形成封闭的容纳空间，以保证放置在芯片基板2上的硅片6不暴露在空气中。
示例性地，每一个散热翅片42可以与散热器底片41一体成型，也可以将散热翅片42焊接在散热器底片41上。本申请实施例对散热翅片42与散热器底片41的连接方式不进行限定。
可以理解的是，相关技术提供的散热结构还包括芯片盖子，芯片盖子与散热器4之间又填充了第二层导热材料，而填充的每层导热材料都会存在热阻，使得硅片6和散热器4之间存在温度差，而温度差会降低散热结构热量的扩散效率。而本申请实施例提供的散热结构用散热器底片41代替了芯片盖子，即不需要再设置芯片盖子。与相关技术相比，本申请实施例提供的散热结构在硅片6与散热器4之间减少了一层热传导环节，进而减少了一层热传导环节之间的热阻，提高了热量扩散的效率。
在示例性实施例中，如图4所示，散热器4还包括：连接部43，连接部43上表面与每一个散热翅片42连接，连接部43下表面与散热器底片41连接；连接部43与散热器底片41之间具有参考角度。
需要说明的是，当芯片的功耗较大时，散热器底片41的大小一定，此时需要较多数量的散热器翅片42以完成芯片散热。因此，通过设置连接部43，并且根据需要设置连接部43的尺寸较大，进而可以使其连接更多的散热翅片42，以满足芯片的散热需求。
作为一种示例，该参考角度可以在180°-90°的范围内，并且，每个散热翅片42固定设置在连接部43的上表面，散热器底片41固定设置在连接部43的下表面。示例性地，每个散热翅片42与连接部43的上表面可以为冲压一体成型，也可以为焊接连接。连接部43与散热器底片41之间可以为冲压一体成型，也可以为焊接连接，本申请实施例对此不进行限定。
在示例性实施例中，散热器底片41的另一面与外围基板1的另一端密封连接。
通过设置散热器底片41的另一面与外围基板1的另一端密封连接，以保证外围基板1、散热器底片41与芯片基板2之间形成的容纳空间的密封性，避免芯片工作时导热材料3泄漏。
在示例性实施例中，散热器底片41的另一面与外围基板1的另一端熔融粘合。
在示例性实施例中，外围基板1的一端沿芯片基板2的周边与芯片基板2密封连接。
同理，由于容纳空间内需要容纳导热材料3，外围基板1不但需要保证导热材料3不暴露在空气外，而且避免散热器4对硅片6造成挤压，还要保证当芯片工作，温度升高时，导热材料3不从外围基板1与芯片基板2之间的缝隙泄漏，因此，设置外围基板1的一端与芯片基板2密封连接。
在示例性实施例中，外围基板1的一端沿芯片基板2的周边与芯片基板2之间熔融粘合。
作为一种示例，当散热器底片41、外围基板1以及芯片基板2的材质均为塑料时，既要达到外围基板1与芯片基板2之间的密封性，又要达到外围基板1与散热器底片41之间的密封性，散热器底片41与外围基板1之间、外围基板1的一端与芯片基板2之间可以采用熔融粘合。
作为另一种示例，当散热器底片41、外围基板1以及芯片基板2的材质均为纯铁时，散热器底片41与外围基板1之间、外围基板1的一端与芯片基板2之间可以采用焊接连接。如此，一方面可以保证散热器底片41与外围基板1之间、外围基板1的一端与芯片基板2之间的密封性，另一方面，还可以提高散热结构的稳定性和牢固性。
作为一种示例，当散热器底片41与外围基板1之间、外围基板1的一端与芯片基板2之间采用焊接连接时，散热器底片41可以通过焊料层焊接在外围基板1上，外围基板1的一端可以通过焊料层焊接在芯片基板2上。示例地，焊料中的焊料可以为锡。由于锡具有较高的导热系数，当作为焊料时不会影响到导热材料3的导热作用，并且，通过设置焊料锡的焊层厚度在参考范围内，可以进一步提高芯片散热的速率，防止大量热量损伤芯片。示例地，焊料层的厚度可以设置在0.1毫米-0.15毫米之间，例如0.1毫米、0.11毫米、0.12毫米、0.13毫米、0.14毫米或0.15毫米等。进一步地，为了尽可能避免芯片工作时，导热材料3溶解焊料锡，可以从外部焊接，尽可能的避免焊料接触导热材料3。
在示例性实施例中，导热材料3为液态金属。
本申请实施例提供的导热材料3为液态金属，即至少在芯片工作时该导热材料的状态为液态。可以理解的是，部分金属在常温，例如25℃的温度下即为液态，即使在0℃以上，也为液态。芯片工作时该金属处于液态状态。或者芯片不工作，但是常温环境下，该金属也为液态。
通过选用液态金属，一方面，减少了热传导环节，可以提高芯片的散热效率，另一方面还可以减少导热材料3与硅片之间的磨损，降低芯片的制备成本。
在示例性实施例中，液态金属为镓或镓合金，其中，镓合金可以是任意含有镓的合金。
可以理解的是，液态金属可以将芯片产生的热量扩散至散热器4。因此，液态金属的选择很重要，既要选择芯片在工作时，该金属可以被液化，即处于液态的金属，又需要该金属具有较高的导热系数，即具有较低的热阻，还可以与硅片6高度结合，高效的扩散热量。金属汞具有很好的导热性，热阻小，但是汞有毒，因此不宜选用汞作为导热材料3。
相反，镓与镓合金在芯片工作时的状态为液态，且镓与镓合金的熔点很低，沸点很高。镓与镓合金均可以与硅片6很好的结合，结合度较高，可以减少热量由硅片6到镓或镓合金的热阻。并且由于镓与镓合金与硅片6的结合度高，因此当镓或镓合金填充在容纳空间内时，不会损坏硅片6，同时也提高了芯片热量扩散的效率。
作为一种示例，液态金属可以单独为镓，也可以为镓合金，也可以为镓与镓合金的混合物。当为镓与镓合金的混合物时，混合比例可以为1:1-2，示例地，可以为1:1或1:2等。本申请实施例对镓与镓合金混合物混合的比例不进行限定。
需要说明的是，相关技术提供的散热结构中，由于散热器4与芯片盖子之间会存在空气，而空气的导热系数很低，热量扩散速率慢。因此，需要在散热器4与芯片盖子之间填充第二层导热材料，以此来提高芯片的散热，但也增加了热传导环节，进而增加了热阻。
而本申请实施例通过在散热器底片41与芯片基板2以及外围基板1形成的容纳空间内填 充镓或镓合金，一方面，避免了在硅片6上设置芯片盖子，减少了热传导环节；另一方面，也避免由于芯片盖子与散热器4之间的空气导热系数低而影响热量扩散效率。
此外，相关技术提供的散热结构，需要在硅片6与芯片盖子之间增加第一层导热材料，以提高芯片的热量扩散，但是由于相关技术提供的第一层导热材料与硅片6的结合度低，与硅片6之间会产生摩擦，损坏硅片6，增加散热结构的制备成本，另一方面，热量扩散效率低。
而本申请实施例提供的散热结构，通过在容纳空间内填充镓或镓合金，不但减少了对硅片6的损坏，还提高了热量扩散的速率，进而降低了散热结构的制备成本。
在示例性实施例中，镓合金选自镓铝合金、镓铋合金、镓锡合金、镓铟合金、镓铜合金、镓金合金和镓银合金中的至少一种。
由于本申请实施例选用的导热材料3为液态金属，即在芯片工作时，导热材料3需为液态，上述镓合金可以在低温下例如0℃为液态，在芯片工作时也保持液态状态，且上述种类的镓合金具有很好的导热性，热阻低，与硅片6的结合度高，可以显著降低与硅片6之间热量扩散的热阻。
作为一种示例，镓合金可以为镓铝合金、镓铋合金、镓锡合金、镓铟合金、镓铜合金、镓金合金和镓银合金中单独一种，也可以为上述任意两种的混合物，例如，镓铝合金与镓铋合金的混合物，或镓铝合金与镓锡合金的混合物，或镓铝合金与镓铟合金的混合物，或镓铋合金与镓锡合金的混合物，或镓锡合金和镓铟合金的混合物，或镓铋合金与镓铟合金的混合物。当镓合金为上述任一两者组合的混合物时，混合比例可以为1:1或1:2。本申请实施例对两者的混合比例不进行限定。镓合金也可以为上述任意三种的混合物，例如，镓铝合金、镓铋合金与镓锡合金三者的混合物，或镓铋合金、镓锡合金和镓铟合金三者的混合物，或镓铝合金、镓锡合金和镓铟合金三者的混合物，混合比例可以为1:1:1或1:2:1。本申请实施例对三者的混合比例不进行限定。镓合金也可以为上述任意四种的混合物，例如，镓铝合金、镓铋合金、镓锡合金和镓铟合金四者的混合物，混合比例可以为1:1:2:1。本申请实施例对四者的混合比例不进行限定。
在示例性实施例中，外围基板1与芯片基板2以及散热器底片41的材质可以为纯铁材质或塑料材质。
由于金属之间有生成合金的趋向，而合金便是不同金属间的互溶现象。一般金属间构成合金需求很高的温度。但有些金属间的互溶并非都需求高温。由于镓的熔点很低，在不到30℃就成为了液态，液态镓能够与其他金属生成合金，也便是可以溶解其他金属，腐蚀其他金属。因此镓不能装在金属容器中。
而金属铁无法与镓直接发生反应，所以高温时液态镓和液态镓合金不与纯铁容器反应。因此本申请实施例提供的外围基板1与芯片基板2以及散热器底片41的材质可以为纯铁材质，也可以是其他金属材料，但是，选择的金属材料需要考虑避免和液态金属之间产生合金的问题。
此外，镓与镓合金不会腐蚀塑料，因此，外围基板1与芯片基板2的材质也可以选用塑料材质。
在示例性实施例中，散热器底片41的材质也可以为塑料材质。由于芯片在工作过程中，导热材料3处于液态状态，散热器底片41也可能会接触到导热材料3，因此，散热器底片41 的材质也可以为塑料材质。
在示例性实施例中，塑料为聚酰亚胺、聚醚醚酮、聚酰胺酰亚胺、聚苯并咪唑、聚醚酰亚胺、聚苯硫醚、聚砜、聚四氟乙烯或聚偏二氟乙烯。
需要说明的是，本申请实施例提供的塑料均为耐高温的热固性塑料，采用耐高温塑料，可以使得外围基板1在芯片工作时，不但能够耐镓或镓合金的溶解和腐蚀，而且在高温下不会变形或溶解。
示例地，聚苯并咪唑长期工作温度可达310℃，短期使用温度可达500℃，因此，选用聚苯并咪唑可以满足芯片高功耗的工作状态。聚酰亚胺长期工作温度可达290℃，短期使用温度可达480℃，也可以在-240℃的环境下工作。聚酰胺酰亚胺也是一种热固性的塑料，长期工作温度可达250℃，同时具有优异的耐磨性能和抗冲击性能。聚醚醚酮长期工作温度可达160℃，短期工作温度可达260℃，具有较好的耐高温性能。聚醚酰亚胺长期工作温度可达170℃，短期工作温度可达200℃。聚苯硫醚长期工作温度可达220℃，短期工作温度可达260℃。聚偏二氟乙烯长期工作温度可达150℃，短期工作温度可达160℃，同时具有优良的耐腐蚀性能，并且具有较高的机械强度和刚性。聚四氟乙烯长期工作温度可达260℃，短期工作温度为280℃，具有优异的耐腐蚀性能，还具有极低的摩擦系数。聚砜长期工作温度150℃，短期工作温度可达180℃。
由此可见，本申请实施例提供的上述塑料均为热固性塑料，且都能在高温下工作，也可以适应低温环境的工作，可以满足芯片在高功耗下的工作需求。
需要说明的是，虽然镓或镓合金可以与其他金属发生互溶，但是由于和某些金属之间的溶解幅度很小，镓或镓合金与其他金属完全溶解所需要的时间很长，即在芯片正常的工作时间内，镓或镓合金与其他金属的溶解不会影响芯片的正常工作。因此，本申请实施例提供的外围基板1与芯片基板2以及散热器底片41的材质也可以为金属，作为一种示例，外围基板1与芯片基板2以及散热器底片41的材质可以为铜，也可以为钢。
在示例性实施例中，导热材料3与散热器4之间可以具有参考间隙。
需要说明的是，本申请实施例提供的导热材料3为液态金属，且该液态金属在芯片工作时，会由固态变为液态，且该液态金属在液态时的密度大于在固态时的密度。因此，当芯片工作时，导热材料3会由固态变为液态，体积减小，当芯片不工作或位于低温环境时，例如零下30℃的环境中，导热材料3会变成固态，体积增大。因此通过在导热材料3与散热器4之间设置有参考间隙，避免导热材料3变为固态时由于容纳空间的容积变小而影响芯片的整体使用功能。
作为一种示例，当导热材料3为镓或镓合金时，镓或镓合金在芯片工作时变为液态，当芯片不工作或处于低温，例如零下30℃时，镓或镓合金变为固态，此时就需要为镓或镓合金预留体积变大的空间。虽然镓或镓合金在30℃以上一般为液态，在0℃时也为液态，即芯片有可能在不工作的情况下镓或镓合金也为液态。但是为了避免芯片的工作环境处于温度极低的情况，例如-20℃或-30℃时，镓或镓合金会变为固态，本申请实施例在导热材料3与散热器4之间设置参考间隙，避免上述情况的发生。
但是由于镓或镓合金从液态至固态变化时，体积变化很小，因此导热材料3与散热器4之间的参考间隙可以不用太大，间隙太大会造成中间存留空气，影响热量的扩散，但是间隙也不能太小，间隙太小，当镓或镓合金由液态变为固态时由于设置的间隙太小，对外围基板 1造成挤压，或对硅片6造成挤压，损坏硅片6。作为一种示例，参考间隙可以为0.1毫米-0.15毫米。例如0.1毫米、0.11毫米、0.12毫米、0.13毫米、0.14毫米或0.15毫米等。
在示例性实施例中，硅片6与导热材料3接触的面为光滑曲面。
通过设置硅片6与导热材料3接触的面为光滑曲面，一方面，可以避免导热材料3对硅片6产生磨损或损坏，另一方面，增加了硅片6与导热材料3的接触面积，提高了硅片6与导热材料3之间的热量扩散速率。
作为一种示例，当导热材料3为镓或镓合金时，通过设置硅片6与导热材料3接触的面为光滑曲面，可以进一步增加镓或镓合金与硅片6的接触面，提高硅片6与镓或镓合金之间的结合度，进而提高热量的扩散，避免多余的热量损坏芯片。
示例地，也可以将硅片6与导热材料3接触的面设置为弧形面。本申请对硅片6与导热材料3接触的面的形状不限于此，只要能达到增加接触面积和提高散热效率的作用即可。
需要说明的是，本申请实施例提供的散热结构，不但可以应用于250W以上大功耗的芯片，也可以应用于功耗较小，例如功耗低于250W的芯片，或者小功耗的芯片在高温环境下的工作，例如汽车电子、无线功放等高温工作环境。
另一方面，本申请实施例还提供了一种芯片结构，该芯片结构包括芯片本体以及设置在芯片本体上的上述任一的散热结构。示例性地，芯片本体包括硅片6。
其中，散热结构采用上述实施例提供的散热结构。散热结构的结构和原理可以参见上述实施例，此处不再赘述。
本实施例中通过在芯片本体的硅片6上设置上述实施例提供的散热结构，由于芯片产生的热量只经过硅片6和导热材料3两个热传导环节，减少了热传导环节，进而减少了热传导环节之间的热阻，即使当芯片的功耗增大时，芯片产生的热量也可以通过硅片6和导热材料3实现传递，提高了热量散出的效率。
还一方面，本申请实施例还提供了一种电路板5，如图5所示，该电路板5上设置有至少一个上述的散热结构。
本申请实施例的电路板5上设置有至少一个上述实施例的芯片结构。
示例地，参见图5，电路板5上设置有至少一个上述实施例的芯片结构，芯片结构与电路板5固定连接。示例地，可以将芯片结构焊接在电路板5上，或通过螺栓固定在电路板5上。对于电路板5上的芯片结构的位置和个数不做限制。例如，可以在电路板5的上表面设置至少一个芯片结构；或者，可以在电路板5的上表面设置至少一个芯片结构，并且，在电路板5的下表面设置至少一个芯片结构。
其中，芯片结构的结构和原理可以参见上述实施例，此处不再赘述。
本申请实施例提供的电路板5，通过在电路板5上设置有至少一个上述实施例的芯片结构，由于芯片产生的热量只经过硅片6和导热材料3两个热传导环节，减少了热传导的环节，进而减少了热传导环节之间的热阻，即使当芯片的功耗增大时，芯片产生的热量也可以通过硅片6和导热材料3实现传递，提高了热量扩散的效率。
再一方面，本申请实施例还提供了一种电子设备，该电子设备中设置有至少一个上述的 电路板5。
图6为本申请实施例提供的电子设备的结构示意图，如图6所示，本申请实施例提供的电子设备中设置有至少一个上述实施例提供的电路板5。电路板5的结构和原理可以参见上述实施例，此处不再赘述。
作为一种示例，电子设备中的各电路板5之间相互并联。
作为一种示例，在电子设备中设置一个或多个电路板5，该电路板5采用上述实施例提供的电路板5。电路板5的结构和功能，可以参见上述实施例的介绍，此处不再赘述。
本实施例中，可以将多个电路板5进行并联，然后将并联的电路板5设置在电子设备中。在一种实施方式中，电子设备可以为服务器。电路板5与电子设备的连接方式可以选择固定连接或滑动连接的方式。示例地，可以在电子设备的机箱上设置有一个或多个滑槽，然后将电路板5设置在滑槽中，使得电路板5可以在滑槽上滑动。其中，在电子设备中设置多个电路板5时，多个电路板5中的每一个电路板5的结构可以相同或不同。每一个电路板5上设置有至少一个上述实施例的芯片结构。其中，芯片结构的结构和原理可以参见上述实施例，此处不再赘述。
本申请实施例提供的电子设备，通过在电子设备中设置上述实施例提供一个或多个的电路板5，在每一个电路板5上设置有至少一个上述实施例的芯片结构，在芯片结构的硅片6上设置上述实施例提供的散热结构。由于芯片产生的热量只经过硅片6和导热材料3两个热传导环节，减少了热传导的环节，进而减少了热传导环节之间的热阻，即使芯片的功耗增大，芯片产生的热量也可以通过硅片6和导热材料3实现传递，提高了热量扩散的效率。
本申请实施例提供了一种散热结构的制造方法，其中，该散热结构包括：外围基板1、芯片基板2、导热材料3与散热器4；关于该散热结构的详细介绍也可参见本申请上述实施例的内容，此处不再赘述。示例性地，该散热结构的制造方法包括如下几个步骤：
步骤11，将外围基板1的一端沿芯片基板2的周边与芯片基板2连接，芯片基板2上放置有硅片6。
示例性地，将外围基板1的一端沿芯片基板2的周边与芯片基板2密封连接。
需要说明的是，将外围基板1的一端沿芯片基板2的周边与芯片基板2连接之前，可以先将硅片6放置于芯片基板2上。除此之外，也可以先将外围基板1的一端沿芯片基板2的周边与芯片基板2连接，再将硅片6放置于芯片基板2上，本申请实施例不对硅片6的放置顺序不进行限定。
步骤12，将导热材料3填充于芯片基板2与外围基板1形成的容纳空间内。
步骤13，将散热器4与外围基板1的另一端连接，以封闭容纳空间。
在示例性实施例中，散热器4包括：散热器底片41和至少一个散热翅片42，因此，将散热器4与外围基板1的另一端连接，包括：将每一个散热翅片42与散热器底片41的一面连接，将散热器底片41的另一面与外围基板1的另一端连接。示例性地，将散热器底片41的另一面与外围基板1的另一端密封连接。
在示例性实施例中，散热器4还包括：连接部43，则该方法还包括：将连接部43上表面与每一个散热翅片42连接，将连接部43下表面与散热器底片41连接；其中，连接部43与散热器底片41之间具有参考角度。
通过该方法制造的散热结构，由于芯片产生的热量只经过硅片和导热材料两个热传导环节，减少了热传导环节，进而减少了热传导环节之间的热阻，即使当芯片的功耗增大时，芯片产生的热量也可以通过硅片和导热材料实现传递，提高了热量散出的效率。
以上制造方法的各个步骤之间的顺序也可以改变，不影响方案的实现。
上述所有可选技术方案，可以采用任意结合形成本申请的可选实施例，在此不再一一赘述。
以上所述仅为本申请的说明性实施例，并不用以限制本申请的保护范围，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (14)

  1. 一种散热结构，其特征在于，所述散热结构包括：外围基板(1)、芯片基板(2)、导热材料(3)与散热器(4)；
    所述外围基板(1)的一端沿所述芯片基板(2)的周边与所述芯片基板(2)连接，所述散热器(4)与所述外围基板(1)的另一端连接；
    所述外围基板(1)、所述散热器(4)与所述芯片基板(2)之间具有容纳空间，所述导热材料(3)填充于所述容纳空间内，所述芯片基板(2)用于放置硅片(6)。
  2. 根据权利要求1所述的散热结构，其特征在于，所述散热器(4)包括：散热器底片(41)和至少一个散热翅片(42)；
    每一个散热翅片(42)与所述散热器底片(41)的一面连接；
    所述散热器底片(41)的另一面与所述外围基板(1)的另一端连接，所述散热器底片(41)、所述外围基板(1)与所述芯片基板(2)之间具有所述容纳空间。
  3. 根据权利要求2所述的散热结构，其特征在于，所述散热器(4)还包括：连接部(43)，所述连接部(43)上表面与每一个散热翅片(42)连接，所述连接部(43)下表面与所述散热器底片(41)连接；
    所述连接部(43)与所述散热器底片(41)之间具有参考角度。
  4. 根据权利要求2或3所述的散热结构，其特征在于，所述散热器底片(41)的另一面与所述外围基板(1)的另一端密封连接。
  5. 根据权利要求1-4任一所述的散热结构，其特征在于，所述外围基板(1)的一端沿所述芯片基板(2)的周边与所述芯片基板(2)密封连接。
  6. 根据权利要求1-5任一所述的散热结构，其特征在于，所述导热材料(3)为液态金属。
  7. 根据权利要求6所述的散热结构，其特征在于，所述液态金属为镓或镓合金。
  8. 根据权利要求7所述的散热结构，其特征在于，所述镓合金选自镓铝合金、镓铋合金、镓锡合金、镓铟合金、镓铜合金、镓金合金和镓银合金中的至少一种。
  9. 根据权利要求1-8任一所述的散热结构，其特征在于，所述硅片(6)与所述导热材料(3)接触的面为光滑曲面。
  10. 一种芯片结构，其特征在于，所述芯片结构包括芯片本体以及设置在所述芯片本体 上散热结构，所述散热结构如所述权利要求1-9任一所述的散热结构。
  11. 一种电子设备，其特征在于，所述电子设备包括电路板，所述电路板上具有权利要求10所述的芯片结构。
  12. 一种散热结构的制造方法，其特征在于，所述散热结构包括：外围基板(1)、芯片基板(2)、导热材料(3)与散热器(4)；所述方法包括：
    将所述外围基板(1)的一端沿所述芯片基板(2)的周边与所述芯片基板(2)连接，所述芯片基板(2)上放置有硅片(6)；
    将所述导热材料(3)填充于所述芯片基板(2)与所述外围基板(1)形成的容纳空间内；
    将所述散热器(4)与所述外围基板(1)的另一端连接，以封闭所述容纳空间。
  13. 根据权利要求12所述的方法，其特征在于，所述散热器(4)包括：散热器底片(41)和至少一个散热翅片(42)；
    所述将所述散热器(4)与所述外围基板(1)的另一端连接，包括：
    将每一个散热翅片(42)与所述散热器底片(41)的一面连接，将所述散热器底片(41)的另一面与所述外围基板(1)的另一端连接。
  14. 根据权利要求13所述的方法，其特征在于，所述散热器(4)还包括：连接部(43)；
    所述方法还包括：
    将所述连接部(43)上表面与每一个散热翅片(42)连接，将所述连接部(43)下表面与所述散热器底片(41)连接，所述连接部(43)与所述散热器底片(41)之间具有参考角度。
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