WO2021142856A1 - 一种电压补偿电路及显示器 - Google Patents

一种电压补偿电路及显示器 Download PDF

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Publication number
WO2021142856A1
WO2021142856A1 PCT/CN2020/073075 CN2020073075W WO2021142856A1 WO 2021142856 A1 WO2021142856 A1 WO 2021142856A1 CN 2020073075 W CN2020073075 W CN 2020073075W WO 2021142856 A1 WO2021142856 A1 WO 2021142856A1
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Prior art keywords
transistor
voltage
drain
source
compensation circuit
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PCT/CN2020/073075
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English (en)
French (fr)
Inventor
郑士嵩
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重庆康佳光电技术研究院有限公司
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Priority to US17/265,215 priority Critical patent/US11657753B2/en
Publication of WO2021142856A1 publication Critical patent/WO2021142856A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • This application relates to the technical field of electronic circuits, and in particular to a voltage compensation circuit and a display.
  • Electroluminescence (EL for short) devices including OLED, LED... and other devices, have been widely used in the production of display products in recent years. Compared with traditional displays (CRT, LCD... etc.), their applications have shown more Good optical characteristics, lower power consumption and better product formability.
  • AM Active Matrix
  • PM Passive Matrix
  • the large electrical load caused by the circuit and the EL device will inevitably cause the IR-drop problem.
  • This problem causes a drop in the voltage value and deviates from the supply voltage value of the original voltage source.
  • This problem directly causes the driving of the EL device.
  • the decrease in cross voltage affects the decrease in the current flowing through the EL device, and finally decreases the brightness, which reflects the decrease in the brightness uniformity of the panel, and the big sign impacts the picture quality of the display.
  • the technical problem to be solved by this application is to provide a voltage compensation circuit to compensate for the decreased voltage value, thereby improving the brightness uniformity of the display and improving the picture quality.
  • an embodiment of the present application provides a voltage compensation circuit, the circuit including:
  • the driving unit is used to drive the electrical excitation light device
  • a light-emitting duration control unit respectively connected to the driving unit and the electro-optical device, for controlling the light-emitting time of the electro-optical device
  • the compensation unit is respectively connected with the driving unit and the light-emitting duration control unit, and is used to provide a compensation voltage for the voltage compensation circuit.
  • a fixed current is input to the compensation unit through an external circuit, the compensation unit receives the fixed current and outputs a compensation voltage to the driving unit, and the driving unit receives the compensation voltage and outputs A stable current passes through the light-emitting duration control unit to the electroluminescent device to drive the electroluminescent device.
  • a first reference voltage is input to the compensation unit, and the compensation unit adjusts the magnitude of the compensation voltage according to the first reference voltage.
  • the compensation unit includes:
  • the gate of the fourth transistor is connected to the first signal control terminal, the source of the fourth transistor is connected to the first reference voltage, and the drain of the fourth transistor is connected to the first terminal of the capacitor;
  • the second terminal of the capacitor is connected to the source of the third transistor, the drain of the third transistor is connected to the source of the second transistor, and the drain of the second transistor is connected to the fixed current input terminal
  • the first signal control terminal is also connected to the gate of the second transistor and the gate of the third transistor, respectively;
  • the source of the fifth transistor is connected to the second reference voltage, the drain of the fifth transistor is connected to the first end of the capacitor, and the gate of the fifth transistor is connected to the second signal control end (the first The gate of the five transistor receives the second control signal).
  • the driving unit includes:
  • the gate of the first transistor is connected to the second end of the capacitor, the source of the first transistor is connected to the power terminal, and the drain of the first transistor is connected to the source of the first switching transistor.
  • the light-emitting duration control unit includes:
  • the source of the first switching transistor is connected to the drain of the first transistor, the drain of the first switching transistor is connected to the source of the second switching transistor, and the gate of the first switching transistor is Connected to the second signal control terminal; the source of the second switching transistor is connected to the drain of the first switching transistor, and the drain of the second switching transistor is connected to the anode of the electroluminescent device , The gate of the second switch transistor is connected to the third signal control terminal; the cathode of the electro-optical device is grounded.
  • the first signal control terminal is used to provide a first control signal
  • the first control signal is used to control the on and off of the second transistor, the third transistor, and the fourth transistor.
  • the second control terminal provides a second control signal for controlling the opening and closing of the fifth transistor and the first switching transistor.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the first switch transistor, and the second switch transistor are all P-type transistors.
  • the compensation unit includes:
  • the gate of the fourth transistor is connected to the first signal control terminal, the source of the fourth transistor is connected to the first reference voltage, and the drain of the fourth transistor is connected to the first end of the capacitor; the capacitor The second terminal of the second transistor is connected to the source of the third transistor, the drain of the third transistor is connected to the source of the second transistor, and the drain of the second transistor is connected to the fixed current input terminal; A signal control terminal is also connected to the gate of the second transistor and the gate of the third transistor respectively;
  • the driving unit includes:
  • the gate of the first transistor is connected to the second end of the capacitor, the source of the first transistor is connected to the drain of the first switching transistor, and the drain of the first transistor is grounded.
  • the light-emitting duration control unit includes:
  • the source of the first switching transistor is connected to the drain of the second switching transistor, the drain of the first switching transistor is connected to the source of the first transistor, and the gate of the first switching transistor is Connected to the second signal control terminal; the drain of the second switching transistor is connected to the source of the first switching transistor, and the source of the second switching transistor is connected to the cathode of the electroluminescent device , The gate of the second switch transistor is connected to the third signal control terminal; the anode of the electroluminescent device is connected to the power terminal.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the first switch transistor, and the second switch transistor are all N-type transistors.
  • an embodiment of the present application provides a display, including: the display includes the above-mentioned voltage compensation circuit.
  • the voltage compensation circuit includes an electro-optical device; a driving unit for driving the electro-optical device; a light-emitting duration control unit, respectively connected to the driving unit and the electro-optical device, for Controlling the light-emitting time of the electroluminescent device; a compensation unit, which is respectively connected with the driving unit and the light-emitting duration control unit, and is used to provide a compensation voltage for the voltage compensation circuit.
  • the voltage compensation circuit in the present application the decreased voltage value is compensated, thereby improving the brightness uniformity of the display and improving the picture quality.
  • FIG. 1 is a schematic structural diagram of a voltage compensation circuit in an embodiment of the application
  • FIG. 2 is a schematic diagram of a voltage compensation circuit in a panel of n rows and m columns in an embodiment of the application;
  • FIG. 3 is a schematic diagram of the structure of a p-type voltage compensation circuit in an embodiment of the application.
  • FIG. 4 is a schematic diagram of signal waveforms of a p-type voltage compensation circuit in an embodiment of the application.
  • FIG. 5 is a schematic diagram of the structure of the first stage voltage compensation circuit of the p-type voltage compensation circuit in the embodiment of the application;
  • FIG. 6 is a schematic diagram of signal waveforms in the first stage of the p-type voltage compensation circuit in an embodiment of the application;
  • FIG. 7 is a schematic structural diagram of the second stage voltage compensation circuit of the p-type voltage compensation circuit in an embodiment of the application.
  • FIG. 8 is a schematic diagram of a second stage signal waveform of the p-type voltage compensation circuit in an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of an n-type voltage compensation circuit in an embodiment of the application.
  • Da Fu impacted the picture quality of the monitor.
  • the fixed current input terminal is used to adjust the current signal
  • the pixel circuit architecture of 7T1C (7 Transistor and 1 Capacitor) is combined to compensate for the dropped voltage value, so as to realize the external compensation circuit system (External Compensation Circuit and System) to improve the brightness uniformity of the display and improve the picture quality.
  • the voltage compensation circuit includes:
  • Electric excitation light device (EL device) 10 Electric excitation light device (EL device) 10;
  • the driving unit 12 is used to drive the electric excitation light device 10;
  • the light-emitting duration control unit 14 is respectively connected to the driving unit 12 and the electro-optical device 10, and is used to control the light-emitting time of the electro-optical device;
  • the compensation unit 16 is connected to the driving unit 12 and the light-emitting duration control unit 14 respectively, and is used to provide a compensation voltage for the voltage compensation circuit.
  • the present invention inputs a fixed current to the compensation unit 16 through an external circuit, the compensation unit 16 receives the fixed current and outputs a compensation voltage to the driving unit 12, and the driving unit 12 receives the compensation voltage And output a stable current to the electro-optical device 10 after the light-emitting duration control unit 14 to drive the electro-optical device 10. Voltage compensation is performed to compensate for the voltage drop caused by the electrical load, thereby improving The problem of brightness uniformity of the display is solved, and the picture display quality is improved.
  • the compensation unit 16 can adjust the magnitude of the compensation voltage according to the first reference voltage VREF1. Furthermore, by inputting a second reference voltage VREF2 to the compensation unit 16, the driving unit 12 obtains an adjustable cross-voltage, and outputs a stable current after passing through the light-emitting duration control unit 14 to the compensation unit 16.
  • the electro-optical device 10 is used to drive the electro-optical device 10.
  • the circuit architecture is established in the nth row and m column in the panel, and its row control signals are S1 and EM, which are used for the functional operation of this pixel circuit, and in its relatively vertical
  • the column control signal of the direction is SEL, which is the PWM function signal used to control the light-emitting time of the EL device.
  • the key IS signal provides an adjustable constant current signal, which is connected to the external circuit (usually connected to the DDIC/display driver chip) to achieve The external compensation circuit system can improve the voltage drop caused by IR-drop.
  • the voltage compensation circuit includes 7 TFT or MOS active devices, including 1 capacitive device, 3 circuit control signals, IS[m] is an adjustable constant current signal.
  • the circuit architecture of n-type differs in the connection position of EL devices and other (including active and passive devices) devices.
  • the connection method of the voltage compensation circuit is as follows:
  • the compensation unit 16 includes:
  • the gate of the fourth transistor T4 is connected to the first signal control terminal (the gate of the fourth transistor receives the first control signal S1), the source of the fourth transistor T4 is connected to the first reference voltage VREF1, the The drain of the fourth transistor T4 is connected to the first end of the capacitor C; the second end of the capacitor C is connected to the source of the third transistor T3, and the drain of the third transistor T3 is connected to the The source of the second transistor T2 is connected, and the drain of the second transistor T2 is connected to the fixed current input terminal (the fixed current input terminal is input with an adjustable constant current signal IS); the first signal control terminal is also Respectively connected to the gate of the second transistor T2 and the gate of the third transistor T3;
  • the source of the fifth transistor T5 is connected to the second reference voltage VREF2, the drain of the fifth transistor T5 is connected to the first end of the capacitor C, and the gate of the fifth transistor T5 is connected to the second signal
  • the control terminal is connected (the gate of the fifth transistor receives the second control signal EM).
  • the driving unit 12 includes:
  • the first transistor T1 The first transistor T1;
  • the gate of the first transistor T1 is connected to the second end of the capacitor C, the source of the first transistor T1 is connected to the power supply terminal VDD, and the drain of the first transistor T1 is connected to the first switching transistor T6.
  • the source connection is not
  • the light-emitting duration control unit 14 includes:
  • the source of the first switching transistor T6 is connected to the drain of the first transistor T1, the drain of the first switching transistor T6 is connected to the source of the second switching transistor T7, and the first switch
  • the gate of the transistor T6 is connected to the second signal control terminal (the gate of the first switching transistor receives the second control signal EM); the source of the second switching transistor T7 and the drain of the first switching transistor T6
  • the drain of the second switching transistor T7 is connected to the anode of the electroluminescence device EL, and the gate of the second switching transistor is connected to the third signal control terminal (the gate of the second switching transistor receives The third control signal SEL); the cathode of the electro-optical device EL is grounded to VSS.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the first switching transistor T6, and the second switching transistor T7 are all P-type transistors.
  • the first control signal S1[n] (active low) is used to control the opening and closing of the second transistor T2, the third transistor T3 and the fourth transistor T4, and the second control signal EM[n] (active low) Used to control the opening and closing of the fifth transistor T5 and the sixth switching transistor T6, the third control signal SEL[m] (normally closed) is a PWM function signal used to control the light-emitting time of the EL device.
  • the sequence action includes the following two stages:
  • the first stage Please refer to Figure 5 and Figure 6.
  • the first control signal S1 since the first control signal S1 is low (active low), the first transistor T1 and the second transistor T2 , The third transistor T3 and the fourth transistor T4 are in the open state. Because the second control signal EM is at a high level, the fifth transistor T5 and the sixth switching transistor T6 are in the off state (" ⁇ " in FIG. 6 Indicates the closed state).
  • the present invention is connected to an external circuit through IS[m] (first control signal) to supply an adjustable fixed current source to determine the Vgs voltage value of the first transistor T1 to complete the compensation function, because the power supply terminal VDD participates in this current path , This voltage value achieves the purpose of compensating the voltage drop caused by IR-drop. More specifically, the relationship between the nodes can be expressed by the following formula:
  • Va VDD-Vth-VIS: Compensation voltage writing, VIS is determined by the current of IS[m].
  • Vb VREF1: Pull to a fixed reference potential, which can be used to adjust the current output size.
  • Second stage As shown in Figures 7 and 8, in the second stage, that is, at time T2, since the first control model S1 is at a high level, the first transistor T1, the second transistor T2, the third transistor T3 and the The fourth transistor T4 is in an off state, and because the second control signal EM is at a low level, the fifth transistor T5 and the sixth switching transistor T6 are in an on state.
  • the second switching transistor T7 is used as a time controller for controlling the current passing through the EL device, and corresponds to the light-emitting brightness and gray scale. More specifically, the relationship between the nodes can be expressed by the following formula:
  • Va VDD-Vth-VIS + (VREF2-VREF1), the final output compensation voltage value.
  • Vb VREF2
  • the voltage difference from VREF1 to VREF2 is coupled to T1 through C.
  • the transistors in the circuit are N-type transistors, that is, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, Both the first switching transistor T6 and the second switching transistor T7 are N-type transistors.
  • the connection method of the voltage compensation circuit is as follows:
  • the compensation unit 16 includes:
  • the gate of the fourth transistor T4 is connected to the first signal control terminal (the gate of the fourth transistor receives the first control signal S1), the source of the fourth transistor T4 is connected to the first reference voltage VREF1, and the fourth transistor T4 is connected to the first reference voltage VREF1.
  • the drain of the transistor T4 is connected to the first terminal of the capacitor C; the second terminal of the capacitor C is connected to the source of the third transistor T3, and the drain of the third transistor T3 is connected to the second terminal.
  • the source of the transistor T2 is connected, and the drain of the second transistor T2 is connected to the fixed current input terminal (the fixed current input terminal is an adjustable constant current signal IS); the first signal control terminal is also connected to the The gate of the second transistor T2 is connected to the gate of the third transistor T3;
  • the source of the fifth transistor T5 is connected to the second reference voltage VREF2, and the drain of the fifth transistor T5 is connected to the first end of the capacitor C.
  • the driving unit 12 includes:
  • the first transistor T1 The first transistor T1;
  • the gate of the first transistor T1 is connected to the second end of the capacitor C, the source of the first transistor T1 is connected to the drain of the first switching transistor T6, and the drain of the first transistor T1 is grounded .
  • the light-emitting duration control unit 14 includes:
  • the source of the first switching transistor T6 is connected to the drain of the second switching transistor T7, the drain of the first switching transistor T6 is connected to the source of the first transistor T1, and the first switch
  • the gate of the transistor T6 is connected to the second signal control terminal (the gate of the first switching transistor receives the second control signal EM); the drain of the second switching transistor T7 is connected to the source of the first switching transistor T6
  • the source of the second switching transistor T7 is connected to the cathode of the electroluminescent device EL, and the gate of the second switching transistor T7 is connected to the third signal control terminal (the gate of the second switching transistor Receive the third control signal SEL); the anode of the electroluminescent device EL is connected to the power supply terminal VDD.
  • the voltage compensation circuit of the present application uses IS[m] to adjust the current signal, combined with the pixel circuit architecture of 7T1C (7 Transistors and 1 Capacitor) to compensate for the decreased voltage value, so as to realize the external compensation circuit system (External Compensation Circuit and System), which solves the problem of the brightness uniformity of the display and improves the picture quality.
  • the present application provides a display including the above-mentioned voltage compensation circuit.

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Abstract

本申请涉及一种电压补偿电路及显示器，所述电压补偿电路包括：电激发光器件；驱动单元，用于驱动电激发光器件；发光时长控制单元，与所述驱动单元和所述电激发光器件分别连接，用于控制电激发光器件的发光时间；补偿单元，与所述驱动单元和所述发光时长控制单元分别连接，用于为所述电压补偿电路提供补偿电压。通过本申请中的电压补偿电路，补偿下降的电压值，从而改善了显示器的亮度均匀性，提高了画面质量。

Description

一种电压补偿电路及显示器 技术领域
本申请涉及电子电路技术领域，特别是涉及一种电压补偿电路及显示器。
背景技术
电激发光(Electroluminescence，简称为EL)器件，包括OLED、LED…等器件，近年来被大量用于制作显示器产品，相较于传统的显示器(CRT、LCD…等)，其应用面展现了更好的光学特性、更低的功耗以及更好的产品型态可塑性。由于电激发光器件为电流驱动属性所致，当用于制作显示器时，搭配典型的主动式矩阵(ActiveMatrix，简称为AM)或是被动式矩阵(Passive Matrix，简称为PM)驱动方法，因受到电流经过线路及EL器件而引起的大电性负载，而必然产生IR-drop问题，该问题引起了电压值的下降，偏离了原始电压源的供应电压值，而此问题直接造成了EL器件的驱动跨压降低，而影响了其流经EL器件的电流下降，最终使亮度降低，反应至面板的亮度均匀性(Brightness Uniformity)下降，大符冲击了显示器的画面质量。
因此，现有技术有待改进。
发明内容
本申请要解决的技术问题是，提供一种电压补偿电路，补偿下降的电压值，从而改善了显示器的亮度均匀性，提高了画面质量。
第一方面，本申请实施例提供了一种电压补偿电路，所述电路包括：
电激发光器件；
驱动单元，用于驱动电激发光器件；
发光时长控制单元，与所述驱动单元和所述电激发光器件分别连接，用于控制电激发光器件的发光时间；
补偿单元，与所述驱动单元和所述发光时长控制单元分别连接，用于为所述电压补偿电路提供补偿电压。
可选地，通过一外部电路输入一固定电流至所述补偿单元，所述补偿单元接 收所述固定电流并输出一补偿电压经至所述驱动单元，所述驱动单元接收所述补偿电压并输出一稳定电流经所述发光时长控制单元后至所述电激发光器件以驱动所述电激发光器件。
可选地，输入一第一参考电压至所述补偿单元，所述补偿单元根据所述第一参考电压调节所述补偿电压的大小。
可选地，输入一第二参考电压至所述补偿单元，以使所述驱动单元获得一可调节跨压，并输出一稳定电流经所述发光时长控制单元后至所述电激发光器件以驱动所述电激发光器件。
可选地，所述补偿单元，包括：
第二晶体管、第三晶体管、第四晶体管、第五晶体管和电容；
所述第四晶体管的栅极与第一信号控制端连接，所述第四晶体管的源极与第一参考电压连接，所述第四晶体管的漏极与所述电容的第一端连接；所述电容的第二端与所述第三晶体管的源极连接，所述第三晶体管的漏极与所述第二晶体管的源极连接，所述第二晶体管的漏极与固定电流输入端连接；所述第一信号控制端还分别与所述第二晶体管的栅极和所述第三晶体管的栅极连接；
所述第五晶体管的源极与第二参考电压连接，所述第五晶体管的漏极与所述电容的第一端连接，所述第五晶体管的栅极与第二信号控制端连接(第五晶体管的栅极接收第二控制信号)。
可选地，所述驱动单元，包括：
第一晶体管；
所述第一晶体管的栅极与所述电容的第二端连接，所述第一晶体管的源极与电源端连接，所述第一晶体管的漏极与第一开关晶体管的源极连接。
可选地，所述发光时长控制单元，包括：
第一开关晶体管和第二开关晶体管；
所述第一开关晶体管的源极与所述第一晶体管的漏极连接，所述第一开关晶体管的漏极与所述第二开关晶体管的源极连接，所述第一开关晶体管的栅极与所述第二信号控制端连接；所述第二开关晶体管的源极与所述第一开关晶体管的漏极连接，所述第二开关晶体管的漏极与所述电激发光器件的阳极连接，所述第二开关晶体管的栅极与第三信号控制端连接；所述电激发光器件的阴极接地。
可选地，所述第一信号控制端用于提供一第一控制信号，所述第一控制信号用于控制所述第二晶体管、所述第三晶体管和所述第四晶体管的启闭。
可选地，所述第二控制端提供一第二控制信号，用于控制所述第五晶体管和所述第一开关晶体管的启闭。
可选地，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一开关晶体管和第二开关晶体管均为P型晶体管。
可选地，所述补偿单元，包括：
第二晶体管、第三晶体管、第四晶体管、第五晶体管和电容；
所述第四晶体管的栅极与第一信号控制端连接，所述第四晶体管的源极与第一参考电压连接，第四晶体管的漏极与所述电容的第一端连接；所述电容的第二端与所述第三晶体管的源极连接，所述第三晶体管的漏极与所述第二晶体管的源极连接，所述第二晶体管的漏极与固定电流输入端连接；第一信号控制端还分别与所述第二晶体管的栅极和所述第三晶体管的栅极连接；
所述第五晶体管的源极与第二参考电压连接，所述第五晶体管的漏极与所述电容的第一端连接。
可选地，所述驱动单元，包括：
第一晶体管；
所述第一晶体管的栅极与所述电容的第二端连接，所述第一晶体管的源极与第一开关晶体管的漏极连接，所述第一晶体管的漏极接地。
可选地，所述发光时长控制单元，包括：
第一开关晶体管和第二开关晶体管；
所述第一开关晶体管的源极与所述第二开关晶体管的漏极连接，所述第一开关晶体管的漏极与所述第一晶体管的源极连接，所述第一开关晶体管的栅极与所述第二信号控制端连接；所述第二开关晶体管的漏极与所述第一开关晶体管的源极连接，所述第二开关晶体管的源极与所述电激发光器件的阴极连接，所述第二开关晶体管的栅极与第三信号控制端连接；所述电激发光器件的阳极与电源端连接。
可选地，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一开关晶体管和第二开关晶体管均为N型晶体管。
第二方面，本申请实施例提供了一种显示器，包括：所述显示器包括上述的电压补偿电路。
与现有技术相比，本申请实施例具有以下优点：
根据本申请实施方式提供的电压补偿电路，包括电激发光器件；驱动单元，用于驱动电激发光器件；发光时长控制单元，与所述驱动单元和所述电激发光器件分别连接，用于控制电激发光器件的发光时间；补偿单元，与所述驱动单元和所述发光时长控制单元分别连接，用于为所述电压补偿电路提供补偿电压。通过本申请中的电压补偿电路，补偿下降的电压值，从而改善了显示器的亮度均匀性，提高了画面质量。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中一种电压补偿电路的结构示意图；
图2为本申请实施例中n行m列面板中的一个电压补偿电路的示意图；
图3为本申请实施例中p-type电压补偿电路的结构示意图；
图4为本申请实施例中p-type电压补偿电路的信号波形示意图；
图5为本申请实施例中p-type电压补偿电路的第一阶段电压补偿电路的结构示意图；
图6为本申请实施例中p-type电压补偿电路的第一阶段信号波形示意图；
图7为本申请实施例中p-type电压补偿电路的第二阶段电压补偿电路的结构示意图；
图8为本申请实施例中p-type电压补偿电路的第二阶段信号波形示意图；
图9为本申请实施例中n-type电压补偿电路的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例 中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
发明人经过研究发现，现有线路设计，在典型EL显示器的AM或PM驱动方法下，因其本质产生的IR-drop(电压降)问题，该问题引起了电压值的下降，偏离了原始电压源的供应电压值，而此问题直接造成了EL器件的驱动跨压降低，而影响了其流经EL器件的电流下降，最终使亮度降低，反应至面板的亮度均匀性(Brightness Uniformity)下降，大符冲击了显示器的画面质量。
为了解决上述问题，在本申请实施例中，利用固定电流输入端调整电流信号，结合7T1C(7个Transistor及1个Capacitor)的像素电路架构补偿其下降的电压值，实现外部补偿电路系统(External Compensation Circuit and System)，改善显示器的亮度均匀性的问题，提高了画面质量。
下面结合附图，详细说明本申请的各种非限制性实施方式。
本申请实施例提供了一种电压补偿电路，如图1所示，所述电压补偿电路包括：
电激发光器件(EL器件)10；
驱动单元12，用于驱动电激发光器件10；
发光时长控制单元14，与所述驱动单元12和所述电激发光器件10分别连接，用于控制电激发光器件的发光时间；
补偿单元16，与所述驱动单元12和所述发光时长控制单元14分别连接，用于为所述电压补偿电路提供补偿电压。
本发明通过一外部电路输入一固定电流至所述补偿单元16，所述补偿单元16接收所述固定电流并输出一补偿电压经至所述驱动单元12，所述驱动单元12接收所述补偿电压并输出一稳定电流经所述发光时长控制单元14后至所述电激发光器件10以驱动所述电激发光器件10，通过进行电压补偿以补偿因电性负载引起的电压降问题，从而改善了显示器亮度均匀性的问题，提高了画面显示质量。
进一步地，请结合图3，通过输入一第一参考电压VREF1至所述补偿单元16，所述补偿单元16可根据所述第一参考电压VREF1调节所述补偿电压的大小。 更进一步地，通过输入一第二参考电压VREF2至所述补偿单元16，以使所述驱动单元12获得一可调节跨压，并输出一稳定电流经所述发光时长控制单元14后至所述电激发光器件10以驱动所述电激发光器件10。
如图2所示，电路架构建立于面板内第n个行(row)及m个列(column)，其row控制信号为S1和EM，作为此像素电路的功能操作用途，而在其相对垂直方向的column控制信号为SEL，为PWM功能信号用来控制EL器件的发光时间，关键的IS信号提供一可调整的定电流信号，连接至外部电路(通常连接到DDIC/显示驱动芯片)，实现外部补偿电路系统，改善因IR-drop所引起的电压降问题。
在本申请实施例中，有两种类型的电压补偿电路：p-type和n-type。电压补偿电路中包括7个TFT或MOS主动器件包括1个电容器件，3个电路控制信号，IS[m]为一可调整的定电流信号。n-type的电路架构相比于p-type，差异为EL器件与其他(含主动及被动器件)器件的连接位置差异。
若电压补偿电路的类型为p-type，则电路中的晶体管为P型晶体管。如图3所示，电压补偿电路的连接方式如下：
所述补偿单元16，包括：
第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和电容C；
所述第四晶体管T4的栅极与第一信号控制端连接(第四晶体管的栅极接收第一控制信号S1)，所述第四晶体管T4的源极与第一参考电压VREF1连接，所述第四晶体管T4的漏极与所述电容C的第一端连接；所述电容C的第二端与所述第三晶体管T3的源极连接，所述第三晶体管T3的漏极与所述第二晶体管T2的源极连接，所述第二晶体管T2的漏极与固定电流输入端连接(固定电流输入端输入的为一可调整的定电流信号IS)；所述第一信号控制端还分别与所述第二晶体管T2的栅极和所述第三晶体管T3的栅极连接；
所述第五晶体管T5的源极与第二参考电压VREF2连接，所述第五晶体管T5的漏极与所述电容C的第一端连接，所述第五晶体管T5的栅极与第二信号控制端连接(第五晶体管的栅极接收第二控制信号EM)。
所述驱动单元12，包括：
第一晶体管T1；
所述第一晶体管T1的栅极与所述电容C的第二端连接，所述第一晶体管T1的源极与电源端VDD连接，所述第一晶体管T1的漏极与第一开关晶体管T6的源极连接。
所述发光时长控制单元14，包括：
第一开关晶体管T6和第二开关晶体管T7；
所述第一开关晶体管T6的源极与所述第一晶体管T1的漏极连接，所述第一开关晶体管T6的漏极与所述第二开关晶体管T7的源极连接，所述第一开关晶体管T6的栅极与所述第二信号控制端连接(第一开关晶体管的栅极接收第二控制信号EM)；所述第二开关晶体管T7的源极与所述第一开关晶体管T6的漏极连接，所述第二开关晶体管T7的漏极与所述电激发光器件EL的阳极连接，所述第二开关晶体管的栅极与第三信号控制端连接(第二开关晶体管的栅极接收第三控制信号SEL)；所述电激发光器件EL的阴极接地VSS。
具体地，所述第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第一开关晶体管T6和第二开关晶体管T7均为P型晶体管。
为更好地理解本发明，以p-type类型的电压补偿电路为例，结合时序动作对其工作过程说明，如图4所示，图4为p-type电压补偿电路的信号波形示意图，其中，第一控制信号S1[n](低电平有效)用于控制第二晶体管T2、第三晶体管T3与第四晶体管T4的启闭，第二控制信号EM[n](低电平有效)用于控制第五晶体管T5和第六开关晶体管T6的启闭，第三控制信号SEL[m](常闭)为PWM功能信号用于控制EL器件的发光时间。具体地，时序动作包括如下两个阶段：
第一阶段：请结合图5和图6所示，在第一阶段，即T1时刻，由于第一控制信号S1为低电平(低电平有效)，因而第一晶体管T1、第二晶体管T2、第三晶体管T3与第四晶体管T4处于打开状态，由于第二控制信号EM为高电平，因而所述第五晶体管T5和第六开关晶体管T6处于断开状态(图6中的“×”表示关闭状态)。本发明透过IS[m](第一控制信号)连结至外部电路，供应可调整的固定电流源，以决定第一晶体管T1的Vgs电压值，完成补偿功能，因电源端VDD参与此电流路径，此电压值达成补偿IR-drop引起的电压降的目的。更具体地，可以通过下式来表达各节点之间的关系：
Va＝VDD-Vth-VIS：补偿电压写入，VIS决定于IS[m]的电流大小。
Vb＝VREF1：拉至一参考固定电位，可用作电流输出大小的调节功能。
第二阶段：如图7和图8所示，在第二阶段，即在T2时刻，由于第一控制型号S1为高电平，因而第一晶体管T1、第二晶体管T2、第三晶体管T3与第四晶体管T4处于断开状态，由于第二控制信号EM为低电平，因而所述第五晶体管T5和第六开关晶体管T6处于打开状态。本发明通过写入第二参考电压VREF2，并通过电容C耦合使第一晶体管T1得到一可调节跨压，使得第一晶体管T1可输出一稳定电流，以达到EL器件所需的发光亮度，而第二开关晶体管T7做为控制电流通过EL器件的时间控制器，对应出发光亮度及灰阶。更具体地，可以通过下式来表达各节点之间的关系：
Va＝VDD-Vth-VIS+(VREF2–VREF1)，最终输出的补偿电压值。
Vb＝VREF2，透过C耦合VREF1至VREF2的压差至T1。
最后，IEL＝k x(VDD–Va-Vth) 2＝k x(VIS+VREF1–VREF2) 2，此式无VDD的参数因子，因此不受VDD压降的影响，完成补偿电流输出。
若电压补偿电路的类型为n-type，则电路中的晶体管为N型晶体管,也即所述第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第一开关晶体管T6和第二开关晶体管T7均为N型晶体管。如图9所示，电压补偿电路的连接方式如下：
所述补偿单元16，包括：
第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和电容C；
所述第四晶体管T4的栅极与第一信号控制端连接(第四晶体管的栅极接收第一控制信号S1)，所述第四晶体管T4的源极与第一参考电压VREF1连接，第四晶体管T4的漏极与所述电容C的第一端连接；所述电容C的第二端与所述第三晶体管T3的源极连接，所述第三晶体管T3的漏极与所述第二晶体管T2的源极连接，所述第二晶体管T2的漏极与固定电流输入端连接(固定电流输入端输入的为一可调整的定电流信号IS)；第一信号控制端还分别与所述第二晶体管T2的栅极和所述第三晶体管T3的栅极连接；
所述第五晶体管T5的源极与第二参考电压VREF2连接，所述第五晶体管T5的漏极与所述电容C的第一端连接。
所述驱动单元12，包括：
第一晶体管T1；
所述第一晶体管T1的栅极与所述电容C的第二端连接，所述第一晶体管T1的源极与第一开关晶体管T6的漏极连接，所述第一晶体管T1的漏极接地。
所述发光时长控制单元14，包括：
第一开关晶体管T6和第二开关晶体管T7；
所述第一开关晶体管T6的源极与所述第二开关晶体管T7的漏极连接，所述第一开关晶体管T6的漏极与所述第一晶体管T1的源极连接，所述第一开关晶体管T6的栅极与所述第二信号控制端连接(第一开关晶体管的栅极接收第二控制信号EM)；所述第二开关晶体管T7的漏极与所述第一开关晶体管T6的源极连接，所述第二开关晶体管T7的源极与所述电激发光器件EL的阴极连接，所述第二开关晶体管T7的栅极与第三信号控制端连接(第二开关晶体管的栅极接收第三控制信号SEL)；所述电激发光器件EL的阳极与电源端VDD连接。
基于典型显示器驱动方法及线路设计，其因采用共电源，除面板边缘的像素点外，显示区内的像素供电，透过线路的直接布线，且EL器件于操作用于发光时，所提供的大电性负载，致使在显示区内的像素点会产生不同的电压降，反应至亮度的直接下降，亮度均匀性劣化。
而本申请的电压补偿电路，利用IS[m]此调整电流信号，结合7T1C(7个Transistor及1个Capacitor)的像素电路架构补偿其下降的电压值，实现外部补偿电路系统(External Compensation Circuit and System)，解决了显示器的亮度均匀性的问题，提高了画面质量。
本申请提供了一种显示器，所述显示器包括上述的电压补偿电路。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种电压补偿电路，其特征在于，所述电路包括：
    电激发光器件；
    驱动单元，用于驱动电激发光器件；
    发光时长控制单元，与所述驱动单元和所述电激发光器件分别连接，用于控制电激发光器件的发光时间；
    补偿单元，与所述驱动单元和所述发光时长控制单元分别连接，用于为所述电压补偿电路提供补偿电压。
  2. 根据权利要求1所述的电压补偿电路，其特征在于，通过一外部电路输入一固定电流至所述补偿单元，所述补偿单元接收所述固定电流并输出一补偿电压经至所述驱动单元，所述驱动单元接收所述补偿电压并输出一稳定电流经所述发光时长控制单元后至所述电激发光器件以驱动所述电激发光器件。
  3. 根据权利要求1所述的电压补偿电路，其特征在于，输入一第一参考电压至所述补偿单元，所述补偿单元根据所述第一参考电压调节所述补偿电压的大小。
  4. 根据权利要求2所述的电压补偿电路，其特征在于，输入一第二参考电压至所述补偿单元，以使所述驱动单元获得一可调节跨压，并输出一稳定电流经所述发光时长控制单元后至所述电激发光器件以驱动所述电激发光器件。
  5. 根据权利要求4所述的电压补偿电路，其特征在于，所述补偿单元，包括：
    第二晶体管、第三晶体管、第四晶体管、第五晶体管和电容；
    所述第四晶体管的栅极与第一信号控制端连接，所述第四晶体管的源极与第一参考电压连接，所述第四晶体管的漏极与所述电容的第一端连接；所述电容的第二端与所述第三晶体管的源极连接，所述第三晶体管的漏极与所述第二晶体管的源极连接，所述第二晶体管的漏极与固定电流输入端连接；所述第一信号控制端还分别与所述第二晶体管的栅极和所述第三晶体管的栅极连接；
    所述第五晶体管的源极与第二参考电压连接，所述第五晶体管的漏极与所述电容的第一端连接，所述第五晶体管的栅极与第二信号控制端连接。
  6. 根据权利要求5所述的电压补偿电路，其特征在于，所述驱动单元，包括：
    第一晶体管；
    所述第一晶体管的栅极与所述电容的第二端连接，所述第一晶体管的源极与电源端连接，所述第一晶体管的漏极与第一开关晶体管的源极连接。
  7. 根据权利要求6所述的电压补偿电路，其特征在于，所述发光时长控制单元，包括：
    第一开关晶体管和第二开关晶体管；
    所述第一开关晶体管的源极与所述第一晶体管的漏极连接，所述第一开关晶体管的漏极与所述第二开关晶体管的源极连接，所述第一开关晶体管的栅极与所述第二信号控制端连接；所述第二开关晶体管的源极与所述第一开关晶体管的漏极连接，所述第二开关晶体管的漏极与所述电激发光器件的阳极连接，所述第二开关晶体管的栅极与第三信号控制端连接；所述电激发光器件的阴极接地。
  8. 根据权利要求5所述的电压补偿电路，其特征在于，所述第一信号控制端用于提供一第一控制信号，所述第一控制信号用于控制所述第二晶体管、所述第三晶体管和所述第四晶体管的启闭。
  9. 根据权利要求7所述的电压补偿电路，其特征在于，所述第二控制端提供一第二控制信号，用于控制所述第五晶体管和所述第一开关晶体管的启闭。
  10. 根据权利要求7所述的电压补偿电路，其特征在于，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一开关晶体管和第二开关晶体管均为P型晶体管。
  11. 根据权利要求4所述的电压补偿电路，其特征在于，所述补偿单元，包括：
    第二晶体管、第三晶体管、第四晶体管、第五晶体管和电容；
    所述第四晶体管的栅极与第一信号控制端连接，所述第四晶体管的源极与第一参考电压连接，第四晶体管的漏极与所述电容的第一端连接；所述电容的第二端与所述第三晶体管的源极连接，所述第三晶体管的漏极与所述第二晶体管的源极连接，所述第二晶体管的漏极与固定电流输入端连接；第一信号控制端还分别与所述第二晶体管的栅极和所述第三晶体管的栅极连接；
    所述第五晶体管的源极与第二参考电压连接，所述第五晶体管的漏极与所述电容的第一端连接。
  12. 根据权利要求11所述的电压补偿电路，其特征在于，所述驱动单元，包括：
    第一晶体管；
    所述第一晶体管的栅极与所述电容的第二端连接，所述第一晶体管的源极与第一开关晶体管的漏极连接，所述第一晶体管的漏极接地。
  13. 根据权利要求12所述的电压补偿电路，其特征在于，所述发光时长控制单元，包括：
    第一开关晶体管和第二开关晶体管；
    所述第一开关晶体管的源极与所述第二开关晶体管的漏极连接，所述第一开关晶体管的漏极与所述第一晶体管的源极连接，所述第一开关晶体管的栅极与所述第二信号控制端连接；所述第二开关晶体管的漏极与所述第一开关晶体管的源极连接，所述第二开关晶体管的源极与所述电激发光器件的阴极连接，所述第二开关晶体管的栅极与第三信号控制端连接；所述电激发光器件的阳极与电源端连接。
  14. 根据权利要求13所述的电压补偿电路，其特征在于，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一开关晶体管和第二开关晶体管均为N型晶体管。
  15. 一种显示器，其特征在于，所述显示器包括权利要求1至14中任意一项所述的电压补偿电路。
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