WO2021142586A1 - Procédé, dispositif et appareil de transmission de données, mcu et support de stockage - Google Patents

Procédé, dispositif et appareil de transmission de données, mcu et support de stockage Download PDF

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Publication number
WO2021142586A1
WO2021142586A1 PCT/CN2020/071827 CN2020071827W WO2021142586A1 WO 2021142586 A1 WO2021142586 A1 WO 2021142586A1 CN 2020071827 W CN2020071827 W CN 2020071827W WO 2021142586 A1 WO2021142586 A1 WO 2021142586A1
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Prior art keywords
data
transmission
transmitted
interface module
data transmission
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PCT/CN2020/071827
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English (en)
Chinese (zh)
Inventor
刘瑛
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2020/071827 priority Critical patent/WO2021142586A1/fr
Priority to CN202080002728.1A priority patent/CN112272824A/zh
Publication of WO2021142586A1 publication Critical patent/WO2021142586A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA

Definitions

  • the embodiments of the present invention relate to the technical field of data processing, and in particular to a data transmission method, a data transmission device, a data transmission device, an MCU, and a storage medium.
  • MCU Microcontroller Unit
  • SPI Serial Peripheral Interface
  • the embodiment of the present invention provides a data transmission method, a data transmission device, a data transmission device, an MCU, and a storage medium, which are used to solve the technical problem that the MCU needs to be interrupted multiple times and the load is large when data is transmitted in the prior art.
  • the first aspect of the present invention provides a data transmission method, including:
  • the memory stores the data to be transmitted
  • the data transmission module obtains the transmission instruction sent by the MCU, and controls the memory according to the transmission instruction to send the data to be transmitted to the interface module;
  • the interface module transmits the data to be transmitted
  • the method further includes: if the transmission rate of the memory is greater than the rate at which the interface module transmits the data to be transmitted, controlling the rate at which the memory transmits the data to be transmitted through the data transmission module It matches the rate at which the interface module transmits the data to be transmitted.
  • the second aspect of the present invention provides a data transmission method, including:
  • the MCU sends the data to be transmitted to the memory
  • a third aspect of the present invention provides a data transmission device, including:
  • Memory used to store the data to be transmitted
  • the data transmission module is used to obtain the transmission instruction sent by the MCU, and control the memory to send the data to be transmitted to the interface module according to the transmission instruction;
  • An interface module for receiving the data to be transmitted from the memory and transmitting the data to be transmitted
  • the data transmission module controls the rate at which the memory transmits the data to be transmitted in accordance with the transmission rate of the interface module.
  • the rate of the data to be transmitted matches.
  • the fourth aspect of the present invention provides an MCU, including:
  • Storage unit for storing computer programs
  • the processing unit is configured to run the computer program stored in the storage unit to realize:
  • a fifth aspect of the present invention provides a data transmission device, including: the data transmission device described in the third aspect and the MCU described in the fourth aspect.
  • a sixth aspect of the present invention provides a computer-readable storage medium in which program instructions are stored, and the program instructions are used to implement the data transmission method described in the first aspect.
  • a seventh aspect of the present invention provides a computer-readable storage medium in which program instructions are stored, and the program instructions are used to implement the data transmission method described in the second aspect.
  • the data transmission method, data transmission device, data transmission equipment, MCU and storage medium provided by the embodiments of the present invention reduce the number of interrupts and interrupt overhead of the MCU, greatly reduce the load of the MCU, and improve the performance of the MCU.
  • FIG. 1 is a schematic diagram of an application scenario provided by Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a data transmission device according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural diagram of another data transmission device according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic flowchart of a data transmission method according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic flowchart of a data transmission module controlling the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted according to the second embodiment of the present invention
  • FIG. 6 is a schematic diagram of module connection corresponding to a data transmission method provided in Embodiment 3 of the present invention.
  • FIG. 7 is a schematic flowchart of a data transmission module controlling the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted according to the third embodiment of the present invention
  • FIG. 8 is a schematic diagram of a timing sequence in a data transmission process provided by Embodiment 3 of the present invention.
  • Embodiment 9 is a schematic flowchart of a data transmission method provided by Embodiment 4 of the present invention.
  • FIG. 10 is a schematic diagram of a corresponding timing sequence when a data transmission method according to Embodiment 4 of the present invention is used to send an operation command;
  • FIG. 10 is a schematic diagram of a corresponding timing sequence when a data transmission method according to Embodiment 4 of the present invention is used to send an operation command;
  • FIG. 11 is a schematic diagram of a corresponding time sequence when a data transmission method according to a fourth embodiment of the present invention is used to send operation commands and information content;
  • FIG. 12 is a schematic diagram of a corresponding time sequence when a data transmission method according to Embodiment 4 of the present invention is used to obtain information content;
  • FIG. 13 is a schematic structural diagram of a data transmission device according to Embodiment 5 of the present invention.
  • FIG. 14 is a schematic structural diagram of an MCU provided by Embodiment 6 of the present invention.
  • FIG. 1 is a schematic diagram of an application scenario provided by Embodiment 1 of the present invention.
  • the embodiment of the present invention can be applied to a camera.
  • the camera can include a host and a lens connected to the host, and the host and the lens can be connected through a bayonet.
  • the host is provided with an MCU and a data transmission device, and the data transmission device can be used to control the data transmission between the host and the lens.
  • the data transmission in the embodiment of the present invention may refer to the sending and/or receiving of data, and specifically may refer to sending data to and/or receiving data from the opposite device, where the opposite device refers to receiving or sending data.
  • the data device for example, the opposite device of the host in FIG. 1 may be a lens.
  • the data transmission device may specifically include a memory, a data transmission module, and an interface module.
  • the interface module can obtain the data stored in the memory and transmit it to the opposite device, and the data transmission module can be used to control data transmission. s speed.
  • the working process of the data transmission device may have multiple implementation schemes, and the following description will be made by taking FIG. 2 and FIG. 3 as examples.
  • FIG. 2 is a schematic structural diagram of a data transmission device according to Embodiment 1 of the present invention.
  • the memory and the interface module are respectively connected to the data transmission module.
  • the data transmission module can read data from the memory and send it to the interface module so that the interface module transmits data and controls the interface module transmission at the same time. The rate of data.
  • FIG. 3 is a schematic structural diagram of another data transmission device according to Embodiment 1 of the present invention.
  • the data transmission device may further include a DMAC (Direct Memory Access Controller).
  • the memory and the interface module are respectively connected to the DMAC.
  • the DMAC can read data from the memory and send it to the interface module.
  • the interface module is made to transmit data, and the data transmission module is respectively connected with the DMAC and the interface module to control the rate of reading and transmitting data.
  • DMAC Direct Memory Access Controller
  • FIG. 4 is a schematic flowchart of a data transmission method according to Embodiment 1 of the present invention.
  • the method can be applied to a data transmission device, and the data transmission device can be used to connect with an MCU.
  • the data transmission device and the MCU can be applied to any device with data transmission requirements, including but not limited to the camera in FIG. 1.
  • the data transmission method in this embodiment may include:
  • Step 401 The memory stores the data to be transmitted.
  • the memory may be any storage device capable of implementing a data access function, for example, may be a random access memory (Random Access Memory, RAM).
  • the data to be transmitted may be pre-stored in the memory, or the memory may be connected to the MCU, and the data to be transmitted may be obtained and stored through the MCU.
  • Step 402 The data transmission module obtains the transmission instruction sent by the MCU, and controls the memory to send the data to be transmitted to the interface module according to the transmission instruction; if the transmission rate of the memory is greater than that of the interface module to transmit the data to be transmitted The rate at which the data transmission module controls the memory to send the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
  • the data transmission module may be connected with the MCU to obtain the transmission instruction sent by the MCU. After the transmission instruction is obtained, the data transmission module may control the memory to send the data to be transmitted to the interface module.
  • the data transmission module may directly obtain the data to be transmitted from the memory and send it to the interface module; or, the data transmission module may control the DMAC to obtain the data to be transmitted from the memory and send it to the interface module.
  • the sending rate of the memory may refer to the corresponding sending rate of the memory without the control of the data transmission module, which can be specifically described as: if the net sending time required for the memory to send a unit byte is T a , then the memory is The sending rate is the unit byte/T a .
  • the corresponding sending rate is 1 byte/8 us.
  • the rate at which the memory transmits the data to be transmitted may refer to the corresponding rate when the memory transmits the data to be transmitted under the control of the data transmission module, and can be specifically described as: when transmitting the data to be transmitted, if the memory transmits every T b Unit byte, the rate at which the memory sends the data to be transmitted is unit byte/T b .
  • the memory when sending data to be transmitted, the memory sends one byte every 10 us, and the rate of sending the data to be transmitted is 1 byte/10 us.
  • the transmission rate in the memory can be controlled by a module that reads its data.
  • the transmission rate of the memory can be controlled by a data transmission module.
  • the transmission rate of the memory can be controlled by the DMAC. Since the transmission rate of the interface module itself may be slow, or because a certain delay may be required when the interface module transmits data, the transmission rate of the memory may be faster than the rate at which the interface module transmits the data to be transmitted .
  • the data transmission module may be used to control the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted.
  • the memory only needs 8us to send one byte, then the sending rate of the memory is 1 byte/8us.
  • the interface module transmits the data to be transmitted it needs to send one byte every 10us, then the interface module transmits the The rate of the data to be transmitted is 1 byte/10us.
  • the transmission rate of the memory is greater than the rate at which the interface module transmits the data to be transmitted.
  • the rate at which the memory transmits the data to be transmitted can be adjusted to 1 byte/10us. , That is, make the memory to send one byte of data every 10 us, which matches the rate at which the interface module transmits the data to be transmitted.
  • the data transmission module controls the memory to send the data to be transmitted at a rate that matches the rate at which the interface module transmits the data to be transmitted, and there may be multiple implementation methods. The following is still based on Figure 2 and Figure 3 to illustrate.
  • the data transmission module can directly obtain data from the memory and send it to the interface module so that the interface module can transmit the data.
  • the data transmission module can directly control the reading and sending Therefore, the rate at which the memory sends the data to be transmitted and the rate at which the interface module transmits the data to be transmitted are controlled.
  • the data transmission module can control the DMAC to obtain data from the memory and send it to the interface module so that the interface module can transmit the data.
  • the data transmission module can output to the DMAC through control.
  • the sending request signal is used to realize that the rate at which the memory sends the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
  • Step 403 The interface module transmits the data to be transmitted.
  • the MCU, memory, data transmission module, and interface module can be set in the device that needs data transmission.
  • the MCU can be used to implement the main functions of the device, and the data transmission module is used to control the data transmission process of the device.
  • the MCU can send a transmission instruction to the data transmission module, and the data transmission module can control the data transmission process according to the transmission instruction, and the transmission process does not require MCU intervention.
  • the data to be transmitted may be at least one of an operation command, information length, and information content.
  • the method may be used for the host of a photographing device; the peer device used to obtain the data to be transmitted may be the lens of the photographing device; wherein the operation command is an autofocus instruction, a zoom instruction, and a shooting mode instruction , Anti-shake instruction or data capture instruction; the information length is the length of the information content transmitted in one data transmission period; the information content includes image data information.
  • the data to be transmitted is stored by the memory, and the data transmission module obtains the transmission instruction sent by the MCU, and controls the memory to transmit the data to be transmitted to the interface module according to the transmission instruction.
  • the data transmission module may control the memory to transmit the data to be transmitted The rate matches the rate at which the interface module transmits the data to be transmitted, ensuring the normal transmission of data, without the need for the MCU to control the data transmission speed through interrupts, reducing the number of interrupts and interrupt overhead of the MCU, and reducing the MCU
  • the load and the complexity of the driving software have improved the performance of the MCU.
  • the second embodiment of the present invention provides a data transmission method. Based on the technical solution provided in the first embodiment, the data transmission module can control the data transmission process by clock counting.
  • FIG. 5 is a schematic flowchart of a data transmission module controlling the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted according to the second embodiment of the present invention.
  • controlling the memory to send the data to be transmitted at a rate to match the interface module to transmit the data to be transmitted may include:
  • Step 501 Determine the number of clocks to be occupied by each byte in the data according to the attribute information of the data to be transmitted.
  • the data transmission module may pre-store the attribute information of the data to be transmitted, or the data transmission module may obtain the attribute information of the data to be transmitted from the MCU or other modules.
  • the transmission instruction sent by the MCU to the data transmission module may include attribute information of the data to be transmitted, and the data transmission module may determine the attribute information contained in the transmission instruction after obtaining the transmission instruction. The number of clocks occupied by each byte in the data.
  • the number of clocks to be occupied by the byte may include the number of clocks to be occupied by the time elapsed from the moment when the current byte starts to be transmitted to the moment when the next byte starts to be transmitted.
  • the number of clocks to be occupied by the byte may include the number of clocks required to transmit the byte and the number of clocks corresponding to the minimum interval time between the bytes.
  • the number of clocks required to transmit the bytes is recorded as the number of transmissions
  • the number of clocks corresponding to the minimum interval between bytes is recorded as the number of intervals.
  • the minimum time interval can be set according to actual needs. In some data communication standards, it is defined that the interval between bytes in the data transmission process should be at least 2us in order to allow enough response time for the device. In this case, the minimum interval can be 2us. .
  • the attribute information may be any information used for the data transmission module to determine the number of clocks to be occupied by each byte.
  • the attribute information may include type information of the data to be transmitted, and different types of data may correspond to different numbers of clocks.
  • the data transmission module can store a correspondence table between type information and the number of clocks (which can be divided into the number of transmissions and the number of intervals), and the table can be used to determine the amount of data occupied by each byte in a certain type of data.
  • the number of clocks the MCU does not need to calculate the number of clocks when transmitting data, which effectively reduces the burden on the MCU.
  • the attribute information may include the time required for each byte in the data to be transmitted, and the data transmission module may determine the time required for each byte according to the time required for each byte and the length of a clock cycle.
  • the number of clocks can realize the transmission of various types of data without storing the correspondence table in advance, and the applicability is strong.
  • the attribute information may also include duration information of one clock cycle of the other modules.
  • the attribute information may include the number of clocks to be occupied by each byte in the data.
  • the data transmission module can directly read the attribute information to obtain the number of clocks required for each byte in the data, which can effectively save the computing resources of the data transmission module.
  • the attribute information may include the minimum interval time between bytes when transmitting the data, or
  • the attribute information includes the number of clocks corresponding to the minimum time interval between bytes when transmitting the data.
  • the data transmission module can determine the number of intervals according to the attribute information, and then determine the number of clocks that each byte needs to occupy.
  • the number of intervals can be calculated at the same time. Reduce the burden of MCU and data transmission module and improve data transmission efficiency.
  • the attribute information may also include any other information used to implement data transmission control. For example, it may include the total number of bytes of data to be transmitted, which is convenient for the data transmission module to determine the The total number of sections determines whether the data transmission is complete.
  • Step 502 Control the transmission of the data according to the determined number of clocks, so that the rate at which the memory sends the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
  • the data transmission module can control the interface module to obtain a byte from the memory, count the clock signal when the byte starts to be transmitted, and then control the interface module when the count value reaches the number of clocks that the byte needs to occupy Obtain the next byte from the memory and start the transmission of the next byte, ensuring that the rate at which the memory sends the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
  • the number of clocks appearing in each embodiment of the present invention may refer to the number of clock cycles of the data transmission module, and may also refer to the number of clock cycles of other modules. Examples are as follows.
  • Implementation mode 1 The number of clocks that the byte needs to occupy is the number of clocks of the data transmission module itself.
  • the number of clocks occupied by the byte may be equal to the ratio of the sum of the time required to transmit the byte and the minimum interval time to the time occupied by one clock cycle of the data transmission module.
  • the minimum interval between bytes is 2us
  • the time occupied by one clock cycle of the data transmission module is T1
  • the number of clocks required for one byte is 10us/T1.
  • T1 1us
  • the data transmission module counts the clock signal at the same time.
  • 8 is counted
  • the byte transmission is completed, and then when the clock signal is counted for 2, it is 2us.
  • the interval timing ends, the number of clocks to be occupied by one byte is all counted, and the transmission of the next byte starts.
  • the implementation method is simple in logic, easy to implement, and high in efficiency.
  • the data transmission module may be connected to clock signal pins of other modules, receive clock signals of other modules, and count the received clock signals.
  • the number of clocks occupied by the byte is equal to the ratio of the sum of the time required to transmit the byte and the minimum interval time to the time occupied by one clock cycle of the other module.
  • the transmission of bytes is controlled by counting the clock signals output by other modules.
  • Implementation mode 3 Among the number of clocks to be occupied by the byte, part is the number of clocks of the data transmission module, and part is the number of clocks of other modules.
  • the number of transmissions can be the number of clocks of other modules
  • the number of intervals can be the number of clocks of the data transmission module.
  • the number of clocks occupied by the byte is equal to the ratio of the time required to transmit the byte to the time occupied by a clock cycle of other modules, plus the minimum interval time and a clock of the data transmission module The ratio of the time occupied by the cycle.
  • T1 0.5us
  • 8 is counted
  • the byte transmission is completed, and then the data transmission module
  • the clock signal of its own is counted.
  • the count reaches 4, it means that the interval time of 2us is over, the number of clocks occupied by one byte is all counted, and the transmission of the next byte is started.
  • the other modules can be any modules with clock signals, such as interface modules. Because the interface module transmits bytes based on its own clock, the number of transmissions is generally 8, and the data transmission module does not need to know the interface. The clock frequency of the module only needs to count the clock of the interface module at least 8 to confirm that the byte transmission is completed, which effectively reduces the calculation amount of the data transmission module and improves the accuracy of data transmission.
  • the minimum time interval corresponding to each byte of the data to be transmitted may be the same or different, which is not limited in the embodiment of the present invention.
  • the data transmission module can count the clock signal, and control the time interval for the memory to transmit each byte and the time interval for the interface module to transmit each byte according to the clock count to ensure that the memory transmits the
  • the rate of the data to be transmitted matches the rate at which the interface module transmits the data to be transmitted.
  • the entire data transmission process does not require the MCU to perform timing, and the MCU does not need to set an interrupt when transmitting each byte.
  • the data transmission module can generate clock signals and also has the function of counting clock signals, which does not affect the MCU's clock signal and counting functions.
  • the MCU still has its own clock signal and counts the clock signal, and further functions such as a timer can also be realized through the counting function.
  • the data transmission module can determine the number of clocks to be occupied by each byte in the data according to the attribute information of the data to be transmitted, and according to the determined number of clocks, Control the transmission of the data. After each byte starts to be transmitted, the determined number of clocks is passed before the next byte is transmitted, so that the rate at which the memory sends the data to be transmitted and the interface module transmits the data to be transmitted. The data rate is matched to ensure that there is enough interval time between each byte, and the stability of data transmission is improved.
  • the interface module in each embodiment of the present invention may refer to any module that can implement data transmission interface functions, such as SPI module, USB (Universal Serial Bus, Universal Serial Bus) interface module, UART (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Transceiver) and so on.
  • SPI Serial Bus
  • USB Universal Serial Bus
  • UART Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Transceiver
  • the interface module as an SPI module as an example to introduce a specific implementation scheme of the embodiment of the present invention.
  • Implementation schemes based on other similar modules can refer to the scheme based on the SPI module, which will not be repeated in the embodiment of the present invention. .
  • FIG. 6 is a schematic diagram of module connection corresponding to a data transmission method provided in Embodiment 3 of the present invention.
  • an interface module in order to realize the function of data transmission, an interface module, a DMAC, and a memory may be provided in this embodiment, where the interface module is an SPI module, and the memory is a random access memory RAM.
  • DMAC is responsible for writing bytes in RAM to TX BUFFER of SPI module when sending data, or writing bytes received by SPI module from RX BUFFER of SPI module to RAM when receiving data.
  • the SPI module can be connected to the opposite device and undertake the implementation of the SPI communication protocol.
  • the existing SPI IP can be used as the SPI module, and the chip select signal output by the IP itself may not be used in the embodiment of the present invention.
  • the data transmission module is respectively connected with the DMAC and SPI modules to control the transmission of bytes.
  • the data transmission module, DMAC, and SPI module can be respectively connected to the MCU (not shown in the figure), and the drive software in the MCU enables, disables and configures the data transmission module, DMAC, and SPI module.
  • FIG. 7 is a schematic flowchart of a data transmission module controlling the rate at which the memory sends the data to be transmitted to match the rate at which the interface module transmits the data to be transmitted according to the third embodiment of the present invention.
  • controlling the memory to send the data to be transmitted at a rate that matches the interface module to transmit the data to be transmitted may include:
  • Step 701 Determine the number of clocks to be occupied by each byte in the data according to the attribute information of the data to be transmitted.
  • step 701 in this embodiment implements the following steps 702 to 706 to control the transmission of the data according to the determined number of clocks, so that the rate at which the memory sends the data to be transmitted and the interface module transmits the data to be transmitted. Match the rate of the transmitted data.
  • Step 702 Control the SPI module to obtain the first byte of the data from the RAM and start to transmit the first byte of the data.
  • the first byte can be acquired and transmitted immediately after the attribute information of the data is obtained from the MCU; or, after the attribute information is obtained, you can wait for a period of time and wait for the MCU to notify the opposite device before starting the acquisition And transmit the first byte.
  • controlling the SPI module in step 702 to obtain the first byte of the data from the RAM and start transmitting the first byte of the data may include:
  • FIG. 8 is a schematic diagram of a time sequence in a data transmission process according to Embodiment 3 of the present invention.
  • the transmission start signal is marked as a noti signal, which is valid when the noti signal is low;
  • the transmission start confirmation signal is marked as a rec signal, and it is valid when the rec signal is high.
  • noti is a kind of request information
  • rec signal is a kind of response signal.
  • the data transmission module can control the noti signal to be low, and the opposite device controls the rec signal to be high after the noti signal is low.
  • the data transmission module detects that the rec signal is high, it controls the SPI module to start transmitting the first byte of data.
  • the data transmission module can control the SPI module to transmit bytes through the DMAC.
  • the data transmission module can also be integrated with the DMAC function to directly control the SPI to transmit bytes. The following describes in detail the scheme of controlling the transmission of bytes by the SPI module through the DMAC.
  • controlling the SPI module to obtain the first byte of the data from the RAM and start transmitting the first byte of the data may include: after obtaining the valid transmission After the confirmation signal is started, the transmission request signal output to the DMAC is controlled to be consistent with the transmission request signal obtained from the SPI module, so that the DMAC controls the SPI module to obtain the first byte of the data from the RAM according to the received transmission request signal. And start to transmit the bytes.
  • the transmission request signal output by the SPI module is valid by default, and when the transmission request signal obtained by the DMAC becomes valid, the DMAC will automatically write bytes to the SPI module, so that the SPI module starts to send bytes.
  • a transparent transmission flag signal is set in the embodiment of the present invention to control the time point of outputting the transmission request signal to the DMAC through the value of the transparent transmission flag.
  • controlling the transmission request signal output to the DMAC to be consistent with the transmission request signal obtained from the SPI module may include: after obtaining the valid transmission start confirmation When the signal and the transmission request signal obtained from the SPI module are valid, the control transparent transmission flag signal is valid. When the transparent transmission flag signal is valid, the transmission request signal output to the DMAC is consistent with the transmission request signal obtained from the SPI module.
  • the logical relationship between the transparent transmission flag signal and the two sending request signals can be realized by a gate circuit or a switch circuit, and has a simple structure and is not prone to errors.
  • the transmission request signal output by the SPI is marked as dma_tx_req, dma_tx_req is high (valid) by default; the transparent transmission flag signal is marked as dma_tx_req_mask, which is high (invalid) by default; the transmission request signal output by the data transmission module to the DMAC is marked It is dma_tx_req_new.
  • dma_tx_req_mask is invalid, the transmission request signal dma_tx_req_new output to the DMAC is low (invalid), and the DMAC considers that the SPI module has no data transmission request at this time.
  • the data transmission module After the data transmission module detects that the rec signal is high (that is, a valid transmission start confirmation signal), it pulls down the dma_tx_req_mask signal to make it valid. When the dma_tx_req_mask signal is valid, dma_tx_req_new and dma_tx_req are consistent (that is, output to the DMAC).
  • the sending request signal is consistent with the sending request signal obtained from the SPI module), which is equivalent to the dma_tx_req signal output by the SPI module can be transparently transmitted to the DMAC.
  • the SPI module can send the written bytes to the opposite device. Specifically, the SPI module can send data through the mosi signal line and receive data through the miso signal line; the DMAC can read data from the RAM or write data to the RAM through the receiving signal line rx and the sending signal line tx.
  • Step 703 Count the clock signal when the byte starts to be transmitted.
  • the SPI module pulls down dma_tx_req and starts transmitting bytes at the same time.
  • the data transmission module can start counting the clock signal when the dma_tx_req is changed from high to low (invalid).
  • the clock signal of the data transmission module itself can be counted, or the clock signal of other modules can also be counted.
  • the data transmission module can be connected to the clock signal output pin of the SPI module to obtain and count the clock signal sclk of the SPI module.
  • the data transmission module can first count the clock signals output by the SPI module. After 8 are counted, the 1 byte transmission/reception process is considered to be over, and the 2us delay count is started. The 2us delay count can be correct The clock signal of the data transmission module itself counts. After the 2us count is completed, it is considered that the count has met the requirements.
  • the SPI module can output a clock signal while transmitting the byte. After the byte is transmitted, the clock signal is not output within a time interval of 2 us, thereby saving SPI resources and reducing the burden of SPI.
  • the data transmission module can control the sending request signal dma_tx_req_new output to the DMAC to be invalid when the DMAC controls the SPI module to start transmitting bytes, so as to facilitate the control of the next byte.
  • the control transparent transmission flag signal dma_tx_req_mask is invalid, and when the transparent transmission flag signal dma_tx_req_mask is invalid, the transmission request signal dma_tx_req_new output to the DMAC is invalid.
  • controlling the transparent transmission flag signal dma_tx_req_mask is invalid, which may include: when the transmission request signal dma_tx_req obtained from the SPI module changes from valid to invalid, controlling the transparent transmission flag signal dma_tx_req_mask invalid.
  • the data transmission module can pull up dma_tx_req_mask to make it invalid when it obtains that dma_tx_req changes from high to low (invalid). In the case where dma_tx_req_mask is invalid, dma_tx_req_new remains invalid.
  • Step 704 After the count meets the requirement, it is judged whether all bytes of the data have been transmitted. If not, go to step 705; if yes, go to step 706.
  • the attribute information sent by the MCU may also include the total number of bytes of the data to be transmitted.
  • the data transmission device can determine whether all the bytes of the data to be transmitted have been transmitted according to the total number of bytes, with high accuracy.
  • judging whether all the bytes of the data to be transmitted is completed according to the total number of bytes may include: determining the total number of clocks required to complete the data transmission according to the total number of bytes; After a valid transmission start confirmation signal is obtained, and the total count of clock signals reaches the total number of clocks, it is determined that all bytes of the data to be transmitted have been transmitted.
  • the data transmission module can also determine whether all bytes have been transmitted in other ways, for example, by counting the number of times that the requirements are met, or the number of times the transmission request signal dma_tx_req or the transparent transmission flag signal dma_tx_req_mask has been changed from the SPI module. judge.
  • a counter is set in the data transmission module according to the total number of bytes of the data to be transmitted in the attribute information . For example, if the total number of bytes of data to be transmitted is n, the value of the counter is set to n. Each time a byte is transmitted, the value of the counter is reduced by one. When the value of the counter is 0, it is confirmed that all bytes have been transmitted.
  • step 705 If it is determined as a result of the judgment that all bytes have not been transmitted, step 705 is executed, otherwise, step 706 is executed.
  • Step 705 Control the SPI module to obtain the next byte from the RAM and start to transmit the next byte, and perform step 703 again.
  • the transmission request signal dma_tx_req_new output to the DMAC can be effectively controlled by controlling the transparent transmission flag signal dma_tx_req_mask to be consistent with the transmission request signal dma_tx_req obtained from the SPI module, so that the DMAC can control according to the received transmission request signal
  • the SPI module obtains the next byte from the RAM and starts to transmit the byte; when the DMAC controls the SPI module to start transmitting the byte, the transmission request signal dma_tx_req_new output to the DMAC is invalid.
  • the transmission request signal dma_tx_req_new and the transmission request signal dma_tx_req obtained from the SPI module are effectively controlled by controlling the transparent transmission flag signal dma_tx_req_mask to be consistent with the transmission request signal dma_tx_req obtained from the SPI module by controlling the transparent transmission flag signal dma_tx_req_mask.
  • the control transparent transmission flag signal dma_tx_req_mask is valid.
  • the transmission request signal dma_tx_req_new output to the DMAC is consistent with the transmission request signal dma_tx_req obtained from the SPI module.
  • the SPI module can send the written bytes to the opposite device.
  • the process of receiving bytes from the peer device is similar to the sending process, because the clock signal required by the SPI module to receive bytes can only be generated by writing an invalid byte in the TXBUFFER of the SPI module, so after the dma_tx_req_new signal obtained by the DMAC is valid , Write an invalid byte to the TX BUFFER of the SPI module, and then the DMAC pulls up the dma_tx_ack signal. After TX BUFFER is written with invalid bytes, the SPI module receives bytes from the opposite device, and the received bytes are stored in the RXBUFFER of the SPI module, read by DMAC and stored in RAM.
  • step 702 The specific implementation principle of this step is similar to step 702, except that in step 702, the transparent transmission flag signal dma_tx_req_mask is pulled down when the rec signal is valid, and in this step, the transparent transmission flag signal dma_tx_req_mask is pulled down after the count meets the requirement.
  • the transparent transmission flag signal dma_tx_req_mask is pulled down, so that dma_tx_req_new and dma_tx_req are consistent (that is, the transmission request signal output to the DMAC is consistent with the transmission request signal obtained from the SPI module),
  • the dma_tx_req signal equivalent to the output of the SPI module can be transparently transmitted to the DMAC.
  • Step 706 After all bytes of the to-be-transmitted data are transmitted, send transmission completion information to the MCU.
  • the transmission start signal may be controlled to be invalid, so that the opposite end device controls the transmission start confirmation signal to be invalid according to the invalid transmission start signal; After the acquired transmission start confirmation signal is invalid, the transmission completion information is sent to the MCU.
  • the data transmission module raises the noti signal, waits for the opposite device to raise the rec signal, and then informs the MCU that the SPI sending/receiving process ends normally.
  • the transmission completion information may be sent to the MCU in an interrupt manner.
  • the MCU, data transmission module, DMAC and SPI modules can be set in devices with data transmission requirements.
  • the MCU can be pre-configured with the relevant working parameters of the DMAC and SPI modules: DMAC BURST is set to 1 byte, the DMAC BLOCK transmission length is set to the total number of bytes sent or received by the SPI module this time, and the SPI BURST request parameter is set to 1 byte; and the attribute information is sent to the data transmission module.
  • the data transmission module can use the method provided in this embodiment to control the transmission of bytes, and count the transmission process, and enter the next cycle after the count is completed, until all the bytes are transmitted. It should be noted that, according to an embodiment of the present invention, the data transmission module can be combined with the general DMAC and SPI modules, and there is no need to make major improvements to the general DMAC and SPI modules. Therefore, the data transmission module according to an embodiment of the present invention has high application promotion value.
  • the MCU can multiplex the noti signal line and the rec signal line with the data transmission module.
  • the MCU can disable the data transmission module and use the existing method to control the DMAC and SPI modules for data transmission, so that the embodiment of the present invention can be compatible with existing solutions, and the data transmission is more flexible and convenient to meet the needs of different occasions.
  • DMAC can also be integrated in the data transmission module.
  • the data transmission module directly controls the SPI module to realize data transmission, which can effectively reduce the number of modules and wiring, simplify intermediate logic, reduce equipment footprint, and enhance equipment stability .
  • the data transmission module can control the SPI module to obtain bytes from the memory and transmit the bytes, and when the bytes start to transmit, count the clock signal, and after the count meets the requirements, control
  • the SPI module obtains the next byte from the memory and starts to transmit the next byte until the transmission of all bytes is completed, and can control the memory to send the data to be transmitted at a rate that matches the rate at which the interface module transmits the data to be transmitted , To meet the requirements of each byte on the time interval, to ensure the correct transmission of data.
  • part or all of the data transmission module, the memory, and the interface module can be integrated.
  • the data transmission module may be packaged with the memory as a module, and the module is connected with the interface module; or the data transmission module may be packaged with the interface module as a module, and the module is connected with the memory; and so on.
  • FIG. 9 is a schematic flowchart of a data transmission method according to Embodiment 4 of the present invention.
  • the method can be applied to an MCU, and the MCU can be connected to a data transmission device.
  • the data transmission method in this embodiment may include:
  • Step 901 Send the data to be transmitted to the memory.
  • Step 902 Send a transmission instruction to the data transmission module, so that the data transmission module controls the transmission of the data to be transmitted stored in the memory according to the transmission instruction.
  • the transmission instruction may include attribute information of the data to be transmitted, so that the data transmission module determines the number of clocks to be occupied by each byte in the data according to the attribute information and according to the attribute information. The determined number of clocks controls the transmission of the data.
  • the number of clocks to be occupied by the byte may be the sum of the number of transmissions and the number of intervals; wherein, the number of transmissions is the number of clocks required to transmit the bytes, and the number of intervals is The number is the number of clocks corresponding to the minimum interval time between bytes.
  • the attribute information may include the minimum time interval between bytes when transmitting the data, or the attribute information may include a clock corresponding to the minimum time interval between bytes when transmitting the data. Number.
  • the method may further include: obtaining transmission completion information sent by the data transmission module after all bytes of the data have been transmitted.
  • the method may further include: after obtaining the transmission completion information corresponding to the data, determining whether there is the next data to be transmitted; if so, determining the next data
  • the attribute information is sent to the data transmission module.
  • the data transmission module can control the transmission of the next data according to the methods in the foregoing embodiments.
  • the data to be transmitted may be at least one of an operation command, information length, and information content; the method may be used for a host of a photographing device; a peer device used to obtain the data to be transmitted Is the lens of the shooting device; wherein the operation command is an autofocus command, a zoom command, a shooting mode command, an anti-shake command, or a data capture command; the length of the information is the length of the information transmitted in one data transmission cycle Length; the information content includes image data information.
  • the operation command is an autofocus command, a zoom command, a shooting mode command, an anti-shake command, or a data capture command
  • the length of the information is the length of the information transmitted in one data transmission cycle Length
  • the information content includes image data information.
  • the next data of the data is the information length
  • the next data of the information length is the information content.
  • FIG. 10 is a schematic diagram of a corresponding time sequence when a data transmission method according to Embodiment 4 of the present invention is used to send an operation command.
  • the operation command may be an operation command that does not require information content, such as enabling a lens. Assume that the operation command occupies 5 bytes, which are AT, CD, P1, P2, and CS.
  • the MCU configures the relevant parameters of the DMAC and SPI modules by sending 5 bytes of data before time 1. Write the byte content to be sent by the SPI module in the RAM, and enable the data transmission module , DMAC and SPI modules. Time 2 and 3 are invisible to the MCU, and the data transmission module implements the control of data transmission according to the method in the foregoing embodiment. It should be noted that the MCU does not participate in the data processing at time 2 and 3. In one embodiment, the MCU can enter other processes at 2 and 3 to handle other matters. At time 4, after the data transmission module detects that the opposite device pulls up the rec signal, it generates an interrupt to notify the MCU that all bytes of the operation command are sent normally.
  • FIG. 11 is a schematic diagram of a corresponding time sequence when a data transmission method according to Embodiment 4 of the present invention is used to send operation commands and information content.
  • the operation command may be any instruction that requires additional information content, such as indicating lens configuration parameters, etc., and the attached information content may be a specific parameter value.
  • the operation command can be sent first, then the length of the message, and then the content of the message. Assuming that the operation command occupies 5 bytes, which are AT, CD, P1, P2, and CS, the information length occupies two bytes, which are L1, L2, and the information content occupies n+1 bytes, which are D1, D2. , D3, ..., Dn and CS.
  • the MCU configures the relevant parameters of the DMAC and SPI modules by sending 5 bytes before time 1, write the byte content to be sent by the SPI module in the RAM, and enable the data transmission module, DMAC, SPI module.
  • Time 2 and 3 are invisible to the MCU, and the data transmission module implements the control of data transmission according to the method in the foregoing embodiment.
  • the MCU does not participate in the data processing at time 2 and 3. In one embodiment, the MCU can enter other processes at 2 and 3 to handle other matters.
  • the data transmission module detects that the opposite device pulls up the rec signal, it generates an interrupt to notify the MCU that all bytes of the operation command are sent normally. So far, the opposite device has received the operation command, but has not yet obtained the corresponding information length and information content.
  • the MCU configures the relevant parameters of the DMAC and SPI modules by sending 2 bytes before time 5, writes the contents of the bytes to be sent by the SPI module in the RAM, and enables the data transmission module, DMAC, SPI module. It is not visible to the MCU at time 6 and 7. It should be noted that the MCU does not participate in the data processing at time 6 and 7. In one embodiment, the MCU can enter other processes to handle other matters at time 6 and 7. At time 8, after the data transmission module detects that the opposite device pulls up rec, it generates an interrupt to notify the MCU that all bytes of the information length are normally sent. So far, the opposite device has received the operation command and the length of the message, but has not yet obtained the corresponding message content.
  • the MCU configures the relevant parameters of the DMAC and SPI modules according to the n+1 bytes sent before 9 hours, writes the contents of the bytes to be sent by the SPI module in the RAM, and enables Data transmission module, DMAC, SPI module. 10 and 11 are not visible to the MCU. It should be noted that the MCU does not participate in the data processing at 10 and 11 time. In an embodiment, the MCU can enter other processes at 10 and 11 to handle other matters.
  • the data transmission module detects that the opposite device pulls up the rec signal, it generates an interrupt to notify the MCU that all bytes of the information content are normally sent. So far, the opposite device has received the configuration command, the length of the information, and the content of the information, and can parse the received information according to the standard communication data packet format to complete the configuration of the parameters.
  • FIG. 12 is a schematic diagram of a corresponding time sequence when a data transmission method according to Embodiment 4 of the present invention is used to obtain information content.
  • the MCU When the MCU needs to obtain data from the opposite device, it can first send an operation command, then receive the length of the information from the opposite device, and then receive the content of the information. Assuming that the operation command occupies 5 bytes, which are AT, CD, P1, P2, and CS, the information length occupies two bytes, which are L1, L2, and the information content occupies n+1 bytes, which are D1, D2. , D3, ..., Dn and CS.
  • the MCU configures the relevant parameters of the DMAC and SPI modules by sending 5 bytes before time 1.
  • Time 2 and 3 are invisible to the MCU, and the data transmission module implements the control of data transmission according to the method in the foregoing embodiment.
  • the MCU does not participate in the data processing at time 2 and 3.
  • the MCU can enter other processes at 2 and 3 to handle other matters.
  • the data transmission module detects that the opposite device pulls up the rec signal, it generates an interrupt to notify the MCU that all bytes of the operation command are sent normally. So far, the opposite device has received the operation command, and the information length and content of the information returned internally are prepared.
  • the MCU After the operation command is sent, the MCU will send 2 bytes (invalid bytes) before time 5 to configure the relevant parameters of the DMAC and SPI modules, write the contents of the bytes to be sent by the SPI module in the RAM, and enable Data transmission module, DMAC, SPI module. It is not visible to the MCU at time 6 and 7. It should be noted that the MCU does not participate in the data processing at time 6 and 7. In one embodiment, the MCU can enter other processes to handle other matters at time 6 and 7. At time 8, after the data transmission module detects that the opposite device pulls up the rec signal, it generates an interrupt to notify the MCU that all bytes of the information length are normally received. The MCU reads the RAM and obtains L1+L2 bytes of information. So far, the MCU has received the length of the information, but has not yet received the corresponding information content.
  • the MCU configures the relevant parameters of the DMAC and SPI modules by sending n+1 bytes (invalid bytes) before 9 hours, and writes the contents of the bytes to be sent by the SPI module in the RAM, so that Capable of data transmission module, DMAC, SPI module. 10 and 11 are not visible to the MCU. It should be noted that the MCU does not participate in the data processing at 10 and 11 time. In an embodiment, the MCU can enter other processes at 10 and 11 to handle other matters.
  • the data transmission module detects that the opposite device pulls up the rec signal, it generates an interrupt to notify the MCU that all bytes of the information content have been received normally. So far, the opposite device has returned the corresponding information content according to the operation command sent by the MCU, and the returned data is read by the DMAC from the RX BUFFER of the SPI module and stored in the RAM.
  • the embodiment of the present invention controls the transmission process through the data transmission module, which can effectively reduce the load of the MCU.
  • the MCU driver software needs to respond to 5+2+n+1 interrupts during the entire communication process; while using the solution provided by this embodiment, the entire communication
  • the driver software of the process MCU only needs to respond to three interrupts, which greatly reduces the number of interrupt interactions, thereby greatly reducing the load of the MCU.
  • FIG. 13 is a schematic structural diagram of a data transmission device according to Embodiment 5 of the present invention. As shown in FIG. 13, this embodiment provides a data transmission device for connecting with an MCU. The data transmission device can execute the data transmission method corresponding to FIG. 4 above. Specifically, the data transmission device may include :
  • the memory 11 is used to store data to be transmitted
  • the data transmission module 12 is configured to obtain a transmission instruction sent by the MCU, and control the memory 11 according to the transmission instruction to send the data to be transmitted to the interface module 13;
  • the interface module 13 is configured to receive the data to be transmitted from the memory 11 and transmit the data to be transmitted;
  • the data transmission module 12 controls the memory 11 to transmit the data to be transmitted at a rate that is greater than the rate at which the data to be transmitted is transmitted.
  • the rate at which the interface module 13 transmits the data to be transmitted matches.
  • the data transmission device further includes a direct memory access controller
  • the data transmission module 12 is used to connect to the direct memory access controller, and the data transmission module 12 controls the sending request signal output to the direct memory access controller to make the memory 11 send all
  • the rate of the data to be transmitted matches the rate of the interface module 13 to transmit the data to be transmitted.
  • the transmission instruction includes attribute information of the data to be transmitted; the data transmission module 12 is further configured to:
  • the transmission of the data is controlled so that the rate at which the memory 11 sends the data to be transmitted matches the rate at which the interface module 13 transmits the data to be transmitted.
  • the number of clocks that the byte needs to occupy is the sum of the number of transmissions and the number of intervals;
  • the number of transmissions is the number of clocks required to transmit the bytes
  • the number of intervals is the number of clocks corresponding to the minimum interval between bytes.
  • the attribute information includes the minimum interval time between bytes when transmitting the data
  • the attribute information includes the number of clocks corresponding to the minimum time interval between bytes when transmitting the data.
  • the interface module 13 is a serial peripheral interface module 13;
  • the data transmission module 12 is also used for:
  • the clock signal is counted; after the count meets the requirement, the serial peripheral interface module 13 is controlled to obtain the next byte from the memory 11 and start to transmit the next byte.
  • the serial peripheral interface module 13 when the serial peripheral interface module 13 is controlled to obtain the first byte of the data from the memory 11 and start to transmit the first byte of the data, the data transmission module 12 Also used for:
  • the serial peripheral interface module 13 After obtaining the valid transmission start confirmation signal, the serial peripheral interface module 13 is controlled to obtain the first byte of the data from the memory 11 and start to transmit the first byte of the data.
  • the data transmission module 12 is also used to:
  • transmission completion information is sent to the MCU.
  • the attribute information further includes the total number of bytes of the data to be transmitted
  • the data transmission module 12 is also used to determine whether all bytes of the data to be transmitted have been transmitted according to the total number of bytes.
  • the data transmission module 12 is further configured to:
  • the data transmission device further includes a direct memory access controller
  • the serial peripheral interface module 13 After obtaining the valid transmission start confirmation signal, when the serial peripheral interface module 13 is controlled to obtain the first byte of the data from the memory 11 and start to transmit the first byte of the data, the The data transmission module 12 is also used for:
  • the sending request signal output to the direct memory access controller is controlled to be consistent with the sending request signal obtained from the serial peripheral interface module 13, so that the direct memory access controller Controlling the serial peripheral interface module 13 to obtain the first byte of the data from the memory 11 and start transmitting the byte according to the obtained sending request signal;
  • the send request signal output to the direct memory access controller is invalid.
  • the data transmission module 12 is also used for:
  • the transparent transmission flag signal is controlled to be valid, and when the transparent transmission flag signal is valid, it is output to the direct memory access
  • the sending request signal of the controller is consistent with the sending request signal obtained from the serial peripheral interface module 13.
  • the serial peripheral interface module 13 is controlled to obtain the next byte from the memory 11 and start to transmit the next byte, the data transmission module 12 returns Used for:
  • the transmission request signal output to the direct memory access controller is effectively controlled by controlling the transparent transmission flag signal to be consistent with the transmission request signal obtained from the serial peripheral interface module 13, so that the direct memory access controller can be
  • the received sending request signal controls the serial peripheral interface module 13 to obtain the next byte from the memory 11 and start transmitting the byte;
  • the send request signal output to the direct memory access controller is invalid.
  • the transmission request signal output to the direct memory access controller is effectively controlled by controlling the transparent transmission flag signal when the transmission request signal obtained from the serial peripheral interface module 13 is consistent,
  • the data transmission module 12 is also used for:
  • the control transparent transmission flag signal is valid.
  • the transmission request signal output to the direct memory access controller is The transmission request signals obtained from the serial peripheral interface module 13 are consistent.
  • the data transmission module 12 is further configured to:
  • the control transparent transmission flag signal is invalid.
  • the transparent transmission flag signal is invalid, the sending request signal output to the direct memory access controller is invalid.
  • the data transmission module 12 is further configured to:
  • the data to be transmitted is at least one of an operation command, information length, and information content.
  • the device is used for the host of a photographing device; the opposite device used for acquiring the data to be transmitted is the lens of the photographing device; wherein, the operation command is an autofocus instruction, Zoom instruction, shooting mode instruction, anti-shake instruction, or data capture instruction; the information length is the length of the information content transmitted in one data transmission period; the information content includes image data information.
  • the data transmission device shown in FIG. 13 may be specifically implemented as the structure of FIG. 2 or FIG. 3.
  • the data transmission apparatus may execute the method of the embodiment shown in FIG. 1 to FIG. 8.
  • the related description of the embodiment shown in FIG. 1 to FIG. 8 For the implementation process and technical effects of this technical solution, please refer to the description in the embodiment shown in FIG. 1 to FIG. 8, which will not be repeated here.
  • an embodiment of the present invention provides a storage medium, the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used to implement the embodiments shown in FIGS. 1 to 8 above.
  • the data transmission method in.
  • FIG. 14 is a schematic structural diagram of an MCU provided by Embodiment 6 of the present invention. As shown in FIG. 14, this embodiment provides an MCU for connecting with a data transmission device. The MCU can execute the data transmission method corresponding to FIG. 9. Specifically, the MCU may include:
  • the storage unit 21 is used to store computer programs
  • the processing unit 22 is configured to run the computer program stored in the storage unit to realize:
  • the structure of the MCU may also include a communication interface 23 for communicating with other devices or communication networks.
  • the transmission instruction includes attribute information of the data to be transmitted, so that the data transmission module determines the number of clocks to be occupied by each byte in the data according to the attribute information And control the data transmission according to the determined number of clocks.
  • the number of clocks that the byte needs to occupy is the sum of the number of transmissions and the number of intervals;
  • the number of transmissions is the number of clocks required to transmit the bytes
  • the number of intervals is the number of clocks corresponding to the minimum interval between bytes.
  • the attribute information includes the minimum interval time between bytes when transmitting the data
  • the attribute information includes the number of clocks corresponding to the minimum time interval between bytes when transmitting the data.
  • processing unit 22 is further configured to:
  • processing unit 22 is further configured to:
  • the attribute information of the next data is determined and sent to the data transmission module.
  • the next data of the data is the information length, and the information length The next data is the information content.
  • the data to be transmitted is at least one of an operation command, information length, and information content
  • the MCU is used for the host of the photographing equipment; the opposite device used for acquiring the data to be transmitted is the lens of the photographing equipment; wherein, the operation commands are auto-focusing instructions, zooming instructions, shooting mode instructions, protection A jitter instruction or a data capture instruction; the information length is the length of the information content transmitted in one data transmission period; the information content includes image data information.
  • the MCU shown in FIG. 14 can execute the methods of the embodiments shown in FIGS. 9-12.
  • parts that are not described in detail in this embodiment please refer to the related descriptions of the embodiments shown in FIGS. 9-12.
  • an embodiment of the present invention provides a storage medium, the storage medium is a computer-readable storage medium, the computer-readable storage medium stores program instructions, and the program instructions are used to implement the embodiments shown in FIGS. 9-12.
  • An embodiment of the present invention also provides a data transmission device, including: the data transmission device described in any of the foregoing embodiments and the MCU described in any of the foregoing embodiments.
  • the data transmission device further includes a peer device connected to the data transmission device.
  • the data transmission device is a photographing device; the data transmission device is a host of the photographing device; and the opposite device is a lens of the photographing device.
  • the shooting device may be a single-lens reflex camera, a movie camera, a drone, etc., and the host and the lens in the shooting device may communicate based on the SPI four-wire communication standard, the host being SPI MASTER, and the lens being SPI SLAVE.
  • the disclosed related devices and methods can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be other division methods for example, multiple units or components may be It can be combined or integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present invention essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium.
  • the aforementioned storage media include: U disk, mobile hard disk, Read-Only Memory (ROM), Random Access Memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes.

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Abstract

La présente invention porte, selon des modes de réalisation, sur un procédé de transmission de données, un dispositif de transmission de données, un appareil de transmission de données, un MCU et un support de stockage. Le procédé comprend les étapes suivantes : un dispositif de stockage stocke des données à transmettre ; un module de transmission de données acquiert une instruction de transmission envoyée par une unité de microcontrôleur, et commande, en fonction de l'instruction de transmission, le dispositif de stockage de façon à transmettre les données à un module d'interface ; et le module d'interface transmet les données. Le procédé comprend en outre les étapes suivantes : si un débit de transmission du dispositif de stockage est supérieur à un débit auquel les données seront transmises par le module d'interface, la commande, au moyen du module de transmission de données, du dispositif de stockage de façon à transmettre les données à un débit correspondant au débit auquel les données seront transmises par le module d'interface. La solution technique fournie dans les modes de réalisation de la présente invention peut réduire le nombre d'interruptions d'une MCU et des surcharges subies par les interruptions, ce qui permet de réduire considérablement la charge de la MCU, et d'améliorer les performances de la MCU.
PCT/CN2020/071827 2020-01-13 2020-01-13 Procédé, dispositif et appareil de transmission de données, mcu et support de stockage WO2021142586A1 (fr)

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PCT/CN2020/071827 WO2021142586A1 (fr) 2020-01-13 2020-01-13 Procédé, dispositif et appareil de transmission de données, mcu et support de stockage
CN202080002728.1A CN112272824A (zh) 2020-01-13 2020-01-13 数据传输方法、装置、设备、mcu和存储介质

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