WO2021137625A1 - Display panel, display device, and method for manufacturing same - Google Patents

Display panel, display device, and method for manufacturing same Download PDF

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Publication number
WO2021137625A1
WO2021137625A1 PCT/KR2020/019421 KR2020019421W WO2021137625A1 WO 2021137625 A1 WO2021137625 A1 WO 2021137625A1 KR 2020019421 W KR2020019421 W KR 2020019421W WO 2021137625 A1 WO2021137625 A1 WO 2021137625A1
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WO
WIPO (PCT)
Prior art keywords
led chips
support member
layer
adhesive layer
light
Prior art date
Application number
PCT/KR2020/019421
Other languages
French (fr)
Korean (ko)
Inventor
정부기
박만금
Original Assignee
주식회사 에이맵플러스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020190179605A external-priority patent/KR102306773B1/en
Priority claimed from KR1020200008737A external-priority patent/KR20210094907A/en
Application filed by 주식회사 에이맵플러스 filed Critical 주식회사 에이맵플러스
Publication of WO2021137625A1 publication Critical patent/WO2021137625A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements

Definitions

  • An embodiment of the invention relates to a display panel and a display device.
  • An embodiment of the present invention relates to a method of manufacturing a display panel or a display device having a light source module.
  • An embodiment of the present invention relates to a panel in which LED chips having a size of micrometers or less are packaged and a method for manufacturing the same.
  • An embodiment of the invention relates to a display device having a display panel.
  • Conventional display devices are mainly composed of a display panel composed of a liquid crystal display (LCD) and a backlight, but recently, a semiconductor device such as a light emitting diode (LED) is used as a pixel as it is.
  • a display device using such an LED is being developed in a form that does not require a separate backlight.
  • a display device using such an LED can be made compact, and a high-brightness display with superior light efficiency compared to a conventional LCD can be realized.
  • the aspect ratio of the display screen can be freely changed and implemented in a large area, various types of large displays can be provided. In advertising or screen display in public places, the demand for large screens is increasing, and LEDs are used as display means of large screens.
  • An embodiment of the present invention provides a display device, a display panel, and a method of manufacturing the same for bonding a plurality of LED chips to one surface of a transparent circuit board and irradiating light through the other surface (or lower surface) of the circuit board.
  • An embodiment of the present invention provides a display device, a display panel, and a method of manufacturing the same in which one surface of a plurality of LED chips is adhered to a transparent circuit board and packaged.
  • An embodiment of the present invention provides a display device, a display panel, and a method for manufacturing the same in which one surface of a plurality of LED chips emitting light of at least three colors or the same color is adhered to a transparent circuit board and packaged.
  • An embodiment of the present invention provides a display panel in which a plurality of LED chips are picked up on a conductive carrier, and a lower surface of each of the LED chips is adhered to a transparent circuit board, and a method of manufacturing the same.
  • An embodiment of the present invention provides a display panel in which an adhesive layer is adhered to a lower surface of each of a plurality of LED chips and then adhered to the circuit board, and a method for manufacturing the same.
  • An embodiment of the present invention is a display panel and a display device capable of sealing a plurality of LED chips attached to a transparent circuit board with a resin member, and electrically connecting the electrodes of the LED chip to the pads of the circuit board with a pattern of a connection part can provide
  • An embodiment of the present invention may provide a display panel and a device thereof in which a light blocking unit is disposed between the other surface of a circuit board and a transparent cover, and an area overlapping each of the LED chips is opened in the light blocking unit area.
  • An embodiment of the present invention may provide a display panel in which a light blocking part and a phosphor layer are disposed between the other surface of a circuit board and a transparent cover, and an apparatus thereof.
  • a display panel includes a transparent support member; a thin film transistor (TFT) unit disposed on the upper surface of the support member and having pads; a plurality of LED chips disposed on the upper surface of the support member and having electrodes thereon; a transparent adhesive layer for adhering each of the plurality of LED chips to the upper surface of the support member; a resin member covering the plurality of LED chips; a plurality of connecting portions disposed on the resin member and connecting the electrodes and the pads, respectively; and a light blocking layer having a plurality of openings, each of which is open to a region facing the LED chip, on a lower surface of the support member, wherein light emitted from each of the LED chips is emitted to each of the openings through the support member.
  • TFT thin film transistor
  • the plurality of connection parts may include a photosensitive conductive material.
  • the light blocking layer may be adhered between the lower surface of the support member and the adhesive layer.
  • the light blocking layer may be adhered between the adhesive layer and the upper surface of the transparent cover.
  • the plurality of LED chips emit red, green, and blue light to form a pixel region, and a portion of the adhesive layer may be disposed in each of the openings.
  • the plurality of LED chips emit light of blue color, and among the plurality of LED chips forming the pixel region, a first phosphor layer in a first opening facing the first LED chip; and a second phosphor layer in a second opening facing the first LED chip among the plurality of LED chips. and a transparent layer is formed in the third opening facing the third LED chip among the plurality of LED chips, and a unit pixel is formed using the blue color light and the light wavelength converted by the first and second phosphor layers.
  • a passivation layer for protecting the plurality of connection parts, the resin member, and the upper part of the TFT part may be included.
  • the resin member and the light blocking layer may include a light or heat absorbing material.
  • a plurality of the adhesive layers are adhered to each of the LED chips, and may include thermally conductive inorganic fillers.
  • the adhesive layer may be adhered to an upper surface of the support member, and the resin member may be adhered to a side surface and an upper surface of each of the LED chips, and an outer surface of each of the adhesive layers.
  • the thickness of the adhesive layer is in the range of 0.1 ⁇ m to 50 ⁇ m
  • the transparent cover and the support member may be made of a glass material.
  • Each of the LED chips includes a first electrode and a second electrode
  • the TFT includes a first pad and a second pad on the periphery of each LED chip
  • the connection part includes a first electrode and the first electrode on the resin member.
  • a first connection part connected between the pads and a second connection part connected between the second electrode and the second pad may be included, and the first and second connection parts may include a photosensitive conductive material.
  • a method of manufacturing a display panel includes: a first step of picking up a plurality of LED chips having upper electrodes disposed on a lower surface of a conductive carrier; a second step of facing the conductive carrier on an auxiliary substrate on which a transparent adhesive layer is formed, and stamping the adhesive layer on each of the lower surfaces of the LED chips; When the adhesive layer is stamped on each of the LED chips, a conductive carrier is placed on a circuit board having a thin-film transistor (TFT) part, and the LED chips are attached to the upper surface of the transparent support member of the circuit board with an adhesive layer.
  • TFT thin-film transistor
  • the third step of making and a fourth step of forming a light blocking layer having a plurality of openings in which regions facing the LED chips are opened on a lower surface of the support member, wherein light emitted from each of the LED chips passes through the support member and enters the openings. can be released separately.
  • forming a resin member on the circuit board sealing the plurality of LED chips and the TFT pad; opening electrodes disposed on the plurality of LED chips and pads of the TFT unit; forming a photosensitive conductive layer on the resin member; and exposing and developing an area on the photosensitive conductive layer except for the connection area, and then forming connection portions made of a photosensitive material connected to each of the pad and the electrodes, respectively.
  • the method includes forming a passivation layer on the resin member and the connection parts, wherein the resin member and the light blocking layer are light or heat absorbing materials, and the resin member is the adhesive layer and the LED chip.
  • the method may include bonding a transparent cover to the lower surface of the support member with an adhesive layer made of a transparent material, wherein the adhesive layer may be adhered between the transparent cover and the lower surface of the support member.
  • the light blocking layer may be adhered between the lower surface of the support member and the adhesive layer.
  • the light blocking layer may be adhered between the adhesive layer and the upper surface of the transparent cover.
  • the plurality of LED chips emit red, green, and blue light to form a pixel region, and a portion of the adhesive layer may be disposed in each of the openings.
  • the plurality of LED chips emit light of blue color, and among the plurality of LED chips forming the pixel region, a first phosphor layer in a first opening facing the first LED chip; and a second phosphor layer in a second opening facing the first LED chip among the plurality of LED chips. and a transparent layer is formed in the third opening facing the third LED chip among the plurality of LED chips, and a unit pixel is formed using the blue color light and the light wavelength converted by the first and second phosphor layers.
  • a process of inspecting and replacing defective LED chips before and after picking up the plurality of LED chips may be performed.
  • an adhesive layer is attached to one surface of a plurality of LED chips in advance through a stamping process and then adhered to a transparent circuit board, so that the manufacturing process can be simplified, and the thickness of the adhesive layer can be provided uniformly
  • the embodiment of the present invention has a technical effect of removing the bonding process on the surface of the circuit board by attaching an adhesive layer to one surface of the LED chip through a stamping process.
  • the embodiment of the present invention has a technical effect that can protect the LED chips by bonding a plurality of LED chips having an adhesive layer formed thereon to a circuit board through a conductive carrier having elasticity.
  • An embodiment of the invention has a technical effect that can adhere a plurality of LED chips to the circuit board for each block or color.
  • the embodiment of the present invention has an effect of sealing the area except for the emitting surface of the LED chips by sealing the plurality of LED chips attached to the circuit board with a resin member.
  • An embodiment of the present invention may electrically connect the electrodes of the LED chip to the pads of the circuit board through a connection part disposed on the surface of the resin member for a plurality of LED chips attached to the circuit board. Accordingly, interference of light emitted to the lower surface of the circuit board may be blocked and light extraction efficiency may be improved.
  • the TFT unit and the LED chips are arranged on one surface of the circuit board, and the light emitting area may be provided through the other surface. Accordingly, a connection pattern for connecting to the lower pattern may not be formed on the side surface or the outer portion of the circuit board, and components such as a driver chip may be disposed on one surface of the circuit board.
  • An embodiment of the present invention simplifies the process by sealing a plurality of LED chips on one surface of a circuit board with a resin member, forming a conductive layer in a wet method, and then forming a connection part through a patterning process, thereby simplifying the process and patterning the connection part. It can improve reliability.
  • An embodiment of the invention provides a technical effect that can select and replace a defective LED chip before or/and after attaching a plurality of LED chips to a conductive carrier, and/or after attaching the LED chips to a circuit board, or additionally disposed there is
  • An embodiment of the present invention may provide a light source module, display panel or display device in which a plurality of LED chips are adhered to one surface of a circuit board with an adhesive layer and at least one of a light blocking unit, a phosphor layer, or a transparent cover is disposed on the other surface. .
  • the embodiment of the invention has a technical effect that the process yield of a light source module, a display panel, or a display device having a plurality of LED chips can be improved.
  • LED chips that emit light of the same color according to an embodiment of the present invention, or arranging LED chips that emit at least two or three kinds of light, improve the reliability of a light source module, a display panel, and a display device There are possible technical effects.
  • 1 and 2 are examples of cutting a circuit board having a TFT unit in units of panels according to an embodiment of the present invention.
  • FIG. 3 is a view showing an example of a display device having a plurality of LED chips according to an embodiment of the present invention.
  • FIGS. 4 and 5 are views illustrating a process of picking up a plurality of LED chips on a conductive carrier according to an embodiment of the present invention.
  • FIG. 6 is a cross-sectional view showing an example of an LED chip as an example of the invention.
  • FIG. 7 is a view showing a process of facing the adhesive layer on the lower surface of a plurality of LED chips in an embodiment of the present invention.
  • FIG 8 is a view illustrating a process in which an adhesive layer is coated on an auxiliary substrate according to an embodiment of the present invention.
  • FIG. 9 is a detailed configuration diagram of a conductive carrier in an embodiment of the present invention.
  • 10A and 10B are diagrams for explaining a pick-up process of an electrostatic chuck according to a comparative example.
  • FIG. 11 is a view illustrating an example of a conductive carrier layer in which LED chips to which an adhesive layer is adhered are arranged in an embodiment of the present invention.
  • FIG. 12 is a view showing an example of bonding LED chips picked up on a conductive carrier to a circuit board in an embodiment of the present invention.
  • 13 is an example in which LED chips are attached to one surface of a circuit board according to an embodiment of the present invention.
  • first to third LED chips are arranged on a circuit board according to an embodiment of the present invention.
  • 15A and 15B are diagrams illustrating a packaging process of an LED chip attached to a circuit board according to an embodiment of the present invention.
  • 16 is a detailed view of a process of exposing an electrode of an LED chip on the circuit board of FIG. 15A.
  • 17 is a view for explaining a packaging process of the LED chip attached to the circuit board of FIG. 15A.
  • FIGS. 15A and 17 are a detailed view of a process of exposing an electrode of an LED chip and forming a conductive layer on the circuit board of FIGS. 15A and 17 .
  • 19(A)-(C) are views for explaining a process of forming a connection part on an LED chip according to an embodiment of the present invention.
  • 20 is a diagram illustrating an example in which light is emitted by first to third LED chips on a circuit board in a display device according to an embodiment of the present invention.
  • 21 is a diagram illustrating an example of a connection between a TFT unit and an LED chip disposed on one surface of a circuit board according to an embodiment of the present invention.
  • FIG. 22 is a first modified example of the display device according to the embodiment of the present invention of FIG. 20 .
  • 29 is a second modified example of the display device according to the embodiment of the invention of FIG. 20 .
  • FIG. 30 is an example of a lens array of the transparent cover of FIG.
  • FIG. 31 is an example in which a driving board is connected to the circuit board of FIG. 22 .
  • FIG. 32 is an example of the plan view of FIG. 31 .
  • 33 is an example illustrating an edge side of a circuit board according to an embodiment of the present invention.
  • 34(A)(B) is a view showing an example of replacing an LED chip on a circuit board according to an embodiment of the present invention.
  • 35 and 36 are examples of arrangement of the region P11 and LEDs on the circuit board according to an embodiment of the present invention.
  • FIG. 37 is a graph comparing an adsorption force for adsorbing LED chips, a dechucking force for releasing, and an adhesive force of an adhesive layer according to an embodiment of the present invention.
  • each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be
  • a thin-film transistor (TFT) and LED chips are mounted in an individual light emitting area A1 on one surface (or an upper surface) of the support member 1 and a wiring pattern for driving them is formed.
  • the other surface (or the rear surface) of the support member 1 may be a light emitting surface or a display surface from which the lights emitted from the LED chips are emitted.
  • Each of the LED chips may be a mini LED or micro (eg, 100 ⁇ m or less) sized LEDs.
  • Each of the LED chips may be a nano-sized LED.
  • a driver IC or various components for driving the LED chip or TFT may be disposed on one surface of the support member 1 .
  • the driver IC or various components may be disposed on one surface of the support member 1 instead of on the other surface. Accordingly, light may be emitted through the transparent material of the support member 1 .
  • the support member 1 may be cut into unit-sized display panels 11, 12, 13, and 14 through cutting lines C21 and C22.
  • the individual support member 1 having the wiring pattern may be defined as a circuit board.
  • the support member 1 includes a support layer of the circuit board, and may be formed of a transparent material, and may include at least one of a plastic material, a glass material, a ceramic material, and a transparent insulating film.
  • the support member 1 may be a transparent flexible substrate having a pattern formed thereon or a non-flexible substrate.
  • the support member 1 may or may not have a lower pattern formed around the periphery.
  • each of the display panels 11, 12, 13, and 14 may be implemented in a size suitable for various application fields, such as a wrist watch, a mobile phone terminal, or a tiling-type monitor or TV, or a large TV or a single panel of a billboard.
  • the size of each of the display panels 11 , 12 , 13 , and 14 may be 2 inches or more or the size of a display having a micro LED, but is not limited thereto.
  • the boundary portion between the adjacent display panels 11, 12, 13, and 14 is a portion in which the support member 1 is cut to the size of individual panels.
  • the high heat emitted from the laser beam There may be a problem in that thermal shock is applied to or destroyed by the device or parts, and also various wiring adjacent to the cutting line may be deteriorated.
  • An example of the invention is to cut along the cutting lines C21 and C22 by a laser beam in a low-temperature vacuum chamber. Accordingly, thermal shock to the edge regions A2 and A3 of the individual support member 1 is minimized, and deterioration of the TFT and various components or wiring can be reduced.
  • the low-temperature vacuum chamber is a chamber in an environment in the range of 0 degrees to -50 degrees, and when gas is injected, a laser beam is irradiated.
  • the gas supplied from the low-temperature vacuum chamber may be selected and controlled, and may include at least one or both of an inert gas and a fluorine gas.
  • the gas is, for example, at least one of N 2 , Ar, He, CF 4 , SF 6 , NH 3 , CF 4 /H 2 , CHF 3 , C 2 F 6 , H 2 , C 2 H 4 , CH 4 and O 2 may be included.
  • the content of oxygen in the gas may be provided in the range of 0.1% or more, for example, 0.1% to 10%.
  • the type of gas may be selected through the synthesis unit and the content thereof may be adjusted. At this time, since plasma is generated and cut with a laser beam in an environment in the low-temperature vacuum chamber, deterioration of parts, elements, wiring, etc. caused by cutting of the support member 1 can be reduced. In addition, it is possible to minimize the heat damage (HAZ) in the vicinity due to high temperature during cutting, and it is possible to reduce the heat damage area to an area of 20 ⁇ m or less from the cutting lines C21 and C22. Accordingly, it is possible to improve the thermal reliability of the display panel or the substrate.
  • HZ heat damage
  • the process is carried out at a low temperature, it is possible to increase the processing speed.
  • heat damage to the substrate is reduced, and cracks, chipping, and condensation caused by humidity can be reduced. Accordingly, since the substrates are precisely cut in the low-temperature vacuum chamber, the gap between the panels can be reduced and the processing tolerance can be minimized.
  • the cut display panel 11 may be divided into a central emission area A1 and edge areas A2 and A3 which are non-emission areas.
  • upper pads or edge patterns 31 may be disposed on the upper surface Sa, or pads may be disposed at upper and lower edge areas. In this case, the pads may be formed in areas other than the display area. have.
  • the upper pads or edge patterns 31 may be conductive leads, and some may be used as test terminals.
  • the upper edge pattern 31 may be disposed on a cutting line passing through an edge portion of the unit panel.
  • unit pixels having a TFT unit 50 and a plurality of LED chips 2A, 2B, and 2C are arranged in a matrix form on one surface (or upper surface) Sa of the individual support member 1 .
  • the embodiment of the present invention provides blocks D1, D2, and D3 having previously provided LED chips 2A, 2B, and 2C, and the blocks (D1, D2, D3)
  • Each of 10 or more or 100 or more LED chips may be arranged at a preset interval.
  • the preset interval may be an interval for mounting the LED chips on the display panel.
  • Each of the blocks D1, D2, and D3 is, for example, a first block D1 in which first LED chips 2A are arranged, a second block D2 in which second LED chips 2B are arranged, and a third A third block D3 in which the LED chips 2C are arranged may be included.
  • the first LED chips 2A may emit red light
  • the second LED chips 2B may emit green light
  • the third LED chips 2C may emit blue light.
  • a plurality of first to third LED chips 2A, 2B, and 2C may be arranged at preset intervals in horizontal and vertical directions in each of the first to third blocks D1, D2, and D3.
  • Each of these blocks (D1, D2, D3) is sequentially adhered to a predetermined area on the support member 1, and then the LED chips of each block are electrically connected to each other, so that the LED on the support member 1 is It is possible to mount chips 2A, 2B, and 2C.
  • the LED chips a lower surface from which light is emitted is attached to one surface Sa of the support member 1 , and electrodes may be exposed on top of the LED chips.
  • the LED chips emit light of the same color (eg, blue)
  • all LED chips required for the panel are arranged in one block, and then the support member 1 ) can be mounted on
  • a first defective chip inspection process is performed.
  • the first defective chip inspection process may be performed on the first to third LED chips for each color block, or after inspecting the defective LED chips for the same color blocks, the defective LED chips may be removed and remounted. As the number of LED chips arranged on the unit panel of the LED display increases, the number of defective LED chips may increase, so that the defective LED chips may be removed and replaced in advance.
  • the inspection process of the defective LED chip may be performed using (Probe) equipment, wireless lighting equipment, automatic optical inspection (AOI) equipment, or the like. By extracting defective LED chips through this inspection process, the yield of the panel can be improved. Thereafter, after replacing the defective LED chip in the first defective chip inspection process, the panel yield can be further increased through the re-inspection process.
  • a resin member 150 that absorbs or blocks light may be disposed on the support member 1 to block light leakage or emission in the upper direction, and the other surface Sb or the lower direction of the support member 1 can be released as
  • the resin member 150 may include a resin member made of a light absorbing, heat absorbing or heat dissipating material and a passivation layer, which will be described later.
  • the LED chips 2A, 2B, and 2C of each block disposed on the support member 1 may be electrically connected to the TFT unit 50 to be driven, and the first to third LED chips 2A, 2B , 2C) may each be a sub-pixel, and a minimum area in which at least one of the first to third LED chips 2A, 2B, and 2C is disposed may be defined as a unit pixel.
  • the unit pixel three types of LED chips 2A, 2B, and 2C emitting different colors may be used, or a pixel area may be implemented by combining a blue LED chip and a phosphor layer.
  • the unit pixel may be implemented with LED chips 2A, 2B, and 2C emitting different colors, for example, at least three colors, or a combination of LED chips emitting the same color and sheets such as quantum dots or phosphors. have.
  • the unit pixel may emit red, green, and blue light.
  • the LED chips 2A, 2B, and 2C may include red (R), green (G), and blue (B) LED chips.
  • the LED chips 2A, 2B, and 2C may all include LED chips emitting the same color.
  • the LED chips 2A, 2B, and 2C are chips having a micro size for sub-pixels, and for example, the length of one side of each LED chip may be in the range of 10 ⁇ m to 100 ⁇ m.
  • the size of the LED chips 2A, 2B, and 2C may be in the range of a microscopic size ( ⁇ 1 ⁇ m, or 1 ⁇ m-50 ⁇ m) with one side length depending on the micro-manufacturing technology of the LED chip.
  • the size of the LED chips 2A, 2B, and 2C may be in a range of 1 ⁇ m to 50 ⁇ m ⁇ 1 ⁇ m to 50 ⁇ m or a nano size, but is not limited thereto.
  • the display panels when a plurality of display panels are closely coupled for a display device, they may be closely coupled so as not to be distinguished from the outside. That is, the display panels may have an arrangement structure or a coupling structure in which dark lines are not generated at the boundary portion.
  • the size of the display device including the display panels may vary according to the number of the display panels combined and the size of each panel. Also, in the display device, each panel has a structure that can be combined, separated or removed.
  • the circuit board of the display panel a TFT array board capable of driving a plurality of LED chips 2A, 2B, and 2C is used. That is, the circuit board has a TFT unit 50 for driving the plurality of LED chips 2A, 2B, and 2C and various wirings are formed.
  • the circuit board may include a circuit, for example, a thin film transistor, configured to independently drive sub-pixels, for example, the LED chips 2A, 2B, and 2C, disposed in each pixel region 2 .
  • a circuit for example, a thin film transistor, configured to independently drive sub-pixels, for example, the LED chips 2A, 2B, and 2C, disposed in each pixel region 2 .
  • the LED chips 2A, 2B, and 2C disposed in each pixel region 2 .
  • each pixel area 2 of the circuit board 20 at least three LED chips 2A, 2B, and 2C emitting monochromatic light of red, green, and blue are arranged, and the LED is illuminated by a signal applied from the outside. Lights of red, green and blue colors are emitted from the chip to display an image.
  • the plurality of LED chips 2A, 2B, and 2C may be mounted in a process separate from the TFT array process. That is, the TFT and various wirings are formed by a photo process, but the LED chips 2A, 2B, and 2C may be mounted through a separate bonding process or a reflow process.
  • the configuration of the circuit board having the TFT and the plurality of LED chips 2A, 2B, and 2C may be defined as a light source module.
  • the circuit board may include the LED chips 2A, 2B, and 2C and the TFT unit 50 connected thereto.
  • the circuit board may be formed of a transparent support member 1 such as glass, and the TFT unit 50 may be disposed on a first surface (one surface or an upper surface) of the support member 1 .
  • the light generated from the LED chips 2A, 2B, and 2C may be emitted through the second surface (the other surface or the lower surface) Sb of the support member 1 to function as a display device.
  • blocks D1, D2, and D3 having previously provided LED chips 2A, 2B, and 2C are prepared.
  • 10 or more or 100 or more LED chips may be arranged at a preset interval.
  • the preset interval may be an interval for mounting the LED chips on the display panel, and may be arranged to be arranged on different positions.
  • Each of the blocks D1, D2, and D3 is, for example, a first block D1 in which first LED chips 2A are arranged, a second block D2 in which second LED chips 2B are arranged, and a third A third block D3 in which the LED chips 2C are arranged may be included.
  • the first LED chips 2A may emit red light
  • the second LED chips 2B may emit green light
  • the third LED chips 2C may emit blue light.
  • a plurality of first to third LED chips 2A, 2B, and 2C may be arranged at preset intervals in horizontal and vertical directions in each of the first to third blocks D1, D2, and D3.
  • the process of attaching and packaging the first LED chip 2A will be described, and the description of the second and third LED chips 2B and 2C will be omitted or refer to the description of the first LED chip 2A. do it with
  • a conductive carrier connected to the support shaft 230 of the carrier body 250 ( 210) is aligned on the first block D1.
  • the electrodes K1 and K2 may be disposed on the upper portions of the first LED chips 2A, and a member or sheet emitting light may be disposed on the lower portions.
  • the light emitting member may be a transparent layer or a growth substrate.
  • LED chips of the same color may be arranged in one block, and may be aligned on a conductive carrier.
  • the first LED chips 2A are attached to the conductive carrier 210 as shown in FIG.
  • the conductive carrier 210 to which the first block D1 is attached may be moved in a vertical upward direction or the support body 310 may be moved in a different direction.
  • the lower portion of the conductive carrier 210 is provided with an elastic member 215 to reduce the impact transmitted to the first LED chip (2A) when the conductive carrier 210 is moved in the vertical downward direction. and the first LED chip 2A or other LED chips may be attached thereto.
  • Electrodes K1 and K2 disposed on the first LED chip 2A are attached to the conductive carrier 210 , and the electrodes K1 and K2 may include at least two electrodes.
  • the electrodes K1 and K2 may be pads of the first LED chip 2A.
  • a lower surface of the first LED chip 2A may be exposed.
  • a second defective chip inspection process is performed. When the first to third LED chips 2A, 2B, and 2C for each color are attached to the conductive carrier 210 or a single color LED chip is attached to the entire area, the LED chip or non-attached chip area is detected. will do Through this inspection, the defective LED chip can be removed through double-sided tape, and the defective LED chip can be removed or the LED chip can be attached to the non-attached area. Through the second defective chip inspection process, a defect rate that may be generated during the process may be reduced, and the yield of panels may be improved.
  • At least one or both of the LED chips 2A, 2B, and 2C is a light-transmitting substrate 101, light-emitting structures 102, 103, 104 on the light-transmitting substrate 101, and electrodes K1 and K2 disposed on the light-emitting structures 102, 103, 104. ) may be included.
  • a reflective layer 107 may be included between the uppermost layer of the light emitting structures 102 , 103 , and 104 and the electrodes K1 and K2 .
  • the light-transmitting substrate 101 is a growth substrate or a transparent layer, and may be formed of an insulating material or a semiconductor material.
  • the light-transmitting substrate 101 may be selected from a group including, for example, a sapphire substrate (Al 2 O 3 ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge, and may be removed.
  • the light emitting structures 1021 , 103 , and 104 may be formed of a compound semiconductor.
  • the light emitting structures 102 , 103 , and 104 may be formed of, for example, a group II-VI or group III-V compound semiconductor.
  • the light emitting structures 1021 , 103 , and 104 include at least two or more elements selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As), and nitrogen (N).
  • the light emitting structures 102 , 103 , and 104 include a first conductivity type semiconductor layer 102 connected to the first electrode K1 , a second conductivity type semiconductor layer 104 connected to the second electrode K2 , and the first and first The active layer 103 may be disposed between the two conductive semiconductor layers 102 and 104 .
  • the first and second conductivity-type semiconductor layers 102 and 104 may be implemented with at least one of group III-V or group II-VI compound semiconductors.
  • the first and second conductivity-type semiconductor layers 102 and 104 include, for example, at least one selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. can do.
  • the first conductivity-type semiconductor layer 102 may be an n-type semiconductor layer doped with an n-type dopant such as Si, Ge, Sn, Se, or Te.
  • the second conductivity-type semiconductor layer 104 may be a p-type semiconductor layer doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.
  • the first and second conductivity-type semiconductor layers 102 and 104 may be p-type and n-type semiconductor layers.
  • the active layer 103 may be implemented with a compound semiconductor.
  • the active layer 103 may be embodied, for example, by at least one of a group 3-5 or group 2-6 compound semiconductor.
  • the active layer 103 may include a plurality of well layers and a plurality of barrier layers arranged alternately, and may include InGaN/GaN, GaN/AlGaN, AlGaN/AlGaN.
  • the reflective layer 107 may be formed of a metal or non-metal material, and may include a single layer or multiple layers. As another example, the reflective layer 107 may include a DBR structure having different refractive indices.
  • the first and second electrodes K1 and K2 may be disposed on the LED chips 2A, 2B, and 2C.
  • the LED chips 2A, 2B, and 2C may be provided as flip chips, vertical chips, or horizontal chips depending on the positions of the first and second electrodes K1 and K2.
  • the first and second electrodes K1 and K2 are Ti, Al, In, Ir, Ta, Pd, Co, Cr, Mg, Zn, Ni, Si, Ge, Ag, Ag alloy, Au, Hf, Pt, It contains at least one or two or more of Ru and Rh, and may be formed as a single layer or multiple layers.
  • the first and second electrodes K1 and K2 include a stacked structure of Ti/Ag or Ti/ITO, and the Ag or ITO layer may be applied to prevent oxidation of Ti.
  • a protective layer, an insulating layer, or an insulating reflective layer may be further disposed in the region between the first and second electrodes K1 and K2 or on the surface of the light emitting structure, but is not limited thereto.
  • the structure of the LED chips 2A, 2B, and 2C is an example, and other semiconductor layers may be further disposed between each layer, but is not limited thereto.
  • a layer or film having a wavelength conversion material such as a phosphor may be disposed under the light-transmitting substrate 101 of the LED chips 2A, 2B, and 2C.
  • the phosphor may include at least one of yellow, green, red, and blue.
  • the phosphor may wavelength-convert the light emitted from the LED chips 2A, 2B, and 2C into red, green, yellow, and blue light.
  • a phosphor layer is further disposed on the lower surface of each LED chip, it may be adhered to the transparent support member with an adhesive layer.
  • the conductive carrier 210 to which the first LED chips 2A are attached respectively corresponds to or faces the auxiliary substrate 353 .
  • the auxiliary substrate 353 is disposed on the upper body 351 rotated by the rotation shaft 350 , and may be rotated together with the upper body 351 .
  • An adhesive layer B0 may be formed on a surface or an upper surface of the auxiliary substrate 353 .
  • the adhesive layer B0 may include a transparent material.
  • the adhesive layer B0 may be a transparent adhesive material.
  • the adhesive layer B0 may be made of a transparent inorganic oxide-based material, and in this case, it is possible to reduce discoloration due to light.
  • the adhesive layer B0 may include an adhesive material, a heat dissipation material having thermally conductive nanopowder, and/or a scattering prevention material.
  • the adhesive layer B0 may include a thermally conductive inorganic filler, or a carbon material or a ceramic material.
  • the adhesive layer B0 is another material, and may be a transparent material of an organic or inorganic material.
  • the thickness of the adhesive layer B0 may be 2 ⁇ m or less, for example, 0.2 ⁇ m to 2 ⁇ m.
  • the adhesive layer B0 may be provided with a uniform thickness over the entire region on the auxiliary substrate 353 .
  • the transmittance of the adhesive layer B0 may be 95% or more, for example, 98% or more.
  • the adhesive layer B0 may include an oxide material having at least one of Ag, Ti, Al, and Mo.
  • the adhesive layer B0 may include a multilayer structure, for example, a multilayer oxide structure such as Ti/Al/Ti or Mo/Al/Mo.
  • the auxiliary substrate 353 after dispensing a liquid adhesive material on the auxiliary substrate 353 , it may be formed in the form of spin coating. At this time, since the auxiliary substrate 353 is rotated, the thickness of the adhesive layer B0 may be provided with a uniform thickness. When a separate adhesive layer is formed on the LED chip, a thickness deviation may occur, and there is a problem in that a difference in adhesive strength with each LED chip is generated.
  • the auxiliary substrate 353 may be made of glass or plastic.
  • the liquid adhesive layer B0 may be deposited on the auxiliary substrate 353 by a spray method, or may be formed by a dipping method, a slit method, a roll coating method, or a printing method.
  • the adhesive material may have a viscosity of 1 CP or more, for example, a viscosity of about 1 to 150 CP.
  • the conductive carrier 210 is moved vertically downward or in the direction of the auxiliary substrate 353 , and the first LED chip 2A is brought into contact with the auxiliary substrate 353 . , moving in the vertical direction.
  • the adhesive layer B0 may be attached or adhered to the lower surface of the first LED chip 2A in the form of a stamp. That is, the adhesive layer B0 may be formed on the transparent substrate of each of the first LED chips 2A through the stamping process of the first LED chips 2A (see FIG. 11 ). 11 , the adhesive layer B10 may be formed to have a uniform thickness on the transparent substrate disposed under each of the first LED chips 2A.
  • the width or area of the adhesive layer B10 disposed on the lower surface of each of the LED chips 2A, 2B, 2C is the same as the width or area of the lower surface of the LED chips 2A, 2B, 2C, or the width or the lower surface It may be less than or equal to 120% of the area.
  • a third defective chip inspection process may be performed.
  • the LED chip of each color block to which the adhesive layer B10 is attached may be provided through the third defective chip inspection process, or the LED chip of a single block of the same color may be provided.
  • the conductive carrier 210 may include an elastic member 215 at a lower portion and may be a support plate 211 .
  • the elastic member 215 may include a conductive elastic member 212 , a dielectric layer 214 and an electrode layer 213 between the support plate 211 and the conductive elastic member 212 .
  • the dielectric layer 214 is formed under the support plate 211 and may support the dielectric layer 214 .
  • the support plate 211 may be a metal material or a non-metal material, or may include, for example, an aluminum material.
  • the dielectric layer 214 may include a non-metal material, for example, at least one of polyimide, polyester, ceramic, tantalum, and a silicon film.
  • the ceramic material is an amorphous ceramic material Al 2 O 3 , Y 2 O 3 , ZrO 2 , AlC, TiN, AlN, TiC, MgO, CaO, CeO 2 , TiO 2 , BxCy, BN, SiO 2 , SiC, YAG, In the group consisting of AlF 3 , one type or two or more types are each mixed and used.
  • the thickness of the dielectric layer 214 may be 1 mm or less, for example, in the range of 0.1 mm to 1 mm.
  • the electrode layer 213 may be disposed between the dielectric layer 214 and the conductive elastic member 212 .
  • An adhesive layer 216 may be disposed around the electrode layer 231 to bond the dielectric layer 214 and the elastic member 212 to each other.
  • the adhesive layer 216 may be a material of the dielectric layer 214 or a material such as silicone or epoxy.
  • the electrode layer 213 may receive power through the electrode line 218 and may include at least one or two or more of a conductive metal, for example, tungsten, molybdenum, titanium, silver, and copper.
  • electrode patterns in the form of a mesh are arranged, and may be uniformly distributed over the entire area.
  • the thickness of the electrode layer 213 may be 50 ⁇ m or less, for example, 15 to 50 ⁇ m.
  • the electrode layer 213 may be formed as a single layer or a multilayer.
  • the conductive elastic member 212 may include a conductive material having elasticity, and may be a polymer having viscosity and elasticity.
  • the conductive elastic member 212 may be rubber, a thermoplastic polymer, or a thermosetting polymer.
  • the conductive elastic member 212 may include a metal such as Ni, Cu, Ag, Al, or a metal oxide powder or a filler such as carbon black therein, and may function as an electrically conductive polymer.
  • the conductive carrier 210 is brought into contact with the LED chips 2A, 2B, and 2C, power is supplied through the electrode line 218.
  • an electrostatic attraction is generated between the dielectric layer 214 and the LED chips 2A, 2B, 2C or the conductive elastic member 212, and as time cures, the amount of charge decreases Each can be accumulated. Accordingly, the LED chips 2A, 2B, and 2C can be picked up on the lower surface of the conductive carrier 210 or the lower surface of the conductive elastic member 212 without a separate adhesive, and the conductive elastic member 212 in the pickup process. can decrease or buffer the pressure applied to the LED chips 2A, 2B, and 2C.
  • the pick-up process can be performed in the process of FIG. 4, and after being picked up, as shown in FIG. 11, the process of stamping the adhesive layer B0 to each LED chip 2A, 2B, 2C can be performed.
  • the power may be a DC voltage.
  • the first LED chip 2A having the adhesive layer B10 disposed on the lower portion of the conductive carrier 210 may correspond to or face the support member 1 or the circuit board. have.
  • the positions at which the plurality of first LED chips 2A are mounted on the circuit board 20 are set in advance, so that the conductive carrier 210 on which the first LED chips 2A is picked up is held by the support member 1 . ) or it can be aligned on the circuit board.
  • the first LED chips 2A attached to the conductive carrier 210 are placed on the support member 1 . It can be placed on (Release) and adhered with an adhesive layer (B10).
  • the support frame BS on which the support member 1 is disposed is a support member, and maintains a predetermined temperature, that is, 250 degrees or less, for example, 100 degrees to 250 degrees to facilitate curing of the transparent adhesive layer B10. It may be an electrostatic chuck. By providing a constant temperature deviation at this time, crack prevention in the resin formation process mentioned later can be suppressed. In this way, the LED chips 2A, 2B, and 2C of blocks of each color may be sequentially disposed on the upper surface of the support member 1, or LED chips of blocks of the same color may be disposed through a single attachment process.
  • the support member 1 has a plurality of pads 61 around or outside the area where the LED chips are to be arranged. , 63) can be arranged. That is, the pads 61 and 63 may be connected to the respective electrodes of the respective LED chips 2A, 2B, and 2C.
  • the plurality of pads 61 and 63, the plurality of first LED chips 2A, the plurality of second LED chips 2B, and the plurality of third LED chips 2C are provided on the support member 1 . It may be disposed on the upper surface.
  • the plurality of pads 61 and 63 may include a first pad 61 and a second pad 63 and may be alternately repeated.
  • the first LED chips 2A may be arranged on the support member 1 or the circuit board.
  • the adhesive layer B10 may be respectively disposed between the upper surface of the support member 1 and the first LED chip 2A.
  • the present invention can attach the LED chips 2A, 2B, and 2C to the adhesive layer B10 without performing a process of forming a separate solder on the pads 61 and 63 on the support member 1 .
  • the LED chip is attached on the circuit board or the support member by a natural unloading method rather than a pressurization method, there is no damage to the LED chip and hardening the adhesive layer (B10) by heat treatment after loading, the process This can be simplified.
  • a portion of the adhesive layer B10 may extend to the outer side surfaces of the LED chips 2A, 2B, and 2C by the loading process.
  • the second LED chip 2B of each second block and the third LED chip 2C of the third block shown in FIG. 4 are further aligned on the circuit board 20, respectively. can give That is, after the conductive carrier 210 is placed on the support member 1, the LED chips 2A, 2B, and 2C for each block are attached to the upper surface of the support member 1 as an adhesive layer B10, and then, the It will cut off the power supply.
  • the adhesive layer B10 is adhered to the upper surface of the support member 1 by a predetermined pressure, so that the LED chips for each block can be arranged, and the flow of the LED chips can be suppressed when attached.
  • 0V may be charged to the conductive elastic member 212 . That is, when the same voltage is applied and then blocked, a voltage of 0V is applied due to the conductive material of the conductive elastic member 212 , so that the LED chips can be separated from the conductive carrier 210 . Since the residual charge is easily discharged by the conductive elastic member 212, when a voltage is applied, the adsorption force can be increased, and when the power is turned off, the charged amount can be discharged without affecting the LED chip.
  • FIG. 37 is a graph comparing the adsorption force for adsorbing the LED chips, the dechucking force for releasing the LED chips, and the adhesion force of the adhesive layer.
  • the holding force of the upper conductive carrier (ESC) and the lower conductive carrier (ESC (backplane)) In the first step TA1, when the plurality of LED chips are attached to the support member, the adsorption force moves to the lower conductive carrier, and in the second step TA2, the upper conductive carrier is dechucked while the adsorption force moves to the lower part. This prevents the LED chips mLED from being separated from the top, and in the third step TA3 , the lower conductive carrier can adhere the LED chips uniformly while maintaining the horizontal correction of the LED chips while the adhesive layer is cured.
  • the pickup or separation method using the electrostatic carrier 210A is a device for accumulating charges similarly to that of a capacitor, in which two parallel metal plates 210B, Electrodes 1 and 2 are used.
  • the electrode plate to which the + electrode is applied becomes positively charged, and the electrode plate to which the - electrode is applied becomes to have a - charge.
  • electrostatic force is generated between the two parallel plates that are charged.
  • the electrostatic carrier 210A is a place where the substrate is placed inside the vacuum chamber.
  • the conductive elastic member 212 is disposed under the conductive carrier to protect the LED chip, while blocking the problem of residual charges affecting the LED chip.
  • each pixel region 2 of the circuit board 20 at least three LED chips 2A, 2B, and 2C emitting monochromatic light of red, green, and blue are arranged, and are applied from the outside. Lights of red, green, and blue colors are emitted from the LED chip by the signal to display an image.
  • a plurality of LED chips eg, blue LED chips
  • the plurality of LED chips 2A, 2B, and 2C may be mounted in a process separate from the TFT array process of the circuit board 20 . That is, the LED chips 2A, 2B, and 2C disposed on the circuit board 20 may be packaged and electrically connected through a process to be described later.
  • the boundary region P10 may be a region defined by a plurality of gate lines and data lines, and may be connected to the plurality of LED chips 2A, 2B, and 2C.
  • the thicknesses of the plurality of LED chips 2A, 2B, and 2C may be the same or the top surface height may be the same.
  • the top surface heights of different types of LED chips 2A, 2B, and 2C may be equalized by using the adhesive layer B10.
  • the resin member 151 molds the upper portion of the support member 1 .
  • the resin member 151 molds the first to third LED chips 2A, 2B, and 2C.
  • the resin member 151 may cover the surfaces of the LED chips 2A, 2B, and 2C and the pads 61 and 63 .
  • the resin member 151 may cover the surface of the TFT part.
  • the resin member 151 may include a material that absorbs, reflects, or blocks the light emitted through the LED chips 2A, 2B, and 2C.
  • the resin member 151 may prevent light leakage.
  • the resin member 151 may include at least one of a binder resin, a photopolymerization initiator, a black pigment, and a solvent.
  • the binder resin may include an epoxy resin, an acrylic resin, a polyimide resin, a panel resin, a silicone resin, or a car It may include a dog-based resin material.
  • the resin member 151 may be made of a resin-based or epoxy-based black material, and may include a light-blocking, reflective, or absorptive additive therein.
  • the resin member 151 may include a highly refractive inorganic spray, for example, TiO 2 sol, SrTiO 3 sol, ZnS, ZnSe, potassium bromide, AgCl, MgO, cesium iodide, cesium bromide, CaCO 3 , Phosphor.
  • a highly refractive inorganic spray for example, TiO 2 sol, SrTiO 3 sol, ZnS, ZnSe, potassium bromide, AgCl, MgO, cesium iodide, cesium bromide, CaCO 3 , Phosphor.
  • the resin member 151 may include a light absorbing material or a heat absorbing or heat dissipating material.
  • the outer surface of the resin member 151 may include a concave first recess R0, and the first recess R0 may include a concave curved surface and/or an inclined surface. That is, the surface of the first recess R0 may be formed so as not to be provided with an abruptly curved surface or a stepped surface.
  • the resin member 151 is disposed on top of the LED chips 2A, 2B, and 2C, on the sides of the LED chips 2A, 2B, and 2C, between adjacent LED chips 2A, 2B, and 2C, between the LED chips 2A, 2B. , 2C) and the pads 61 and 63 and between the electrodes K1 and K2, respectively.
  • the minimum distance between the LED chips 2A, 2B, and 2C and the pads 61 and 63 may be provided in a range of 2 ⁇ m or more, for example, 2 ⁇ m to 5 ⁇ m.
  • the electrodes K1, K2 and the pads 61 and 63 of the LED chips 2A, 2B, 2C are opened. do.
  • the opening process of the electrodes K1 and K2 and the pads 61 and 63 may be performed as a hard baking process through, for example, an exposure process using a mask, a developing process, and the like.
  • the electrodes K1 and K2 and the pads 61 and 63 may be exposed in the rear direction through the regions R1 , R2 , R3 , and R4 in which the resin member 151 is removed. As shown in (C) (D) of FIG.
  • a liquid conductive layer 160 is formed on the surface of the resin member 151 . do.
  • the conductive layer 160 may be formed on the upper surface of the resin member 151 , the electrodes K1 and K2 , and the upper surface of the pads 61 and 63 .
  • the conductive layer 160 may be formed by spraying the liquid conductive layer 160 over the entire upper surface of the resin member 151 and on the electrodes K1 and K2 and the pads 61 and 63.
  • the conductive layer 160 is covered with a single ink layer on the electrodes K1 and K2 and the pads 61 and 63 .
  • the conductive layer 160 may include a metal nano-powder and an adhesive binder.
  • the conductive layer 160 may include a photoinitiator, a metal nano-powder, and an adhesive binder.
  • the conductive layer 160 may include a graphene material, a metal nanopowder, an adhesive binder, and a photoinitiator.
  • the photoinitiator may be in the range of 10% by weight or less, for example, 0.01 to 10% by weight of the total weight of the ink composition.
  • the photoinitiator is a UV-sensitive material, and may be used by selectively combining three types of HP-8, TPO, and DETX.
  • the photoinitiator is 1-hydroxy-cyclohexyl-phenyl ketone, 2-hydroxy-2-methyl-1-phenyl-1-propanone, 2-hydroxy-1-[4-(2-hydroxyethoxy) Phenyl]-2-methyl-1-propanone, methylbenzoylformate, ⁇ -dimethoxy- ⁇ -phenylacetophenone, 2-benzoyl-2-(dimethylamino)-1-[4-(4-morpholinyl) Phenyl]-1-butanone, 2-methyl-1-[4-(methyl thio)phenyl]-2-(4-morpholinyl)-1-propanone diphenyl (2,4,6-trimethylbenzoyl) -phosphine oxide, or bis(2,4,6-trimethylbenzoyl)-phenylphosphine oxide, etc., but is not necessarily limited thereto.
  • the metal nanopowder may include at least one of Al, Si, Au, Ag, Pt, Cr, Mo, Ta, and Cu.
  • the metal nanopowder may have the highest proportion in the ink composition, for example, 50 wt% or more or may be in the range of 50 to 80 wt%.
  • the adhesive binder may include at least one of inorganic binders, for example, SiO 2 based, Na 2 O based, Al 2 O 3 based, Fe 2 O 3 based, and CaO based materials.
  • the adhesive binder may be in the range of 60% by weight or less, for example, 20 to 60% by weight of the total weight of the ink composition.
  • the graphene material may be in the range of 10% by weight or less, for example, 0.01 to 10% by weight.
  • the forming process of the conductive layer 160 may be formed by a wet method.
  • the conductive layer 160 may be formed by a sputtering process, but the sputtering process is more complicated than the wet process, and the thickness of the conductive layer may be thinner than the wet process.
  • a mask 170 may be disposed on the conductive layer 160 .
  • the opening OP1 of the mask 170 may be formed in a region overlapping the region to be removed. That is, the mask 170 may open an area excluding the area of the connection part.
  • a developing process is performed. At this time, as shown in FIGS. 15B (F) and 17 (A) (B), the developing process removes only the exposed region R5, and the unexposed region remains (FIG. 19B) ( see C)).
  • the connection part may connect the electrodes K1 and K2 of the LED chip and the pads 61 and 63 of the circuit board to each other. That is, the first connector 161 connects the first electrode K1 and the first pad 61 , and the second connector 162 connects the second electrode K2 and the second pad 63 .
  • the conductive layer on the resin member 151 covering each of the LED chips 2A, 2B, and 2C regions of the first and second connection parts 161 and 162 may remain separated from each other.
  • the passivation layer 155 may be formed thereon.
  • the passivation layer 155 may be formed on the upper surfaces of the first and second connection parts 161 and 162 and the exposed surface of the resin member 151 .
  • the passivation layer 155 may be a layer made of a material such as silicon or epoxy, or an insulating layer made of a heat dissipation material.
  • the resin member 151 may be adhered to the side surfaces of the LED chips 2A, 2B, and 2C, for example, the side surface of the light emitting structure 105 , the side surface of the light-transmitting substrate 101 , the electrode ( It can be attached to the side of K1, K2).
  • the resin member 151 may be adhered to the upper surfaces of the LED chips 2A, 2B, and 2C, and may be disposed higher than the upper surfaces of the electrodes K1 and K2.
  • the resin member 151 may be adhered to the protrusion B11 of the adhesive layer B10.
  • the adhesive layer B10 has a minimum thickness T1 of 1 ⁇ m or less, for example, 0.2 ⁇ m to 0.5 ⁇ m, and adheres the lower surfaces of the LED chips 2A, 2B, and 2C to the upper surface of the support member 1 , It can prevent the transmittance
  • the protrusion B11 is adhered to the side surface of the light-transmitting substrate 101 , and adhesion to the resin member 151 may be increased. Accordingly, the resin member 151 may be adhered to and supported around the LED chips 2A, 2B, and 2C to prevent flow.
  • a liquid photosensitive conductive layer 160 is formed on the entire surface of the resin member 151, and the connection part is exposed and developed through exposure and development.
  • the photosensitive conductive layer 160 may be made of a photosensitive conductive ink (PCI) material.
  • PCI photosensitive conductive ink
  • the process of forming the connection part using the PCI can be simplified to a heat treatment process after coating-exposure-developing without a photoresist (PR) process. If, compared to the sputtering process of forming the connection part, the process of coating the photoresist and removing it, the process of removing the remaining film of the photoresist, the metal etching process, etc. may be reduced.
  • the thickness of the connection parts 161 and 162 may be uniformly formed over the entire area and thicker than the sputtering method by performing a wet process.
  • the thickness of the connecting portions 161 and 162 may be formed in a thickness of 1.5 ⁇ m or more, for example, in the range of 1.5 to 5 ⁇ m. Accordingly, cracks in the connection portions 161 and 162 may be prevented, and a delamination phenomenon may be reduced. Also, the resistance at the connection portions 161 and 162 may be lowered to 50 m ⁇ or less.
  • the PCI process for example, has a high adhesion between ITO, which is a pad side material, and Au, which is an electrode side material, and can simplify the process through wet coating without a process of forming a separate bump.
  • the wet method may be formed by at least one of a spray coating method, a dip coating method, a spin coating method, or a printing method (eg, screen printing, inkjet printing).
  • a spray coating method e.g, a dip coating method, a spin coating method, or a printing method (eg, screen printing, inkjet printing).
  • connection part when forming the connection part in the same way as sputtering, the adhesive strength between ITO as the pad side material and Au as the electrode side material is low, so an adhesive layer such as Ti or TiW is further deposited, and then a connection layer such as Au or Cu is formed.
  • the thickness when forming a connection portion by a method such as sputtering, the thickness may be formed to be 1 ⁇ m or less, so that a peeling phenomenon or a crack may occur. As shown in FIG.
  • the connecting portions 161 and 162 in a wet manner, it is possible to reduce the phenomenon that liquid is drawn to an angled portion or a stepped portion on the surface of the resin member 151, and high resistance, heat generation, disconnection, etc. The problem can be eliminated.
  • the connecting portions 161 and 162 in a wet manner, the adhesive force and electrical characteristics between the connecting portions 161 and 162 and the resin member 151 may be improved.
  • the sputtering method is not excluded as a method of forming the connection part, and the above descriptions mean that the wet method may have improved technical characteristics compared to the sputter method.
  • the resin member 151 is sealed on the first to third LED chips 2A, 2B, and 2C, and the first electrode K1 of each LED chip 2A, 2B, and 2C and the TFT part are formed.
  • a first connection part 161 may be connected between the first pads 61
  • a second connection part 162 may be connected between the second electrode K2 and the second pad 63 of the TFT unit.
  • the first to third LED chips 2A, 2B, and 2C may be electrically connected to the TFT unit and selectively driven.
  • the first to third LED chips 2A, 2B, and 2C may emit light of different colors, for example, red, green, and blue light.
  • the first to third LED chips 2A, 2B, and 2C may emit light of the same color, for example, blue.
  • the emitted light may be emitted to the other surface through the transparent support member 1 .
  • the resin member 151 disposed around the LED chips 2A, 2B, and 2C absorbs or blocks the side exposure light, thereby increasing the visibility of the light.
  • the configuration of the circuit board 20 having the TFT and the plurality of LED chips 2A, 2B, and 2C disposed on the circuit board 20 may be defined as a light source module.
  • the circuit board 20 may include a TFT unit 50 connected to the LED chips 2A, 2B, and 2C.
  • the circuit board 20 may include a transparent support member 1 such as glass and a pad or line pattern thereon.
  • the TFT unit 50 may be disposed on one surface or an upper surface of the support member 1 .
  • the TFT unit 50 includes a gate electrode 51 , a semiconductor layer 53 , a source electrode 55 , and a drain electrode 57 .
  • a gate electrode 51 is formed on the circuit board 20 , a gate insulating layer 49 is formed over the entire area of the circuit board 110 to cover the gate electrode 51 , and a semiconductor layer 53 is formed with the gate It is formed on the insulating layer 49 , and a source electrode 55 and a drain electrode 57 are formed on the semiconductor layer 53 .
  • the gate electrode 51 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy or an alloy thereof, and the gate insulating layer 49 is made of an inorganic insulating material such as SiOx or SiNx. It may be made of a single layer made of or a plurality of layers made of SiOx and SiNx.
  • the semiconductor layer 53 may be formed of an amorphous semiconductor such as amorphous silicon, or an oxide semiconductor such as indium gallium zinc oxide (IGZO), TiO 2 , ZnO, WO 3 or SnO 2 .
  • IGZO indium gallium zinc oxide
  • TiO 2 , ZnO, WO 3 or SnO 2 oxide semiconductor
  • the semiconductor layer 53 is not limited to a specific material, and all kinds of semiconductor materials currently used in the TFT may be used.
  • the source electrode 55 and the drain electrode 57 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy or an alloy thereof.
  • the drain electrode 57 may be used as a first connection electrode for applying a signal to the LED chips 2A, 2B, and 2C.
  • the TFT unit 50 is a bottom gate type TFT in the drawing, the present invention is not limited to a TFT having a specific structure, and thin film transistors having various structures such as a top gate type TFT are used. could be applied.
  • a second connection electrode 59 is formed under the first insulating layer 41 .
  • the second connection electrode 59 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al or Al alloy or an alloy thereof, and the second connection electrode 59 (ie, the drain of the TFT). It may be formed by the same process as the electrode 57).
  • a first insulating layer 41 is formed on the circuit board 20 on which the TFT unit 50 is formed, and the LED chips 2A, 2B, and 2C are disposed in the opening of the first insulating layer 41 of the light emitting region. In this case, in the drawing, a portion of the first insulating layer 114 is removed and the LED chips 2A, 2B, and 2C may be arranged on the removed area.
  • the first insulating layer 41 may be composed of an organic layer such as a polyimide (PI) film or photoacrylic, or may have a multilayer structure such as an inorganic layer/organic layer or an inorganic layer/organic layer/inorganic layer.
  • First and second pads 61 and 63 may be disposed in the area where the first insulating layer 41 is opened.
  • the first pad 61 may be disposed on the first connection electrode 57 or may be a part of the material of the first connection electrode 57 .
  • the second pad 63 may be disposed on the second connection electrode 59 or may be a part of the second connection electrode 59 .
  • Both ends P2 and P4 of the first connection part 161 are connected to the first electrode K1 of each LED chip 2A, 2B, and 2C and the first pad 61 of the TFT part, and the second electrode K2 Both ends P1 and P3 of the second connection unit 162 may be connected to the second pad 63 of the TFT unit.
  • the first and second connection electrodes 57 and 59 may be formed on the upper surface of the support member 1 .
  • the resin member 151 and the adhesive layer B10 may be disposed in a region from which the gate insulating layer 49 formed on the upper surface of the support member 1 is removed.
  • the gate insulating layer 49 may extend on the lower surface of the resin member 151 and the adhesive layer B10 .
  • the first and second pads 61 and 63 may include at least two or more of Ti, Ni, Pt, TiN, Mo, Al, W, Cu, Ag, and Au.
  • the first and second pads 61 and 63 may be formed in multiple layers. Thereafter, when the LED chips for each color are mounted on the display panel, a cleaning process may be performed, and an abnormal portion such as flux may be removed through the cleaning process. At least one or both of the resin member 151 and the passivation layer 155 may be further extended on the surface of the TFT unit 50 to protect the surface of the TFT unit 50 .
  • a plurality of LED chips 2A, 2B, and 2C are disposed on a transparent support member 1 of a circuit board, molded with a resin member 151 , and electrically connected with connection parts 161 and 162 , , the surface may be protected by the passivation layer 155 .
  • the other surface (or lower surface) of the transparent support member 1 may be a surface from which light emitted through the LED chips 2A, 2B, and 2C is emitted.
  • the transparent cover 1A may be disposed on the other surface (or lower surface) of the support member 1 .
  • the transparent cover 1A may include at least one of a plastic material, a glass material, a ceramic material, and a transparent insulating film.
  • the transparent cover 1A may be made of a transparent flexible material or a non-ductile material.
  • the transparent cover 1A may be attached to the other surface of the support member 1 with an adhesive layer 1B.
  • the transparent cover 1A may be made of the same material as the support member 1 .
  • the transparent cover 1A may have the same thickness as the support member 1 or have a difference of ⁇ 30 ⁇ m from the thickness of the support member 1, and may be coupled to a display device or a panel.
  • the adhesive layer 1B may be disposed between the transparent cover 1A and the other surface of the support member 1 .
  • the adhesive layer 1B may be made of a transparent inorganic oxide-based material, and may be formed of, for example, a transparent mold or an optically clear resin. Discoloration of the adhesive layer 1B due to the light C1, C2, and C3 may be reduced.
  • the adhesive layer 1B may include an adhesive material, a heat dissipation material having thermally conductive nanopowder, and/or a scattering prevention material.
  • the adhesive layer 1B may include a thermally conductive inorganic filler, a carbon material, or a ceramic material.
  • the adhesive layer 1B is another material, and may be a transparent material of an organic or inorganic material.
  • the thickness of the adhesive layer 1B may be 60 ⁇ m or less, for example, in the range of 2 ⁇ m to 60 ⁇ m.
  • the adhesive layer 1B may be provided with a uniform thickness in the entire area.
  • the transmittance of the adhesive layer 1B may be 90% or more, for example, 95% or more.
  • the adhesive layer 1B may include an oxide material having at least one of Ag, Ti, Al, and Mo.
  • the adhesive layer 1B may include a multilayer structure, for example, a multilayer oxide structure such as Ti/Al/Ti or Mo/Al/Mo.
  • the light blocking layer M1 may be disposed between the transparent support member 1 and the transparent cover 1A.
  • the light blocking layer M1 may be adhered between the lower surface of the transparent support member 1 and the upper surface of the transparent cover 1A.
  • the light blocking layer M1 may be disposed between the adhesive layer 1B and the lower surface of the support member 1 .
  • the light blocking layer M1 may be disposed between the adhesive layer 1B and the upper surface of the transparent cover 1A.
  • the light-blocking layer M1 may be made of a resin-based black material, and may include at least one of a light-blocking, reflective, and absorptive additive therein.
  • the light blocking layer M1 may include a high refractive inorganic spray, for example, TiO 2 sol, SrTiO 3 sol, ZnS, ZnSe, potassium bromide, MgO, cesium iodide, cesium bromide, CaCO 3 , phosphorus tree. Bromide, phenyltrichloride, trichroman-4-one, thionyl bromide, ZnO 2 , CeO 2 , ITO sol, Ta 2 O 5 , Ti 2 O 5 , Ti 2 O 3 , ZrO 2 , Br 2 , CS 2 , ZrO 2 -TiO 2 sol, and SiO 2 -Fe 2 O 3 It may include at least one selected from the group consisting of compounds.
  • a high refractive inorganic spray for example, TiO 2 sol, SrTiO 3 sol, ZnS, ZnSe, potassium bromide, MgO, cesium iodide, cesium bromide, CaCO
  • the light blocking layer M1 may include a light absorbing material or a heat absorbing or heat dissipating material.
  • the light blocking layer M1 may have a thickness capable of blocking or absorbing light, and may be, for example, 30 ⁇ m or less or a range of 3 ⁇ m to 30 ⁇ m.
  • the light-blocking layer M1 may perform a heat dissipation function by the above-described thickness and additives.
  • the light blocking layer M1 may include a plurality of openings Ma, Mb, and Mc. Each of the openings Ma, Mb, and Mc may face each of the LED chips 2A, 2B, and 2C.
  • the plurality of openings Ma, Mb, and Mc may be spaced apart from each other, and an interval between the openings Ma, Mb, and Mc may be the same as an interval between adjacent LED chips.
  • a width W2 or a length of each of the openings Ma, Mb, and Mc may be greater than a width or length of the LED chip facing each of the openings Ma, Mb, and Mc. That is, the openings Ma, Mb, and Mc may be emission regions from which the light C1, C2, and C3 emitted from the LED chips 2A, 2B, and 2C are emitted.
  • a portion of the adhesive layer 1B may be formed in the openings Ma, Mb, and Mc of the light blocking layer M1.
  • the minimum thickness of the adhesive layer 1B is the thickness between the light blocking layer M1 and the transparent cover 1A, and may be formed to be 30 ⁇ m or less, and the maximum thickness is at the openings Ma, Mb, Mc. As a thickness of, it may be in the range of 0.1 ⁇ m to 60 ⁇ m.
  • Lights of each LED chip 2A, 2B, and 2C are emitted through the openings Ma, Mb, and Mc of the light blocking layer M1, and lights of different colors are emitted through the lower surface of the transparent cover 1A. can By controlling the driving of these LED chips, display control can be performed.
  • the process of forming the cover 1A, the adhesive layer 1B, and the light-blocking layer M1 under the support member 1 may be performed after forming the connection part or after forming the passivation layer.
  • the process of attaching the LED chips may be performed after forming the above configuration in advance on the lower portion of the support member 1 .
  • FIG. 23 is another example of the display panel of FIG. 22, including phosphor layers PS1 and PS2, a light blocking layer M1, an adhesive layer 1B, and a transparent cover 1A under the support member 1 can
  • the phosphor layers PS1 and PS2 may be disposed in at least two areas of the openings Ma, Mb, and Mb of the light blocking layer M1, and may be disposed between the transparent cover 1A and the lower surface of the support member 1 .
  • the phosphor layers PS1 and PS2 may be disposed between the adhesive layer 1B and the lower surface of the support member 1 .
  • the phosphor layers PS1 and PS2 may be disposed inside the openings Ma and Mb, or may be disposed on upper and/or lower surfaces of the openings Ma and Mb.
  • the phosphor layers PS1 and PS2 may be adhered to a lower surface of the support member 1 and/or an upper surface of the transparent cover 1A.
  • the phosphor layers PS1 and PS2 include a first phosphor layer PS1 in an area facing the first LED chip 2A, and a second phosphor layer PS2 in an area facing the second LED chip 2B. ) may be included. A portion of the transparent adhesive layer 1B may be formed in a region facing the third LED chip 2C.
  • the first phosphor layer PS1 may be disposed in the first opening Ma of the light blocking layer M1
  • the second phosphor layer PS2 may be disposed in the second opening Mb of the light blocking layer M1 .
  • the LED chip 2C emitting the same color emits blue light for example, the first phosphor layer PS1 converts blue light to emit red light, and the second phosphor layer PS2 emits blue light.
  • the wavelength of light By converting the wavelength of light, green light may be emitted. Accordingly, red, green, and blue light may be emitted through the first to third openings Ma, Mb, and Mc.
  • a blue phosphor layer may be further disposed in the third opening Mc.
  • the wavelength may be converted to another color using a phosphor layer to emit light. Accordingly, a pixel area emitting at least three colors or multi-color light of three or more colors may be implemented in the display panel or device, respectively.
  • the LED chip 2C emits the same color, the entire LED chip can be attached to the surface of the support member 1 at least once, so that the process can be simplified.
  • the unit pixel may be implemented in R/G/B like red, green, and blue light, or R/G/B/W (white) as sub-pixels, but the present invention is not limited thereto.
  • 24 to 28 are modified examples of the display panel of FIG. 23 .
  • the first phosphor layer PS1 may be disposed between the transparent adhesive layer B10 facing the first opening Ma and the transparent support member 1 .
  • the first phosphor layer PS1 may be in contact with the resin member 151 under the LED chip 2C on the first opening Ma.
  • the width or upper surface area of the first phosphor layer PS1 positioned on the first opening Ma may be smaller than the width or lower surface area of the adhesive layer B10 attached to the LED chip 2C.
  • the second phosphor layer PS2 may be disposed between the transparent adhesive layer B10 facing the second opening Mb and the transparent support member 1 .
  • the second phosphor layer PS2 may be in contact with the resin member 151 under the LED chip 2C positioned on the second opening Mb.
  • the width or upper surface area of the first phosphor layer PS2 positioned on the second opening Mb may be smaller than the width or lower surface area of the adhesive layer B10 bonded to the LED chip 2C on the second opening Mb.
  • the LED chip 2C positioned on the third opening Mc may be adhered to the support member 1 with an adhesive layer B10 .
  • a portion of the adhesive layer 1B may be disposed in each of the openings Ma, Mb, and Mc of the light blocking layer M1.
  • the first and second phosphor layers PS1 and PS2 may be respectively adhered between the adhesive layer 1B and the transparent cover 1A.
  • Each of the first and second phosphor layers PS1 and PS2 corresponds to the first and second openings Ma and Mb of the light blocking layer M1, and the widths of the first and second openings Ma and Mb or It may be provided with a width or an area greater than the area. Accordingly, it is possible to block light leakage to the outside of the phosphor layers PS1 and PS2 to which the adhesive layer 1B is adhered.
  • the first and second phosphor layers PS1 and PS2 may be respectively adhered between the adhesive layer 1B and the transparent support member 1 .
  • the light blocking layer M1 may be disposed between the adhesive layer 1B and the transparent cover 1A.
  • Each of the first and second phosphor layers PS1 and PS2 may be spaced apart from the upper portions of the first and second openings Ma and Mb of the light blocking layer M1, or may partially contact the light blocking layer M1. .
  • Each of the first and second phosphor layers PS1 and PS2 may have a width or area greater than that of the first and second openings Ma and Mb. Accordingly, it is possible to block light leakage through the outside and the openings Ma and Mb of the phosphor layers PS1 and PS2 to which the adhesive layer 1B is attached.
  • a light blocking layer M1 having an adhesive layer 1B/openings Ma, Mb, Mc) is disposed on the lower surface of the transparent support member 1, and a transparent cover is provided under the light blocking layer M1.
  • (1A) can be combined.
  • the openings Ma, Mb, and Mc may be disposed in regions corresponding to the respective LED chips 1C on the upper surface of the transparent cover 1A.
  • a first phosphor layer PS1 may be disposed in the first opening Ma, and a second phosphor layer PS2 may be disposed in the second opening Mb.
  • a portion of the adhesive layer 1B may extend to the third opening Mc to be adhered to the transparent cover 1A. As shown in FIG.
  • the transparent support member 1 and the transparent cover 1A may be adhered to each other with the light blocking layer M1 without an adhesive layer.
  • the light-blocking layer M1 may have a double-sided adhesive function or may be adhered by pressing.
  • the light blocking layer M1 has a plurality of openings Ma, Mb, Mc corresponding to each LED chip 2C, and the first phosphor layer PS1 is disposed in the first opening Ma, and the second opening A second phosphor layer PS2 may be disposed in (Mb).
  • a transparent resin part M5 may be disposed in the second opening Mc to transmit light.
  • the light blocking layer M1 having the openings Ma, Mb, Mc and the phosphor layers PS1 and PS2 are disposed between the transparent support member 1 and the transparent cover 1A, and through selective wavelength conversion Lights necessary for the pixel area may be emitted.
  • the transparent support member 1 is coated with the light blocking layer M1 and the phosphor layers PS1 and PS2, if the TFT substrate has poor coating, the unit cost of failure may be high. Accordingly, when the phosphor layers PS1 and PS2 and the light blocking layer M1 are formed on the transparent cover 1A, and a coating defect occurs, only the transparent cover can be replaced. In addition, since the transparent cover can be replaced or reworked, it can be economical.
  • a lens array Rn may be included on the lower surface of the transparent cover 1A.
  • Each lens shape of the lens array Rn may be formed in a convex hemispherical shape, and a plurality of lenses may be arranged on the lower surface of each of the LED chips 2A, 2B, and 2C and/or the lower surface of the phosphor layer.
  • Each lens of the lens array Rn has a width w1 and/or a height h1 of nanometer size, and may be formed to be 500 nm or less, for example, 100 nm to 500 nm. The width w1 or height h1 of each lens may be the same or different.
  • the lens array Rn of the transparent cover 1A may increase the transmittance of incident light and may increase light sensitivity and light efficiency.
  • the lens array Rn of the transparent cover 1A may be formed on the entire lower surface, thereby providing an anti-reflective function and a sun blocking function.
  • FIG. 36 when the lower surface of the transparent cover 1A is a flat surface and when a lens is formed, it is a graph comparing transmittance for each wavelength according to the lens size. As shown in this graph, it can be seen that, in the case of the nano size, the light transmittance is 95% or more.
  • the lens array Rn of the transparent cover 1A may provide different lens sizes in the area corresponding to the lower surface of each LED chip, thereby further increasing the transmittance.
  • the lens array Rn may be formed through a wet etching process.
  • the metal layer 192 and the insulating member 194 are formed in the boundary region P10 between the LED chips 2A, 2B, and 2C, and then the insulating member A part of 194 is opened to form a conductive portion 196 .
  • the conductive part 196 may include an anisotropic conductive film (ACF), and the conductive part 196 may be connected to the driving substrate 190 .
  • the driving substrate 190 may be selectively connected to each of the LED chips 2A, 2B, and 2C and the TFT unit 50 in FIG. 21 , and may be connected to a component such as a driver IC.
  • a plurality of the conductive parts 196 may be spaced apart from each other, and may be connected to other wirings or patterns through the contact parts 192 .
  • the insulating part 194 may be a layer of a light blocking material, a reflective material, or an absorbing material.
  • the driving board 190 may include a PCB or FPCB made of a resin material.
  • a heat dissipation member is further disposed on the upper portion of the support member 1 to effectively dissipate heat.
  • the process of forming the connection part does not proceed after forming the resin member 151, but after forming the insulating part 194, the connection part, the contact part 192, and the connection parts 161 and 162 for the driving board in one process. ) can be formed.
  • At least one of the passivation layer 155 and the resin member 151 may include an extension portion E10 extending to the upper surface adjacent to the side surface Sc of the support member 1 (E10). have. Accordingly, the extension portion E10 may protect the edge pattern 31 .
  • a side coating layer C11 may be formed by a laser cutting process, and the side coating layer C11 may extend the extension. It may be in contact with the portion E10.
  • the distance D11 from the edge pattern 31 to the side surface Sc may be 15 ⁇ m or less, for example, in the range of 0.5 ⁇ m to 15 ⁇ m, so that the edge pattern 31 is passed through the extension part E10. can protect
  • the dummy area A portion of the areas A11 , A12 , and A13 may be opened, and packaging and electrical connection processes may be performed as described above to replace a defective LED chip with a new (NEW) LED chip 2D.
  • This replacement process may be a third defective LED chip inspection and replacement process. After the defective LED chip is removed, the wiring process may form a partial connection part through the wet process using the conductive ink disclosed above.
  • each pixel region 2 has a pair of first to third LED chips 2A, 2B, and 2C, and is divided into pixel boundary regions P11 through the lower portion of the support member 1 .
  • Light L1 may be emitted.
  • a group of two pairs of first to third LED chips 2A, 2B, and 2C or dummy LED chip areas (ie, dummy pads) 22 may be further disposed in each pixel area 2 , as shown in FIG. 36 . have.

Abstract

A display panel disclosed in an embodiment of the invention comprises: a thin film transistor (TFT) unit disposed on an upper surface of a transparent support member and having pads; a plurality of LED chips disposed on the upper surface of the support member and having electrodes on an upper portion thereof; a transparent adhesive layer bonding each of the plurality of LED chips to the upper surface of the support member; a resin member covering the plurality of LED chips; a plurality of connection parts disposed on the resin member and respectively connecting the electrodes and the pads; and a light blocking layer having a plurality of openings, of which areas facing the LED chips are respectively opened, on a lower surface of the support member, wherein light emitted from each of the LED chips may be emitted to each of the openings through the support member.

Description

디스플레이 패널, 디스플레이 장치 및 그 제조방법Display panel, display device and manufacturing method thereof
발명의 실시 예는 디스플레이 패널 및 디스플레이 장치에 관한 것이다. 발명의 실시 예는 광원 모듈을 갖는 디스플레이 패널 또는 디스플레이 장치의 제조방법에 관한 것이다. 발명의 실시 예는 마이크로미터 이하의 크기를 갖는 LED칩들을 패키징한 패널 및 그 제조방법에 관한 것이다. 발명의 실시 예는 디스플레이 패널을 갖는 디스플레이 장치에 관한 것이다.An embodiment of the invention relates to a display panel and a display device. An embodiment of the present invention relates to a method of manufacturing a display panel or a display device having a light source module. An embodiment of the present invention relates to a panel in which LED chips having a size of micrometers or less are packaged and a method for manufacturing the same. An embodiment of the invention relates to a display device having a display panel.
종래의 디스플레이 장치는 주로 액정 디스플레이(LCD)로 구성된 디스플레이 패널과 백라이트로 구성되었으나, 최근에는 발광 다이오드(LED)와 같은 반도체 소자를 그대로 하나의 픽셀로서 사용하고 있다. 이러한 LED를 사용한 디스플레이 장치는 백라이트가 별도로 요구되지 않는 형태로 개발되고 있다. 또한 이러한 LED를 사용한 디스플레이 장치는 컴팩트화할 수 있을 뿐만 아니라, 기존 LCD에 비해 광효율도 우수한 고휘도 디스플레이를 구현될 수 있다. 또한, 디스플레이 화면의 종횡비를 자유롭게 바꾸고 대면적으로 구현할 수 있으므로 다양한 형태의 대형 디스플레이로 제공할 수 있다. 공공장소의 광고나, 화면표시에 있어서, 대형화면의 수요가 점점 늘고 있으며, 대형화면의 표시수단으로 LED를 사용하고 있다. 이는 종래의 액정 발광 패널을 이용한 표시수단에 비해 대형화가 용이하고, 전기 에너지의 소모가 적으며, 적은 유지보수비용으로 긴 수명을 가지기 때문이다. 최근 LED를 이용한 대형 표시수단은 TV, 모니터, 경기장용 전광판, 옥외광고, 옥내광고, 공공표지판, 및 정보표시판 등의 여러 곳에 사용되고 있으며, 그 구성방법 또한 다양하다.Conventional display devices are mainly composed of a display panel composed of a liquid crystal display (LCD) and a backlight, but recently, a semiconductor device such as a light emitting diode (LED) is used as a pixel as it is. A display device using such an LED is being developed in a form that does not require a separate backlight. In addition, a display device using such an LED can be made compact, and a high-brightness display with superior light efficiency compared to a conventional LCD can be realized. In addition, since the aspect ratio of the display screen can be freely changed and implemented in a large area, various types of large displays can be provided. In advertising or screen display in public places, the demand for large screens is increasing, and LEDs are used as display means of large screens. This is because it is easy to enlarge the display means using a conventional liquid crystal light emitting panel, consumes less electrical energy, and has a long lifespan with low maintenance cost. Recently, large display means using LEDs are used in various places such as TVs, monitors, electric signs for stadiums, outdoor advertisements, indoor advertisements, public signs, and information display boards, and the configuration methods are also various.
발명의 실시 예는 투명한 회로기판의 일면에 복수의 LED칩을 접착시키고, 회로기판의 타면(또는 하면)을 통해 광을 조사하는 디스플레이 장치, 디스플레이 패널 및 그 제조방법을 제공한다. 발명의 실시 예는 복수의 LED칩의 일면을 투명한 회로기판에 접착시키고 패키징한 표시 장치, 디스플레이 패널 및 그 제조방법을 제공한다. 발명의 실시 예는 적어도 3개의 컬러 또는 서로 동일한 컬러의 광을 발광하는 복수의 LED칩의 일면을 투명한 회로기판에 접착시키고 패키징한 디스플레이 장치, 디스플레이 패널 및 그 제조방법을 제공한다. 발명의 실시 예는 도전성 캐리어 상에 복수의 LED칩을 픽업한 후, 상기 LED칩들 각각의 하면을 투명한 회로기판에 접착시킨 디스플레이 패널 및 그 제조방법을 제공한다. 발명의 실시 예는 복수의 LED칩 각각의 하면에 접착층을 접착시킨 다음, 상기 회로기판에 접착시킨 디스플레이 패널 및 그 제조방법을 제공한다. 발명의 실시 예는 투명한 회로기판 상에 부착된 복수의 LED칩들을 수지부재로 밀봉하고, 연결부의 패턴으로 상기 회로기판의 패드들과 LED칩의 전극들을 전기적으로 연결해 줄 수 있는 디스플레이 패널 및 디스플레이 장치를 제공할 수 있다. 발명의 실시 예는 회로기판의 타면과 투명한 커버 사이에 광 차단부를 배치하고, 광 차단부의 영역에서 LED칩들 각각과 중첩되는 영역을 오픈시킨 디스플레이 패널 및 그 장치를 제공할 수 있다. 발명의 실시 예는 회로기판의 타면과 투명한 커버 사이에 광 차단부 및 형광체층을 배치한 디스플레이 패널 및 그 장치를 제공할 수 있다.An embodiment of the present invention provides a display device, a display panel, and a method of manufacturing the same for bonding a plurality of LED chips to one surface of a transparent circuit board and irradiating light through the other surface (or lower surface) of the circuit board. An embodiment of the present invention provides a display device, a display panel, and a method of manufacturing the same in which one surface of a plurality of LED chips is adhered to a transparent circuit board and packaged. An embodiment of the present invention provides a display device, a display panel, and a method for manufacturing the same in which one surface of a plurality of LED chips emitting light of at least three colors or the same color is adhered to a transparent circuit board and packaged. An embodiment of the present invention provides a display panel in which a plurality of LED chips are picked up on a conductive carrier, and a lower surface of each of the LED chips is adhered to a transparent circuit board, and a method of manufacturing the same. An embodiment of the present invention provides a display panel in which an adhesive layer is adhered to a lower surface of each of a plurality of LED chips and then adhered to the circuit board, and a method for manufacturing the same. An embodiment of the present invention is a display panel and a display device capable of sealing a plurality of LED chips attached to a transparent circuit board with a resin member, and electrically connecting the electrodes of the LED chip to the pads of the circuit board with a pattern of a connection part can provide An embodiment of the present invention may provide a display panel and a device thereof in which a light blocking unit is disposed between the other surface of a circuit board and a transparent cover, and an area overlapping each of the LED chips is opened in the light blocking unit area. An embodiment of the present invention may provide a display panel in which a light blocking part and a phosphor layer are disposed between the other surface of a circuit board and a transparent cover, and an apparatus thereof.
발명의 실시 예에 따른 디스플레이 패널은, 투명한 지지부재; 상기 지지부재의 상면에 배치되며 패드들을 갖는 박막트랜지터(TFT)부; 상기 지지부재의 상면에 배치되며 상부에 전극들을 갖는 복수의 LED칩; 상기 복수의 LED칩 각각을 상기 지지부재의 상면에 접착하는 투명한 접착층; 상기 복수의 LED칩을 덮는 수지부재; 상기 수지부재 상에 배치되며 상기 전극과 패드를 각각 연결하는 복수의 연결부; 및 상기 지지부재의 하면에 상기 LED칩과 대면하는 영역 각각이 오픈된 복수의 개구부를 갖는 광차단층을 포함하며, 상기 LED칩들 각각에서 방출된 광은 상기 지지부재를 거쳐 상기 개구부들 각각으로 방출될 수 있다.A display panel according to an embodiment of the present invention includes a transparent support member; a thin film transistor (TFT) unit disposed on the upper surface of the support member and having pads; a plurality of LED chips disposed on the upper surface of the support member and having electrodes thereon; a transparent adhesive layer for adhering each of the plurality of LED chips to the upper surface of the support member; a resin member covering the plurality of LED chips; a plurality of connecting portions disposed on the resin member and connecting the electrodes and the pads, respectively; and a light blocking layer having a plurality of openings, each of which is open to a region facing the LED chip, on a lower surface of the support member, wherein light emitted from each of the LED chips is emitted to each of the openings through the support member. can
발명의 실시 예에 의하면, 상기 복수의 연결부는 감광성 도전 재질을 포함할 수 있다. 발명의 실시 예에 의하면, 상기 지지부재의 하면에 투명한 커버; 및 상기 투명한 커버와 상기 지지부재의 하면 사이에 투명한 접착제층을 포함할 수 있다. 상기 광차단층은 상기 지지부재의 하면과 상기 접착제층 사이에 접착될 수 있다. 상기 광차단층은 상기 접착제층과 상기 투명 커버의 상면 사이에 접착될 수 있다. 발명의 실시 예에 의하면, 상기 복수의 LED칩은 픽셀 영역을 형성하기 위해 적색, 녹색 및 청색의 광을 발광하며, 상기 개구부들 각각에는 상기 접착제층의 일부가 배치될 수 있다. 발명의 실시 예에 의하면, 상기 복수의 LED칩은 청색 컬러의 광을 발광하며, 픽셀 영역을 형성하는 복수의 LED칩 중 제1 LED칩에 대면하는 제1개구부에 제1형광체층; 및 상기 복수의 LED칩 중 제1 LED칩에 대면하는 제2개구부에 제2형광체층; 및 상기 복수의 LED칩 중 제3 LED칩에 대면하는 제3개구부에 투명한 층이 형성되며, 상기 청색 컬러의 광과 제1 및 제2형광체층에 의해 파장 변환된 광들을 갖고 단위 픽셀을 형성할 수 있다. According to an embodiment of the present invention, the plurality of connection parts may include a photosensitive conductive material. According to an embodiment of the invention, a transparent cover on the lower surface of the support member; and a transparent adhesive layer between the transparent cover and the lower surface of the support member. The light blocking layer may be adhered between the lower surface of the support member and the adhesive layer. The light blocking layer may be adhered between the adhesive layer and the upper surface of the transparent cover. According to an embodiment of the present invention, the plurality of LED chips emit red, green, and blue light to form a pixel region, and a portion of the adhesive layer may be disposed in each of the openings. According to an embodiment of the present invention, the plurality of LED chips emit light of blue color, and among the plurality of LED chips forming the pixel region, a first phosphor layer in a first opening facing the first LED chip; and a second phosphor layer in a second opening facing the first LED chip among the plurality of LED chips. and a transparent layer is formed in the third opening facing the third LED chip among the plurality of LED chips, and a unit pixel is formed using the blue color light and the light wavelength converted by the first and second phosphor layers. can
발명의 실시 예에 의하면, 상기 복수의 연결부, 상기 수지부재 및 상기 TFT부의 상부를 보호하는 패시베이션층을 포함할 수 있다. 상기 수지부재 및 상기 광차단층은 광 또는 열 흡수 재질을 포함할 수 있다. 상기 접착층은 복수개가 상기 LED칩들 각각에 접착되며, 열 전도성의 무기 필러를 포함할 수 있다. 상기 접착층은 상기 지지부재의 상면에 접착되며, 상기 수지부재는 상기 LED칩들 각각의 측면 및 상면, 상기 접착층들 각각의 외면에 접착될 수 있다. According to an embodiment of the present invention, a passivation layer for protecting the plurality of connection parts, the resin member, and the upper part of the TFT part may be included. The resin member and the light blocking layer may include a light or heat absorbing material. A plurality of the adhesive layers are adhered to each of the LED chips, and may include thermally conductive inorganic fillers. The adhesive layer may be adhered to an upper surface of the support member, and the resin member may be adhered to a side surface and an upper surface of each of the LED chips, and an outer surface of each of the adhesive layers.
발명의 실시 예에 의하면, 상기 접착층의 두께는 0.1㎛ 내지 50㎛의 범위이며, 상기 투명 커버와 상기 지지부재는 글라스 재질일 수 있다. 상기 LED칩들 각각은 제1전극 및 제2전극을 포함하며, 상기 TFT는 각 LED칩의 주변에 제1패드 및 제2패드를 포함하며, 상기 연결부는 상기 수지부재 상에서 제1전극과 상기 제1패드 사이에 연결된 제1연결부, 및 상기 제2전극과 상기 제2패드 사이에 연결된 제2연결부를 포함하며, 상기 제1 및 제2연결부는 감광성 도전재질을 포함할 수 있다. 발명의 실시 예에 따른 디스플레이 패널의 제조방법은, 도전성 캐리어의 하면에 상부 전극들이 배치된 복수의 LED칩을 픽업하는 제1단계; 상기 도전성 캐리어를 투명한 접착층이 형성된 보조기판 상에 대향시키고, 상기 LED칩들의 하면 각각에 상기 접착층을 스템핑하는 제2단계; 상기 LED칩들 각각에 상기 접착층이 스템핑되면, 박막트랜지스터(TFT: Thin-film transistor)부를 갖는 회로기판 상에 도전성 캐리어를 위치시키고, 상기 LED칩들을 회로기판의 투명한 지지부재의 상면에 접착층으로 부착시키는 제3단계; 및 상기 지지부재의 하면에 LED칩과 대면하는 영역이 오픈된 복수의 개구부를 갖는 광차단층을 형성하는 제4단계를 포함하며, 상기 LED칩들 각각에서 방출된 광은 상기 지지부재를 거쳐 상기 개구부들 각각으로 방출될 수 있다. 발명의 실시 예에 의하면, 상기 회로기판 상부에 수지부재를 형성하여 상기 복수의 LED칩 및 TFT부의 패드를 밀봉하는 단계; 상기 복수의 LED칩의 상부에 배치된 전극들과 상기 TFT부의 패드들을 오픈시키는 단계; 상기 수지부재 상에 감광성 도전층을 형성하는 단계; 및 상기 감광성 도전층 상에 연결부 영역을 제외한 영역에 대해 노광하고 현상한 후 상기 패드와 전극들 각각에 연결된 감광성 재질의 연결부들을 각각 형성하는 단계를 포함할 수 있다.According to an embodiment of the present invention, the thickness of the adhesive layer is in the range of 0.1 μm to 50 μm, and the transparent cover and the support member may be made of a glass material. Each of the LED chips includes a first electrode and a second electrode, the TFT includes a first pad and a second pad on the periphery of each LED chip, and the connection part includes a first electrode and the first electrode on the resin member. A first connection part connected between the pads and a second connection part connected between the second electrode and the second pad may be included, and the first and second connection parts may include a photosensitive conductive material. A method of manufacturing a display panel according to an embodiment of the present invention includes: a first step of picking up a plurality of LED chips having upper electrodes disposed on a lower surface of a conductive carrier; a second step of facing the conductive carrier on an auxiliary substrate on which a transparent adhesive layer is formed, and stamping the adhesive layer on each of the lower surfaces of the LED chips; When the adhesive layer is stamped on each of the LED chips, a conductive carrier is placed on a circuit board having a thin-film transistor (TFT) part, and the LED chips are attached to the upper surface of the transparent support member of the circuit board with an adhesive layer. the third step of making; and a fourth step of forming a light blocking layer having a plurality of openings in which regions facing the LED chips are opened on a lower surface of the support member, wherein light emitted from each of the LED chips passes through the support member and enters the openings. can be released separately. According to an embodiment of the invention, forming a resin member on the circuit board, sealing the plurality of LED chips and the TFT pad; opening electrodes disposed on the plurality of LED chips and pads of the TFT unit; forming a photosensitive conductive layer on the resin member; and exposing and developing an area on the photosensitive conductive layer except for the connection area, and then forming connection portions made of a photosensitive material connected to each of the pad and the electrodes, respectively.
발명의 실시 예에 의하면, 상기 수지부재, 및 상기 연결부들 상에 패시베이션층을 형성하는 단계를 포함하며, 상기 수지부재 및 광차단층은 광 또는 열 흡수 재질이며, 상기 수지부재는 상기 접착층과 LED칩의 측면에 접착될 수 있다. 발명의 실시 예에 의하면, 상기 지지부재의 하면에 투명 커버를 투명한 재질의 접착제층으로 접착시키는 단계를 포함하며, 상기 접착제층은 상기 투명 커버와 상기 지지부재의 하면 사이에 접착될 수 있다. 상기 광차단층은 상기 지지부재의 하면과 상기 접착제층 사이에 접착될 수 있다. 상기 광차단층은 상기 접착제층과 상기 투명 커버의 상면 사이에 접착될 수 있다. 발명의 실시 예에 의하면, 상기 복수의 LED칩은 픽셀 영역을 형성하기 위해 적색, 녹색 및 청색의 광을 발광하며, 상기 개구부들 각각에는 상기 접착제층의 일부가 배치될 수 있다. 발명의 실시 예에 의하면, 상기 복수의 LED칩은 청색 컬러의 광을 발광하며, 픽셀 영역을 형성하는 복수의 LED칩 중 제1 LED칩에 대면하는 제1개구부에 제1형광체층; 및 상기 복수의 LED칩 중 제1 LED칩에 대면하는 제2개구부에 제2형광체층; 및 상기 복수의 LED칩 중 제3 LED칩에 대면하는 제3개구부에 투명한 층이 형성되며, 상기 청색 컬러의 광과 제1 및 제2형광체층에 의해 파장 변환된 광들을 갖고 단위 픽셀을 형성할 수 있다. 발명의 실시 예에 의하면, 상기 복수의 LED칩을 픽업하기 전 및 픽업한 다음에 불량 LED칩을 검사하여 교체하는 공정을 수행할 수 있다.According to an embodiment of the invention, the method includes forming a passivation layer on the resin member and the connection parts, wherein the resin member and the light blocking layer are light or heat absorbing materials, and the resin member is the adhesive layer and the LED chip. can be attached to the side of According to an embodiment of the invention, the method may include bonding a transparent cover to the lower surface of the support member with an adhesive layer made of a transparent material, wherein the adhesive layer may be adhered between the transparent cover and the lower surface of the support member. The light blocking layer may be adhered between the lower surface of the support member and the adhesive layer. The light blocking layer may be adhered between the adhesive layer and the upper surface of the transparent cover. According to an embodiment of the present invention, the plurality of LED chips emit red, green, and blue light to form a pixel region, and a portion of the adhesive layer may be disposed in each of the openings. According to an embodiment of the present invention, the plurality of LED chips emit light of blue color, and among the plurality of LED chips forming the pixel region, a first phosphor layer in a first opening facing the first LED chip; and a second phosphor layer in a second opening facing the first LED chip among the plurality of LED chips. and a transparent layer is formed in the third opening facing the third LED chip among the plurality of LED chips, and a unit pixel is formed using the blue color light and the light wavelength converted by the first and second phosphor layers. can According to an embodiment of the present invention, a process of inspecting and replacing defective LED chips before and after picking up the plurality of LED chips may be performed.
발명의 실시 예는 복수의 LED칩들의 일면에 접착층을 미리 스템핑 공정을 통해 부착한 후 투명한 회로기판에 접착시켜 줄 수 있어, 제조 공정이 간단해질 수 있으며, 접착층의 두께를 균일하게 제공할 수 있는 기술적 효과가 있다. 발명의 실시 예는 스템핑 공정을 통해 LED칩의 일면에 접착층을 부착해 줌으로써, 회로기판의 표면 상에서의 접착 공정이 제거되는 기술적 효과가 있다. 발명의 실시 예는 탄성을 갖는 도전성 캐리어를 통해 접착층이 형성된 복수의 LED칩들을 회로기판에 접착시켜 줄 수 있어, LED칩들을 보호할 수 있는 기술적 효과가 있다.In an embodiment of the present invention, an adhesive layer is attached to one surface of a plurality of LED chips in advance through a stamping process and then adhered to a transparent circuit board, so that the manufacturing process can be simplified, and the thickness of the adhesive layer can be provided uniformly There are technical effects. The embodiment of the present invention has a technical effect of removing the bonding process on the surface of the circuit board by attaching an adhesive layer to one surface of the LED chip through a stamping process. The embodiment of the present invention has a technical effect that can protect the LED chips by bonding a plurality of LED chips having an adhesive layer formed thereon to a circuit board through a conductive carrier having elasticity.
발명의 실시 예는 복수의 LED칩들을 블록별 또는 컬러별로 회로기판에 접착시켜 줄 수 있는 기술적 효과가 있다. 발명의 실시 예는 회로기판 상에 부착된 복수의 LED칩들을 수지부재로 밀봉함으로써, LED칩들의 출사면을 제외한 영역을 밀봉할 수 있는 효과가 있다. 발명의 실시 예는 회로기판 상에 부착된 복수의 LED칩들을 수지부재의 표면에 배치된 연결부를 통해 LED칩의 전극과 회로기판의 패드들을 전기적으로 연결해 줄 수 있다. 이에 따라 회로기판의 하면으로 방출되는 광의 간섭을 차단할 수 있고 광 추출 효율을 개선할 수 있다. An embodiment of the invention has a technical effect that can adhere a plurality of LED chips to the circuit board for each block or color. The embodiment of the present invention has an effect of sealing the area except for the emitting surface of the LED chips by sealing the plurality of LED chips attached to the circuit board with a resin member. An embodiment of the present invention may electrically connect the electrodes of the LED chip to the pads of the circuit board through a connection part disposed on the surface of the resin member for a plurality of LED chips attached to the circuit board. Accordingly, interference of light emitted to the lower surface of the circuit board may be blocked and light extraction efficiency may be improved.
발명의 실시 예는 회로기판의 일면에 TFT부와 LED칩들이 배열시키고 타면을 통해 광 출사 영역으로 제공할 수 있다. 이에 따라 회로기판의 측면 또는 외곽부에서 하부 패턴과 연결하기 위한 연결 패턴을 형성하지 않을 수 있으며, 드라이버 칩과 같은 부품들을 회로기판의 일면 상부에 배치할 수 있는 효과가 있다. 발명의 실시 예는 회로기판의 일면에 복수의 LED칩들을 수지부재로 밀봉한 후, 웻(Wet) 방식으로 도전성 층을 형성한 다음 패터닝 공정을 통해 연결부를 형성함으로써, 공정을 단순화시키고 연결부의 패턴 신뢰성을 개선시켜 줄 수 있다. 발명의 실시 예는 도전성 캐리어에 복수의 LED칩들을 부착하기 전 또는/및 후, 및/또는 회로기판에 LED칩들을 접착한 후 불량 LED칩을 선택하여 교체하거나, 추가적으로 더 배치할 수 있는 기술적 효과가 있다. 발명의 실시 예는 회로기판의 일면에 복수의 LED칩을 접착층으로 접착시키고, 타면에 광 차단부, 형광체층 또는 투명한 커버 중 적어도 하나를 배치한 광원 모듈, 디스플레이 패널 또는 디스플레이 장치를 제공할 수 있다.According to an embodiment of the present invention, the TFT unit and the LED chips are arranged on one surface of the circuit board, and the light emitting area may be provided through the other surface. Accordingly, a connection pattern for connecting to the lower pattern may not be formed on the side surface or the outer portion of the circuit board, and components such as a driver chip may be disposed on one surface of the circuit board. An embodiment of the present invention simplifies the process by sealing a plurality of LED chips on one surface of a circuit board with a resin member, forming a conductive layer in a wet method, and then forming a connection part through a patterning process, thereby simplifying the process and patterning the connection part. It can improve reliability. An embodiment of the invention provides a technical effect that can select and replace a defective LED chip before or/and after attaching a plurality of LED chips to a conductive carrier, and/or after attaching the LED chips to a circuit board, or additionally disposed there is An embodiment of the present invention may provide a light source module, display panel or display device in which a plurality of LED chips are adhered to one surface of a circuit board with an adhesive layer and at least one of a light blocking unit, a phosphor layer, or a transparent cover is disposed on the other surface. .
발명의 실시 예는 복수의 LED칩을 갖는 광원 모듈, 디스플레이 패널 또는 디스플레이 장치의 공정 수율이 개선될 수 있는 기술적 효과가 있다. 발명의 실시 예에 따른 서로 동일한 컬러의 광을 발광하는 LED칩들을 사용하거나, 적어도 2종류 또는 3종류의 광을 발광하는 LED칩들을 배열한 광원 모듈, 디스플레이 패널 및 디스플레이 장치의 신뢰성을 개선시켜 줄 수 있는 기술적 효과가 있다.The embodiment of the invention has a technical effect that the process yield of a light source module, a display panel, or a display device having a plurality of LED chips can be improved. Using LED chips that emit light of the same color according to an embodiment of the present invention, or arranging LED chips that emit at least two or three kinds of light, improve the reliability of a light source module, a display panel, and a display device There are possible technical effects.
도 1 및 도 2는 발명의 실시 예에서 TFT부를 갖는 회로기판을 패널 단위로 커팅한 예이다.1 and 2 are examples of cutting a circuit board having a TFT unit in units of panels according to an embodiment of the present invention.
도 3은 발명의 실시 예에 따른 복수의 LED칩을 갖는 디스플레이 장치의 예를 나타낸 도면이다. 3 is a view showing an example of a display device having a plurality of LED chips according to an embodiment of the present invention.
도 4 및 도 5는 발명의 실시 예에 따른 복수의 LED칩을 도전성 캐리어에 픽업하는 과정을 설명한 도면이다. 4 and 5 are views illustrating a process of picking up a plurality of LED chips on a conductive carrier according to an embodiment of the present invention.
도 6은 발명의 예로서, LED칩의 예를 나타낸 단면도이다.6 is a cross-sectional view showing an example of an LED chip as an example of the invention.
도 7은 발명의 실시 예에서 복수의 LED칩의 하면에 접착층을 대향시킨 공정을 나타낸 도면이다. 7 is a view showing a process of facing the adhesive layer on the lower surface of a plurality of LED chips in an embodiment of the present invention.
도 8은 발명의 실시 예에 따른 보조기판 상에 접착층이 코팅되는 과정을 나타낸 도면이다.8 is a view illustrating a process in which an adhesive layer is coated on an auxiliary substrate according to an embodiment of the present invention.
도 9는 발명의 실시 예에서 도전성 캐리어의 상세 구성도이다.9 is a detailed configuration diagram of a conductive carrier in an embodiment of the present invention.
도 10의 (A)(B)는 비교 예의 정전척의 픽업 과정을 설명하기 위한 도면이다.10A and 10B are diagrams for explaining a pick-up process of an electrostatic chuck according to a comparative example.
도 11은 발명의 실시 예에서 접착층이 접착된 LED칩들을 배열한 도전성 캐리어층을 예를 나타낸 도면이다.11 is a view illustrating an example of a conductive carrier layer in which LED chips to which an adhesive layer is adhered are arranged in an embodiment of the present invention.
도 12는 발명의 실시 예에서 도전성 캐리어에 픽업된 LED칩들을 회로기판에 접합시킨 예를 나타낸 도면이다.12 is a view showing an example of bonding LED chips picked up on a conductive carrier to a circuit board in an embodiment of the present invention.
도 13은 발명의 실시 예에서 LED칩들이 회로기판의 일면에 부착된 예이다.13 is an example in which LED chips are attached to one surface of a circuit board according to an embodiment of the present invention.
도 14는 발명의 실시 예에서 회로기판 상에 제1 내지 제3LED칩들이 배열된 예 예이다.14 is an example in which first to third LED chips are arranged on a circuit board according to an embodiment of the present invention.
도 15a 및 도 15b는 발명의 실시 예에서 회로기판 상에 부착된 LED칩의 패키징 과정을 설명한 도면이다.15A and 15B are diagrams illustrating a packaging process of an LED chip attached to a circuit board according to an embodiment of the present invention.
도 16은 도 15a의 회로기판 상에서 LED칩의 전극을 노출한 과정의 상세 도면이다.16 is a detailed view of a process of exposing an electrode of an LED chip on the circuit board of FIG. 15A.
도 17은 도 15a의 회로기판 상에 부착된 LED칩의 패키징 과정을 설명한 도면이다.17 is a view for explaining a packaging process of the LED chip attached to the circuit board of FIG. 15A.
도 18은 도 15a 및 도 17의 회로기판 상에서 LED칩의 전극을 노출하고 도전층을 형성한 과정의 상세 도면이다.18 is a detailed view of a process of exposing an electrode of an LED chip and forming a conductive layer on the circuit board of FIGS. 15A and 17 .
도 19의 (A)-(C)는 발명의 실시 예에서 LED칩 상에 연결부를 형성하는 과정을 설명한 도면이다.19(A)-(C) are views for explaining a process of forming a connection part on an LED chip according to an embodiment of the present invention.
도 20은 발명의 실시 예에 따른 디스플레이 장치에서 회로기판 상에 제1내지 제3LED칩에 의해 광이 방출된 예를 나타낸 도면이다.20 is a diagram illustrating an example in which light is emitted by first to third LED chips on a circuit board in a display device according to an embodiment of the present invention.
도 21은 발명의 실시 예에서 회로기판의 일면에 배치된 TFT부와 LED칩의 연결 예를 나타낸 도면이다.21 is a diagram illustrating an example of a connection between a TFT unit and an LED chip disposed on one surface of a circuit board according to an embodiment of the present invention.
도 22는 도 20의 발명의 실시 예에 따른 디스플레이 장치의 제1변형 예이다.22 is a first modified example of the display device according to the embodiment of the present invention of FIG. 20 .
도 23은 발명의 다른 실시 예에 따른 디스플레이 장치의 예이다.23 is an example of a display device according to another embodiment of the present invention.
도 24 내지 28은 발명의 다른 디스플레이 장치의 변형 예들이다.24 to 28 are modified examples of other display devices of the present invention.
도 29는 도 20의 발명의 실시 예에 따른 디스플레이 장치의 제2변형 예이다.29 is a second modified example of the display device according to the embodiment of the invention of FIG. 20 .
도 30은 도 29의 투명 커버의 렌즈 어레이의 예이다.30 is an example of a lens array of the transparent cover of FIG.
도 31은 도 22의 회로기판 상에 구동 기판을 연결한 예이다.FIG. 31 is an example in which a driving board is connected to the circuit board of FIG. 22 .
도 32는 도 31의 평면도의 예이다.FIG. 32 is an example of the plan view of FIG. 31 .
도 33은 발명의 실시 예에서 회로기판의 에지 측을 설명한 예이다.33 is an example illustrating an edge side of a circuit board according to an embodiment of the present invention.
도 34의 (A)(B)는 발명의 실시 예에서 회로기판 상에서 LED칩의 교체 예를 나타낸 도면이다.34(A)(B) is a view showing an example of replacing an LED chip on a circuit board according to an embodiment of the present invention.
도 35 및 도 36은 발명의 실시 예에서 회로기판 상에서 영역(P11)과 LED들의 배열 예이다.35 and 36 are examples of arrangement of the region P11 and LEDs on the circuit board according to an embodiment of the present invention.
도 37은 발명의 실시 예에 따른 LED칩들을 흡착하기 위한 흡착력, 해제하기 위한 디척킹력, 접착층의 접착력을 비교한 그래프이다.37 is a graph comparing an adsorption force for adsorbing LED chips, a dechucking force for releasing, and an adhesive force of an adhesive layer according to an embodiment of the present invention.
도 38은 발명의 실시 예에 따른 투명 커버에서의 렌즈 어레이와 플랫한 면에서의 투과율을 비교한 그래프이다.38 is a graph comparing transmittance on a flat surface with a lens array in a transparent cover according to an embodiment of the present invention.
본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다.Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims.
본 발명의 실시예를 설명하기 위한 도면에 개시된 형상, 크기, 비율, 각도, 개수 등은 예시적인 것이므로 본 발명이 도시된 사항에 한정되는 것은 아니다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다. 또한, 본 발명을 설명함에 있어서, 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다. 본 명세서 상에서 언급한 '포함한다', '갖는다', '이루어진다' 등이 사용되는 경우 '~만'이 사용되지 않는 이상 다른 부분이 추가될 수 있다. 구성 요소를 단수로 표현한 경우에 특별히 명시적인 기재 사항이 없는 한 복수를 포함하는 경우를 포함한다. 구성 요소를 해석함에 있어서, 별도의 명시적 기재가 없더라도 오차 범위를 포함하는 것으로 해석한다. 위치 관계에 대한 설명일 경우, 예를 들어, '~상에', '~상부에', '~하부에', '~옆에' 등으로 두 부분의 위치 관계가 설명되는 경우, '바로' 또는 '직접'이 사용되지 않는 이상 두 부분 사이에 하나 이상의 다른 부분이 위치할 수도 있다. 시간 관계에 대한 설명일 경우, 예를 들어, '~후에', '~에 이어서', '~다음에', '~전에' 등으로 시간적 선후 관계가 설명되는 경우, '바로' 또는 '직접'이 사용되지 않는 이상 연속적이지 않은 경우도 포함할 수 있다. 제1, 제2 등이 다양한 구성요소들을 서술하기 위해서 사용되나, 이들 구성요소들은 이들 용어에 의해 제한되지 않는다. 이들 용어들은 단지 하나의 구성 요소를 다른 구성요소와 구별하기 위하여 사용하는 것이다. 따라서, 이하에서 언급되는 제1 구성요소는 본 발명의 기술적 사상 내에서 제2 구성요소일 수도 있다. 본 발명의 여러 실시예들의 각각 특징들이 부분적으로 또는 전체적으로 서로 결합 또는 조합 가능하고, 기술적으로 다양한 연동 및 구동이 가능하며, 각 실시예들이 서로에 대하여 독립적으로 실시 가능할 수도 있고 연관 관계로 함께 실시할 수도 있다.The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated. In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description. In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used. In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used. Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention. Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be
이하, 첨부한 도면을 참조하여 본 발명에 대해 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5를 참조하면, 지지부재(1)의 일면(또는 상면)에는 개별 발광 영역(A1)에 TFT(Thin-film transistor)와 LED칩들을 탑재하고 이들의 구동을 위한 배선 패턴을 형성하며, 지지부재(1)의 타면(또는 배면)에는 상기 LED칩들로부터 방출된 광들이 방출되는 발광 면이거나 디스플레이 표면일 수 있다. 상기 LED칩들 각각은 미니 LED 또는 마이크로(예: 100㎛ 이하) 크기의 LED들일 수 있다. 상기 LED칩들 각각은 나노 사이즈의 LED일 수 있다. 여기서, 상기 LED칩이나 TFT를 구동하기 위한 드라이버 IC나 각종 부품은 상기 지지부재(1)의 일면 상에 배치될 수 있다. 즉, 드라이버 IC나 각종 부품은 지지부재(1)의 타면에 배치하지 않고, 일면 상에 배치할 수 있다. 이에 따라 지지부재(1)의 투명한 재질을 통해 광이 방출될 수 있다. 상기 지지부재(1)는 커팅 라인(C21,C22)을 통해 단위 크기의 디스플레이 패널(11,12,13,14)로 커팅될 수 있다. 여기서, 상기 배선 패턴을 갖는 개별 지지부재(1)는 회로기판으로 정의될 수 있다. 상기 지지부재(1)는 회로기판의 지지 층을 포함하며, 투명한 재질로 형성될 수 있으며, 플라스틱 재질, 글라스 재질, 세라믹 재질, 또는 투명 절연 필름 중 적어도 하나를 포함할 수 있다. 상기 지지부재(1)는 상부에 패턴이 형성된 투명한 연성 기판이거나 비 연성의 기판일 수 있다. 여기서, 상기 지지부재(1)는 하부 패턴이 외곽 둘레에 형성되거나 형성되지 않을 수 있다. 1 to 5 , a thin-film transistor (TFT) and LED chips are mounted in an individual light emitting area A1 on one surface (or an upper surface) of the support member 1 and a wiring pattern for driving them is formed. And, the other surface (or the rear surface) of the support member 1 may be a light emitting surface or a display surface from which the lights emitted from the LED chips are emitted. Each of the LED chips may be a mini LED or micro (eg, 100 μm or less) sized LEDs. Each of the LED chips may be a nano-sized LED. Here, a driver IC or various components for driving the LED chip or TFT may be disposed on one surface of the support member 1 . That is, the driver IC or various components may be disposed on one surface of the support member 1 instead of on the other surface. Accordingly, light may be emitted through the transparent material of the support member 1 . The support member 1 may be cut into unit- sized display panels 11, 12, 13, and 14 through cutting lines C21 and C22. Here, the individual support member 1 having the wiring pattern may be defined as a circuit board. The support member 1 includes a support layer of the circuit board, and may be formed of a transparent material, and may include at least one of a plastic material, a glass material, a ceramic material, and a transparent insulating film. The support member 1 may be a transparent flexible substrate having a pattern formed thereon or a non-flexible substrate. Here, the support member 1 may or may not have a lower pattern formed around the periphery.
상기 각 디스플레이 패널(11,12,13,14)의 사이즈는 손목시계, 휴대폰 단말기, 혹은 타일링방식의 모니터나 TV, 혹은 대형 TV, 광고판의 단일패널 등 다양한 응용분야에 맞는 사이즈로 구현될 수 있다. 예를 들어, 상기 각 디스플레이 패널(11,12,13,14)의 사이즈는 2인치(inch) 이상이거나, 마이크로 LED를 갖는 디스플레이의 사이즈일 수 있으며, 이에 한정되는 것은 아니다. 여기서, 인접한 디스플레이 패널(11,12,13,14) 사이의 경계 부분은 지지부재(1)가 개별 패널 크기로 커팅되는 부분으로서, 상온에서 레이저 빔에 의해 커팅할 경우, 레이저 빔에서 나오는 고열에 의해 소자나 부품에 열 충격이 가해지거나 파괴되는 문제가 있으며, 또한 커팅 라인에 인접한 각종 배선이 열화되는 문제가 발생될 수 있다. 발명의 일 예는 저온진공챔버에서 레이저 빔에 의해 상기 커팅 라인(C21,C22)을 따라 커팅하게 된다. 이에 따라 개별 지지부재(1)의 에지 영역(A2,A3)에 열 충격이 최소화되고 TFT와 각종 부품이나 배선의 열화를 줄여줄 수 있다. 여기서, 상기 저온진공챔버는 0도 내지 -50도의 범위의 환경의 챔버이며, 가스가 주입되면 레이저 빔을 조사하게 되며, 이때 국부적으로 플라즈마가 발생하여, 지지부재(1)의 커팅 라인(C21,C22)을 따라 커팅하게 된다. 이때 저온진공챔버 내에서 커팅 공정을 진행하게 되므로, 대기중의 산소와 같은 가스와의 반응으로 인한 문제를 줄여줄 수 있다. 상기 저온진공챔버에서 공급되는 가스는 선택되고 조절될 수 있으며, 불활성 가스 및 불소 가스 중 적어도 하나 또는 모두를 포함할 수 있다. 상기 가스는, 예컨대 N 2, Ar, He, CF 4, SF 6, NH 3, CF 4/H 2, CHF 3, C 2F 6, H 2, C 2H 4, CH 4 중 적어도 하나와 O 2를 포함할 수 있다. 여기서, 상기 가스에서 산소의 함유량은 0.1% 이상 예컨대, 0.1% 내지 10%의 범위로 제공될 수 있다. 또한 상기 가스는 합성부를 통해 가스 종류를 선택할 수 있고 그 함량도 조절할 수 있다. 이때 저온진공챔버 내의 환경에서 레이저 빔으로 플라즈마를 발생시켜 커팅하게 되므로, 지지부재(1)의 커팅에 따른 부품, 소자, 배선 등에 열화를 줄일 수 있다. 또한 커팅 시 고온으로 인한 주변의 열 손해(HAZ)를 최소화시켜 줄 수 있고, 상기 열 손해 영역을 커팅 라인(C21,C22)으로부터 20㎛ 이하의 영역으로 줄여줄 수 있다. 따라서, 디스플레이 패널이나 기판에 대해 열에 대한 신뢰성을 개선시켜 줄 수 있다. 또한 저온에서 공정을 진행하게 되므로, 가공속도를 높여줄 수 있다. 또한 기판에 열에 의한 손해가 줄어들어, 크랙이나 칩핑, 습도에 의한 결로 발생을 줄여줄 수 있다. 이에 따라 저온진공챔버에서 기판들을 정밀하게 커팅하게 되므로, 패널 간의 간격을 줄여줄 수 있고, 가공 공차를 최소화할 수 있다.The size of each of the display panels 11, 12, 13, and 14 may be implemented in a size suitable for various application fields, such as a wrist watch, a mobile phone terminal, or a tiling-type monitor or TV, or a large TV or a single panel of a billboard. . For example, the size of each of the display panels 11 , 12 , 13 , and 14 may be 2 inches or more or the size of a display having a micro LED, but is not limited thereto. Here, the boundary portion between the adjacent display panels 11, 12, 13, and 14 is a portion in which the support member 1 is cut to the size of individual panels. When cutting by a laser beam at room temperature, the high heat emitted from the laser beam There may be a problem in that thermal shock is applied to or destroyed by the device or parts, and also various wiring adjacent to the cutting line may be deteriorated. An example of the invention is to cut along the cutting lines C21 and C22 by a laser beam in a low-temperature vacuum chamber. Accordingly, thermal shock to the edge regions A2 and A3 of the individual support member 1 is minimized, and deterioration of the TFT and various components or wiring can be reduced. Here, the low-temperature vacuum chamber is a chamber in an environment in the range of 0 degrees to -50 degrees, and when gas is injected, a laser beam is irradiated. At this time, plasma is locally generated, and the cutting line C21 of the support member 1, C22) will be cut. At this time, since the cutting process is performed in the low-temperature vacuum chamber, it is possible to reduce problems caused by the reaction with gases such as oxygen in the atmosphere. The gas supplied from the low-temperature vacuum chamber may be selected and controlled, and may include at least one or both of an inert gas and a fluorine gas. The gas is, for example, at least one of N 2 , Ar, He, CF 4 , SF 6 , NH 3 , CF 4 /H 2 , CHF 3 , C 2 F 6 , H 2 , C 2 H 4 , CH 4 and O 2 may be included. Here, the content of oxygen in the gas may be provided in the range of 0.1% or more, for example, 0.1% to 10%. In addition, the type of gas may be selected through the synthesis unit and the content thereof may be adjusted. At this time, since plasma is generated and cut with a laser beam in an environment in the low-temperature vacuum chamber, deterioration of parts, elements, wiring, etc. caused by cutting of the support member 1 can be reduced. In addition, it is possible to minimize the heat damage (HAZ) in the vicinity due to high temperature during cutting, and it is possible to reduce the heat damage area to an area of 20 μm or less from the cutting lines C21 and C22. Accordingly, it is possible to improve the thermal reliability of the display panel or the substrate. In addition, since the process is carried out at a low temperature, it is possible to increase the processing speed. In addition, heat damage to the substrate is reduced, and cracks, chipping, and condensation caused by humidity can be reduced. Accordingly, since the substrates are precisely cut in the low-temperature vacuum chamber, the gap between the panels can be reduced and the processing tolerance can be minimized.
도 2의 (A)(B)와 같이, 커팅된 디스플레이 패널(11)은 중앙의 발광 영역(A1)과 비 발광 영역인 에지 영역(A2,A3)으로 구분될 수 있다. 상기 에지 영역은 상면(Sa)에 상부 패드 또는 에지 패턴(31)들이 배치되거나, 상부 및 하부의 에지 영역에 패드들이 배치될 수 있으며, 이 경우에는 표시 영역을 제외한 영역에 상기 패드들이 형성될 수 있다. 상기 상부 패드 또는 에지 패턴(31)들은 도전성 리드로서, 일부는 테스트 단자로 사용될 수 있다. 도 2의 (B)와 같이, 상부의 에지 패턴(31)은 단위 패널의 에지 부분을 지나는 커팅 라인 상에 배치될 수 있다. As shown in (A) (B) of FIG. 2 , the cut display panel 11 may be divided into a central emission area A1 and edge areas A2 and A3 which are non-emission areas. In the edge area, upper pads or edge patterns 31 may be disposed on the upper surface Sa, or pads may be disposed at upper and lower edge areas. In this case, the pads may be formed in areas other than the display area. have. The upper pads or edge patterns 31 may be conductive leads, and some may be used as test terminals. As shown in FIG. 2B , the upper edge pattern 31 may be disposed on a cutting line passing through an edge portion of the unit panel.
종래의 지지부재 또는 디스플레이 패널은 에지 영역에 상부에 LED칩 및 상부 패드를 배치하고, 하부에 하부 패드 및 드라이버 IC 등을 배치하고 이들을 서로 연결해 주는 공정이 진행되며, 이때 상부 패드와 하부 패드를 연결하기 위해 패널의 측면으로 연장되는 패턴 또는 패널을 관통하는 패턴을 형성해야 하는 문제가 있으며, 상기 패턴을 보호하기 위한 층을 별도로 더 형성하여야 하는 문제가 있다. 또한 상기 패턴을 형성할 때, 증착력이 낮고 증착된 후 경화 공정이 진행되므로 복잡할 수 있다. 또한 종래에는 관통 패턴을 형성할 때 각 에지 영역에서 수 백개 이상의 패드마다 비아 홀을 가공하고, 그 비아 홀들 각각에 금속 물질을 디스펜싱하고 경화하여, 비아를 형성하는 복잡한 문제가 있다.In the conventional support member or display panel, a process of arranging an LED chip and an upper pad on an edge area, placing a lower pad and a driver IC on the lower part, and connecting them to each other is performed, in which case the upper pad and the lower pad are connected In order to do this, there is a problem in that a pattern extending to the side of the panel or a pattern penetrating the panel must be formed, and there is a problem in that a layer for protecting the pattern must be formed separately. In addition, when forming the pattern, since the deposition force is low and the curing process proceeds after deposition, it may be complicated. Also, in the related art, there is a complicated problem of forming a via by processing a via hole in each of several hundred or more pads in each edge region when forming a through pattern, dispensing and curing a metal material in each of the via holes.
도 3과 같이, 디스플레이 패널은 개별 지지부재(1)의 일면(또는 상면)(Sa)에 TFT부(50)와 복수의 LED칩(2A,2B,2C)을 갖는 단위 픽셀들이 매트릭스 형태로 배열될 수 있다. 여기서, 도 3의 (A)(B)(C)와 같이, 발명의 실시 예는 미리 제공된 LED칩들(2A,2B,2C)을 갖는 블록(D1,D2,D3)을 제공하고, 상기 블록들(D1,D2,D3) 각각은 10개 이상 또는 100개 이상의 LED칩들이 미리 설정된 간격으로 배열될 수 있다. 여기서, 미리 설정된 간격은 디스플레이 패널에 LED칩들이 탑재되기 위한 간격일 수 있다. 상기 블록들(D1,D2,D3) 각각은 예컨대, 제1 LED칩(2A)들이 배열된 제1블록(D1), 제2 LED칩(2B)들이 배열된 제2블록(D2), 제3 LED칩(2C)들이 배열된 제3블록(D3)을 포함할 수 있다. 상기 제1 LED칩(2A)들은 적색 광을 발광하며, 제2 LED칩(2B)들은 녹색 광을 발광하며, 제3 LED칩(2C)들은 청색 광을 발광할 수 있다. 상기 제1 내지 제3블록(D1,D2,D3) 각각에는 복수의 제1 내지 제3 LED칩(2A,2B,2C)들이 가로 및 세로 방향으로 미리 설정된 간격으로 배열될 수 있다. As shown in FIG. 3 , in the display panel, unit pixels having a TFT unit 50 and a plurality of LED chips 2A, 2B, and 2C are arranged in a matrix form on one surface (or upper surface) Sa of the individual support member 1 . can be Here, as shown in (A) (B) (C) of FIG. 3, the embodiment of the present invention provides blocks D1, D2, and D3 having previously provided LED chips 2A, 2B, and 2C, and the blocks (D1, D2, D3) Each of 10 or more or 100 or more LED chips may be arranged at a preset interval. Here, the preset interval may be an interval for mounting the LED chips on the display panel. Each of the blocks D1, D2, and D3 is, for example, a first block D1 in which first LED chips 2A are arranged, a second block D2 in which second LED chips 2B are arranged, and a third A third block D3 in which the LED chips 2C are arranged may be included. The first LED chips 2A may emit red light, the second LED chips 2B may emit green light, and the third LED chips 2C may emit blue light. A plurality of first to third LED chips 2A, 2B, and 2C may be arranged at preset intervals in horizontal and vertical directions in each of the first to third blocks D1, D2, and D3.
이러한 각 블록(D1,D2,D3)별을 순차적으로, 지지부재(1) 상에 정해진 영역에 각각 접착시킨 후, 전기적으로 각 블록의 LED칩들을 연결해 줌으로서, 지지부재(1) 상에 LED칩(2A,2B,2C)들을 탑재할 수 있다. 상기 LED칩들은 광이 출사되는 하면이 지지부재(1)의 일면(Sa)에 부착되며, LED칩들의 상부에 전극들이 노출될 수 있다. 다른 예로서, 여기서, 상기 LED칩들이 동일한 컬러(예: 청색)를 발광한 경우, 각 컬러별 블록으로 구분하지 않고, 패널에 필요한 전체 LED칩을 하나의 블록에 배열한 후, 지지부재(1)에 탑재할 수 있다. 여기서, 블록 상에 LED칩들이 배치되면, 제1불량 칩 검사 공정을 수행하게 된다. 상기 제1불량 칩 검사 공정은 각 컬러 블록별 제1 내지 제3 LED칩에 대해 수행하거나, 동일 컬러 블록별 LED칩에 대해, 불량 LED칩을 검사한 후, 이를 제거하고 재 탑재할 수 있다. 이는 LED 표시 장치의 단위 패널에 배열되는 LED칩들의 개수가 증가하면 증가할수록 불량 LED칩의 개수는 증가될 수 있어, 미리 불량 LED칩을 제거하고 교체할 수 있다. 상기 불량 LED칩의 검사 공정은 (Probe) 장비로 진행하거나, 무선점등장비, 자동 광학 검사(AOI) 장비 등을 통해 진행될 수 있다. 이러한 검사 공정을 통해 불량 LED칩을 추출해 줌으로써, 패널의 수율이 향상될 수 있다. 이후, 제1불량 칩 검사 공정에서 불량 LED칩을 교체한 다음, 재 검사 공정을 통해 패널의 수율을 더 높여줄 수 있다.Each of these blocks (D1, D2, D3) is sequentially adhered to a predetermined area on the support member 1, and then the LED chips of each block are electrically connected to each other, so that the LED on the support member 1 is It is possible to mount chips 2A, 2B, and 2C. In the LED chips, a lower surface from which light is emitted is attached to one surface Sa of the support member 1 , and electrodes may be exposed on top of the LED chips. As another example, here, when the LED chips emit light of the same color (eg, blue), instead of dividing each color into blocks, all LED chips required for the panel are arranged in one block, and then the support member 1 ) can be mounted on Here, when the LED chips are arranged on the block, a first defective chip inspection process is performed. The first defective chip inspection process may be performed on the first to third LED chips for each color block, or after inspecting the defective LED chips for the same color blocks, the defective LED chips may be removed and remounted. As the number of LED chips arranged on the unit panel of the LED display increases, the number of defective LED chips may increase, so that the defective LED chips may be removed and replaced in advance. The inspection process of the defective LED chip may be performed using (Probe) equipment, wireless lighting equipment, automatic optical inspection (AOI) equipment, or the like. By extracting defective LED chips through this inspection process, the yield of the panel can be improved. Thereafter, after replacing the defective LED chip in the first defective chip inspection process, the panel yield can be further increased through the re-inspection process.
상기 지지부재(1) 상에는 광을 흡수 또는 차단하는 수지부재(150)가 배치될 수 있어, 광이 상부 방향으로 누설되거나 방출되는 것을 차단하고, 지지부재(1)의 타면(Sb) 또는 하부 방향으로 방출되도록 할 수 있다. 상기 수지부재(150)는 후술되는 광 흡수, 또는 열 흡수 또는 방열 재질의 수지부재와 패시베이션층을 포함할 수 있다. 상기 지지부재(1) 상에 배치된 각 블록의 LED칩(2A,2B,2C)은 TFT부(50)에 전기적으로 연결되어 구동될 수 있으며, 상기 제1 내지 제3 LED칩(2A,2B,2C) 각각은 서브 픽셀일 수 있고, 적어도 하나의 제1 내지 제3 LED칩(2A,2B,2C)이 배치된 최소 영역은 단위 픽셀이라고 정의할 수 있다. 여기서, 상기 단위 픽셀은 서로 다른 컬러를 발광하는 3종류의 LED칩(2A,2B,2C)을 이용하거나, 청색 LED칩과 형광체층과 조합하여 픽셀 영역을 구현할 수 있다. 상기 단위 픽셀은 서로 다른 컬러 예컨대, 적어도 삼색 컬러를 발광하는 LED칩(2A,2B,2C)들로 구현되거나, 서로 동일한 컬러를 발광하는 LED칩과 양자점 또는 형광체와 같은 시트의 조합으로 구현될 수 있다. 상기 단위 픽셀은 적색, 녹색 및 청색의 광을 발광할 수 있으며, 예컨대 LED칩(2A,2B,2C)들은 적색(R), 녹색(G) 및 청색(B)의 LED칩을 포함할 수 있다. 예컨대 LED칩(2A,2B,2C)들은 모두 동일한 컬러를 발광하는 LED칩을 포함할 수 있다. 상기 LED칩(2A,2B,2C)은 서브 픽셀을 위해 마이크로 사이즈를 갖는 칩이며, 예컨대, 각 LED칩의 한 변의 길이는 10㎛ 내지 100㎛의 범위일 수 있다. 상기 LED칩(2A,2B,2C)의 사이즈는 LED칩의 미세제조 기술에 따라 한 변의 길이가 미세크기(≤１㎛, 또는 1㎛-50㎛)의 범위일 수도 있다. 예를 들어, 상기 LED칩(2A,2B,2C)의 사이즈는 1㎛ 내지 50㎛ × 1㎛ 내지 50㎛의 범위이거나 나노 크기일 수 있으며, 이에 한정되는 것은 아니다.A resin member 150 that absorbs or blocks light may be disposed on the support member 1 to block light leakage or emission in the upper direction, and the other surface Sb or the lower direction of the support member 1 can be released as The resin member 150 may include a resin member made of a light absorbing, heat absorbing or heat dissipating material and a passivation layer, which will be described later. The LED chips 2A, 2B, and 2C of each block disposed on the support member 1 may be electrically connected to the TFT unit 50 to be driven, and the first to third LED chips 2A, 2B , 2C) may each be a sub-pixel, and a minimum area in which at least one of the first to third LED chips 2A, 2B, and 2C is disposed may be defined as a unit pixel. Here, as the unit pixel, three types of LED chips 2A, 2B, and 2C emitting different colors may be used, or a pixel area may be implemented by combining a blue LED chip and a phosphor layer. The unit pixel may be implemented with LED chips 2A, 2B, and 2C emitting different colors, for example, at least three colors, or a combination of LED chips emitting the same color and sheets such as quantum dots or phosphors. have. The unit pixel may emit red, green, and blue light. For example, the LED chips 2A, 2B, and 2C may include red (R), green (G), and blue (B) LED chips. . For example, the LED chips 2A, 2B, and 2C may all include LED chips emitting the same color. The LED chips 2A, 2B, and 2C are chips having a micro size for sub-pixels, and for example, the length of one side of each LED chip may be in the range of 10 μm to 100 μm. The size of the LED chips 2A, 2B, and 2C may be in the range of a microscopic size (≤1 μm, or 1 μm-50 μm) with one side length depending on the micro-manufacturing technology of the LED chip. For example, the size of the LED chips 2A, 2B, and 2C may be in a range of 1 μm to 50 μm × 1 μm to 50 μm or a nano size, but is not limited thereto.
또한 표시장치를 위해 여러 개의 디스플레이 패널들이 밀착될 경우, 외부에서 구분되지 않도록 밀착 결합될 수 있다. 즉, 디스플레이 패널들은 경계 부분에서의 암선이 발생되지 않는 배치 구조 또는 결합 구조를 가질 수 있다. 상기 디스플레이 패널들을 갖는 디스플레이 장치의 사이즈는 상기 디스플레이 패널의 결합 개수와 각 패널의 사이즈에 따라 달라질 수 있다. 또한 디스플레이 장치에서 각 패널들은 결합, 분리 또는 제거가 가능한 구조이다. 상기 디스플레이 패널의 회로기판은 복수의 LED칩(2A,2B,2C)을 구동할 수 있는 TFT 어레이 기판을 사용하게 된다. 즉, 회로기판은 복수의 LED칩(2A,2B,2C)을 구동하기 위한 TFT부(50)와 각종 배선들이 형성되어 있으며, 상기 TFT가 턴-온되면, 배선을 통해 외부로부터 입력된 구동신호가 LED칩(2A,2B,2C)에 인가되고 각 LED칩이 발광하게 되어 화상을 구현하게 된다. 상기 회로기판은 각 픽셀 영역(2)에 배치된 서브 픽셀 예컨대, LED칩(2A,2B,2C)들이 각각 독립적으로 구동되도록 구성된 회로 예컨대, 박막 트랜지스터를 포함할 수 있다. 상기 회로기판(20)의 각각의 픽셀 영역(2)은 적색, 녹색 및 청색의 단색 광을 발광하는 적어도 3개의 LED칩(2A,2B,2C)들이 배열되며, 외부로부터 인가되는 신호에 의해 LED칩으로부터 적색, 녹색 및 청색 컬러의 광이 발광되어 화상을 표시할 수 있게 된다. 패널의 커팅 전 또는 후에 복수의 LED칩(2A,2B,2C)은 TFT 어레이 공정과는 별도의 공정으로 탑재될 수 있다. 즉, TFT와 각종 배선은 포토 공정에 의해 형성되지만, LED칩(2A,2B,2C)들은 별도의 본딩 공정이나 리플로우 공정을 통해 탑재될 수 있다. 여기서, TFT를 갖는 회로기판과 복수의 LED칩(2A,2B,2C)의 구성은 광원 모듈로 정의될 수 있다. 상기 회로기판은 상기 LED칩(2A,2B,2C)과 이에 연결되는 TFT부(50)를 포함할 수 있다. 상기 회로기판은 유리와 같은 투명한 지지부재(1)로 형성될 수 있으며, 상기 TFT부(50)는 상기 지지부재(1)의 제1면(일면 또는 상면)에 배치될 수 있다. 상기 LED칩(2A,2B,2C)으로부터 발생된 광은 상기 지지부재(1)의 제2면(타면 또는 하면)(Sb)을 통해 방출될 수 있어, 디스플레이 장치로 기능할 수 있다. In addition, when a plurality of display panels are closely coupled for a display device, they may be closely coupled so as not to be distinguished from the outside. That is, the display panels may have an arrangement structure or a coupling structure in which dark lines are not generated at the boundary portion. The size of the display device including the display panels may vary according to the number of the display panels combined and the size of each panel. Also, in the display device, each panel has a structure that can be combined, separated or removed. As the circuit board of the display panel, a TFT array board capable of driving a plurality of LED chips 2A, 2B, and 2C is used. That is, the circuit board has a TFT unit 50 for driving the plurality of LED chips 2A, 2B, and 2C and various wirings are formed. When the TFT is turned on, a driving signal input from the outside through the wiring is formed. is applied to the LED chips 2A, 2B, and 2C, and each LED chip emits light to realize an image. The circuit board may include a circuit, for example, a thin film transistor, configured to independently drive sub-pixels, for example, the LED chips 2A, 2B, and 2C, disposed in each pixel region 2 . In each pixel area 2 of the circuit board 20, at least three LED chips 2A, 2B, and 2C emitting monochromatic light of red, green, and blue are arranged, and the LED is illuminated by a signal applied from the outside. Lights of red, green and blue colors are emitted from the chip to display an image. Before or after the panel cutting, the plurality of LED chips 2A, 2B, and 2C may be mounted in a process separate from the TFT array process. That is, the TFT and various wirings are formed by a photo process, but the LED chips 2A, 2B, and 2C may be mounted through a separate bonding process or a reflow process. Here, the configuration of the circuit board having the TFT and the plurality of LED chips 2A, 2B, and 2C may be defined as a light source module. The circuit board may include the LED chips 2A, 2B, and 2C and the TFT unit 50 connected thereto. The circuit board may be formed of a transparent support member 1 such as glass, and the TFT unit 50 may be disposed on a first surface (one surface or an upper surface) of the support member 1 . The light generated from the LED chips 2A, 2B, and 2C may be emitted through the second surface (the other surface or the lower surface) Sb of the support member 1 to function as a display device.
이하, 구체적으로 디스플레이 패널의 제조 공정 및 디스플레이 장치에 대해 설명하기로 한다. 도 4 및 도 5와 같이, 미리 제공된 LED칩들(2A,2B,2C)을 갖는 블록(D1,D2,D3)을 준비하게 된다. 상기 블록들(D1,D2,D3) 각각은 10개 이상 또는 100개 이상의 LED칩들이 미리 설정된 간격으로 배열될 수 있다. 여기서, 미리 설정된 간격은 디스플레이 패널에 LED칩들이 탑재되기 위한 간격일 수 있으며, 서로 다른 위치 상에 배열될 수 있도록 정렬될 수 있다. 상기 블록들(D1,D2,D3) 각각은 예컨대, 제1 LED칩(2A)들이 배열된 제1블록(D1), 제2 LED칩(2B)들이 배열된 제2블록(D2), 제3 LED칩(2C)들이 배열된 제3블록(D3)을 포함할 수 있다. 상기 제1 LED칩(2A)들은 적색 광을 발광하며, 제2 LED칩(2B)들은 녹색 광을 발광하며, 제3 LED칩(2C)들은 청색 광을 발광할 수 있다. 상기 제1 내지 제3블록(D1,D2,D3) 각각에는 복수의 제1 내지 제3 LED칩(2A,2B,2C)들이 가로 및 세로 방향으로 미리 설정된 간격으로 배열될 수 있다. 여기서, 제1 LED칩(2A)를 부착 및 패키징하는 공정을 설명하기로 하며, 제2 및 제3 LED칩(2B,2C)의 설명은 생략하거나 제1 LED칩(2A)의 설명을 참조하기로 한다. Hereinafter, a process for manufacturing a display panel and a display device will be described in detail. 4 and 5, blocks D1, D2, and D3 having previously provided LED chips 2A, 2B, and 2C are prepared. In each of the blocks D1, D2, and D3, 10 or more or 100 or more LED chips may be arranged at a preset interval. Here, the preset interval may be an interval for mounting the LED chips on the display panel, and may be arranged to be arranged on different positions. Each of the blocks D1, D2, and D3 is, for example, a first block D1 in which first LED chips 2A are arranged, a second block D2 in which second LED chips 2B are arranged, and a third A third block D3 in which the LED chips 2C are arranged may be included. The first LED chips 2A may emit red light, the second LED chips 2B may emit green light, and the third LED chips 2C may emit blue light. A plurality of first to third LED chips 2A, 2B, and 2C may be arranged at preset intervals in horizontal and vertical directions in each of the first to third blocks D1, D2, and D3. Here, the process of attaching and packaging the first LED chip 2A will be described, and the description of the second and third LED chips 2B and 2C will be omitted or refer to the description of the first LED chip 2A. do it with
상기 제1 LED칩(2A)들이 지지몸체(310)의 지지 프레임(312) 상에 배열되어 제1블록(D1)을 형성하면, 캐리어 몸체(250)의 지지 축(230)에 연결된 도전성 캐리어(210)를 상기 제1블록(D1) 상에 위치 정렬하게 된다. 여기서, 상기 제1 LED칩(2A)들의 상부에는 전극(K1,K2)들이 배치되며, 하부에는 광을 방출하는 부재 또는 시트가 배치될 수 있다. 여기서, 상기 광을 방출하는 부재는 투명한 재질의 층 또는 성장 기판일 수 있다. 다른 예로서, 3개의 컬러별 블록이 아닌, 동일 컬러의 LED칩이 하나의 블록으로 배열될 수 있고, 이를 도전성 캐리어에 위치 정렬할 수 있다. 상기 도전성 캐리어(210)의 하면을 상기 제1블록(D1)의 상면에 수직 하 방향으로 이동시켜 위치시키면, 도 5와 같이 상기 도전성 캐리어(210)에 상기 제1 LED칩(2A)들이 부착될 수 있으며, 상기 제1블록(D1)이 부착된 상기 도전성 캐리어(210)를 수직 상 방향으로 이동시키거나 지지 몸체(310)를 다른 방향으로 이동시킬 수 있다. 여기서, 상기 도전성 캐리어(210)의 하부는 탄성부재(215)를 구비하고 있어, 상기 도전성 캐리어(210)가 수직 하 방향으로 이동될 때, 제1 LED칩(2A)에 전달되는 충격을 줄여줄 수 있고, 제1 LED칩(2A) 또는 다른 LED칩들이 부착될 수 있다. 상기 도전성 캐리어(210)에는 제1 LED칩(2A)의 상부에 배치된 전극(K1,K2)들이 부착되며, 상기 전극(K1,K2)들은 적어도 2개의 전극을 포함할 수 있다. 상기 전극(K1,K2)들은 제1 LED칩(2A)의 패드일 수 있다. 상기 제1 LED칩(2A)의 하면은 노출될 수 있다. 여기서, 제2불량 칩 검사 공정을 수행하게 된다. 상기 도전성 캐리어(210)에 컬러별 제1 내지 제3 LED칩(2A,2B,2C)이 부착되거나, 단일 컬러의 LED칩이 전 영역에 부착되면, 접착 불량 LED칩 또는 미 부착 칩 영역을 검출하게 된다. 이러한 검사를 통해 부착 불량 LED칩을 양면 테이프를 통해 제거할 수 있고, 불량 LED칩이 제거되거나 미 부착 영역에 해당 LED칩을 부착시켜 줄 수 있다. 이러한 제2불량 칩 검사 공정을 통해 공정 중에 발생될 수 있는 불량 율을 낮출 수 있고, 패널들의 수율을 개선시켜 줄 수 있다. When the first LED chips 2A are arranged on the support frame 312 of the support body 310 to form the first block D1, a conductive carrier connected to the support shaft 230 of the carrier body 250 ( 210) is aligned on the first block D1. Here, the electrodes K1 and K2 may be disposed on the upper portions of the first LED chips 2A, and a member or sheet emitting light may be disposed on the lower portions. Here, the light emitting member may be a transparent layer or a growth substrate. As another example, instead of three blocks for each color, LED chips of the same color may be arranged in one block, and may be aligned on a conductive carrier. When the lower surface of the conductive carrier 210 is moved and positioned in a vertical downward direction on the upper surface of the first block D1, the first LED chips 2A are attached to the conductive carrier 210 as shown in FIG. In addition, the conductive carrier 210 to which the first block D1 is attached may be moved in a vertical upward direction or the support body 310 may be moved in a different direction. Here, the lower portion of the conductive carrier 210 is provided with an elastic member 215 to reduce the impact transmitted to the first LED chip (2A) when the conductive carrier 210 is moved in the vertical downward direction. and the first LED chip 2A or other LED chips may be attached thereto. Electrodes K1 and K2 disposed on the first LED chip 2A are attached to the conductive carrier 210 , and the electrodes K1 and K2 may include at least two electrodes. The electrodes K1 and K2 may be pads of the first LED chip 2A. A lower surface of the first LED chip 2A may be exposed. Here, a second defective chip inspection process is performed. When the first to third LED chips 2A, 2B, and 2C for each color are attached to the conductive carrier 210 or a single color LED chip is attached to the entire area, the LED chip or non-attached chip area is detected. will do Through this inspection, the defective LED chip can be removed through double-sided tape, and the defective LED chip can be removed or the LED chip can be attached to the non-attached area. Through the second defective chip inspection process, a defect rate that may be generated during the process may be reduced, and the yield of panels may be improved.
도 6을 참조하여, LED칩의 일 예를 설명하기로 한다. LED칩(2A,2B,2C) 중 적어도 하나 또는 모두는 투광성 기판(101), 상기 투광성 기판(101) 상에 발광 구조물(102,103,104), 상기 발광 구조물(102,103,104) 상부에 배치된 전극(K1,K2)을 포함할 수 있다. 상기 발광 구조물(102,103,104)의 최상층과 전극(K1,K2) 사이에 반사층(107)을 포함할 수 있다. 상기 투광성 기판(101)은 성장 기판이거나 투명한 층으로서, 절연성 재질 또는 반도체 재질로 형성될 수 있다. 상기 투광성 기판(101)은 예컨대, 사파이어 기판(Al 2O 3), SiC, GaAs, GaN, ZnO, Si, GaP, InP, Ge을 포함하는 그룹 중에서 선택될 수 있으며, 제거될 수 있다. 상기 발광 구조물(1021,103,104)은 화합물 반도체로 제공될 수 있다. 상기 발광 구조물(102,103,104)은, 예로서 II족-VI족 또는 III족-V족 화합물 반도체로 제공될 수 있다. 예로서, 상기 발광 구조물(1021,103,104)은 알루미늄(Al), 갈륨(Ga), 인듐(In), 인(P), 비소(As), 질소(N)로부터 선택된 적어도 두 개 이상의 원소를 포함하여 제공될 수 있다. 상기 발광 구조물(102,103,104)은 제1전극(K1)에 연결된 제1 도전형 반도체층(102)과, 상기 제2전극(K2)에 연결된 제2 도전형 반도체층(104), 상기 제1 및 제2도전형 반도체층(102,104) 사이에 배치된 활성층(103)을 포함할 수 있다. 상기 제1 및 제2 도전형 반도체층(102,104)은 III족-V족 또는 II족-VI족의 화합물 반도체 중에서 적어도 하나로 구현될 수 있다. 상기 제1 및 제2 도전형 반도체층(102,104)은 예컨대, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP 등을 포함하는 그룹 중에서 선택된 적어도 하나를 포함할 수 있다. 상기 제1 도전형 반도체층(102)은 Si, Ge, Sn, Se, Te 등의 n형 도펀트가 도핑된 n형 반도체층일 수 있다. 상기 제2 도전형 반도체층(104)은 Mg, Zn, Ca, Sr, Ba 등의 p형 도펀트가 도핑된 p형 반도체층일 수 있다. 다른 예로서, 상기 제1 및 제2도전형 반도체층(102,104)은 p형 및 n형 반도체층일 수 있다. 상기 활성층(103)은 화합물 반도체로 구현될 수 있다. 상기 활성층(103)은 예로서, 3족-5족 또는 2족-6족의 화합물 반도체 중에서 적어도 하나로 구현될 수 있다. 상기 활성층(103)이 다중 우물 구조로 구현된 경우, 상기 활성층(103)은 교대로 배치된 복수의 우물층과 복수의 장벽층을 포함할 수 있고, InGaN/GaN, GaN/AlGaN, AlGaN/AlGaN, InGaN/AlGaN, InGaN/InGaN, AlGaAs/GaAs, InGaAs/GaAs, InGaP/GaP, AlInGaP/InGaP, InP/GaAs을 포함하는 그룹 중에서 선택된 적어도 하나를 포함할 수 있다. 상기 반사층(107)은 금속 또는 비 금속 재질로 형성될 수 있으며, 단층 또는 다층을 포함할 수 있다. 상기 반사층(107)은 다른 예로서, 서로 다른 굴절률을 갖는 DBR 구조를 포함할 수 있다. 상기 LED칩(2A,2B,2C) 각각은 상기 제1 및 제2전극(K1,K2)이 LED칩(2A,2B,2C)의 상부에 배치될 수 있다. 여기서, 상기 LED칩(2A,2B,2C)은 상기 제1 및 제2전극(K1,K2)의 위치에 따라 플립 칩, 수직형 칩, 또는 수평형 칩으로 제공될 수 있다. 상기 제1 및 제2전극(K1,K2)은 Ti, Al, In, Ir, Ta, Pd, Co, Cr, Mg, Zn, Ni, Si, Ge, Ag, Ag alloy, Au, Hf, Pt, Ru, Rh 중 적어도 하나 또는 둘 이상을 포함하며, 단층 또는 다층으로 형성될 수 있다. 상기 제1 및 제2전극(K1,K2)은 Ti/Ag 또는 Ti/ITO의 적층 구조를 포함하여, 상기 Ag 또는 ITO층은 Ti의 산화 방지를 위해 도포될 수 있으며, 열 공정에 따른 접착력이 증대될 수 있다. 상기 제1 및 제2전극(K1,K2) 사이의 영역 또는 발광 구조물의 표면에는 보호층, 절연층 또는 절연성 반사층이 더 배치될 수 있으며, 이에 대해 한정하지는 않는다. 이러한 LED칩(2A,2B,2C)의 구조는 일 예이며, 다른 반도체층들이 각 층 사이에 더 배치될 수 있으며, 이에 대해 한정하지는 않는다. 상기 LED칩(2A,2B,2C)의 투광성 기판(101)의 하부에는 형광체와 같은 파장변환 물질을 갖는 층이나 필름이 배치될 수 있다. 상기 형광체는 황색, 녹색, 적색 또는 청색 중 적어도 하나를 포함할 수 있다. 예컨대, 상기 형광체는 상기 LED칩(2A,2B,2C)에서 방출된 광을 적색, 녹색, 황색, 청색의 광으로 파장 변환할 수 있다. 상기 각 LED칩의 하면에 형광체층이 더 배치된 경우, 투명한 지지부재와 접착층으로 접착될 수 있다.An example of an LED chip will be described with reference to FIG. 6 . At least one or both of the LED chips 2A, 2B, and 2C is a light-transmitting substrate 101, light-emitting structures 102, 103, 104 on the light-transmitting substrate 101, and electrodes K1 and K2 disposed on the light-emitting structures 102, 103, 104. ) may be included. A reflective layer 107 may be included between the uppermost layer of the light emitting structures 102 , 103 , and 104 and the electrodes K1 and K2 . The light-transmitting substrate 101 is a growth substrate or a transparent layer, and may be formed of an insulating material or a semiconductor material. The light-transmitting substrate 101 may be selected from a group including, for example, a sapphire substrate (Al 2 O 3 ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, and Ge, and may be removed. The light emitting structures 1021 , 103 , and 104 may be formed of a compound semiconductor. The light emitting structures 102 , 103 , and 104 may be formed of, for example, a group II-VI or group III-V compound semiconductor. For example, the light emitting structures 1021 , 103 , and 104 include at least two or more elements selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As), and nitrogen (N). can be provided. The light emitting structures 102 , 103 , and 104 include a first conductivity type semiconductor layer 102 connected to the first electrode K1 , a second conductivity type semiconductor layer 104 connected to the second electrode K2 , and the first and first The active layer 103 may be disposed between the two conductive semiconductor layers 102 and 104 . The first and second conductivity-type semiconductor layers 102 and 104 may be implemented with at least one of group III-V or group II-VI compound semiconductors. The first and second conductivity-type semiconductor layers 102 and 104 include, for example, at least one selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. can do. The first conductivity-type semiconductor layer 102 may be an n-type semiconductor layer doped with an n-type dopant such as Si, Ge, Sn, Se, or Te. The second conductivity-type semiconductor layer 104 may be a p-type semiconductor layer doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba. As another example, the first and second conductivity-type semiconductor layers 102 and 104 may be p-type and n-type semiconductor layers. The active layer 103 may be implemented with a compound semiconductor. The active layer 103 may be embodied, for example, by at least one of a group 3-5 or group 2-6 compound semiconductor. When the active layer 103 is implemented as a multi-well structure, the active layer 103 may include a plurality of well layers and a plurality of barrier layers arranged alternately, and may include InGaN/GaN, GaN/AlGaN, AlGaN/AlGaN. , InGaN/AlGaN, InGaN/InGaN, AlGaAs/GaAs, InGaAs/GaAs, InGaP/GaP, AlInGaP/InGaP, and at least one selected from the group consisting of InP/GaAs. The reflective layer 107 may be formed of a metal or non-metal material, and may include a single layer or multiple layers. As another example, the reflective layer 107 may include a DBR structure having different refractive indices. In each of the LED chips 2A, 2B, and 2C, the first and second electrodes K1 and K2 may be disposed on the LED chips 2A, 2B, and 2C. Here, the LED chips 2A, 2B, and 2C may be provided as flip chips, vertical chips, or horizontal chips depending on the positions of the first and second electrodes K1 and K2. The first and second electrodes K1 and K2 are Ti, Al, In, Ir, Ta, Pd, Co, Cr, Mg, Zn, Ni, Si, Ge, Ag, Ag alloy, Au, Hf, Pt, It contains at least one or two or more of Ru and Rh, and may be formed as a single layer or multiple layers. The first and second electrodes K1 and K2 include a stacked structure of Ti/Ag or Ti/ITO, and the Ag or ITO layer may be applied to prevent oxidation of Ti. can be increased A protective layer, an insulating layer, or an insulating reflective layer may be further disposed in the region between the first and second electrodes K1 and K2 or on the surface of the light emitting structure, but is not limited thereto. The structure of the LED chips 2A, 2B, and 2C is an example, and other semiconductor layers may be further disposed between each layer, but is not limited thereto. A layer or film having a wavelength conversion material such as a phosphor may be disposed under the light-transmitting substrate 101 of the LED chips 2A, 2B, and 2C. The phosphor may include at least one of yellow, green, red, and blue. For example, the phosphor may wavelength-convert the light emitted from the LED chips 2A, 2B, and 2C into red, green, yellow, and blue light. When a phosphor layer is further disposed on the lower surface of each LED chip, it may be adhered to the transparent support member with an adhesive layer.
도 7을 참조하면, 상기 제1 LED칩(2A)들이 각각 부착된 상기 도전성 캐리어(210)는 보조기판(353) 상에 대응하거나 대면하게 된다. 여기서, 상기 보조기판(353)은 회전 축(350)에 의해 회전되는 상부 몸체(351) 상에 배치되며, 상기 상부 몸체(351)와 함께 회전될 수 있다. 상기 보조기판(353)의 표면 또는 상면에는 접착층(B0)이 형성될 수 있다. 상기 접착층(B0)은 투명한 재질을 포함할 수 있다. 상기 접착층(B0)는 투명한 접착 재질일 수 있다. 상기 접착층(B0)은 투명한 무기질 옥사이드계 재질일 수 있으며, 이 경우 광에 의한 변색을 줄여줄 수 있다. 상기 접착층(B0) 내에는 접착 재료, 열전도성 나노 파우더를 갖는 방열 재료 또는/및 산란 방지 재료가 포함할 수 있다. 상기 접착층(B0)은 열 전도성의 무기 필러를 포함하거나, 탄소 재료 또는 세라믹 소재를 포함할 수 있다. 상기 접착층(B0)은 다른 재질로서, 유기질 또는 무기질 재료의 투명한 재질일 수 있다. 상기 접착층(B0)의 두께는 2㎛ 이하 예컨대, 0.2㎛ 내지 2㎛의 범위일 수 있다. 상기 접착층(B0)은 보조기판(353) 상의 전 영역에서 균일한 두께로 제공될 수 있다. 상기 접착층(B0)의 투과율은 95% 이상 예컨대, 98% 이상일 수 있다. 상기 접착층(B0)은 Ag, Ti, Al, Mo 중 적어도 하나를 갖는 산화물 재질을 포함할 수 있다. 상기 접착층(B0)은 다층 구조 예컨대, Ti/Al/Ti 또는 Mo/Al/Mo와 같은 다층 산화물 구조를 포함할 수 있다.Referring to FIG. 7 , the conductive carrier 210 to which the first LED chips 2A are attached respectively corresponds to or faces the auxiliary substrate 353 . Here, the auxiliary substrate 353 is disposed on the upper body 351 rotated by the rotation shaft 350 , and may be rotated together with the upper body 351 . An adhesive layer B0 may be formed on a surface or an upper surface of the auxiliary substrate 353 . The adhesive layer B0 may include a transparent material. The adhesive layer B0 may be a transparent adhesive material. The adhesive layer B0 may be made of a transparent inorganic oxide-based material, and in this case, it is possible to reduce discoloration due to light. The adhesive layer B0 may include an adhesive material, a heat dissipation material having thermally conductive nanopowder, and/or a scattering prevention material. The adhesive layer B0 may include a thermally conductive inorganic filler, or a carbon material or a ceramic material. The adhesive layer B0 is another material, and may be a transparent material of an organic or inorganic material. The thickness of the adhesive layer B0 may be 2 μm or less, for example, 0.2 μm to 2 μm. The adhesive layer B0 may be provided with a uniform thickness over the entire region on the auxiliary substrate 353 . The transmittance of the adhesive layer B0 may be 95% or more, for example, 98% or more. The adhesive layer B0 may include an oxide material having at least one of Ag, Ti, Al, and Mo. The adhesive layer B0 may include a multilayer structure, for example, a multilayer oxide structure such as Ti/Al/Ti or Mo/Al/Mo.
여기서, 도 8을 참조하면, 보조기판(353) 상에 액상의 접착 재료를 디스펜싱한 다음, 스핀 코팅 형태로 형성해 줄 수 있다. 이때 상기 보조기판(353)이 회전하게 되므로, 접착층(B0)의 두께는 균일한 두께로 제공될 수 있다. LED칩에 별도의 접착층을 형성할 경우, 두께 편차가 발생될 수 있고, 각 LED칩과의 접착력 차이가 발생되는 문제가 있다. 상기 보조기판(353)의 재질은 유리 또는 플라스틱 재질일 수 있다. 상기 액상의 접착층(B0)은 보조기판(353) 상에 스프레이 방식으로 증착되거나, 디핑(Dipping), 슬릿(slit), 롤 코팅(roll coating), 또는 프린트 방식으로 형성될 수 있다. 상기 접착 재료는 1 CP 이상의 점성 예컨대, 1 내지 150 CP 정도의 점성을 가질 수 있다. 상기 접착층(B0)이 보조기판(353) 상에 코팅되면, 상기 보조기판(353) 상에 배치된 스템핑 영역(A5)에 상기 도전성 캐리어(210)의 하부에 배치된 제1블록(D1)에 배치된 LED칩들의 하면이 대면할 수 있다. Here, referring to FIG. 8 , after dispensing a liquid adhesive material on the auxiliary substrate 353 , it may be formed in the form of spin coating. At this time, since the auxiliary substrate 353 is rotated, the thickness of the adhesive layer B0 may be provided with a uniform thickness. When a separate adhesive layer is formed on the LED chip, a thickness deviation may occur, and there is a problem in that a difference in adhesive strength with each LED chip is generated. The auxiliary substrate 353 may be made of glass or plastic. The liquid adhesive layer B0 may be deposited on the auxiliary substrate 353 by a spray method, or may be formed by a dipping method, a slit method, a roll coating method, or a printing method. The adhesive material may have a viscosity of 1 CP or more, for example, a viscosity of about 1 to 150 CP. When the adhesive layer B0 is coated on the auxiliary substrate 353 , the first block D1 is disposed under the conductive carrier 210 in the stamping area A5 disposed on the auxiliary substrate 353 . The lower surfaces of the LED chips disposed on the .
도 7 및 도 11과 같이, 상기 도전성 캐리어(210)는 수직 하 방향 또는 상기 보조기판(353) 방향으로 이동되고, 상기 제1 LED칩(2A)을 상기 보조기판(353) 상에 접촉시킨 후, 수직 상 방향으로 이동하게 된다. 이때 상기 제1 LED칩(2A)의 하면에는 상기 접착층(B0)이 스템프 형태로 부착 또는 접착될 수 있다. 즉, 제1 LED칩(2A)을 스템핑 공정을 통해 상기 접착층(B0)을 각 제1 LED칩(2A)의 투명 기판에 형성해 줄 수 있다(도 11 참조). 도 11과 같이, 각 제1 LED칩(2A)의 하부에 배치된 투명 기판에는 접착층(B10)이 균일한 두께로 형성될 수 있다. 또한 상기 각 LED칩(2A,2B,2C)의 하면에 배치된 접착층(B10)의 폭 또는 면적은 상기 LED칩(2A,2B,2C)의 하면 폭 또는 하면 면적과 같거나, 하면 폭 또는 하면 면적의 120% 이하일 수 있다. 이러한 접착층(B10)을 부착하는 공정 후에 제3불량 칩 검사 공정을 수행할 수 있다. 이때의 제3불량 칩 검사 공정을 통해 접착층(B10)이 부착된 컬러별 블록의 LED칩을 제공하거나, 동일 컬러의 단일 블록의 LED칩으로 제공할 수 있다.7 and 11 , the conductive carrier 210 is moved vertically downward or in the direction of the auxiliary substrate 353 , and the first LED chip 2A is brought into contact with the auxiliary substrate 353 . , moving in the vertical direction. In this case, the adhesive layer B0 may be attached or adhered to the lower surface of the first LED chip 2A in the form of a stamp. That is, the adhesive layer B0 may be formed on the transparent substrate of each of the first LED chips 2A through the stamping process of the first LED chips 2A (see FIG. 11 ). 11 , the adhesive layer B10 may be formed to have a uniform thickness on the transparent substrate disposed under each of the first LED chips 2A. In addition, the width or area of the adhesive layer B10 disposed on the lower surface of each of the LED chips 2A, 2B, 2C is the same as the width or area of the lower surface of the LED chips 2A, 2B, 2C, or the width or the lower surface It may be less than or equal to 120% of the area. After the process of attaching the adhesive layer B10, a third defective chip inspection process may be performed. In this case, the LED chip of each color block to which the adhesive layer B10 is attached may be provided through the third defective chip inspection process, or the LED chip of a single block of the same color may be provided.
도 9를 참조하여, 발명에서 도전성 캐리어를 이용한 LED칩의 픽업 또는 분리시키는 공정에 대해 설명하기로 한다. 상기 도전성 캐리어(210)는 하부에 탄성부재(215)를 구비하며, 지지 플레이트(211)일 수 있다. 상기 탄성부재(215)는 전도성 탄성부재(212), 상기 지지 플레이트(211)와 전도성 탄성부재(212) 사이에 유전체층(214) 및 전극층(213)을 포함할 수 있다. 상기 지지 플레이트(211)의 하부에는 상기 유전체층(214)이 형성되며, 상기 유전체층(214)을 지지할 수 있다. 상기 지지 플레이트(211)는 금속 재질 또는 비 금속 재질이거나, 예컨대, 알루미늄 재질을 포함할 수 있다. 상기 유전체층(214)은 비금속 물질 예컨대, 폴리이미드, 폴리에스테르, 세라믹, 탄탈리움, 실리콘 필름 중 적어도 하나를 포함할 수 있다. 상기 세라믹 재질은 비정질상의 세라믹재인 Al 2O 3, Y 2O 3, ZrO 2, AlC, TiN, AlN, TiC, MgO, CaO, CeO 2, TiO 2, BxCy, BN, SiO 2, SiC, YAG, AlF 3로 이루어진 군에서 1종 또는 2종 이상이 각각 혼합되어 사용되는 것이다. 상기 유전체층(214)의 두께는 1mm 이하 예컨대, 0.1mm 내지 1mm의 범위에 배치될 수 있다. 상기 전극층(213)은 상기 유전체층(214)과 상기 전도성 탄성부재(212) 사이에 배치될 수 있다. 상기 전극층(231)의 둘레에는 접착층(216)이 배치되어, 상기 유전체층(214)과 상기 탄성부재(212) 사이를 접착시켜 줄 수 있다. 상기 접착층(216)은 상기 유전체층(214)의 재질이거나 실리콘 또는 에폭시와 같은 재질일 수 있다. 상기 전극층(213)은 전극 라인(218)을 통해 전원을 공급받을 수 있으며, 도전성 금속 예컨대, 텅스텐, 몰리브덴, 타이타늄, 은 및 구리 중 적어도 하나 또는 둘 이상을 포함할 수 있다. 상기 전극층(213)은 메쉬 형태의 전극 패턴들이 배열되어 있으며, 전 영역에 균일한 분포로 배치될 수 있다. 상기 전극층(213)의 두께는 50 ㎛ 이하 예컨대, 15 내지 50 ㎛의 범위로 제공될 수 있다. 상기 전극층(213)은 단층 또는 다층으로 형성될 수 있다. 상기 전도성 탄성부재(212)는 탄성을 갖는 전도성 재질을 포함할 수 있으며, 점성과 탄성을 갖는 중합체일 수 있다. 상기 전도성 탄성부재(212)는 고무, 열 가소성 중합체이거나 열 경화성 중합체일 수 있다. 상기 전도성 탄성부재(212)는 내부에 Ni, Cu, Ag, Al과 같은 금속 또는 금속 산화물 분말이나 카본 블랙과 같은 충전재를 포함할 수 있어, 전기 전도성 중합체로 기능할 수 있다. With reference to FIG. 9, a process for picking up or separating an LED chip using a conductive carrier in the present invention will be described. The conductive carrier 210 may include an elastic member 215 at a lower portion and may be a support plate 211 . The elastic member 215 may include a conductive elastic member 212 , a dielectric layer 214 and an electrode layer 213 between the support plate 211 and the conductive elastic member 212 . The dielectric layer 214 is formed under the support plate 211 and may support the dielectric layer 214 . The support plate 211 may be a metal material or a non-metal material, or may include, for example, an aluminum material. The dielectric layer 214 may include a non-metal material, for example, at least one of polyimide, polyester, ceramic, tantalum, and a silicon film. The ceramic material is an amorphous ceramic material Al 2 O 3 , Y 2 O 3 , ZrO 2 , AlC, TiN, AlN, TiC, MgO, CaO, CeO 2 , TiO 2 , BxCy, BN, SiO 2 , SiC, YAG, In the group consisting of AlF 3 , one type or two or more types are each mixed and used. The thickness of the dielectric layer 214 may be 1 mm or less, for example, in the range of 0.1 mm to 1 mm. The electrode layer 213 may be disposed between the dielectric layer 214 and the conductive elastic member 212 . An adhesive layer 216 may be disposed around the electrode layer 231 to bond the dielectric layer 214 and the elastic member 212 to each other. The adhesive layer 216 may be a material of the dielectric layer 214 or a material such as silicone or epoxy. The electrode layer 213 may receive power through the electrode line 218 and may include at least one or two or more of a conductive metal, for example, tungsten, molybdenum, titanium, silver, and copper. In the electrode layer 213 , electrode patterns in the form of a mesh are arranged, and may be uniformly distributed over the entire area. The thickness of the electrode layer 213 may be 50 μm or less, for example, 15 to 50 μm. The electrode layer 213 may be formed as a single layer or a multilayer. The conductive elastic member 212 may include a conductive material having elasticity, and may be a polymer having viscosity and elasticity. The conductive elastic member 212 may be rubber, a thermoplastic polymer, or a thermosetting polymer. The conductive elastic member 212 may include a metal such as Ni, Cu, Ag, Al, or a metal oxide powder or a filler such as carbon black therein, and may function as an electrically conductive polymer.
도 9, 도 4 및 도 7을 참조하여 설명하면, 상기 도전성 캐리어(210)를 LED칩(2A,2B,2C) 상에 접촉시킨 후, 전극 라인(218)을 통해 전원을 공급하게 된다. 상기 전극층(213)에 전원이 공급되면, 상기 유전체층(214)과 상기 LED칩(2A,2B,2C) 또는 전도성 탄성부재(212) 사이에는 정전기적 인력이 발생되고, 시간이 경화함에 따라 전하량은 각각에 누적될 수 있다. 이에 따라 상기 도전성 캐리어(210)의 하면 또는 전도성 탄성부재(212)의 하면에는 별도의 접착제 없이 LED칩(2A,2B,2C)이 픽업될 수 있고, 상기 픽업 과정에서 상기 전도성 탄성부재(212)는 LED칩(2A,2B,2C)에 가해지는 압력을 낮추거나 완충시켜 줄 수 있다. 이러한 과정을 통해 도 4의 공정에서 픽업 공정을 수행할 수 있고, 픽업된 후, 도 11과 같이, 접착층(B0)을 각 LED칩(2A,2B,2C)에 스템핑하는 공정을 수행할 수 있다. 상기 전원은 직류 전압일 수 있다. 9, 4 and 7, after the conductive carrier 210 is brought into contact with the LED chips 2A, 2B, and 2C, power is supplied through the electrode line 218. When power is supplied to the electrode layer 213, an electrostatic attraction is generated between the dielectric layer 214 and the LED chips 2A, 2B, 2C or the conductive elastic member 212, and as time cures, the amount of charge decreases Each can be accumulated. Accordingly, the LED chips 2A, 2B, and 2C can be picked up on the lower surface of the conductive carrier 210 or the lower surface of the conductive elastic member 212 without a separate adhesive, and the conductive elastic member 212 in the pickup process. can decrease or buffer the pressure applied to the LED chips 2A, 2B, and 2C. Through this process, the pick-up process can be performed in the process of FIG. 4, and after being picked up, as shown in FIG. 11, the process of stamping the adhesive layer B0 to each LED chip 2A, 2B, 2C can be performed. have. The power may be a DC voltage.
도 11 및 도 12를 참조하면, 상기 도전성 캐리어(210)의 하부에 접착층(B10)이 배치된 제1 LED칩(2A)을 지지부재(1) 또는 회로기판 상에 대응시키거나 대면시켜 줄 수 있다. 이때 상기 회로기판(20) 상에서 상기 복수의 제1 LED칩(2A)들이 탑재될 위치가 미리 설정되어 있어, 상기 제1 LED칩(2A)이 픽업된 도전성 캐리어(210)를 상기 지지부재(1) 또는 회로기판 상에 위치 정렬시켜 줄 수 있다. 상기 도전성 캐리어(210)를 수직 하 방향으로 이동시켜 상기 회로기판(20) 상에 위치시킨 상태에서, 상기 도전성 캐리어(210)에 부착된 제1 LED칩(2A)들을 상기 지지부재(1) 상에 배치(Release)하고 접착층(B10)으로 접착시켜 줄 수 있다. 상기 지지부재(1)이 배치된 지지 프레임(BS)은 지지하는 부재로서, 상기 투명한 접착층(B10)의 경화가 용이하도록 소정의 온도 즉, 250도 이하 예컨대, 100도 내지 250도의 온도를 유지하는 정전척일 수 있다. 이때의 온도 편차가 일정하게 제공하여, 후술되는 수지 형성 공정에서의 크랙 방지를 억제할 수 있다. 이러한 방식으로 상기 지지부재(1)의 상면에 컬러별 블록의 LED칩(2A,2B,2C)들이 차례대로 배치되거나, 동일 컬러의 블록의 LED칩이 한 번의 부착 공정을 통해 배치될 수 있다. 11 and 12 , the first LED chip 2A having the adhesive layer B10 disposed on the lower portion of the conductive carrier 210 may correspond to or face the support member 1 or the circuit board. have. At this time, the positions at which the plurality of first LED chips 2A are mounted on the circuit board 20 are set in advance, so that the conductive carrier 210 on which the first LED chips 2A is picked up is held by the support member 1 . ) or it can be aligned on the circuit board. In a state in which the conductive carrier 210 is vertically moved and positioned on the circuit board 20 , the first LED chips 2A attached to the conductive carrier 210 are placed on the support member 1 . It can be placed on (Release) and adhered with an adhesive layer (B10). The support frame BS on which the support member 1 is disposed is a support member, and maintains a predetermined temperature, that is, 250 degrees or less, for example, 100 degrees to 250 degrees to facilitate curing of the transparent adhesive layer B10. It may be an electrostatic chuck. By providing a constant temperature deviation at this time, crack prevention in the resin formation process mentioned later can be suppressed. In this way, the LED chips 2A, 2B, and 2C of blocks of each color may be sequentially disposed on the upper surface of the support member 1, or LED chips of blocks of the same color may be disposed through a single attachment process.
도 13과 같이, 상기 지지부재(1)는 상부에 컬러별 블록의 LED칩(2A,2B,2C)들이 차례대로 배치되면, 상기 LED칩들이 배치될 영역의 주변 또는 외측에 복수의 패드(61,63)들이 배열될 수 있다. 즉, 각 LED칩(2A,2B,2C) 각각의 전극과 연결되기 위한 패드(61,63)들일 수 있다. 상기 복수의 패드(61,63)들과 상기 복수의 제1 LED칩(2A)과, 복수의 제2 LED칩(2B), 및 복수의 제3 LED칩(2C)들은 지지부재(1)의 상면 상에 배치될 수 있다. 상기 복수의 패드(61,63)는 제1패드(61) 및 제2패드(63)를 포함할 수 있으며, 교대로 반복될 수 있다. 이에 따라 지지부재(1) 또는 회로기판 상에 제1 LED칩(2A)들이 배열될 수 있다. 상기 지지부재(1)의 상면과 상기 제1 LED칩(2A) 사이 각각에는 상기 접착층(B10)이 각각 배치될 수 있다. 여기서, 발명은 지지부재(1) 상의 패드(61,63) 상에 별도의 솔더를 형성하는 공정을 수행하지 않고, LED칩(2A,2B,2C)를 접착층(B10)으로 부착시켜 줄 수 있다. 여기서, 상기 LED칩은 가압 방식이 아닌 자연적인 언로딩(Natural unloading) 방식으로 회로기판 또는 지지부재 상에 부착되므로, LED칩의 손해가 없고 로딩 후 열처리로 접착층(B10)을 경화시켜 주어, 공정이 단순화될 수 있다. 또한 접착층(B10)의 일부는 상기 로딩 공정에 의해 LED칩(2A,2B,2C)의 외 측면으로 연장될 수 있다. 상기한 공정을 반복적으로 수행하여, 도 4에 개시된 각 제2블록의 제2 LED칩(2B), 및 제3블록의 제3 LED칩(2C)을 각각 회로기판(20) 상에 더 정렬시켜 줄 수 있다. 즉, 도전성 캐리어(210)를 상기 지지부재(1) 상에 위치시킨 후 상기 블록별 LED칩(2A,2B,2C)들을 지지부재(1)의 상면에 접착층(B10)으로 부착한 다음, 상기 전원의 공급을 차단하게 된다. 이때 소정의 압력에 의해 상기 접착층(B10)은 상기 지지부재(1)의 상면에 접착되어, 각 블록별 LED칩들이 배치될 수 있고, 부착시 LED칩들의 유동을 억제시켜 줄 수 있다. 상기 전원의 공급이 차단되면, 상기 전도성 탄성부재(212)에는 0V가 충전될 수 있다. 즉, 같은 전압을 인가한 후 차단할 경우, 전도성 탄성부재(212)의 전도성 재질로 인해 0V의 전압이 걸리게 되므로, 상기 LED칩들은 상기 도전성 캐리어(210)로부터 분리될 수 있다. 이는 전도성 탄성부재(212)에 의해 잔류 전하의 방전이 용이하게 이루어지므로, 전압을 인가하면 흡착력이 증가될 수 있고 전원을 차단시키면 충전된 전하량이 LED칩에 영향을 주지 않고 방전될 수 있다. 여기서, 도 37은 LED칩들을 흡착하기 위한 흡착력, 해제하기 위한 디척킹력, 접착층의 접착력을 비교한 그래프로서, 상부 도전성 캐리어(ESC)와 하부 도전성 캐리어(ESC(backplane))의 흡착력(holding force)에서 제1스텝(TA1)에서 복수의 LED칩이 지지부재 상에 부착될 때, 흡착력은 하부 도전성 캐리어로 이동하게 되며, 제2스텝(TA2)에서 상부 도전성 캐리어가 디척킹되면서 흡착력은 하부로 이동되어 LED칩(mLED)들의 상부 이탈을 방지하며, 제3스텝(TA3)에서 하부 도전성 캐리어는 접착층이 경화하는 동안 LED칩들의 수평 보정을 유지하며 균일하게 접착시켜 줄 수 있다.13, when the LED chips 2A, 2B, and 2C of blocks for each color are sequentially arranged on the support member 1, the support member 1 has a plurality of pads 61 around or outside the area where the LED chips are to be arranged. , 63) can be arranged. That is, the pads 61 and 63 may be connected to the respective electrodes of the respective LED chips 2A, 2B, and 2C. The plurality of pads 61 and 63, the plurality of first LED chips 2A, the plurality of second LED chips 2B, and the plurality of third LED chips 2C are provided on the support member 1 . It may be disposed on the upper surface. The plurality of pads 61 and 63 may include a first pad 61 and a second pad 63 and may be alternately repeated. Accordingly, the first LED chips 2A may be arranged on the support member 1 or the circuit board. The adhesive layer B10 may be respectively disposed between the upper surface of the support member 1 and the first LED chip 2A. Here, the present invention can attach the LED chips 2A, 2B, and 2C to the adhesive layer B10 without performing a process of forming a separate solder on the pads 61 and 63 on the support member 1 . . Here, since the LED chip is attached on the circuit board or the support member by a natural unloading method rather than a pressurization method, there is no damage to the LED chip and hardening the adhesive layer (B10) by heat treatment after loading, the process This can be simplified. In addition, a portion of the adhesive layer B10 may extend to the outer side surfaces of the LED chips 2A, 2B, and 2C by the loading process. By repeatedly performing the above process, the second LED chip 2B of each second block and the third LED chip 2C of the third block shown in FIG. 4 are further aligned on the circuit board 20, respectively. can give That is, after the conductive carrier 210 is placed on the support member 1, the LED chips 2A, 2B, and 2C for each block are attached to the upper surface of the support member 1 as an adhesive layer B10, and then, the It will cut off the power supply. At this time, the adhesive layer B10 is adhered to the upper surface of the support member 1 by a predetermined pressure, so that the LED chips for each block can be arranged, and the flow of the LED chips can be suppressed when attached. When the power supply is cut off, 0V may be charged to the conductive elastic member 212 . That is, when the same voltage is applied and then blocked, a voltage of 0V is applied due to the conductive material of the conductive elastic member 212 , so that the LED chips can be separated from the conductive carrier 210 . Since the residual charge is easily discharged by the conductive elastic member 212, when a voltage is applied, the adsorption force can be increased, and when the power is turned off, the charged amount can be discharged without affecting the LED chip. Here, FIG. 37 is a graph comparing the adsorption force for adsorbing the LED chips, the dechucking force for releasing the LED chips, and the adhesion force of the adhesive layer. The holding force of the upper conductive carrier (ESC) and the lower conductive carrier (ESC (backplane)) In the first step TA1, when the plurality of LED chips are attached to the support member, the adsorption force moves to the lower conductive carrier, and in the second step TA2, the upper conductive carrier is dechucked while the adsorption force moves to the lower part. This prevents the LED chips mLED from being separated from the top, and in the third step TA3 , the lower conductive carrier can adhere the LED chips uniformly while maintaining the horizontal correction of the LED chips while the adhesive layer is cured.
이와는 다르게, 도 10의 비교 예와 같이, 정전 캐리어(210A)를 이용한 픽업 또는 분리 방식은, 콘덴서와 원리가 유사하게 전하를 축적하는 장치로서, 평행한 두 금속판(210B, Electrode 1,2)을 마주보게 한 상태에서 전압을 가하게 되면 +전극이 걸린 전극 판은 +전하를 띠게 되고, -전극이 걸린 전극 판은 -전하를 띠게 된다. 이때 대전된 두 평행판 사이에는 전하에 의한 힘이 발생하는데 이를 정전력(Electrostatic Force)이라 하며, 정전 캐리어(210A)는 진공챔버 내부에 기판이 놓이는 곳으로, 정전기의 힘을 사용하여 기판을 하부전극(Electrodes 1, 2)에 고정시켜주는 기능을 하게 되며, 극성(+) 또는 (-)의 전원을 인가하면 대상물(101A)에는 반대의 전위가 대전되고, 대전된 전위에 의하여 서로 끌어당기는 힘이 발생하는 원리를 이용하게 된다. 하지만, LED칩을 갖는 대상물(101A)과의 접촉면 전체에 걸친 고른 정전기 힘의 작용에 의해 대상물(101A)을 고착시키는 구조이다. 하지만, 전원을 차단할 경우, 두 유전체층에 걸리는 전하가 천천히 방전하게 되고, 방전 면적이 큰 이유로 LED칩들에 영향을 주는 문제가 있다. 발명의 실시 예는 전도성 탄성부재(212)를 도전성 캐리어의 하부에 배치시켜, LED칩을 보호하는 한편, 상기 LED칩에 영향을 주는 잔류 전하의 문제를 차단할 수 있다.On the other hand, as in the comparative example of FIG. 10 , the pickup or separation method using the electrostatic carrier 210A is a device for accumulating charges similarly to that of a capacitor, in which two parallel metal plates 210B, Electrodes 1 and 2 are used. When a voltage is applied in the state of facing each other, the electrode plate to which the + electrode is applied becomes positively charged, and the electrode plate to which the - electrode is applied becomes to have a - charge. At this time, a force is generated between the two parallel plates that are charged. This is called electrostatic force. The electrostatic carrier 210A is a place where the substrate is placed inside the vacuum chamber. It functions to fix the electrodes (Electrodes 1 and 2), and when power of polarity (+) or (-) is applied, the opposite potential is charged to the object 101A, and the force that attracts each other by the charged potential The principle of this occurrence is used. However, it has a structure in which the object 101A is fixed by the action of an even electrostatic force over the entire contact surface with the object 101A having the LED chip. However, when the power is turned off, the charges applied to the two dielectric layers are slowly discharged, and there is a problem in that the LED chips are affected due to the large discharge area. In an embodiment of the present invention, the conductive elastic member 212 is disposed under the conductive carrier to protect the LED chip, while blocking the problem of residual charges affecting the LED chip.
도 14와 같이, 회로기판(20)의 각각의 픽셀 영역(2)은 적색, 녹색 및 청색의 단색 광을 발광하는 적어도 3개의 LED칩(2A,2B,2C)들이 배열되며, 외부로부터 인가되는 신호에 의해 LED칩으로부터 적색, 녹색 및 청색 컬러의 광이 발광되어 화상을 표시할 수 있게 된다. 다른 예로서, 회로기판(20)의 각각의 픽셀 영역(2)은 동일 컬러의 복수의 LED칩(예: 청색 LED칩)들이 배열될 수 있다. 상기 복수의 LED칩(2A,2B,2C)은 회로기판(20)의 TFT 어레이 공정과는 별도의 공정으로 탑재될 수 있다. 즉, 회로기판(20) 상에 배치되는 LED칩(2A,2B,2C)들은 후술되는 공정을 통해 패키징되고 전기적으로 연결될 수 있다. 경계 영역(P10)에는 복수의 게이트라인과 데이터라인에 의해 정의된 영역일 수 있으며, 상기 복수의 LED칩(2A,2B,2C)과 연결될 수 있다. 여기서, 상기 복수의 LED칩(2A,2B,2C)의 두께는 서로 동일하거나, 상면 높이는 서로 동일할 수 있다. 상기 복수의 LED칩(2A,2B,2C)의 두께 차이가 존재할 경우, 접착층(B10)을 이용하여 서로 다른 종류의 LED칩(2A,2B,2C)의 상면 높이를 같게 할 수 있다. 14, in each pixel region 2 of the circuit board 20, at least three LED chips 2A, 2B, and 2C emitting monochromatic light of red, green, and blue are arranged, and are applied from the outside. Lights of red, green, and blue colors are emitted from the LED chip by the signal to display an image. As another example, a plurality of LED chips (eg, blue LED chips) of the same color may be arranged in each pixel region 2 of the circuit board 20 . The plurality of LED chips 2A, 2B, and 2C may be mounted in a process separate from the TFT array process of the circuit board 20 . That is, the LED chips 2A, 2B, and 2C disposed on the circuit board 20 may be packaged and electrically connected through a process to be described later. The boundary region P10 may be a region defined by a plurality of gate lines and data lines, and may be connected to the plurality of LED chips 2A, 2B, and 2C. Here, the thicknesses of the plurality of LED chips 2A, 2B, and 2C may be the same or the top surface height may be the same. When there is a difference in thickness between the plurality of LED chips 2A, 2B, and 2C, the top surface heights of different types of LED chips 2A, 2B, and 2C may be equalized by using the adhesive layer B10.
이하, 상기 LED칩들의 패키징 공정 및 배선 공정은 설명하기로 한다.Hereinafter, a packaging process and a wiring process of the LED chips will be described.
도 15a의 (A)(B)와 같이, 상기 지지부재(1) 상에 LED칩(2A,2B,2C)가 접착층(B10)으로 부착되면, LED칩(2A,2B,2C)의 상부에는 전극(K1,K2)들이 배치될 수 있다. 상기 수지부재(151)는 지지부재(1)의 상부를 몰딩하게 된다. 상기 수지부재(151)는 제 1내지 제3 LED칩(2A,2B,2C)들을 몰딩하게 된다. 상기 수지부재(151)는 상기 LED칩(2A,2B,2C)들과 패드(61,63)의 표면을 덮을 수 있다. 상기 수지부재(151)는 TFT부의 표면을 덮을 수 있다. 상기 수지부재(151)는 상기 LED칩(2A,2B,2C)을 통해 방출된 광을 흡수, 반사 또는 차단하는 재질을 포함할 수 있다. 상기 수지부재(151)는 광의 빛샘을 방지할 수 있다. 상기 수지부재(151)는 바인더 수지, 광중합 개시제, 블랙 안료, 용제 중 적어도 하나를 포함할 수 있으며, 예컨대, 바인더 수지는 에폭시계 수지, 아크릴계 수지, 폴리이미드 수지, 페널 수지, 실리콘계 수지, 또는 카도계 수지 재료를 포함할 수 있다. 상기 수지부재(151)는 레진계 또는 에폭시계의 블랙 재질일 수 있으며, 내부에 차광성, 반사성 또는 흡수성의 첨가제를 포함할 수 있다. 상기 수지부재(151)는 고굴절성 무기 분사체를 포함할 수 있으며, 예컨대 TiO 2　졸, SrTiO 3　졸, ZnS, ZnSe, 포타슘 브로마이드, AgCl, MgO, 세슘 아이오다이드, 세슘브로마이드, CaCO 3, 포스포러스 트리브로마이드, 페닐트리클로라이드, 트리크로만-4-온(Triochroman-4-one), 티오닐 브로마이드, ZnO 2, CeO 2, ITO 졸, Ta 2O 5, Ti 2O 5, Ti 2O 3, ZrO 2, Br 2, CS 2, ZrO 2-TiO 2　계 졸 및 SiO 2-Fe 2O 3계 화합물 중에서 선택된 1종 이상을 포함할 수 있다. 상기 수지부재(151)는 광 흡수 재질, 또는 열 흡수 또는 방열 재질을 포함할 수 있다.15A (A) (B), when the LED chips (2A, 2B, 2C) are attached to the adhesive layer (B10) on the support member (1), the upper portion of the LED chips (2A, 2B, 2C) Electrodes K1 and K2 may be disposed. The resin member 151 molds the upper portion of the support member 1 . The resin member 151 molds the first to third LED chips 2A, 2B, and 2C. The resin member 151 may cover the surfaces of the LED chips 2A, 2B, and 2C and the pads 61 and 63 . The resin member 151 may cover the surface of the TFT part. The resin member 151 may include a material that absorbs, reflects, or blocks the light emitted through the LED chips 2A, 2B, and 2C. The resin member 151 may prevent light leakage. The resin member 151 may include at least one of a binder resin, a photopolymerization initiator, a black pigment, and a solvent. For example, the binder resin may include an epoxy resin, an acrylic resin, a polyimide resin, a panel resin, a silicone resin, or a car It may include a dog-based resin material. The resin member 151 may be made of a resin-based or epoxy-based black material, and may include a light-blocking, reflective, or absorptive additive therein. The resin member 151 may include a highly refractive inorganic spray, for example, TiO 2 sol, SrTiO 3 sol, ZnS, ZnSe, potassium bromide, AgCl, MgO, cesium iodide, cesium bromide, CaCO 3 , Phosphor. Porous tribromide, phenyltrichloride, trichroman-4-one (Triochroman-4-one), thionyl bromide, ZnO 2 , CeO 2 , ITO sol, Ta 2 O 5 , Ti 2 O 5 , Ti 2 O 3 , ZrO 2 , Br 2 , CS 2 , ZrO 2 -TiO 2 sol, and SiO 2 -Fe 2 O 3 It may include at least one selected from the group consisting of compounds. The resin member 151 may include a light absorbing material or a heat absorbing or heat dissipating material.
여기서, 상기 수지부재(151)의 외측 표면은 오목한 제1리세스(R0)를 포함할 수 있으며, 상기 제1리세스(R0)는 오목한 곡면 또는/및 경사면을 포함할 수 있다. 즉, 상기 제1리세스(R0)의 표면은 급격한 곡면이나 단차진 면으로 제공되지 않도록 형성될 수 있다. 상기 수지부재(151)는 LED칩(2A,2B,2C)들의 상부, LED칩(2A,2B,2C)의 측면, 인접한 LED칩(2A,2B,2C)들의 사이, LED칩(2A,2B,2C)과 패드(61,63)들 사이에, 전극(K1,K2) 사이에 각각 배치될 수 있다. 여기서, 상기 LED칩(2A,2B,2C)과 패드(61,63) 사이의 최소 간격은 2㎛ 이상 예컨대, 2㎛ 내지 5㎛의 범위로 제공될 수 있다.Here, the outer surface of the resin member 151 may include a concave first recess R0, and the first recess R0 may include a concave curved surface and/or an inclined surface. That is, the surface of the first recess R0 may be formed so as not to be provided with an abruptly curved surface or a stepped surface. The resin member 151 is disposed on top of the LED chips 2A, 2B, and 2C, on the sides of the LED chips 2A, 2B, and 2C, between adjacent LED chips 2A, 2B, and 2C, between the LED chips 2A, 2B. , 2C) and the pads 61 and 63 and between the electrodes K1 and K2, respectively. Here, the minimum distance between the LED chips 2A, 2B, and 2C and the pads 61 and 63 may be provided in a range of 2 μm or more, for example, 2 μm to 5 μm.
도 15a의 (B)(C)와 같이, 상기 수지부재(151)가 형성되면, 상기 LED칩(2A,2B,2C)의 전극(K1,K2)와 패드(61,63)을 오픈시켜 주게 된다. 여기서, 상기 전극(K1,K2)와 패드(61,63)의 오픈 공정은 예컨대, 마스크를 이용한 노광(exposure) 공정, 현상(developing) 공정을 거쳐 하드 베이킹(Baking) 공정으로 진행될 수 있다. 상기 수지부재(151)이 제거된 영역(R1,R2,R3,R4)을 통해 상기 전극(K1,K2)과 패드(61,63)가 후 방향으로 노출될 수 있다. 도 15a의 (C)(D)와 같이, 상기 전극(K1,K2)와 패드(61,63)가 노출되면, 상기 수지부재(151)의 표면 상에 액상의 도전층(160)을 형성하게 된다. 상기 도전층(160)은 상기 수지부재(151)의 상면, 전극(K1,K2)들과 패드(61,63)들의 상면에 형성될 수 있다. 이때 상기 도전층(160)은 스프레이 방식으로 액상의 도전층(160)을 상기 수지부재(151)의 상면 전체와 전극(K1,K2)와 패드(61,63) 상의 전 영역에 형성될 수 있다. 이때 상기 도전층(160)은 상기 전극(K1,K2)와 패드(61,63) 상에 단일 잉크 층으로 덮고 있다. 상기 도전층(160)은 금속 재질의 나노 파우더와 접착 바인더를 포함할 수 있다. 상기 도전층(160)은 광개시제, 금속 재질의 나노 파우더와 접착 바인더를 포함할 수 있다. 상기 도전층(160)은 그래핀 재질, 금속 재질의 나노 파우더, 접착 바인더, 및 광 개시제를 포함할 수 있다. 상기 광개시제는 잉크 조성물의 총 중량의 10중량% 이하 예컨대, 0.01 내지 10 중량%의 범위일 수 있다. 상기 광개시제는 자외선 감응형 재료로서, HP-8, TPO 및 DETX 3종을 선택적으로 조합하여 사용할 수 있다. 상기 광개시제는 1-히드록시-시클로헥실-페닐 케톤, 2-히드록시-2-메틸 -1-페닐-1-프로판온, 2-히드록시-1-[4-(2-히드록시에톡시)페닐]-2-메틸-1-프로판온, 메틸벤조일포르메이트, α디메톡시-α-페닐아세토페논, 2-벤조일-2-(디메틸아미노)-1-[4-(4-모포린일)페닐]-1-부타논, 2-메틸-1-[4-(메틸 씨오)페닐]-2-(4-몰포린일)-1-프로판온 디페닐(2,4,6-트리메틸벤조일)-포스핀옥사이드, 또는 비스(2,4,6-트리메 틸벤조일)-페닐포스핀옥사이드 등을 들 수 있으나, 반드시 이에 제한되지는 않는다. 상기 금속 나노 파우더는 Al, Si, Au, Ag, Pt, Cr, Mo, Ta, 및 Cu 중 적어도 하나를 포함할 수 있다. 상기 금속 나노 파우더는 잉크 조성물 중에서 가장 높은 비율을 가질 수 있으며, 예컨대 50 중량% 이상이거나 50 내지 80 중량% 범위일 수 있다. 상기 접착 바인더는 무기물 바인더 예컨대, SiO 2계, Na 2O계, Al 2O 3계, Fe 2O 3계, CaO계 재질 중 적어도 하나를 포함할 수 있다. 상기 접착 바인더는 잉크 조성물의 총 중량의 60 중량% 이하 예컨대, 20 내지 60중량%의 범위일 수 있다. 상기 그래핀 재질은 10중량% 이하 예컨대, 0.01 내지 10중량% 범위일 수 있다. 상기 도전층(160)의 형성공정은 웻(Wet) 방식의 공정으로 형성될 수 있다. 상기 도전층(160)의 형성은 스퍼터링 공정으로 형성될 수 있으나, 상기 스퍼터링 공정은 웻방식의 공정보다 복잡하고 웻 방식보다 도전층의 박막 두께가 더 얇을 수 있다. 15A (B) (C), when the resin member 151 is formed, the electrodes K1, K2 and the pads 61 and 63 of the LED chips 2A, 2B, 2C are opened. do. Here, the opening process of the electrodes K1 and K2 and the pads 61 and 63 may be performed as a hard baking process through, for example, an exposure process using a mask, a developing process, and the like. The electrodes K1 and K2 and the pads 61 and 63 may be exposed in the rear direction through the regions R1 , R2 , R3 , and R4 in which the resin member 151 is removed. As shown in (C) (D) of FIG. 15A , when the electrodes K1 and K2 and the pads 61 and 63 are exposed, a liquid conductive layer 160 is formed on the surface of the resin member 151 . do. The conductive layer 160 may be formed on the upper surface of the resin member 151 , the electrodes K1 and K2 , and the upper surface of the pads 61 and 63 . In this case, the conductive layer 160 may be formed by spraying the liquid conductive layer 160 over the entire upper surface of the resin member 151 and on the electrodes K1 and K2 and the pads 61 and 63. . In this case, the conductive layer 160 is covered with a single ink layer on the electrodes K1 and K2 and the pads 61 and 63 . The conductive layer 160 may include a metal nano-powder and an adhesive binder. The conductive layer 160 may include a photoinitiator, a metal nano-powder, and an adhesive binder. The conductive layer 160 may include a graphene material, a metal nanopowder, an adhesive binder, and a photoinitiator. The photoinitiator may be in the range of 10% by weight or less, for example, 0.01 to 10% by weight of the total weight of the ink composition. The photoinitiator is a UV-sensitive material, and may be used by selectively combining three types of HP-8, TPO, and DETX. The photoinitiator is 1-hydroxy-cyclohexyl-phenyl ketone, 2-hydroxy-2-methyl-1-phenyl-1-propanone, 2-hydroxy-1-[4-(2-hydroxyethoxy) Phenyl]-2-methyl-1-propanone, methylbenzoylformate, α-dimethoxy-α-phenylacetophenone, 2-benzoyl-2-(dimethylamino)-1-[4-(4-morpholinyl) Phenyl]-1-butanone, 2-methyl-1-[4-(methyl thio)phenyl]-2-(4-morpholinyl)-1-propanone diphenyl (2,4,6-trimethylbenzoyl) -phosphine oxide, or bis(2,4,6-trimethylbenzoyl)-phenylphosphine oxide, etc., but is not necessarily limited thereto. The metal nanopowder may include at least one of Al, Si, Au, Ag, Pt, Cr, Mo, Ta, and Cu. The metal nanopowder may have the highest proportion in the ink composition, for example, 50 wt% or more or may be in the range of 50 to 80 wt%. The adhesive binder may include at least one of inorganic binders, for example, SiO 2 based, Na 2 O based, Al 2 O 3 based, Fe 2 O 3 based, and CaO based materials. The adhesive binder may be in the range of 60% by weight or less, for example, 20 to 60% by weight of the total weight of the ink composition. The graphene material may be in the range of 10% by weight or less, for example, 0.01 to 10% by weight. The forming process of the conductive layer 160 may be formed by a wet method. The conductive layer 160 may be formed by a sputtering process, but the sputtering process is more complicated than the wet process, and the thickness of the conductive layer may be thinner than the wet process.
도 15a의 (D), 도 15b의 (E)(F), 도 17 및 도 19와 같이, 상기 도전층(160) 상에 마스크(170)를 배치할 수 있다. 상기 마스크(170)의 개구부(OP1)는 제거하고자 하는 영역과 중첩되는 영역에 형성될 수 있다. 즉, 상기 마스크(170)는 연결부의 영역을 제외한 영역을 오픈시켜 줄 수 있다. 이러한 개구부(OP1)를 통해 노광 공정을 수행한 다음, 현상 공정을 진행하게 된다. 이때 도 15b의 (F) 및 도 17의 (A)(B)와 같이, 현상 공정은 상기 노광된 영역(R5)만을 제거하고, 노광되지 않는 영역은 남아있게 된다(도 19의 (B)(C) 참조). 이러한 현상 공정 후 열 처리후 연결부가 LED칩의 전극(K1,K2)과 회로기판의 패드(61,63)들을 서로 연결시켜 줄 수 있다. 즉, 상기 제1연결부(161)는 제1전극(K1)과 제1패드(61)를 연결해 주며, 제2연결부(162)는 제2전극(K2)와 제2패드(63)를 연결해 줄 수 있다. 상기 각 LED칩(2A,2B,2C)을 덮는 수지부재(151) 상에서 도전층 중에서 상기 제1 및 제2연결부(161,162)의 영역들이 서로 분리된 상태로 남아있을 수 있다. 도 15b의 (G)(H)와 같이, 패시베이션층(155)은 상부에 형성될 수 있다. 상기 패시베이션층(155)은 상기 제1 및 제2연결부(161,162)의 상면 및 노출된 수지부재(151)의 표면 상에 형성될 수 있다. 상기 패시베이션층(155)은 실리콘 또는 에폭시와 같은 재질의 층이거나, 방열 재질의 절연층일 수 있다. 15A (D), 15B (E) (F), as shown in FIGS. 17 and 19 , a mask 170 may be disposed on the conductive layer 160 . The opening OP1 of the mask 170 may be formed in a region overlapping the region to be removed. That is, the mask 170 may open an area excluding the area of the connection part. After performing an exposure process through the opening OP1, a developing process is performed. At this time, as shown in FIGS. 15B (F) and 17 (A) (B), the developing process removes only the exposed region R5, and the unexposed region remains (FIG. 19B) ( see C)). After the developing process and heat treatment, the connection part may connect the electrodes K1 and K2 of the LED chip and the pads 61 and 63 of the circuit board to each other. That is, the first connector 161 connects the first electrode K1 and the first pad 61 , and the second connector 162 connects the second electrode K2 and the second pad 63 . can In the conductive layer on the resin member 151 covering each of the LED chips 2A, 2B, and 2C, regions of the first and second connection parts 161 and 162 may remain separated from each other. As shown in (G) (H) of FIG. 15B , the passivation layer 155 may be formed thereon. The passivation layer 155 may be formed on the upper surfaces of the first and second connection parts 161 and 162 and the exposed surface of the resin member 151 . The passivation layer 155 may be a layer made of a material such as silicon or epoxy, or an insulating layer made of a heat dissipation material.
도 16을 참조하면, 상기 수지부재(151)는 상기 LED칩(2A,2B,2C)의 측면에 접착될 수 있으며, 예컨대 발광구조물(105)의 측면, 투광성 기판(101)의 측면, 전극(K1,K2)의 측면에 접착될 수 있다. 또한 수지부재(151)는 LED칩(2A,2B,2C)의 상면에 접착될 수 있으며, 전극(K1,K2)의 상면보다 높게 배치될 수 있다. 상기 수지부재(151)는 상기 접착층(B10)의 돌출부(B11)에 접착될 수 있다. 상기 접착층(B10)은 최소 두께(T1)가 1㎛ 이하 예컨대, 0.2㎛ 내지 0.5㎛ 범위를 갖고, 지지부재(1)의 상면에 LED칩(2A,2B,2C)의 하면을 밀착시켜, 광 투과율이 저하되는 것을 방지할 수 있다. 상기 돌출부(B11)는 상기 투광성 기판(101)의 측면에 접착되며, 수지부재(151)과의 접착력이 증가될 수 있다. 이에 따라 상기 수지부재(151)는 LED칩(2A,2B,2C)의 주변에 접착되어, 지지하여 유동을 방지할 수 있다.Referring to FIG. 16 , the resin member 151 may be adhered to the side surfaces of the LED chips 2A, 2B, and 2C, for example, the side surface of the light emitting structure 105 , the side surface of the light-transmitting substrate 101 , the electrode ( It can be attached to the side of K1, K2). In addition, the resin member 151 may be adhered to the upper surfaces of the LED chips 2A, 2B, and 2C, and may be disposed higher than the upper surfaces of the electrodes K1 and K2. The resin member 151 may be adhered to the protrusion B11 of the adhesive layer B10. The adhesive layer B10 has a minimum thickness T1 of 1 μm or less, for example, 0.2 μm to 0.5 μm, and adheres the lower surfaces of the LED chips 2A, 2B, and 2C to the upper surface of the support member 1 , It can prevent the transmittance|permeability from falling. The protrusion B11 is adhered to the side surface of the light-transmitting substrate 101 , and adhesion to the resin member 151 may be increased. Accordingly, the resin member 151 may be adhered to and supported around the LED chips 2A, 2B, and 2C to prevent flow.
도 16, 도 17(A)(B) 및 도 19의 (A)를 참조하면, 액상의 감광성 도전층(160)을 상기 수지부재(151)의 전체 표면에 형성해 주고, 노광 및 현상을 통해 연결부를 형성하게 된다. 즉, 감광성 도전층(160)은 PCI(Photosensitive conductive ink) 재질일 수 있다. 이러한 PCI를 이용한 연결부의 형성 공정은 포토 레지스트(PR) 공정 없이 코팅-노광-현상 후 열처리 공정으로 단순화할 수 있다. 만약, 스퍼터 방식으로 연결부를 형성하는 공정에 비해, 포토레지스터 코팅하고 이를 제거하는 공정, 포토 레지스트의 잔막을 제거하는 공정, 메탈 에칭 공정 등이 줄어들 수 있다. 또한 상기 연결부(161,162)의 두께는 웻 공정을 통해 진행됨으로써, 전 영역에 균일하고 스퍼터 방식에 비해 두꺼운 두께로 형성될 수 있다. 또한 상기 연결부(161,162)의 두께는 1.5㎛ 이상의 두께 예컨대, 1.5 내지 5㎛의 범위로 형성될 수 있다. 이에 따라 연결부(161,162)에서의 크랙이 방지될 수 있고, 벗겨짐(delamination) 현상이 줄어들 수 있다. 또한 연결부(161,162)에서의 저항은 50mΩ 이하로 낮아질 수 있다. 또한 PCI 공정은 예컨대, 패드측 재질인 ITO와 전극측 재질인 Au와의 접착력이 높고 별도의 범프를 형성하는 공정 없이 웻 코팅을 통해 공정을 단순화시켜 줄 수 있다. 이러한 웻 방식은 스프레이 코팅 방식, 딥 코팅(dip coating), 스핀 코팅(spin coating), 또는 프린트 방식(예: 스크린 프린팅, 잉크젯 프린팅) 중 적어도 하나로 형성될 수 있다. 여기서, 스퍼터와 같은 방식으로 연결부를 형성할 경우, 다층으로 진행 시 많은 시간이 필요하고, 파티클로 인한 쇼트가 발생될 수 있다. 예를 들면, 스퍼터와 같은 방식으로 연결부를 형성할 경우, 패드측 재질인 ITO와 전극측 재질인 Au와의 접착력이 낮아 Ti 또는 TiW와 같은 접착층을 더 증착한 다음 Au 또는 Cu와 같은 연결층을 형성해야 하는 복잡하고 다양한 문제들이 노출되고 있다. 예를 들면, 스퍼터와 같은 방식으로 인한 연결부를 형성할 때, 그 두께는 1㎛ 이하로 형성될 수 있어, 벗겨짐 현상이나 크랙이 발생될 수 있다. 도 18과 같이, 증착되는 연결부의 두께가 얇을 경우, 수지부재(151)의 표면 상에 단차지거나 각진 부분(A20)와 같은 영역 상에 연결된 부분(A22)은 저항 값이 상승하는 요인이 되고 발열 및 단락의 위험이 있는 문제가 있다. 따라서, 발명의 실시 예는 웻 방식으로 연결부(161,162)를 형성해 줌으로써, 수지부재(151)의 표면 상에서 각진 부분이나 단차진 부분으로 액상이 쏠리는 현상을 줄일 수 있고, 고저항, 발열 및 단선 등의 문제는 제거할 수 있다. 또한 웻 방식으로 연결부(161,162)를 형성해 줌으로서, 연결부(161,162)와 수지부재(151) 사이의 접착력 및 전기적 특성이 개선될 수 있다. 다만, 실시예에서 연결부를 형성방법으로 스퍼터 방식을 배제하는 것은 아니며, 위 설명들은 웻 방식이 스퍼터 방식에 비해 기술적 특성이 좀 더 개선될 수 있는 것을 의미한다.16, 17 (A) (B) and 19 (A), a liquid photosensitive conductive layer 160 is formed on the entire surface of the resin member 151, and the connection part is exposed and developed through exposure and development. will form That is, the photosensitive conductive layer 160 may be made of a photosensitive conductive ink (PCI) material. The process of forming the connection part using the PCI can be simplified to a heat treatment process after coating-exposure-developing without a photoresist (PR) process. If, compared to the sputtering process of forming the connection part, the process of coating the photoresist and removing it, the process of removing the remaining film of the photoresist, the metal etching process, etc. may be reduced. In addition, the thickness of the connection parts 161 and 162 may be uniformly formed over the entire area and thicker than the sputtering method by performing a wet process. In addition, the thickness of the connecting portions 161 and 162 may be formed in a thickness of 1.5 μm or more, for example, in the range of 1.5 to 5 μm. Accordingly, cracks in the connection portions 161 and 162 may be prevented, and a delamination phenomenon may be reduced. Also, the resistance at the connection portions 161 and 162 may be lowered to 50 mΩ or less. In addition, the PCI process, for example, has a high adhesion between ITO, which is a pad side material, and Au, which is an electrode side material, and can simplify the process through wet coating without a process of forming a separate bump. The wet method may be formed by at least one of a spray coating method, a dip coating method, a spin coating method, or a printing method (eg, screen printing, inkjet printing). Here, when the connection part is formed in the same way as sputtering, a lot of time is required when proceeding to a multilayer, and a short circuit due to particles may occur. For example, when forming the connection part in the same way as sputtering, the adhesive strength between ITO as the pad side material and Au as the electrode side material is low, so an adhesive layer such as Ti or TiW is further deposited, and then a connection layer such as Au or Cu is formed. There are many complex and diverse issues that need to be addressed. For example, when forming a connection portion by a method such as sputtering, the thickness may be formed to be 1 μm or less, so that a peeling phenomenon or a crack may occur. As shown in FIG. 18 , when the thickness of the deposited connection portion is thin, the portion A22 connected on the same area as the stepped or angled portion A20 on the surface of the resin member 151 causes an increase in resistance value and heat and a risk of short circuit. Therefore, in the embodiment of the present invention, by forming the connecting portions 161 and 162 in a wet manner, it is possible to reduce the phenomenon that liquid is drawn to an angled portion or a stepped portion on the surface of the resin member 151, and high resistance, heat generation, disconnection, etc. The problem can be eliminated. In addition, by forming the connecting portions 161 and 162 in a wet manner, the adhesive force and electrical characteristics between the connecting portions 161 and 162 and the resin member 151 may be improved. However, in the embodiment, the sputtering method is not excluded as a method of forming the connection part, and the above descriptions mean that the wet method may have improved technical characteristics compared to the sputter method.
도 20과 같이, 제1 내지 제3 LED칩(2A,2B,2C) 상에는 수지부재(151)이 밀봉되며, 각 LED칩(2A,2B,2C)의 제1 전극(K1)와 TFT부의 제1패드(61) 사이에는 제1연결부(161)가 연결되며, 제2 전극(K2)과 TFT부의 제2패드(63) 사이에는 제2연결부(162)가 연결될 수 있다. 이에 따라 제1 내지 제3 LED칩(2A,2B,2C)는 TFT부와 전기적으로 연결되어, 선택적으로 구동될 수 있다. 제1 내지 제3 LED칩(2A,2B,2C)는 서로 다른 컬러 예컨대, 적색, 녹색 및 청색의 광을 발광할 수 있다. 다른 예로서, 제1 내지 제3 LED칩(2A,2B,2C)은 동일 컬러 예컨대, 청색의 광을 발광할 수 있다. 상기 복수의 LED칩(2A,2B,2C)이 선택적으로 구동되면, 방출된 광들은 투명한 지지부재(1)를 통해 타면으로 방출될 수 있다. 이때 상기 LED칩(2A,2B,2C)의 주변에 배치된 상기 수지부재(151)는 측면 노출 광들을 흡수되거나 차단하여, 광의 시인성을 높여줄 수 있다. As shown in Fig. 20, the resin member 151 is sealed on the first to third LED chips 2A, 2B, and 2C, and the first electrode K1 of each LED chip 2A, 2B, and 2C and the TFT part are formed. A first connection part 161 may be connected between the first pads 61 , and a second connection part 162 may be connected between the second electrode K2 and the second pad 63 of the TFT unit. Accordingly, the first to third LED chips 2A, 2B, and 2C may be electrically connected to the TFT unit and selectively driven. The first to third LED chips 2A, 2B, and 2C may emit light of different colors, for example, red, green, and blue light. As another example, the first to third LED chips 2A, 2B, and 2C may emit light of the same color, for example, blue. When the plurality of LED chips 2A, 2B, and 2C are selectively driven, the emitted light may be emitted to the other surface through the transparent support member 1 . In this case, the resin member 151 disposed around the LED chips 2A, 2B, and 2C absorbs or blocks the side exposure light, thereby increasing the visibility of the light.
도 21을 참조하면, TFT를 갖는 회로기판(20)과 상기 회로기판(20) 상에 배치된 복수의 LED칩(2A,2B,2C)의 구성은 광원 모듈로 정의될 수 있다. 상기 회로기판(20)은 상기 LED칩(2A,2B,2C)과 연결되는 TFT부(50)를 포함할 수 있다. 상기 회로기판(20)은 유리와 같은 투명한 지지부재(1) 및 그 상부의 패드 또는 라인 패턴을 포함할 수 있다. 상기 TFT부(50)는 상기 지지부재(1)의 일면 또는 상면에 배치될 수 있다. 상기 회로기판(20)에서 상기 TFT부(50)는 게이트 전극(51), 반도체층(53), 소스 전극(55) 및 드레인 전극(57)으로 구성된다. 회로기판(20) 상에 게이트 전극(51)이 형성되고, 게이트 절연층(49)이 회로기판(110)의 전체 영역에 걸쳐 형성되어 게이트 전극(51)을 덮고, 반도체층(53)이 게이트 절연층(49) 위에 형성되며, 소스 전극(55) 및 드레인 전극(57)이 반도체층(53) 위에 형성된다. Referring to FIG. 21 , the configuration of the circuit board 20 having the TFT and the plurality of LED chips 2A, 2B, and 2C disposed on the circuit board 20 may be defined as a light source module. The circuit board 20 may include a TFT unit 50 connected to the LED chips 2A, 2B, and 2C. The circuit board 20 may include a transparent support member 1 such as glass and a pad or line pattern thereon. The TFT unit 50 may be disposed on one surface or an upper surface of the support member 1 . In the circuit board 20 , the TFT unit 50 includes a gate electrode 51 , a semiconductor layer 53 , a source electrode 55 , and a drain electrode 57 . A gate electrode 51 is formed on the circuit board 20 , a gate insulating layer 49 is formed over the entire area of the circuit board 110 to cover the gate electrode 51 , and a semiconductor layer 53 is formed with the gate It is formed on the insulating layer 49 , and a source electrode 55 and a drain electrode 57 are formed on the semiconductor layer 53 .
상기 게이트 전극(51)은 Cr, Mo, Ta, Cu, Ti, Al 또는 Al합금 등의 금속 또는 이들의 합금으로 형성될 수 있으며, 게이트 절연층(49)은 SiOx 또는 SiNx와 같은 무기 절연물질로 이루어진 단일층 또는 SiOx 및 SiNx으로 이루어진 복수의 층으로 이루어질 수 있다. 반도체층(53)은 비정질 실리콘과 같은 비정질 반도체로 구성될 수도 있고, IGZO(Indium Gallium Zinc Oxide), TiO 2, ZnO, WO 3, SnO 2와 같은 산화물 반도체로 구성될 수 있다. 산화물 반도체로 반도체층(53)을 형성하는 경우, TFT의 크기를 감소시킬 수 있고 구동 전력을 감소시킬 수 있고 전기 이동도를 향상시킬 수 있게 된다. 물론, 본 발명에서는 TFT의 반도체층이 특정 물질에 한정되는 것이 아니라, 현재 TFT에 사용되는 모든 종류의 반도체물질을 사용할 수 있을 것이다.The gate electrode 51 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy or an alloy thereof, and the gate insulating layer 49 is made of an inorganic insulating material such as SiOx or SiNx. It may be made of a single layer made of or a plurality of layers made of SiOx and SiNx. The semiconductor layer 53 may be formed of an amorphous semiconductor such as amorphous silicon, or an oxide semiconductor such as indium gallium zinc oxide (IGZO), TiO 2 , ZnO, WO 3 or SnO 2 . When the semiconductor layer 53 is formed of an oxide semiconductor, the size of the TFT can be reduced, the driving power can be reduced, and the electric mobility can be improved. Of course, in the present invention, the semiconductor layer of the TFT is not limited to a specific material, and all kinds of semiconductor materials currently used in the TFT may be used.
소스 전극(55) 및 드레인 전극(57)은 Cr, Mo, Ta, Cu, Ti, Al, Al합금 등과 같은 금속 또는 이들의 합금으로 이루어질 수 있다. 이때, 드레인 전극(57)은 LED칩(2A,2B,2C)에 신호를 인가하는 제1 연결전극으로 활용될 수 있다. 한편, 도면에서는 TFT부(50)가 바텀 게이트(bottom gate)방식 TFT지만, 본 발명이 이러한 특정 구조의 TFT에 한정되는 것이 아니라 탑 게이트(top gate)방식 TFT와 같이 다양한 구조의 박막트랜지터가 적용될 수 있을 것이다.The source electrode 55 and the drain electrode 57 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy or an alloy thereof. In this case, the drain electrode 57 may be used as a first connection electrode for applying a signal to the LED chips 2A, 2B, and 2C. On the other hand, although the TFT unit 50 is a bottom gate type TFT in the drawing, the present invention is not limited to a TFT having a specific structure, and thin film transistors having various structures such as a top gate type TFT are used. could be applied.
제1절연층(41)의 하부에는 제2연결 전극(59)이 형성된다. 이때, 제2연결전극(59)은 Cr, Mo, Ta, Cu, Ti, Al 또는 Al합금 등의 금속 또는 이들의 합금으로 형성될 수 있으며, 제2 연결전극(59)(즉, TFT의 드레인 전극(57))과 동일한 공정에 의해 형성될 수 있다. TFT부(50)가 형성된 회로기판(20) 위에는 제1 절연층(41)이 형성되며, 발광영역의 제1 절연층(41)의 개구부에 LED칩(2A,2B,2C)이 배치된다. 이때, 도면에서는 제1 절연층(114)의 일부가 제거되고 제거된 영역 상에 LED칩(2A,2B,2C)들이 배열될 수 있다. 상기 제1 절연층(41)은 폴리 이미드(PI) 필름, 포토아크릴과 같은 유기층으로 구성될 수도 있고, 무기층/유기층 또는 무기층/유기층/무기층 등의 복층 구조로 구성될 수도 있다. 상기 제1절연층(41)이 오픈된 영역에는 제1 및 제2패드(61,63)가 배치될 수 있다. 상기 제1패드(61)는 상기 제1연결 전극(57) 상에 배치되거나, 상기 제1연결 전극(57)의 일부 물질일 수 있다. 상기 제2패드(63)는 상기 제2연결 전극(59) 상에 배치되거나, 상기 제2연결 전극(59)의 일부 물질일 수 있다. 각 LED칩(2A,2B,2C)의 제1 전극(K1)와 TFT부의 제1패드(61)에는 제1연결부(161)의 양단(P2,P4)이 연결되며, 제2 전극(K2)과 TFT부의 제2패드(63)에는 제2연결부(162)의 양단(P1,P3)이 연결될 수 있다. 상기 제1 및 제2연결 전극(57,59)는 지지부재(1)의 상면에 형성될 수 있다. 다른 예로서, 지지부재(1)의 상면에 형성된 게이트 절연층(49)이 제거된 영역에 상기 수지부재(151) 및 접착층(B10)이 배치될 수 있다. 다른 예로서, 상기 게이트 절연층(49)는 수지부재(151) 및 접착층(B10)의 하면에 연장될 수 있다. 상기 제1 및 제2패드(61,63)는 Ti, Ni, Pt, TiN, Mo, Al, W, Cu, Ag, Au 중 적어도 둘 이상을 포함할 수 있다. 상기 제1 및 제2패드(61,63)는 다층으로 형성될 수 있다. 이후, 디스플레이 패널 상에 각 컬러별 LED칩들이 실장되면, 클리닝 공정을 수행할 수 있으며, 상기 클리닝 공정을 통해 플럭스와 같은 비정상적인 부분을 제거할 수 있다. 상기 수지부재(151) 및 패시베이션층(155) 중 적어도 하나 또는 모두는 상기 TFT부(50)의 표면 상에 더 연장되어 배치될 수 있어, TFT부(50)의 표면을 보호할 수 있다. A second connection electrode 59 is formed under the first insulating layer 41 . In this case, the second connection electrode 59 may be formed of a metal such as Cr, Mo, Ta, Cu, Ti, Al or Al alloy or an alloy thereof, and the second connection electrode 59 (ie, the drain of the TFT). It may be formed by the same process as the electrode 57). A first insulating layer 41 is formed on the circuit board 20 on which the TFT unit 50 is formed, and the LED chips 2A, 2B, and 2C are disposed in the opening of the first insulating layer 41 of the light emitting region. In this case, in the drawing, a portion of the first insulating layer 114 is removed and the LED chips 2A, 2B, and 2C may be arranged on the removed area. The first insulating layer 41 may be composed of an organic layer such as a polyimide (PI) film or photoacrylic, or may have a multilayer structure such as an inorganic layer/organic layer or an inorganic layer/organic layer/inorganic layer. First and second pads 61 and 63 may be disposed in the area where the first insulating layer 41 is opened. The first pad 61 may be disposed on the first connection electrode 57 or may be a part of the material of the first connection electrode 57 . The second pad 63 may be disposed on the second connection electrode 59 or may be a part of the second connection electrode 59 . Both ends P2 and P4 of the first connection part 161 are connected to the first electrode K1 of each LED chip 2A, 2B, and 2C and the first pad 61 of the TFT part, and the second electrode K2 Both ends P1 and P3 of the second connection unit 162 may be connected to the second pad 63 of the TFT unit. The first and second connection electrodes 57 and 59 may be formed on the upper surface of the support member 1 . As another example, the resin member 151 and the adhesive layer B10 may be disposed in a region from which the gate insulating layer 49 formed on the upper surface of the support member 1 is removed. As another example, the gate insulating layer 49 may extend on the lower surface of the resin member 151 and the adhesive layer B10 . The first and second pads 61 and 63 may include at least two or more of Ti, Ni, Pt, TiN, Mo, Al, W, Cu, Ag, and Au. The first and second pads 61 and 63 may be formed in multiple layers. Thereafter, when the LED chips for each color are mounted on the display panel, a cleaning process may be performed, and an abnormal portion such as flux may be removed through the cleaning process. At least one or both of the resin member 151 and the passivation layer 155 may be further extended on the surface of the TFT unit 50 to protect the surface of the TFT unit 50 .
도 22를 참조하면, 회로기판의 투명한 지지부재(1) 상에 복수의 LED칩(2A,2B,2C)이 배치되고, 수지부재(151)로 몰딩되고, 연결부(161,162)로 전기적으로 연결되며, 패시베이션층(155)에 의해 표면이 보호될 수 있다. 투명한 지지부재(1)의 타면(또는 하면)은 상기 LED칩들(2A,2B,2C)을 통해 방출된 광이 출사되는 면일 수 있다. 투명 커버(1A)는 상기 지지부재(1)의 타면(또는 하면)에 배치될 수 있다. 상기 투명 커버(1A)는 플라스틱 재질, 글라스 재질, 세라믹 재질, 또는 투명 절연 필름 중 적어도 하나를 포함할 수 있다. 상기 투명한 커버(1A)는 투명한 연성 재질이거나 비 연성의 재질일 수 있다. 상기 투명한 커버(1A)는 상기 지지부재(1)의 타면에 접착제층(1B)으로 부착될 수 있다. 상기 투명한 커버(1A)는 상기 지지부재(1)와 동일한 재질일 수 있다. 상기 투명한 커버(1A)는 상기 지지부재(1)와 동일한 두께이거나 상기 지지부재(1)의 두께보다 ±30㎛의 범위 차이를 가지고, 표시장치 또는 패널에 결합될 수 있다. Referring to FIG. 22 , a plurality of LED chips 2A, 2B, and 2C are disposed on a transparent support member 1 of a circuit board, molded with a resin member 151 , and electrically connected with connection parts 161 and 162 , , the surface may be protected by the passivation layer 155 . The other surface (or lower surface) of the transparent support member 1 may be a surface from which light emitted through the LED chips 2A, 2B, and 2C is emitted. The transparent cover 1A may be disposed on the other surface (or lower surface) of the support member 1 . The transparent cover 1A may include at least one of a plastic material, a glass material, a ceramic material, and a transparent insulating film. The transparent cover 1A may be made of a transparent flexible material or a non-ductile material. The transparent cover 1A may be attached to the other surface of the support member 1 with an adhesive layer 1B. The transparent cover 1A may be made of the same material as the support member 1 . The transparent cover 1A may have the same thickness as the support member 1 or have a difference of ±30 μm from the thickness of the support member 1, and may be coupled to a display device or a panel.
상기 접착제층(1B)은 상기 투명한 커버(1A)와 상기 지지부재(1)의 타면 사이에 배치될 수 있다. 상기 접착제층(1B)은 투명한 무기질 옥사이드계 재질일 수 있으며, 예컨대 투명한 몰드 또는 광학적 클리어 몰드(optically clear resin)로 형성될 수 있다. 이러한 접착제층(1B)은 광(C1,C2,C3)에 의한 변색이 줄어들 수 있다. 상기 접착제층(1B) 내에는 접착 재료, 열전도성 나노 파우더를 갖는 방열 재료 또는/및 산란 방지 재료가 포함할 수 있다. 상기 접착제층(1B)은 열 전도성의 무기 필러를 포함하거나, 탄소 재료 또는 세라믹 소재를 포함할 수 있다. 상기 접착제층(1B)은 다른 재질로서, 유기질 또는 무기질 재료의 투명한 재질일 수 있다. 상기 접착제층(1B)의 두께는 60㎛ 이하, 예컨대, 2㎛ 내지 60㎛의 범위일 수 있다. 상기 접착제층(1B)은 전 영역에서 균일한 두께로 제공될 수 있다. 상기 접착제층(1B)의 투과율은 90% 이상 예컨대, 95% 이상일 수 있다. 상기 접착제층(1B)은 Ag, Ti, Al, Mo 중 적어도 하나를 갖는 산화물 재질을 포함할 수 있다. 상기 접착제층(1B)은 다층 구조 예컨대, Ti/Al/Ti 또는 Mo/Al/Mo와 같은 다층 산화물 구조를 포함할 수 있다.The adhesive layer 1B may be disposed between the transparent cover 1A and the other surface of the support member 1 . The adhesive layer 1B may be made of a transparent inorganic oxide-based material, and may be formed of, for example, a transparent mold or an optically clear resin. Discoloration of the adhesive layer 1B due to the light C1, C2, and C3 may be reduced. The adhesive layer 1B may include an adhesive material, a heat dissipation material having thermally conductive nanopowder, and/or a scattering prevention material. The adhesive layer 1B may include a thermally conductive inorganic filler, a carbon material, or a ceramic material. The adhesive layer 1B is another material, and may be a transparent material of an organic or inorganic material. The thickness of the adhesive layer 1B may be 60 μm or less, for example, in the range of 2 μm to 60 μm. The adhesive layer 1B may be provided with a uniform thickness in the entire area. The transmittance of the adhesive layer 1B may be 90% or more, for example, 95% or more. The adhesive layer 1B may include an oxide material having at least one of Ag, Ti, Al, and Mo. The adhesive layer 1B may include a multilayer structure, for example, a multilayer oxide structure such as Ti/Al/Ti or Mo/Al/Mo.
광차단층(M1)은 투명한 지지부재(1)와 투명한 커버(1A) 사이에 배치될 수 있다. 상기 광차단층(M1)은 투명한 지지부재(1)의 하면과 투명한 커버(1A) 상면 사이에 접착될 수 있다. 상기 광차단층(M1)은 상기 접착제층(1B)과 상기 지지부재(1)의 하면 사이에 배치될 수 있다. 다른 예로서, 상기 광차단층(M1)은 상기 접착제층(1B)과 상기 투명한 커버(1A) 상면 사이에 배치될 수 있다. 상기 광차단층(M1)은 레진계 블랙 재질일 수 있으며, 내부에 차광성, 반사성 또는 흡수성의 첨가제 중 적어도 하나를 포함할 수 있다. 상기 광차단층(M1)은 고굴절성 무기 분사체를 포함할 수 있으며, 예컨대 TiO 2　졸, SrTiO 3　졸, ZnS, ZnSe, 포타슘 브로마이드, MgO, 세슘 아이오다이드, 세슘브로마이드, CaCO 3, 포스포러스 트리브로마이드, 페닐트리클로라이드, 트리크로만-4-온(Triochroman-4-one), 티오닐 브로마이드, ZnO 2, CeO 2, ITO 졸, Ta 2O 5, Ti 2O 5, Ti 2O 3, ZrO 2, Br 2, CS 2, ZrO 2-TiO 2　계 졸 및 SiO 2-Fe 2O 3계 화합물 중에서 선택된 1종 이상을 포함할 수 있다. 상기 광차단층(M1)은 광 흡수 재질, 또는 열 흡수 또는 방열 재질을 포함할 수 있다. 상기 광차단층(M1)의 두께는 광을 차단하거나 흡수할 수 있는 두께로 형성될 수 있으며, 예컨대 30㎛ 이하이거나 3㎛ 내지 30㎛의 범위일 수 있다. 또한 광차단층(M1)은 상기한 두께 및 첨가제에 의해 방열 기능을 수행할 수 있다. 상기 광차단층(M1)은 복수의 개구부(Ma,Mb,Mc)를 포함할 수 있다. 상기 각 개구부(Ma,Mb,Mc)는 각 LED칩(2A,2B,2C)와 대면할 수 있다. 상기 복수의 개구부(Ma,Mb,Mc)는 서로 이격될 수 있으며, 개구부(Ma,Mb,Mc)들 간의 간격은 인접한 LED칩 간의 간격과 동일할 수 있다. 상기 개구부(Ma,Mb,Mc) 각각의 폭(W2) 또는 길이는 상기 개구부(Ma,Mb,Mc) 각각에 대면하는 상기 LED칩의 폭 또는 길이보다 클 수 있다. 즉, 상기 개구부(Ma,Mb,Mc)는 LED칩(2A,2B,2C)로부터 방출된 광(C1,C2,C3)이 방출되는 출사 영역일 수 있다. 상기 광차단층(M1)의 개구부(Ma,Mb,Mc)에는 상기 접착제층(1B)의 일부가 형성될 수 있다. 여기서, 상기 접착제층(1B)의 최소 두께는 상기 광차단층(M1)과 투명한 커버(1A) 사이의 두께로서, 30㎛ 이하로 형성될 수 있으며, 최대 두께는 개구부(Ma,Mb,Mc)에서의 두께로서, 0.1㎛ 내지 60㎛의 범위일 수 있다. 이러한 광차단층(M1)의 개구부(Ma,Mb,Mc)를 통해 각 LED칩(2A,2B,2C)의 광들이 방출되며, 투명한 커버(1A)의 하면을 통해 서로 다른 컬러의 광들이 발광될 수 있다. 이러한 LED칩들의 구동을 제어하여, 디스플레이 제어를 수행할 수 있다. 상기 지지부재(1)의 하부에 커버(1A), 접착제층(1B) 및 광차단층(M1)을 형성하는 공정은 상기 연결부를 형성한 다음 형성하거나, 패시베이션층을 형성한 다음 형성될 수 있다. 또는 상기 지지부재(1)의 하부에 상기의 구성을 미리 형성한 다음 LED칩들을 부착하는 공정을 진행할 수 있다. The light blocking layer M1 may be disposed between the transparent support member 1 and the transparent cover 1A. The light blocking layer M1 may be adhered between the lower surface of the transparent support member 1 and the upper surface of the transparent cover 1A. The light blocking layer M1 may be disposed between the adhesive layer 1B and the lower surface of the support member 1 . As another example, the light blocking layer M1 may be disposed between the adhesive layer 1B and the upper surface of the transparent cover 1A. The light-blocking layer M1 may be made of a resin-based black material, and may include at least one of a light-blocking, reflective, and absorptive additive therein. The light blocking layer M1 may include a high refractive inorganic spray, for example, TiO 2 sol, SrTiO 3 sol, ZnS, ZnSe, potassium bromide, MgO, cesium iodide, cesium bromide, CaCO 3 , phosphorus tree. Bromide, phenyltrichloride, trichroman-4-one, thionyl bromide, ZnO 2 , CeO 2 , ITO sol, Ta 2 O 5 , Ti 2 O 5 , Ti 2 O 3 , ZrO 2 , Br 2 , CS 2 , ZrO 2 -TiO 2 sol, and SiO 2 -Fe 2 O 3 It may include at least one selected from the group consisting of compounds. The light blocking layer M1 may include a light absorbing material or a heat absorbing or heat dissipating material. The light blocking layer M1 may have a thickness capable of blocking or absorbing light, and may be, for example, 30 μm or less or a range of 3 μm to 30 μm. In addition, the light-blocking layer M1 may perform a heat dissipation function by the above-described thickness and additives. The light blocking layer M1 may include a plurality of openings Ma, Mb, and Mc. Each of the openings Ma, Mb, and Mc may face each of the LED chips 2A, 2B, and 2C. The plurality of openings Ma, Mb, and Mc may be spaced apart from each other, and an interval between the openings Ma, Mb, and Mc may be the same as an interval between adjacent LED chips. A width W2 or a length of each of the openings Ma, Mb, and Mc may be greater than a width or length of the LED chip facing each of the openings Ma, Mb, and Mc. That is, the openings Ma, Mb, and Mc may be emission regions from which the light C1, C2, and C3 emitted from the LED chips 2A, 2B, and 2C are emitted. A portion of the adhesive layer 1B may be formed in the openings Ma, Mb, and Mc of the light blocking layer M1. Here, the minimum thickness of the adhesive layer 1B is the thickness between the light blocking layer M1 and the transparent cover 1A, and may be formed to be 30 μm or less, and the maximum thickness is at the openings Ma, Mb, Mc. As a thickness of, it may be in the range of 0.1 μm to 60 μm. Lights of each LED chip 2A, 2B, and 2C are emitted through the openings Ma, Mb, and Mc of the light blocking layer M1, and lights of different colors are emitted through the lower surface of the transparent cover 1A. can By controlling the driving of these LED chips, display control can be performed. The process of forming the cover 1A, the adhesive layer 1B, and the light-blocking layer M1 under the support member 1 may be performed after forming the connection part or after forming the passivation layer. Alternatively, the process of attaching the LED chips may be performed after forming the above configuration in advance on the lower portion of the support member 1 .
도 23은 도 22의 디스플레이 패널의 다른 예로서, 지지부재(1)의 하부에 형광체층(PS1,PS2), 광차단층(M1), 접착제층(1B), 및 투명 커버(1A)를 포함할 수 있다. 상기의 구성에서 도 22과 동일한 구성은 도 22의 설명을 참조하기로 한다. 형광체층(PS1,PS2)은 광차단층(M1)의 개구부(Ma,Mb,Mb) 중 적어도 2개의 영역에 배치될 수 있으며, 투명한 커버(1A)와 지지부재(1)의 하면 사이에 배치될 수 있다. 상기 형광체층(PS1,PS2)은 접착제층(1B)과 지지부재(1)의 하면 사이에 배치될 수 있다. 상기 형광체층(PS1,PS2)은 개구부(Ma,Mb) 내부에 배치되거나, 개구부(Ma,Mb)의 상면 또는/및 하면에 배치될 수 있다. 상기 형광체층(PS1,PS2)은 상기 지지부재(1)의 하면, 또는/및 상기 투명 커버(1A)의 상면에 접착될 수 있다. 23 is another example of the display panel of FIG. 22, including phosphor layers PS1 and PS2, a light blocking layer M1, an adhesive layer 1B, and a transparent cover 1A under the support member 1 can In the above configuration, the same configuration as that of FIG. 22 will be referred to the description of FIG. 22 . The phosphor layers PS1 and PS2 may be disposed in at least two areas of the openings Ma, Mb, and Mb of the light blocking layer M1, and may be disposed between the transparent cover 1A and the lower surface of the support member 1 . can The phosphor layers PS1 and PS2 may be disposed between the adhesive layer 1B and the lower surface of the support member 1 . The phosphor layers PS1 and PS2 may be disposed inside the openings Ma and Mb, or may be disposed on upper and/or lower surfaces of the openings Ma and Mb. The phosphor layers PS1 and PS2 may be adhered to a lower surface of the support member 1 and/or an upper surface of the transparent cover 1A.
상기 형광체층(PS1,PS2)은 상기 제1 LED칩(2A)과 대면하는 영역에 제1형광체층(PS1), 및 상기 제2 LED칩(2B)과 대면하는 영역에 제2 형광체층(PS2)을 포함할 수 있다. 상기 제3 LED칩(2C)과 대면하는 영역에는 투명한 접착제층(1B)의 일부가 형성될 수 있다. 상기 제1형광체층(PS1)은 광차단층(M1)의 제1개구부(Ma)에 배치될 수 있고, 제2형광체층(PS2)은 상기 광차단층(M1)의 제2개구부(Mb)에 배치될 수 있다. 동일한 컬러를 발광하는 LED칩(2C)이 예컨대, 청색 광을 발광할 경우, 상기 제1 형광체층(PS1)은 청색 광을 파장 변환하여 적색 광을 발광하며, 제2 형광체층(PS2)은 청색 광을 파장 변환하여 녹색 광을 발광할 수 있다. 이에 따라 제1 내지 제3 개구부(Ma,Mb,Mc)를 통해 적색, 녹색 및 청색의 광이 발광될 수 있다. 다른 예로서, LED칩(2C)이 자외 광을 발광할 경우, 제3 개구부(Mc)에 청색 형광체층을 더 배치할 수 있다. 이러한 LED칩에서 발광되는 광에 따라 형광체층을 이용하여 다른 컬러로 파장 변환하여 발광할 수 있다. 따라서, 디스플레이 패널 또는 장치에서 적어도 삼색 또는 삼색 이상의 다색 광을 발광하는 픽셀 영역을 각각 구현할 수 있다. 여기서, LED칩(2C)이 동일 컬러를 발광할 경우, 전체 LED칩을 최소 한 번에 지지부재(1)의 표면에 부착시켜 줄 수 있어, 공정은 단순화될 수 있다. 예컨대, 단위 픽셀이 서브픽셀이 적색, 녹색, 청색의 광과 같이 R/G/B로 이루어지거나, R/G/B/W(White) 등으로 구현할 수 있으며, 이에 대해 한정하지는 않는다. The phosphor layers PS1 and PS2 include a first phosphor layer PS1 in an area facing the first LED chip 2A, and a second phosphor layer PS2 in an area facing the second LED chip 2B. ) may be included. A portion of the transparent adhesive layer 1B may be formed in a region facing the third LED chip 2C. The first phosphor layer PS1 may be disposed in the first opening Ma of the light blocking layer M1 , and the second phosphor layer PS2 may be disposed in the second opening Mb of the light blocking layer M1 . can be When the LED chip 2C emitting the same color emits blue light, for example, the first phosphor layer PS1 converts blue light to emit red light, and the second phosphor layer PS2 emits blue light. By converting the wavelength of light, green light may be emitted. Accordingly, red, green, and blue light may be emitted through the first to third openings Ma, Mb, and Mc. As another example, when the LED chip 2C emits ultraviolet light, a blue phosphor layer may be further disposed in the third opening Mc. Depending on the light emitted from the LED chip, the wavelength may be converted to another color using a phosphor layer to emit light. Accordingly, a pixel area emitting at least three colors or multi-color light of three or more colors may be implemented in the display panel or device, respectively. Here, when the LED chip 2C emits the same color, the entire LED chip can be attached to the surface of the support member 1 at least once, so that the process can be simplified. For example, the unit pixel may be implemented in R/G/B like red, green, and blue light, or R/G/B/W (white) as sub-pixels, but the present invention is not limited thereto.
도 24 내지 도 28은 도 23의 디스플레이 패널의 변형 예들이다. 24 to 28 are modified examples of the display panel of FIG. 23 .
도 24와 같이, 제1형광체층(PS1)은 상기 제1개구부(Ma)와 대면하는 투명한 접착층(B10)과 투명한 지지부재(1) 사이에 배치될 수 있다. 이러한 제1형광체층(PS1)은 제1개구부(Ma) 상의 LED칩(2C)의 하부에서 수지부재(151)와 접촉될 수 있다. 제1개구부(Ma) 상에 위치한 상기 제1형광체층(PS1)의 폭 또는 상면 면적은 상기 LED칩(2C)에 접착된 접착층(B10)의 폭 또는 하면 면적보다 작을 수 있다. 제2형광체층(PS2)은 상기 제2개구부(Mb)와 대면하는 투명한 접착층(B10)과 투명한 지지부재(1) 사이에 배치될 수 있다. 이러한 제2형광체층(PS2)은 제2개구부(Mb) 상에 위치한 LED칩(2C)의 하부에서 수지부재(151)와 접촉될 수 있다. 제2개구부(Mb) 상에 위치한 상기 제1형광체층(PS2)의 폭 또는 상면 면적은 상기 제2개구부(Mb) 상의 LED칩(2C)에 접착된 접착층(B10)의 폭 또는 하면 면적보다 작을 수 있다. 여기서, 제3개구부(Mc) 상에 위치한 LED칩(2C)는 접착층(B10)으로 지지부재(1)에 접착될 수 있다. 상기 광차단층(M1)의 각 개구부(Ma,Mb,Mc)는 접착제층(1B)의 일부가 배치될 수 있다.24 , the first phosphor layer PS1 may be disposed between the transparent adhesive layer B10 facing the first opening Ma and the transparent support member 1 . The first phosphor layer PS1 may be in contact with the resin member 151 under the LED chip 2C on the first opening Ma. The width or upper surface area of the first phosphor layer PS1 positioned on the first opening Ma may be smaller than the width or lower surface area of the adhesive layer B10 attached to the LED chip 2C. The second phosphor layer PS2 may be disposed between the transparent adhesive layer B10 facing the second opening Mb and the transparent support member 1 . The second phosphor layer PS2 may be in contact with the resin member 151 under the LED chip 2C positioned on the second opening Mb. The width or upper surface area of the first phosphor layer PS2 positioned on the second opening Mb may be smaller than the width or lower surface area of the adhesive layer B10 bonded to the LED chip 2C on the second opening Mb. can Here, the LED chip 2C positioned on the third opening Mc may be adhered to the support member 1 with an adhesive layer B10 . A portion of the adhesive layer 1B may be disposed in each of the openings Ma, Mb, and Mc of the light blocking layer M1.
도 25와 같이, 제1 및 제2형광체층(PS1,PS2)은 접착제층(1B)와 투명 커버(1A) 사이에 각각 접착될 수 있다. 제1 및 제2형광체층(PS1,PS2) 각각은 광차단층(M1)의 제1 및 제2개구부(Ma,Mb)와 대응되는 것으로서, 제1 및 제2개구부(Ma,Mb)의 폭 또는 면적보다 큰 폭 또는 면적으로 제공될 수 있다. 이에 따라 접착제층(1B)이 접착된 형광체층(PS1,PS2)의 외측으로 빛샘이 발생되는 것을 차단할 수 있다. 도 26과 같이, 제1 및 제2형광체층(PS1,PS2)은 접착제층(1B)와 투명한 지지부재(1) 사이에 각각 접착될 수 있다. 광차단층(M1)은 접착제층(1B)과 투명 커버(1A) 사이에 배치될 수 있다. 상기 제1 및 제2형광체층(PS1,PS2) 각각은 광차단층(M1)의 제1 및 제2개구부(Ma,Mb)의 상부에 이격되거나, 부분적으로 광차단층(M1)에 접촉될 수 있다. 상기 제1 및 제2형광체층(PS1,PS2) 각각은 상기 제1 및 제2개구부(Ma,Mb)의 폭 또는 면적보다 큰 폭 또는 면적으로 제공될 수 있다. 이에 따라 접착제층(1B)이 접착된 형광체층(PS1,PS2)의 외측과 개구부(Ma,Mb)를 통해 빛샘이 발생되는 것을 차단할 수 있다. 도 27과 같이, 투명한 지지부재(1)의 하면에 접착제층(1B)/개구부(Ma,Mb,Mc)를 갖는 광차단층(M1)이 배치되며, 상기 광차단층(M1)의 하부에 투명 커버(1A)가 결합될 수 있다. 상기 개구부(Ma,Mb,Mc)는 투명 커버(1A)의 상면에서 각 LED칩(1C)와 대응되는 영역에 배치될 수 있다. 제1개구부(Ma) 내에는 제1형광체층(PS1)이 배치되며, 제2개구부(Mb)에는 제2형광체층(PS2)가 배치될 수 있다. 이 경우, 제3개구부(Mc)에는 접착제층(1B)의 일부가 연장되어, 투명 커버(1A)와 접착될 수 있다. 도 28과 같이, 접착제층 없이 광차단층(M1)으로 투명한 지지부재(1)와 투명 커버(1A)를 접착시켜 줄 수 있다. 상기 광차단층(M1)은 양면 접착 기능을 갖거나, 압착되어 접착될 수 있다. 이때 광차단층(M1)은 각 LED칩(2C)에 대응되는 복수의 개구부(Ma,Mb,Mc)를 갖고, 제1개구부(Ma)에는 제1형광체층(PS1)이 배치되며, 제2개구부(Mb)에는 제2형광체층(PS2)이 배치될 수 있다. 제2개구부(Mc)에는 투명한 레진부(M5)가 배치되어, 광을 투과시켜 줄 수 있다. 25 , the first and second phosphor layers PS1 and PS2 may be respectively adhered between the adhesive layer 1B and the transparent cover 1A. Each of the first and second phosphor layers PS1 and PS2 corresponds to the first and second openings Ma and Mb of the light blocking layer M1, and the widths of the first and second openings Ma and Mb or It may be provided with a width or an area greater than the area. Accordingly, it is possible to block light leakage to the outside of the phosphor layers PS1 and PS2 to which the adhesive layer 1B is adhered. 26 , the first and second phosphor layers PS1 and PS2 may be respectively adhered between the adhesive layer 1B and the transparent support member 1 . The light blocking layer M1 may be disposed between the adhesive layer 1B and the transparent cover 1A. Each of the first and second phosphor layers PS1 and PS2 may be spaced apart from the upper portions of the first and second openings Ma and Mb of the light blocking layer M1, or may partially contact the light blocking layer M1. . Each of the first and second phosphor layers PS1 and PS2 may have a width or area greater than that of the first and second openings Ma and Mb. Accordingly, it is possible to block light leakage through the outside and the openings Ma and Mb of the phosphor layers PS1 and PS2 to which the adhesive layer 1B is attached. 27, a light blocking layer M1 having an adhesive layer 1B/openings Ma, Mb, Mc) is disposed on the lower surface of the transparent support member 1, and a transparent cover is provided under the light blocking layer M1. (1A) can be combined. The openings Ma, Mb, and Mc may be disposed in regions corresponding to the respective LED chips 1C on the upper surface of the transparent cover 1A. A first phosphor layer PS1 may be disposed in the first opening Ma, and a second phosphor layer PS2 may be disposed in the second opening Mb. In this case, a portion of the adhesive layer 1B may extend to the third opening Mc to be adhered to the transparent cover 1A. As shown in FIG. 28 , the transparent support member 1 and the transparent cover 1A may be adhered to each other with the light blocking layer M1 without an adhesive layer. The light-blocking layer M1 may have a double-sided adhesive function or may be adhered by pressing. At this time, the light blocking layer M1 has a plurality of openings Ma, Mb, Mc corresponding to each LED chip 2C, and the first phosphor layer PS1 is disposed in the first opening Ma, and the second opening A second phosphor layer PS2 may be disposed in (Mb). A transparent resin part M5 may be disposed in the second opening Mc to transmit light.
이와 같이, 투명한 지지부재(1)와 투명커버(1A) 사이에 개구부(Ma,Mb,Mc)를 갖는 광차단층(M1)과 형광체층(PS1,PS2)들 배치하여, 선택적인 파장 변환을 통해 픽섹 영역에 필요한 광들을 방출할 수 있다. 만약, 투명한 지지부재(1)에 광차단층(M1)과 형광체층(PS1,PS2)을 코팅할 할 경우, TFT기판에 코팅불량이 생기면 불량단가가 클 수 있다. 이에 따라 투명 커버(1A)에 형광체층(PS1,PS2)와 광차단층(M1)를 형성하여, 코팅 불량이 발생될 경우, 투명 커버만 교체할 수 있다. 또한 투명 커버의 교체나 수리(Rework)가 가능하여 경제적일 수 있다. In this way, the light blocking layer M1 having the openings Ma, Mb, Mc and the phosphor layers PS1 and PS2 are disposed between the transparent support member 1 and the transparent cover 1A, and through selective wavelength conversion Lights necessary for the pixel area may be emitted. If the transparent support member 1 is coated with the light blocking layer M1 and the phosphor layers PS1 and PS2, if the TFT substrate has poor coating, the unit cost of failure may be high. Accordingly, when the phosphor layers PS1 and PS2 and the light blocking layer M1 are formed on the transparent cover 1A, and a coating defect occurs, only the transparent cover can be replaced. In addition, since the transparent cover can be replaced or reworked, it can be economical.
도 29 및 도 30을 참조하면, 투명한 커버(1A)의 하면에 렌즈 어레이(Rn)를 포함할 수 있다. 상기 렌즈 어레이(Rn)의 각 렌즈 형상은 볼록한 반구 형상으로 형성될 수 있으며, 각 LED칩(2A,2B,2C)의 하면 또는/및 형광체층의 하면에 복수개가 배열될 수 있다. 상기 렌즈 어레이(Rn)의 각 렌즈 크기는 너비(w1) 또는/및 높이(h1)가 나노미터(Nanometer) 크기로서, 500nm 이하 예컨대, 100nm 내지 500nm의 범위로 형성될 수 있다. 상기 각 렌즈의 너비(w1) 또는 높이(h1)은 동일하거나 다를 수 있다. 상기 투명한 커버(1A)의 렌즈 어레이(Rn)는 입사되는 광의 투과율을 높여줄 수 있고 광 감도와 광 효율을 증가시켜 줄 수 있다. 상기 투명한 커버(1A)의 렌즈 어레이(Rn)는 하면 전체에 형성될 수 있어, 비반사 기능과 햇빛 차단 기능을 제공할 수 있다. 도 36과 같이 투명한 커버(1A)의 하면이 플랫한 면인 경우와 렌즈(lens)를 형성한 경우, 렌즈 사이즈에 따른 파장별 투과율을 비교한 그래프이다. 이러한 그래프와 같이, 나노 사이즈인 경우, 광 투과율이 95% 이상임을 알 수 있다. 상기 투명한 커버(1A)의 렌즈 어레이(Rn)는 각 LED칩의 하면에 대응되는 영역에 렌즈 크기를 다르게 제공하여, 투과율을 더 높여줄 수 있다. 이러한 렌즈 어레이(Rn)는 습식 에칭 공정을 통해 형성될 수 있다. 29 and 30 , a lens array Rn may be included on the lower surface of the transparent cover 1A. Each lens shape of the lens array Rn may be formed in a convex hemispherical shape, and a plurality of lenses may be arranged on the lower surface of each of the LED chips 2A, 2B, and 2C and/or the lower surface of the phosphor layer. Each lens of the lens array Rn has a width w1 and/or a height h1 of nanometer size, and may be formed to be 500 nm or less, for example, 100 nm to 500 nm. The width w1 or height h1 of each lens may be the same or different. The lens array Rn of the transparent cover 1A may increase the transmittance of incident light and may increase light sensitivity and light efficiency. The lens array Rn of the transparent cover 1A may be formed on the entire lower surface, thereby providing an anti-reflective function and a sun blocking function. As shown in FIG. 36, when the lower surface of the transparent cover 1A is a flat surface and when a lens is formed, it is a graph comparing transmittance for each wavelength according to the lens size. As shown in this graph, it can be seen that, in the case of the nano size, the light transmittance is 95% or more. The lens array Rn of the transparent cover 1A may provide different lens sizes in the area corresponding to the lower surface of each LED chip, thereby further increasing the transmittance. The lens array Rn may be formed through a wet etching process.
도 31과 같이, 상기 패시베이션층(155)이 형성되면, LED칩(2A,2B,2C)들이 사이의 경계영역(P10)에는 금속층(192) 및 절연부재(194)를 형성한 다음, 절연부재(194)의 일부를 오픈시켜, 도전부(196)를 형성하게 된다. 이때 상기 도전부(196)는 이방성 도전 필름(ACF)을 포함할 수 있고, 상기 도전부(196)는 구동 기판(190)과 연결될 수 있다. 이러한 구동기판(190)은 각 LED칩(2A,2B,2C) 및 TFT부(도 21의 50)에 선택적으로 연결될 수 있고, 드라이버 IC와 같은 부품과 연결될 수 있다. 도 32와 같이, 상기 도전부(196)는 복수개가 서로 이격될 수 있고, 접촉부(192)를 통해 다른 배선이나 패턴에 연결될 수 있다. 상기 절연부(194)는 차광 재질, 반사 재질 또는 흡수 재질의 층일 수 있다. 구동 기판(190)은 수지 재질의 PCB 또는 FPCB를 포함할 수 있다. 상기 지지부재(1)의 상부에는 방열부재가 더 배치되어, 방열을 효과적으로 수행할 수 있다. 여기서, 상기 연결부의 형성 공정은 수지부재(151)를 형성한 후에 진행하지 않고, 상기 절연부(194)를 형성한 다음, 한 번의 공정으로 구동 기판을 위한 연결부와 접촉부(192)와 연결부(161,162)를 형성할 수 있다. 31, when the passivation layer 155 is formed, the metal layer 192 and the insulating member 194 are formed in the boundary region P10 between the LED chips 2A, 2B, and 2C, and then the insulating member A part of 194 is opened to form a conductive portion 196 . In this case, the conductive part 196 may include an anisotropic conductive film (ACF), and the conductive part 196 may be connected to the driving substrate 190 . The driving substrate 190 may be selectively connected to each of the LED chips 2A, 2B, and 2C and the TFT unit 50 in FIG. 21 , and may be connected to a component such as a driver IC. 32 , a plurality of the conductive parts 196 may be spaced apart from each other, and may be connected to other wirings or patterns through the contact parts 192 . The insulating part 194 may be a layer of a light blocking material, a reflective material, or an absorbing material. The driving board 190 may include a PCB or FPCB made of a resin material. A heat dissipation member is further disposed on the upper portion of the support member 1 to effectively dissipate heat. Here, the process of forming the connection part does not proceed after forming the resin member 151, but after forming the insulating part 194, the connection part, the contact part 192, and the connection parts 161 and 162 for the driving board in one process. ) can be formed.
도 33의 (A)와 같이, 상기 패시베이션층(155) 및 수지부재(151) 중 적어도 하나는 지지부재(1)의 측면(Sc)에 인접한 상면까지 연장된 연장부(E10)를 포함할 수 있다. 이에 따라 상기 연장부(E10)은 에지 패턴(31)을 보호할 수 있다. 또한 도 33의 (B)와 같이, 상기 지지부재(1)의 외곽 라인이 재 커팅될 때, 레이저 커팅 공정에 의해 측면 코팅층(C11)이 형성될 수 있으며, 상기 측면 코팅층(C11)은 상기 연장부(E10)과 접촉될 수 있다. 상기 에지 패턴(31)에서의 측면(Sc)까지의 간격(D11)은 15㎛ 이하 예컨대, 0.5㎛ 내지 15㎛ 사이의 범위일 수 있어, 에지 패턴(31)을 상기 연장부(E10)을 통해 보호할 수 있다. As shown in (A) of Figure 33, at least one of the passivation layer 155 and the resin member 151 may include an extension portion E10 extending to the upper surface adjacent to the side surface Sc of the support member 1 (E10). have. Accordingly, the extension portion E10 may protect the edge pattern 31 . Also, as shown in (B) of FIG. 33 , when the outer line of the support member 1 is re-cut, a side coating layer C11 may be formed by a laser cutting process, and the side coating layer C11 may extend the extension. It may be in contact with the portion E10. The distance D11 from the edge pattern 31 to the side surface Sc may be 15 µm or less, for example, in the range of 0.5 µm to 15 µm, so that the edge pattern 31 is passed through the extension part E10. can protect
도 34의 (A)와 같이, LED칩(2A,2B,2C)들 중에서 어느 하나의 불량(NG) LED칩(예, 2A)가 발생된 경우, 동일한 종류의 뉴 LED칩(2D)으로 교체할 수 있다. 이때 포인트 레이저 공정을 통해 불량 LED칩을 노출시키고 상기 접착층(B10)을 녹인 다음, 픽업을 통해 제거하고, 새로운 LED칩(2D)로 탑재하게 된다. 이때 새로운 LED칩(2D)에는 상기의 공정에 의해 하면에 접착층이 배치되어 있으므로, 상기 지지부재(1) 상에 접착될 수 있다. 이후 상기에 개시된 공정을 통해 패키징하고 전기적으로 연결시켜 줄 수 있다. 이러한 교체 공정은 제3 불량 LED칩 검사 및 교체 공정일 수 있다. 도 34의 (B)와 같이, 하나의 픽셀 영역 내에서 LED칩의 불량(NG)이 발생되면, LED칩들이 배치된 영역 주변에 더미 영역(A11,A12,A13)이 더 형성된 경우, 상기 더미 영역(A11,A12,A13)의 일부를 개방시키고, 상기의 공정과 같이 패키징 및 전기적인 연결 공정을 수행하여, 불량 LED칩을 새로운(NEW) LED칩(2D)로 대체할 수 있다. 이러한 교체 공정은 제3 불량 LED칩 검사 및 교체 공정일 수 있다. 상기 불량 LED칩의 제거 후 배선 공정은 상기에 개시된 전도성 잉크를 이용한 웻 공정을 통해 부분 연결부를 형성할 수 있다. 이때 감광성 전도성 잉크로 연결부를 형성해 줌으로써, 국부적인 영역에서 불량 LED칩이 제거된 영역에서 노광, 현상 및 열 처리 공정을 통해 국부적으로 연결부를 형성할 수 있다. 이때의 연결부의 폭은 조절될 수 있다. 도 35와 같이, 각 픽셀 영역(2)은 한 쌍의 제1 내지 제3LED칩(2A,2B,2C)을 갖고, 화소 경계영역(P11)들로 구분되며 지지부재(1)의 하부를 통해 광(L1)을 방출할 수 있다. 도 36과 같이, 각 픽셀 영역(2)에는 두 쌍의 제1 내지 제3LED칩(2A,2B,2C)의 그룹 또는 더미 LED칩 영역(즉, 더미 패드들)(22)이 더 배치될 수 있다.As shown in (A) of Figure 34, when any one of the LED chips (2A, 2B, 2C) is defective (NG) LED chip (eg, 2A) is generated, replaced with a new LED chip (2D) of the same type can do. At this time, the defective LED chip is exposed through a point laser process, the adhesive layer B10 is melted, and then removed through a pickup and mounted as a new LED chip 2D. At this time, since the adhesive layer is disposed on the lower surface of the new LED chip 2D by the above process, it can be adhered to the support member 1 . Thereafter, it may be packaged and electrically connected through the process disclosed above. This replacement process may be a third defective LED chip inspection and replacement process. As shown in (B) of FIG. 34 , when a defect NG of the LED chip occurs in one pixel area, when the dummy areas A11, A12, and A13 are further formed around the area where the LED chips are disposed, the dummy area A portion of the areas A11 , A12 , and A13 may be opened, and packaging and electrical connection processes may be performed as described above to replace a defective LED chip with a new (NEW) LED chip 2D. This replacement process may be a third defective LED chip inspection and replacement process. After the defective LED chip is removed, the wiring process may form a partial connection part through the wet process using the conductive ink disclosed above. At this time, by forming the connection part with the photosensitive conductive ink, the connection part can be locally formed through exposure, development, and heat treatment processes in the area where the defective LED chip has been removed in the local area. At this time, the width of the connection part can be adjusted. 35 , each pixel region 2 has a pair of first to third LED chips 2A, 2B, and 2C, and is divided into pixel boundary regions P11 through the lower portion of the support member 1 . Light L1 may be emitted. 36 , a group of two pairs of first to third LED chips 2A, 2B, and 2C or dummy LED chip areas (ie, dummy pads) 22 may be further disposed in each pixel area 2 , as shown in FIG. 36 . have.
상기와 같이, 본 발명의 바람직한 실시 예를 참조하여 설명하였지만 해당 기술 분야의 숙련된 당업자라면 하기의 특허청구범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.As described above, although described with reference to the preferred embodiment of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that it can be done.

Claims (20)

  1. 투명한 지지부재;transparent support member;
    상기 지지부재의 상면에 배치되며 패드들을 갖는 박막트랜지터(TFT)부;a thin film transistor (TFT) unit disposed on the upper surface of the support member and having pads;
    상기 지지부재의 상면에 배치되며 상부에 전극들을 갖는 복수의 LED칩;a plurality of LED chips disposed on the upper surface of the support member and having electrodes thereon;
    상기 지지부재와 상기 복수의 LED칩 각각을 접착하는 투명한 접착층;a transparent adhesive layer for bonding the support member and each of the plurality of LED chips;
    상기 복수의 LED칩을 덮는 수지부재; 및a resin member covering the plurality of LED chips; and
    상기 수지부재 상에 배치되며 상기 전극과 패드를 연결하는 복수의 연결부를 포함하며,It is disposed on the resin member and includes a plurality of connection parts for connecting the electrode and the pad,
    상기 복수의 LED칩은 서로 다른 컬러를 발광하는 제1 LED칩 내지 제3LED칩을 갖는 픽섹 영역을 각각 형성하며, The plurality of LED chips each form a pixel region having a first LED chip to a third LED chip emitting different colors,
    상기 복수의 LED칩으로부터 방출된 광은 상기 지지부재를 통해 상기 지지부재의 하면을 통해 방출되는 디스플레이 패널.The light emitted from the plurality of LED chips is emitted through a lower surface of the support member through the support member.
  2. 제1항에 있어서, 상기 지지부재의 하면에 상기 LED칩과 대면하는 영역 각각이 오픈된 복수의 개구부를 갖는 광차단층을 포함하며,According to claim 1, wherein the support member comprises a light blocking layer having a plurality of openings, each of the area facing the LED chip is opened on a lower surface,
    상기 LED칩들 각각에서 방출된 광은 상기 지지부재를 거쳐 상기 개구부들 각각으로 방출되는 디스플레이 패널. The light emitted from each of the LED chips is emitted to each of the openings through the support member.
  3. 제2항에 있어서, 상기 복수의 연결부는 감광성 도전 재질을 포함하는 디스플레이 패널.The display panel of claim 2 , wherein the plurality of connection parts include a photosensitive conductive material.
  4. 제2항에 있어서, 상기 지지부재의 하면에 투명 커버; 및According to claim 2, Transparent cover on the lower surface of the support member; and
    상기 투명 커버와 상기 지지부재의 하면 사이에 투명한 접착제층을 포함하는 디스플레이 패널.A display panel comprising a transparent adhesive layer between the transparent cover and the lower surface of the support member.
  5. 제4항에 있어서, 상기 복수의 LED칩은 픽셀 영역을 형성하기 위해 적색, 녹색 및 청색의 광을 발광하며, 5. The method of claim 4, wherein the plurality of LED chips emit red, green, and blue light to form a pixel area,
    상기 개구부들 각각에는 상기 접착제층의 일부가 배치되는 디스플레이 패널.A display panel in which a portion of the adhesive layer is disposed in each of the openings.
  6. 제4항에 있어서, 상기 복수의 LED칩은 청색 컬러의 광을 발광하며,The method of claim 4, wherein the plurality of LED chips emit light of a blue color,
    픽셀 영역을 형성하는 복수의 LED칩 중 제1 LED칩에 대면하는 제1개구부에 제1형광체층; 및 상기 복수의 LED칩 중 제1 LED칩에 대면하는 제2개구부에 제2형광체층; 및 상기 복수의 LED칩 중 제3 LED칩에 대면하는 제3개구부에 투명한 층이 형성되며,a first phosphor layer in a first opening facing the first LED chip among the plurality of LED chips forming the pixel region; and a second phosphor layer in a second opening facing the first LED chip among the plurality of LED chips. and a transparent layer is formed in the third opening facing the third LED chip among the plurality of LED chips,
    상기 청색 컬러의 광과 제1 및 제2형광체층에 의해 파장 변환된 광들을 갖고 단위 픽셀을 형성하는 디스플레이 패널. A display panel comprising the blue color light and the light wavelength-converted by the first and second phosphor layers to form a unit pixel.
  7. 제4항 내지 제6항 중 어느 한 항에 있어서, 상기 광차단층은 상기 지지부재의 하면과 상기 접착제층 사이에 접착되는 디스플레이 패널.The display panel according to any one of claims 4 to 6, wherein the light blocking layer is adhered between a lower surface of the support member and the adhesive layer.
  8. 제4항 내지 제6항 중 어느 한 항에 있어서, 상기 광차단층은 상기 접착제층과 상기 투명 커버의 상면 사이에 접착되는 디스플레이 패널.The display panel according to any one of claims 4 to 6, wherein the light blocking layer is adhered between the adhesive layer and an upper surface of the transparent cover.
  9. 제1항 내지 제6항 중 어느 한 항에 있어서, 상기 복수의 연결부, 상기 수지부재 및 상기 TFT부의 상부를 보호하는 패시베이션층을 포함하는 디스플레이 패널.The display panel according to any one of claims 1 to 6, comprising a passivation layer for protecting the plurality of connection parts, the resin member, and the upper part of the TFT part.
  10. 제2항 내지 제5항 중 어느 한 항에 있어서, 상기 수지부재 및 상기 광차단층은 광 또는 열 흡수 재질을 포함하는 디스플레이 패널.The display panel according to any one of claims 2 to 5, wherein the resin member and the light blocking layer include a light or heat absorbing material.
  11. 제9항에 있어서, 상기 접착층은 상기 LED칩들 각각에 접착되며, 열 전도성의 무기 필러를 포함하며, The method of claim 9, wherein the adhesive layer is adhered to each of the LED chips, and includes a thermally conductive inorganic filler,
    상기 접착층은 상기 지지부재의 상면에 접착되며, The adhesive layer is adhered to the upper surface of the support member,
    상기 수지부재는 상기 LED칩들 각각의 측면 및 상면, 상기 접착층의 외면에 접착되는 디스플레이 패널.The resin member is adhered to the side and top surfaces of each of the LED chips, and to the outer surface of the adhesive layer.
  12. 제11항에 있어서, 상기 접착층의 두께는 0.1㎛ 내지 50㎛의 범위이며, The method according to claim 11, wherein the thickness of the adhesive layer is in the range of 0.1 μm to 50 μm,
    상기 투명 커버와 상기 지지부재는 글라스 재질인 디스플레이 패널.The transparent cover and the support member is a display panel made of a glass material.
  13. 제9항에 있어서, 상기 LED칩들 각각은 제1전극 및 제2전극을 포함하며,The method of claim 9, wherein each of the LED chips comprises a first electrode and a second electrode,
    상기 TFT부는 각 LED칩의 주변에 제1패드 및 제2패드를 포함하며,The TFT unit includes a first pad and a second pad on the periphery of each LED chip,
    상기 연결부는 상기 수지부재 상에서 제1전극과 상기 제1패드 사이에 연결된 제1연결부, 및 상기 제2전극과 상기 제2패드 사이에 연결된 제2연결부를 포함하며,The connection part includes a first connection part connected between a first electrode and the first pad on the resin member, and a second connection part connected between the second electrode and the second pad,
    상기 제1 및 제2연결부는 감광성 도전재질을 포함하는 디스플레이 패널. The first and second connectors include a photosensitive conductive material.
  14. 도전성 캐리어의 하면에 상부 전극들이 배치된 복수의 LED칩을 픽업하는 제1단계;A first step of picking up a plurality of LED chips having upper electrodes disposed on the lower surface of the conductive carrier;
    상기 도전성 캐리어를 투명한 접착층이 형성된 보조기판 상에 대향시키고, 상기 LED칩들의 하면 각각에 상기 접착층을 스템핑하는 제2단계; a second step of facing the conductive carrier on an auxiliary substrate on which a transparent adhesive layer is formed, and stamping the adhesive layer on each of the lower surfaces of the LED chips;
    상기 LED칩들 각각에 상기 접착층이 스템핑되면, TFT부를 갖는 회로기판 상에 도전성 캐리어를 위치시키고, 상기 LED칩들을 회로기판의 투명한 지지부재의 상면에 접착층으로 부착시키는 제3단계; 및a third step of, when the adhesive layer is stamped on each of the LED chips, placing a conductive carrier on a circuit board having a TFT part, and attaching the LED chips to an upper surface of a transparent support member of the circuit board with an adhesive layer; and
    상기 지지부재의 하면에 LED칩과 대면하는 영역이 오픈된 복수의 개구부를 갖는 광차단층을 형성하는 제4단계를 포함하며,a fourth step of forming a light blocking layer having a plurality of openings in which regions facing the LED chip are opened on the lower surface of the support member;
    상기 LED칩들 각각에서 방출된 광은 상기 지지부재를 거쳐 상기 개구부들 각각으로 방출되는, 디스플레이 패널의 제조방법.Light emitted from each of the LED chips is emitted to each of the openings through the support member.
  15. 제14항에 있어서, 상기 회로기판 상부에 수지부재를 형성하여 상기 복수의 LED칩 및 TFT부의 패드를 밀봉하는 단계;15. The method of claim 14, further comprising: sealing the plurality of LED chips and the TFT pads by forming a resin member on the circuit board;
    상기 복수의 LED칩의 상부에 배치된 전극들과 상기 TFT부의 패드들을 오픈시키는 단계; 및opening electrodes disposed on the plurality of LED chips and pads of the TFT unit; and
    상기 수지부재 상에 감광성 도전층을 형성하는 단계;forming a photosensitive conductive layer on the resin member;
    상기 감광성 도전층 상에 연결부 영역을 제외한 영역에 대해 노광하고 현상한 후 상기 패드와 전극들 각각에 연결된 감광성 재질의 연결부들을 각각 형성하는 단계를 포함하는, 디스플레이 패널의 제조방법.and forming connection parts made of a photosensitive material connected to each of the pad and the electrodes, respectively, after exposing and developing the region on the photosensitive conductive layer except for the connection part region.
  16. 제15항에 있어서, 상기 수지부재, 및 상기 연결부들 상에 패시베이션층을 형성하는 단계를 포함하며, 16. The method of claim 15, comprising the step of forming a passivation layer on the resin member, and the connection parts,
    상기 수지부재 및 광차단층은 광 또는 열 흡수 재질이며,The resin member and the light blocking layer are light or heat absorbing materials,
    상기 수지부재는 상기 접착층과 LED칩의 측면에 접착되는, 디스플레이 패널의 제조방법.The resin member is adhered to the side surface of the adhesive layer and the LED chip, a method of manufacturing a display panel.
  17. 제14항 내지 제16항 중 어느 한 항에 있어서, 상기 지지부재의 하면에 투명 커버를 투명한 재질의 접착제층으로 접착시키는 단계를 포함하며,The method according to any one of claims 14 to 16, comprising adhering a transparent cover to a lower surface of the support member with an adhesive layer made of a transparent material,
    상기 접착제층은 상기 투명 커버의 상면, 상기 지지부재의 하면, 및 상기 광차단층의 상면 또는 하면 중 적어도 하나에 접착되는, 디스플레이 패널의 제조방법.The adhesive layer is adhered to at least one of an upper surface of the transparent cover, a lower surface of the support member, and an upper surface or a lower surface of the light blocking layer.
  18. 제17항에 있어서, 상기 복수의 LED칩은 픽셀 영역을 형성하기 위해 적색, 녹색 및 청색의 광을 발광하며, 18. The method of claim 17, wherein the plurality of LED chips emit red, green and blue light to form a pixel area,
    상기 개구부들 각각에는 상기 접착제층의 일부가 배치되는 디스플레이 패널의 제조방법.A method of manufacturing a display panel in which a portion of the adhesive layer is disposed in each of the openings.
  19. 제17항에 있어서, 상기 복수의 LED칩은 청색 컬러의 광을 발광하며,The method of claim 17, wherein the plurality of LED chips emit light of a blue color,
    픽셀 영역을 형성하는 복수의 LED칩 중 제1 LED칩에 대면하는 제1개구부에 제1형광체층; 및 상기 복수의 LED칩 중 제1 LED칩에 대면하는 제2개구부에 제2형광체층; 및 상기 복수의 LED칩 중 제3 LED칩에 대면하는 제3개구부에 투명한 층이 형성되며,a first phosphor layer in a first opening facing the first LED chip among the plurality of LED chips forming the pixel region; and a second phosphor layer in a second opening facing the first LED chip among the plurality of LED chips. and a transparent layer is formed in the third opening facing the third LED chip among the plurality of LED chips,
    상기 청색 컬러의 광과 제1 및 제2형광체층에 의해 파장 변환된 광들을 갖고 단위 픽셀을 형성하는 디스플레이 패널의 제조방법. A method of manufacturing a display panel to form a unit pixel by using the blue color light and the wavelength-converted light by the first and second phosphor layers.
  20. 제14항 내지 제16항 중 어느 한 항에 있어서, 상기 복수의 LED칩을 픽업하기 전 및 픽업한 다음에 불량 LED칩을 검사하여 교체하는 디스플레이 패널의 제조방법.The method according to any one of claims 14 to 16, wherein defective LED chips are inspected and replaced before and after picking up the plurality of LED chips.
PCT/KR2020/019421 2019-12-31 2020-12-30 Display panel, display device, and method for manufacturing same WO2021137625A1 (en)

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