WO2021135426A1 - 译码方法、译码器和译码装置 - Google Patents

译码方法、译码器和译码装置 Download PDF

Info

Publication number
WO2021135426A1
WO2021135426A1 PCT/CN2020/117022 CN2020117022W WO2021135426A1 WO 2021135426 A1 WO2021135426 A1 WO 2021135426A1 CN 2020117022 W CN2020117022 W CN 2020117022W WO 2021135426 A1 WO2021135426 A1 WO 2021135426A1
Authority
WO
WIPO (PCT)
Prior art keywords
decoding
hard decision
value
subcode
decision result
Prior art date
Application number
PCT/CN2020/117022
Other languages
English (en)
French (fr)
Inventor
李沫
吉德龙·多利
扎罗宾斯基·迈克尔
莱维·杜迪
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20908654.5A priority Critical patent/EP4072023A4/en
Publication of WO2021135426A1 publication Critical patent/WO2021135426A1/zh
Priority to US17/852,218 priority patent/US11750219B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1128—Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding
    • H03M13/2951—Iterative decoding using iteration stopping criteria
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/067—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • This application relates to the field of communications, and in particular to a decoding method, decoder and decoding device.
  • FEC forward error correction
  • the so-called FEC refers to encoding the data to be transmitted at the transmitting end according to certain rules, introducing a certain amount of redundancy (ie overhead); decoding at the receiving end according to the corresponding encoding rules, so as to correct the noise caused by the transmission process Or data transmission errors introduced by channel damage.
  • FEC can be divided into hard decision FEC and soft decision FEC.
  • hard decision FEC means that each bit of data input to the FEC decoder has only two values of 0 and 1. This input data is called hard information, and the decoder only calculates and updates the hard information during the decoding process. The output is hard information.
  • Soft decision FEC means that each bit of data input to the FEC decoder is represented by a floating-point value or a fixed-point value quantized into multiple values. The sign of the value represents the value of 0 and 1 of the bit, and the absolute value represents the value. The credibility of the value, the input data is called soft information, what the decoder calculates and updates in the decoding process is also soft information, and the final output is hard information.
  • hard decision FEC has low complexity and low power consumption, but the performance improvement of the transmission system is not as large as that of soft decision FEC.
  • the performance improvement of soft decision FEC on the transmission system is higher than that of hard decision, but the implementation complexity is high, and the power consumption is high. high. Therefore, different decoding methods need to be selected according to different application scenarios. Therefore, in the current FEC chip design, it is hoped that the same FEC chip can support decoding in multiple application scenarios, while also satisfying the function of the system. Consumption, delay and other requirements.
  • the soft decision decoding is directly used, and the decoding is skipped when the decoding result meets certain conditions.
  • the residual error code is very few in the several soft decision decoding before the skipping decoding. Using soft decision decoding will cause most of the performance of the decoder to be wasted and consume a lot of unnecessary power consumption.
  • the embodiments of the present application provide a decoding method, a decoder, and a decoding device to reduce decoding power consumption.
  • an embodiment of the present application discloses a decoding method, and the decoding method includes:
  • the first hard decision result is the effective hard decision result of the first row of subcodes, that is, the effective subcode.
  • the decoding method disclosed in this application by adding a turn-off flag to each sub-code to be translated, if the first sub-code has generated a valid hard decision result, the value indicated by the turn-off flag of the sub-code is updated to the first sub-code. A value indicating that there is no need to perform soft-decision decoding on the first subcode in the next decoding iteration, thereby saving decoding power consumption and improving decoding efficiency.
  • the first hard decision result is different from the hard decision result saved before the soft decision decoding of the first row of subcodes at least in the value of the first bit.
  • the first bit Corresponding to the first column of subcodes, the first column of subcodes and the first row of subcodes intersect at the first bit position; the turn-off flag corresponding to the first column of subcodes is set to a second value, when the first column of subcodes When the value indicated by the corresponding turn-off flag is the second value, the soft decision decoding is performed on the first column of subcodes in the next decoding iteration.
  • the hard decision result saved before the soft decision decoding of the first row of subcodes this time is usually the hard decision result obtained from the previous iteration of decoding the first row of subcodes.
  • the first row of subcodes are re-decoded with soft decision, but also the first column of subcodes associated with the first row of subcodes are also decoded again, which improves The accuracy and precision of decoding.
  • the second switch-off identifier corresponding to the second sub-code among the plurality of sub-codes of the codeword is acquired, and the value indicated by the second switch-off identifier is the first value; and the first value of the second sub-code is acquired.
  • the second hard decision result, the second hard decision result is the effective hard decision result obtained in the decoding iteration before this decoding iteration; judge whether to jump out of the decoding iteration, when not jumping out of the decoding iteration: according to the second
  • the hard decision result generates second soft information, which is used to perform soft decision decoding in the next decoding iteration of the second subcode; when the decoding iteration exits: the second hard decision The result is output.
  • the second switch-off identifier corresponding to the second sub-code is already stored, and the value indicated by the second switch-off identifier is the second number, so there is no need to The code is decoded.
  • the above generating the second soft information according to the second hard decision result includes: generating the second soft information according to the symbol value corresponding to the second hard decision result and the bit width value of the second soft information, preferably the soft information The maximum bit width value or a relatively large bit width value.
  • the third turn-off identifier corresponding to the third sub-code of the multiple sub-codes is obtained, and the value indicated by the third turn-off identifier is the second value.
  • the third Decode the subcode obtain the third soft information corresponding to the third subcode; perform soft decision decoding on the third subcode according to the third soft information to obtain the third hard decision result;
  • the method further includes:
  • the judging whether the third hard decision result is valid includes:
  • an embodiment of the present application discloses a decoder, which includes: a processor, a first memory, and a second memory;
  • the processor is configured to perform soft decision decoding on the first row of subcodes among the multiple subcodes of the codeword to obtain the first hard decision result;
  • the first memory is used to store the first turn-off identifier corresponding to the first row of subcodes
  • the second memory is used to store the above-mentioned first hard decision result
  • the processor is further configured to set the first off flag to a first value, and the first off flag is used to indicate whether to perform soft decision decoding on the first row of subcodes in the next decoding iteration.
  • the value indicated by the turn-off flag is the first value, then the first row of subcodes will not be subjected to soft decision decoding in the next decoding iteration;
  • the processor is further configured to store the above-mentioned first hard decision result in the second memory.
  • the decoder further includes an output interface, and the output interface is used to output the first hard decision result obtained by decoding the first row of subcodes.
  • the processor is also used to determine that the first hard decision result and the hard decision result saved before the soft decision decoding on the first row of subcodes have at least one bit in the first bit. Values are different, the first bit corresponds to a first column of subcodes, and the first column of subcodes and the first row of subcodes intersect at the first bit;
  • the processor is further configured to set the turn-off flag corresponding to the first column of subcodes to a second value.
  • the value indicated by the turn-off flag corresponding to the first column of subcodes is the second value, the first column of subcodes will be decoded in the next iteration.
  • the column sub-code performs soft-decision decoding.
  • the decoder further includes an input interface, the input interface is used to obtain a second switch-off identifier corresponding to the second sub-code of the plurality of sub-codes, and the value indicated by the second switch-off identifier is the First value
  • the input interface is also used to obtain the second hard decision result of the second subcode
  • the processor is used to determine whether to jump out of the decoding iteration. When it does not jump out of the decoding iteration: the processor generates second soft information according to the second hard decision result, and the second soft information is used in the next decoding iteration of the second subcode Soft decision decoding in the middle;
  • the output interface is also used to output the second hard decision result obtained by decoding the second subcode.
  • the input interface is also used to obtain a third switch-off identifier corresponding to the third sub-code of the multiple sub-codes, and the value indicated by the third switch-off identifier is the second value; the input interface also uses To obtain third soft information corresponding to the third subcode; the processor is further configured to perform soft decision decoding on the third subcode according to the third soft information to obtain a third hard decision result;
  • the processor judges that the third hard decision result is valid: the processor is also used to generate new third soft information, which is used in subsequent decoding iterations of the third subcode; the processor also uses Then, the value indicated by the third off indicator is updated to the first value.
  • the processor after the processor performs soft decision decoding on the third subcode according to the third soft information to obtain the third hard decision result, the processor is also used to jump out of the decoding iteration; the output interface is also used to output the third Hard decision result.
  • the processor determines whether to jump out of the decoding iteration, including:
  • the processor compares whether the current number of iterations reaches the preset number of iterations:
  • the decoding iteration is skipped; when the current number of iterations does not reach the preset number of iterations, the decoding iteration is not skipped.
  • an embodiment of the present application discloses a decoding device, which includes:
  • Memory used to store programs
  • the processor is configured to execute the program stored in the memory, and when the program is executed, the processor is configured to execute any possible implementation method in the first aspect.
  • the decoding device is a chip or an integrated circuit.
  • an embodiment of the present application discloses a computer storage medium, which stores computer-readable instructions, and when the computer reads and executes the computer-readable instructions, the computer executes the instructions in the first aspect Any possible method.
  • the embodiments of the present application also disclose a computer program product.
  • the computer reads and executes the computer program product, the computer is caused to execute any possible method in the first aspect.
  • Figure 1a is a schematic structural diagram of an encoding and decoding system disclosed in an embodiment of the application;
  • FIG. 1b is a schematic diagram of the structure of a TPC codeword disclosed in an embodiment of the application.
  • Figure 2 is a flowchart of a decoding method disclosed in an embodiment of the application.
  • Figure 3a is a schematic diagram of a codeword encoding scheme disclosed in an embodiment of the application.
  • Fig. 3b is a schematic diagram of a codeword decoding scheme disclosed in an embodiment of the application.
  • FIG. 4 is a schematic diagram of a method for obtaining a basic sequence disclosed in an embodiment of the application.
  • FIG. 5 is a schematic diagram of a method for obtaining a test sequence disclosed in an embodiment of the application.
  • Fig. 6 is a flowchart of a decoding method disclosed in an embodiment of the application.
  • FIG. 7 is a flowchart of a decoding method disclosed in an embodiment of this application.
  • FIG. 8 is a flowchart of a decoding method disclosed in an embodiment of this application.
  • FIG. 9 is a schematic structural diagram of a decoder disclosed in an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a decoding device disclosed in an embodiment of this application.
  • FIG. 11 is a schematic diagram of a decoder disclosed in an embodiment of the application.
  • FIG. 12 is a schematic diagram of a decoding device disclosed in an embodiment of the application.
  • This application discloses a decoding method, a decoder and a decoding device, which are used to reduce decoding power consumption, which will be described in detail below.
  • the decoding method, decoder and decoding device disclosed in the present application can be applied to a type of linear code defined by a check matrix, such as low density parity check code (LDPC), which is also more suitable for Two-dimensional codewords, such as TPC (Turbo Product Codes) codewords.
  • LDPC low density parity check code
  • TPC Teurbo Product Codes
  • FIG. 1a is a schematic diagram of an encoding and decoding system provided by an embodiment of the present application.
  • the encoding and decoding system 100 may include an encoding device 101 and a decoding device 102.
  • the encoding device 101 is used to encode each data block in the data stream to obtain the codeword corresponding to each data block, and send the codeword into a code stream to the decoding device 102.
  • the data stream can be any data stream such as a video stream, an audio stream, and a text stream.
  • a codeword is also a result of encoding a data block by the encoding device 101, each codeword can be regarded as a frame, and the data in a codeword is also a frame of data.
  • a codeword is the basic data unit when decoding by a decoding device.
  • a codeword can include multiple rows and multiple columns of bits.
  • a column or row of bits can form a subcode, that is, a codeword includes multiple subcodes.
  • Each subcode includes multiple bits, and the bits belonging to the same subcode are located in the same row or column of a codeword.
  • a codeword includes 128*128 bits, where each 128 bits is a row, and each 128 bits is a column, that is, the codeword may include 128 rows of subcodes or 128 columns of subcodes.
  • the encoding device 101 may use a turbo product (turbo product code, TPC) code encoding scheme for encoding.
  • TPC turbo product code
  • the decoding device 101 encodes one frame of data (for example, 128bit*128bit) as the basic unit, and the data in two adjacent frames meets the coding relationship of BCH(n,k), where n is the code of a BCH subcode Long, k is the information bit of a BCH subcode.
  • the decoding device 101 performs horizontal BCH (256, 239) codeword encoding on the 0th frame and the 1st frame in a data stream, that is, according to the row, the data on each row of the 0th frame and the 1st frame is encoded.
  • the decoding device 101 performs longitudinal BCH (256,239) codeword encoding on the encoded first and second frames, that is, according to the column , Encode the data in each column bit position of the first and second frames after encoding to obtain the first frame after the second encoding and the second frame after the first encoding, so that the first frame after the second encoding
  • Each bit in the frame is protected by a sub-code in the horizontal direction and a sub-code in the vertical direction.
  • the decoding device 102 is used to decode the code words in the received code stream. Each time the decoding device 102 receives a codeword, it can iteratively decode a target number of codewords, and the target number of codewords may include newly received codewords and previously decoded codewords.
  • the TPC codeword is a typical two-dimensional grouped algebraic code.
  • the two dimensions can be jointly encoded with the same or different algebraic code subcodes.
  • the codeword structure is shown in Figure 1b (here, the algebraic code subcode is taken as an example of BCH code. ).
  • the TPC code uses a rectangular (mostly square) information block as the coding unit. First, each line of the information block is line-coded using BCH1 code, and the coding overhead is placed on the right side of the information block; then each line of the information block and line overhead is coded.
  • One column uses BCH2 code for column coding, and the coding overhead is placed below the information block and row overhead.
  • the column overhead encoded by the information block and the row overhead portion in the lower right corner will also automatically meet the coding relationship of the row BCH1 from the perspective of the row dimension.
  • the encoded information block and the row and column overhead form a larger rectangular data block unit, that is, a TPC codeword.
  • the TPC codeword is used as the basic decoding unit to perform row and column iterative decoding.
  • the decoding performance improves as the number of iterations increases.
  • the row/column decoding core in iterative decoding can either use a hard-decision decoding core with less complexity, or a soft-in-soft-out (SISO) soft-decision decoding core with better performance, or Designed as a dynamic decoding architecture that can be switched according to conditions.
  • SISO soft-in-soft-out
  • RAM_HD When using the hard decision decoding core, only a 1-bit wide decoding buffer RAM_HD is needed. After each row/column decoding, only the corresponding bit in RAM_HD needs to be flipped according to the decoding result, and the value of each bit in RAM_HD is continuously updated in the iteration. After the iterative decoding is completed, the final state of RAM_HD is output as the decoding result.
  • RAM_LLR and RAM_EX are required to store the LLR (Log Likel ihood Rat io, log likelihood ratio) value of each bit obtained from the channel and The external information value obtained after each row/column iterative decoding.
  • LLR Log Likel ihood Rat io, log likelihood ratio
  • the content of RAM_LLR remains unchanged, while RAM_EX is updated correspondingly according to the external information value obtained after each row/column decoding.
  • the input soft information of each row/column decoding is jointly calculated by the external information EX_info and the LLR value obtained from the previous column/row decoding. After the iterative decoding is completed, the hard decision result of the last decoding can be simply output as the final decoding result.
  • the decoding method, decoder, and decoding device disclosed in this application are performed in units of subcodes, such as the above-mentioned TPC codeword, assuming a TPC codeword with n rows and n columns, that is, there are a total of 2*n subcodes .
  • the decoding method of the present application can decode each sub-code of the 2*n sub-code during decoding.
  • the shutdown flag cache, hard decision result cache, or soft information cache mentioned in the embodiments of the application below may be a memory object cache system or memory, and the memory may include registers and volatile memory.
  • RAM random-access memory
  • memory can also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid state drive (solid-state drive, SSD), cloud storage (cloud storage), network attached storage (Network Attached Storage, NAS), network drive (network drive), etc.
  • storage can also include a combination of the above types of storage or other storage Any form of media or product of function.
  • the decoded codeword can adopt a staircase TPC (Turbo Product Code, Turbo Product Code) coding scheme.
  • TPC Tribo Product Code, Turbo Product Code
  • a certain number of decoding iterations are usually preset.
  • the Nth decoding iteration can be the preset number of soft-decision decoding iterations except for the first Any decoding iteration other than the decoding iteration
  • the specific process of the decoding method of the present application may include:
  • S201 Obtain the shutdown identifier corresponding to the sub-code to be translated from the shutdown identifier cache, and obtain the hard decision result corresponding to the previously stored sub-code to be translated from the hard decision result cache.
  • each sub-code to be translated has a corresponding shutdown identifier, which is stored in the shutdown identifier cache, and the sub-code to be translated is obtained from the shutdown identifier cache Corresponding turn-off flag; at the same time, a hard decision result cache is set to store the hard decision result in the decoding iteration, and the hard decision result corresponding to the previously stored subcode to be translated is obtained from the hard decision result cache.
  • J201 Determine whether the value indicated by the off indicator corresponding to the subcode to be translated is the second value.
  • the turn-off flag corresponding to the sub-code to be translated is used to determine whether it is necessary to perform soft-decision decoding of the sub-code to be translated in this decoding iteration: if the value indicated by the turn-off flag corresponding to the sub-code to be translated is the second value ( For example, 0), it means that no valid hard decision result has been obtained in the previous soft decision decoding process, continue decoding to improve decoding performance; if the value indicated by the off flag corresponding to the subcode to be translated is not the second value Or when it is the first value (for example, 1), it means that an effective hard decision result was obtained in the previous soft decision decoding process.
  • This decoding iteration does not need to perform soft decision decoding, thereby saving decoding times. Reduce decoding power consumption.
  • step S202 can be directly started, and when the second and subsequent decoding iterations are performed, the execution starts from step S201.
  • the codeword where the subcode to be translated is located using the above staircase TPC coding scheme can be as shown in Figure 3.
  • Each bit using this coding scheme is divided by the horizontal BCH (Bose Ray-Chaudhuri Hocquenghem) 1 and vertical BCH 2 Code coding protection, so it can be called soft decision BCH algorithm.
  • the two subcodes of the horizontal BCH1 and the vertical BCH2 both use BCH (512,491) error correction codewords (BCH1 and BCH2 can also be implemented using different BCH codewords).
  • the encoding is based on one frame of data (256*256 bits), and two adjacent frames of data are encoded with the same type of BCH codeword.
  • the 0th frame and the 1st frame are coded by horizontal BCH1 (512, 491) codewords, and the coded is 256 BCH codewords with a length of 512 bits when viewed horizontally.
  • the first frame and the second frame are coded with longitudinal BCH2 (512,491) codewords (here BCH1 and 2 use the same BCH coding scheme, or different), after coding, they are also 256 512-bit lengths in the longitudinal direction.
  • BCH code word 512, 491 codewords
  • the soft information of the sub-code to be translated refers to the soft information of the value of each bit of the sub-code to be translated, including the value and the confidence of the value, and its mathematical expression is the posterior that each bit is equal to 1.
  • the logarithm of the ratio of the probability to its posterior probability equal to 0.
  • a positive value indicates that the bit is more likely to be equal to 1
  • a negative value indicates that the bit is more likely to be equal to 0, and its absolute value can indicate the credibility of the corresponding value. The larger the absolute value, the greater the value. reliable.
  • the soft information of a certain bit in the subcode can be obtained through the following algorithm:
  • APPN represents the soft information of a certain bit in the Nth decoding iteration
  • LLR Log Likelihood Ratio, log likelihood ratio
  • Ex_infoN-1 is the (N-1)th
  • ⁇ is the weight coefficient, and ⁇ gradually increases with the iteration process.
  • the LLR information of each bit in each subcode input by the channel is obtained as soft information; in the second decoding and subsequent soft-decision decoding steps, according to The LLR information of each bit in the subcode to be translated input by the channel, and the external information Ex_info corresponding to the bit to obtain the soft information of the bit.
  • S203 Perform soft decision decoding on the subcode to be translated to obtain a new hard decision result.
  • At least one test sequence is generated for the sub-code to be translated.
  • the absolute value of a bit of soft information can indicate the reliability of the value of the bit.
  • the smaller the absolute value the more unreliable the value of the bit is, and the probability that it is an error bit is also Bigger. Therefore, for a subcode in a codeword, first select the P bits with the smallest absolute value of the soft information on the subcode, and consider that the error of the subcode is most likely to occur in the P positions (P is greater than zero). Integer, the value of P can be set as required, and there is no limitation here). Then, 2P test sequences (Test Sequence, TS) are constructed according to these P positions. Specific construction methods, such as:
  • the P bits of the sub-code to be translated are sequentially traversed 0 and 1 to obtain values, and the bits in the sub-code except the P bits are set to 0, Obtain 2P basic sequences (Basic Sequence, BS).
  • the decoding result of the sub-code to be translated which is obtained by hard-decision decoding of the soft information of the sub-code to be translated, and record it as D0.
  • the D0 of the sub-code to be translated and the 2P BSs of the sub-code are obtained.
  • 2P TS of the subcode Specifically, the D0 of the sub-code to be translated and the 2P basic sequence of the sub-code can be added modulo two to obtain 2P TS.
  • the four BSs (BS1-BS4) shown in FIG. 4 are used to construct the TS, and the obtained TS (TS1-TS4) may be as shown in FIG. 5.
  • K output subcodes are obtained after soft decision decoding, that is, K effective subcodes, K ⁇ 2P. This is because some TS may exceed the decoding capability and cannot be decoded normally.
  • selecting the optimal effective sub-code from the K effective sub-codes after soft decision decoding of the sub-code to be translated can be achieved by:
  • the Euclidean distance between the K effective subcodes of the subcode and the soft information of the subcode This can be based on the value of each bit of each effective subcode of the subcode, and each of the codewords.
  • the soft information of the bit position is obtained by using the Euclidean distance formula, such as:
  • di represents the Euclidean distance between the effective subcode i in the K effective subcodes of a subcode and the soft information of the subcode
  • the effective subcode i is any one of the K effective subcodes of the codeword
  • x1k represents the value of the k-th bit of the effective sub-code i
  • x2k represents the value of the k-th soft information of the sub-code.
  • the value of the bit in the effective subcode needs to be converted from (1,0) to (1, -1) to correspond to the value range of the soft information.
  • K Euclidean distances can be obtained according to K effective subcodes, and then the effective subcode corresponding to the smallest Euclidean distance is selected as the optimal effective subcode as the new hard decision result of the subcode to be translated.
  • FIG. 3b shows a schematic diagram of an iterative decoding process disclosed in an embodiment of the present application.
  • the dimension of the sliding window in FIG. 3b is 6, and the codeword in the sliding window includes the P-6th codeword.
  • the P-1th codeword is the first codeword in the sliding window
  • the P-6th codeword is the last codeword in the sliding window
  • the P-1th codeword is the last codeword in the sliding window.
  • a codeword is the P-1th frame of data; when the decoding device receives the Pth codeword, the sliding window slides forward by one codeword, so that the Pth codeword is the first in the sliding window Codeword, the P-6th codeword slides out of the sliding window, the P-5th codeword is the last codeword of the sliding window; the decoding device starts to process the P-5th codeword to the Pth codeword Words undergo an iterative decoding process, and the iterative decoding process includes iterative decoding 1-5; the iterative decoding process performed by the decoding device from the P-5th codeword to the Pth codeword may be: first, decoding The device 102 performs a horizontal soft-decision decoding on the P-th codeword and the P-1th codeword to obtain the P-th codeword after decoding and the P-1th codeword after decoding, which are recorded as iterations Decoding 1; Then, the decoding device performs a longitudinal soft-decision decoding on the decoded P-1 codeword and P-2 code
  • the decoding device When the iterative decoding 5 is completed, the decoding device will decode the P-5th codeword.
  • the decoding result of the codeword is output, that is, the P-5th codeword after decoding is output.
  • the horizontal soft-decision decoding is to perform soft-decision decoding on each sub-code in the codeword according to the line. For example, for a codeword, the decoding device first performs soft-decision decoding on the first line of the subcode in the codeword Code, and then perform soft-decision decoding on the second row of sub-codes in the codeword.
  • the decoding device can also perform soft-decision decoding on multiple rows of sub-codes in parallel.
  • Vertical soft-decision decoding is to perform soft-decision decoding on each subcode in a codeword according to the column. For example, for a codeword, the decoding device 102 first performs soft-decision decoding on the first column of subcodes in the codeword. Then perform soft decision decoding on the second column of subcodes in the codeword. Of course, the decoding device can perform soft decision decoding on multiple columns of subcodes in parallel.
  • step S205 is executed; if the decoding iteration of the decoding-to-be-translated sub code this time is iteratively decoded If the number of times does not reach the preset maximum number of decoding times, step S204 is executed.
  • Step S204 If the new hard decision result is valid, store the new hard decision result, and set the off flag corresponding to the subcode to be translated to the first value; generate soft information for the next soft decision decoding of the subcode to be translated. Step S207 is then executed.
  • the new hard decision result and the check matrix corresponding to the sub-code to be translated can be used to determine whether the new hard decision result of the sub-code is valid.
  • the check matrix and the above-mentioned check matrix can be calculated. The product of the new hard decision result. When the product is 0, the new hard decision result is considered valid.
  • the new hard decision result is valid by calculating the syndrome of the BCH subcode. For example, if the error correction capability of a soft decision decoding is t, that is, t bits can be corrected. Based on the new hard decision result of the BCH subcode, 2t syndromes are calculated, if 2t syndromes If the value of is all 0, the above new hard decision result is valid. If the value of 2t syndromes is non-zero, the above new hard decision result is invalid.
  • the syndrome of the BCH subcode to determine that the validity is the default validity in the decoding algorithm, that is, the way to determine the validity of the decoding result set by the decoding algorithm, but there may actually be a certain bit error rate. This application does not limit the method by which the decoding algorithm itself determines whether the decoding result is valid.
  • the soft-decision decoding is used to generate the soft information of the next soft-decision decoding, so as to realize the effective transmission of confidence in the decoding process.
  • wj represents the external information of the j-th bit of a sub-code
  • R represents the input soft information of the soft decision decoding
  • D is the best effective sub-code of the sub-code, that is, the above-mentioned new hard decision result
  • C is the sub-optimal Effective subcode (the optimal effective subcode among all effective subcodes of the subcode except the optimal effective subcode, which can also be called a competing subcode)
  • dj is the value of the jth bit in D ( 1/-1). Due to the limited value of P, it is possible that C that meets the above requirements cannot be found in the K output results. At this time, the external information of this bit can be obtained by the following approximate algorithm:
  • ⁇ is the weight coefficient, and the value gradually increases with the decoding process, and its specific value can be obtained through simulation optimization.
  • each soft-decision decoding affects the next soft-decision decoding through external information, so each soft-decision decoding of a certain sub-code can also be called a decoding iteration of the sub-code. .
  • the new hard decision result and the hard decision result saved before the subcode to be translated have at least one value in the first bit that is different.
  • the subcode to be translated in this decoding iteration is the first row of subcodes.
  • Code the first bit of subcode on the first row of this hard decision is different from the previously saved hard decision result, the first bit also corresponds to the first column of subcode, the first column of subcode is the same as the first row
  • the sub-codes intersect at the first bit position; then the off flag corresponding to the first column of sub-codes is set to the second value (for example, 0), when the value indicated by the off flag is the second value, then in the next decoding iteration It is necessary to perform soft decision decoding on the first column of subcodes.
  • first row of subcodes and the first column of subcodes mentioned in the embodiments of this application can also be two associated subcodes, and there is no need to strictly follow the usual arrangement of rows and columns; in addition, on the subcodes
  • the bits are not always arranged in a row, which is not limited in this application.
  • the first row of subcodes 601 and the first column of subcodes 602 intersect at the first bit position 603 (the semicircular protrusion in FIG.
  • the first bit 603 is related, and the first bit 603 corresponds to the first row of subcodes 601 and the first column of subcodes 602; the first row of subcodes 601 and the first column of subcodes 602 can also be arranged in a bent form in FIG. 6 cloth.
  • Step S205 Output the new hard decision result of the sub-code to be translated obtained above.
  • Step S207 is then executed until the last decoding iteration of the last subcode of all subcodes to be translated is performed.
  • step S205 If the decoding times after the decoding iteration of the sub-code to be translated this time reaches the preset maximum decoding times, then the decoding iteration is skipped and step S205 is executed; if the decoding iteration of the decoding-to-be-translated sub code this time is iteratively decoded If the number of times does not reach the preset maximum number of decoding times, step S206 is executed.
  • Step S206 Generate new soft information according to the hard decision result of the last decoding and storage. Step S207 is then executed.
  • the hard decision result generally only has two bits of 0 and 1 per bit of data.
  • the sign value corresponding to 1 is positive, and the sign value corresponding to 0 is negative
  • the bit width value of the soft information generate new soft information, and store the new soft information in the soft information buffer.
  • the product of the symbol value corresponding to the hard decision result and the bit width value of the soft information is used as the output soft information; preferably, the bit width value of the soft information preferentially selects the maximum bit width value allowed by the soft information bit width or a relatively larger value The bit width value of.
  • the decoding iteration of the sub-code to be translated this time ends, and the decoding iteration of the next sub-code is shifted to.
  • the next sub-code can be a row sub-code or a column sub-code.
  • a subcode in a codeword is used as a basic decoding unit, which improves the decoding accuracy compared with the prior art using a codeword as a decoding unit.
  • a codeword when used as a decoding unit, when one bit of a codeword requires soft decision decoding, the entire codeword needs to be re-decoded with soft decision.
  • the technical solution of this application It only needs to decode the sub-code where the bit is located, which greatly saves decoding power consumption.
  • a turn-off flag is added to each sub-code to be translated. After each decoding iteration, the value indicated by the turn-off flag is updated. If any sub-code has generated a valid hard decision result, Then the value indicated by the off flag of the sub-code is updated to the first value, indicating that there is no need to perform soft-decision decoding in the next decoding iteration; if there are still bits in the sub-code, a valid decoding result has not yet been obtained , The value indicated by the off flag of the subcode is updated to the second value, indicating that soft decision decoding is needed in the next decoding iteration.
  • the decoding method disclosed in the present application greatly saves decoding power consumption and improves decoding efficiency.
  • first, second, etc. in this application are used to distinguish similar objects, and not necessarily used to describe a specific sequence or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that The described embodiments can be implemented in a sequence not described in this application.
  • “And/or” is used to describe the association relationship of associated objects, indicating that there can be three types of relationships. For example, A and/or B can mean: A alone exists, A and B exist at the same time, and B exists alone.
  • the specific operation method in the method embodiment can also be applied to the device embodiment.
  • the present application uses the same figure numbers to represent components with the same or similar functions in the different embodiments.
  • At least one described in the embodiments of the present application means “one” or “more than one”.
  • FIG. 7 is a flow chart of a decoding method disclosed in this application.
  • S represents an execution type step
  • J represents a judgment type step.
  • the decoding method includes:
  • the soft decision decoding process perform soft decision decoding on the first row of subcodes among the multiple subcodes in the codeword.
  • the soft decision decoding process refer to the relevant description of step 203 above to obtain the first hard decision result.
  • the first hard decision result is the effective subcode of the first row of subcodes, and the optimal effective subcode is preferentially selected.
  • step S704 is executed; if the decoding iterations of the first row of subcodes this time, If the number of decoding times does not reach the preset maximum number of decoding times, step S702 is executed.
  • the first line of the subcode corresponds to the first shutdown identifier
  • the first shutdown identifier is stored in the shutdown identifier cache, and the value indicated by the first shutdown identifier is set to the first value.
  • the first off flag is used to indicate whether to perform soft decision decoding on the first row of subcodes in the next decoding iteration.
  • the value indicated by the first off flag is the first value (for example, 1)
  • the second decoding iteration no soft decision decoding is performed on the first row of subcodes, because a valid first hard decision result has been obtained in step S701.
  • step S705 can be optionally executed.
  • Steps S701 to S704 are the steps of the first decoding iteration of a certain subcode.
  • Steps S705 and S706 are optional steps:
  • S705 Set the shutdown identifier corresponding to the subcode in the first column to a second value.
  • step S701 if the hard decision result buffer stores the hard decision result that was previously stored in the soft decision decoding on the first row of subcodes, the first hard decision result obtained in this decoding iteration is the same as the previous one.
  • the hard decision result of the first row of subcodes has a different value on at least one first bit.
  • the first bit corresponds to the first column of subcodes.
  • the first column of subcodes and the first row of subcodes are in the first bit.
  • the next subcode can be a row subcode or It is Liezi code.
  • the next decoding iteration is performed until all sub-codes to be translated in the codeword have completed the preset number of decoding iterations, the decoding is completed .
  • the decoding iteration of the next subcode in step S706 may include the following steps, as shown in FIG. 8:
  • the second turn-off indicator corresponding to the second subcode Since the value indicated by the second turn-off indicator corresponding to the second subcode is the first value, it indicates that the effective hard decision result of the second subcode has been obtained in the previous decoding iteration, so it is not used in this decoding iteration. It is necessary to perform soft decision decoding on the above-mentioned second subcode.
  • step S803 is executed; when the decoding iteration is jumped out, step S804 is executed.
  • S803 Generate second soft information according to the foregoing second hard decision result, where the second soft information is used to perform soft decision decoding in the next decoding iteration of the second subcode.
  • the bit width value of the second soft information generates the second soft information, and saves the second soft information in the soft information cache.
  • the bit width value of the second soft information preferentially selects the largest bit width value or a relatively larger bit width value of the second soft information.
  • Steps S801-S804 show the decoding process after a valid hard decision result has been obtained for the second subcode among the multiple subcodes.
  • performing decoding iteration on the next subcode in step S706 may further include the following steps, as shown in FIG. 9:
  • the third off flag corresponding to the third subcode Since the value indicated by the third off flag corresponding to the third subcode is the second value, it indicates that the effective hard decision result of the third subcode has not been obtained in the previous decoding iteration. In this decoding iteration, it is necessary to The third subcode performs soft decision decoding.
  • S903 Perform soft decision decoding on the third subcode according to the above third soft information to obtain a third hard decision result.
  • the third subcode corresponding to the third subcode is changed.
  • the value indicated by the off flag is updated to the first value.
  • the external information of each bit in the third subcode is acquired according to the soft information of each bit in the third subcode and the third hard decision result, and the new third soft information is generated according to the external information.
  • the decoding iteration of the third subcode is the preset last decoding iteration, the decoding iteration is skipped and the third hard decision result is output.
  • Steps S901-S905 show the decoding process after the third subcode among the multiple subcodes has not yet obtained a valid hard decision result.
  • the decoding process of the first decoding iteration of the sub-code the decoding process of the sub-code that has obtained a valid hard decision result, and the decoding process of the sub-code that has not obtained a valid hard decision result are respectively disclosed.
  • the decoding process of the sub-code greatly saves decoding power consumption and improves decoding efficiency.
  • FIG. 10 is a decoder disclosed in an embodiment of the application. As shown in FIG. 10, the decoder 1000 includes a processor 1001, a first memory 1002, and a second memory 1003;
  • the processor 1001 is configured to perform soft decision decoding on the first row of subcodes among the multiple subcodes to obtain a first hard decision result;
  • the second memory 1003 is used to store the above-mentioned first hard decision result
  • the first memory 1002 is configured to store the first turn-off identifier corresponding to the above-mentioned first row of subcodes
  • the processor 1001 is further configured to set the above-mentioned first off flag to a first value, and the first off flag is used to indicate whether to perform soft decision decoding on the first row of subcodes in the next decoding iteration, When the value indicated by the first switch-off indicator is the first value, no soft decision decoding is performed on the first row of subcodes in the next decoding iteration;
  • the processor 1001 is further configured to store the above-mentioned first hard decision result in the second memory 1003.
  • the first memory and the second memory are only for distinguishing and storing different information. In practice, they may be different parts of the same memory, for example, they may be two independent caches or RAMs in the same memory.
  • the decoder 1000 may further include an output interface 1005, and the output interface 1005 is configured to output the first hard decision result obtained by decoding the above-mentioned first row of subcodes.
  • the processor 1001 is further configured to determine that the first hard decision result and the hard decision result saved before the soft decision decoding on the first row of subcodes have at least one bit taken on the first bit. If the value is different, the first bit corresponds to the first column of subcodes, and the first column of subcodes and the first row of subcodes intersect at the first bit;
  • the processor 1001 is further configured to set the off flag corresponding to the first column of subcodes to a second value. When the value indicated by the off flag corresponding to the first column of subcodes is the second value, it is required in the next decoding iteration. Perform soft decision decoding on the above-mentioned first column of subcodes.
  • the decoder 1000 further includes an input interface 1004,
  • the input interface 1004 is used to obtain a second switch-off identifier corresponding to a second sub-code of the plurality of sub-codes, and the value indicated by the second switch-off identifier is the first value;
  • the input interface 1004 is also used to obtain the second hard decision result of the second subcode
  • the processor 1001 is also used for judging whether to jump out of the decoding iteration, when not jumping out of the decoding iteration:
  • the processor 1001 generates second soft information according to the foregoing second hard decision result, where the second soft information is used to perform soft decision decoding in the next decoding iteration of the second subcode;
  • the output interface 1005 is also used to output the above-mentioned second hard decision result.
  • the input interface 1004 is also used to obtain a third switch-off identifier corresponding to the third sub-code of the multiple sub-codes, and the value indicated by the third switch-off identifier is the second value;
  • the input interface 1004 is also used to obtain the third soft information corresponding to the third subcode
  • the processor 1001 is further configured to perform soft decision decoding on the third subcode according to the above third soft information to obtain a third hard decision result;
  • the processor 1001 judges that the above-mentioned third hard decision result is valid: the processor 1001 is also used to generate new third soft information, which is used for subsequent decoding iterations of the third subcode; the processor 901 It is also used to update the value indicated by the third off indicator to the first value.
  • the processor 1001 performs soft decision decoding on the third subcode according to the above third soft information to obtain the third hard decision result
  • the processor 1001 is also used to jump out of the decoding iteration
  • the output interface 1005 is also used to output the above Three hard judgment results.
  • the processor 1001 determines whether to jump out of the decoding iteration, including:
  • the processor 1001 compares whether the current number of iterations reaches the preset number of iterations: when the current number of iterations reaches the preset number of iterations, the decoding iteration is skipped; the current number of iterations does not reach the preset number of iterations, and the decoding is not skipped Iteration.
  • FIG. 11 is a decoder disclosed in an embodiment of the application. As shown in FIG. 11, the decoder 1100 includes: a soft decision decoding module 1101, a switching module 1102, a shutdown module 1103, and an output module 1105;
  • the soft decision decoding module 1101 is configured to perform soft decision decoding on the first row of subcodes among the multiple subcodes to obtain the first hard decision result;
  • the switching module 1102 is used to determine whether to jump out of the decoding iteration, when not jumping out of the decoding iteration:
  • the turn-off module 1103 sets the first turn-off flag corresponding to the first row of subcodes to a first value, and the first turn-off flag is used to indicate whether to perform soft-decision translation on the first row of subcodes in the next decoding iteration. Code, when the value indicated by the first off indicator is the above-mentioned first value, then the first row of sub-codes will not be soft-decided in the next decoding iteration;
  • the output module 1105 outputs the first hard decision result obtained by decoding the first row of subcodes.
  • the first hard decision result is different from the hard decision result stored before the soft decision decoding of the first row of subcodes at least in the value of the first bit.
  • the bit position corresponds to the first column of subcodes, and the first column of subcodes and the first row of subcodes intersect at the first bit position;
  • the switch-off module 1103 sets the switch-off identifier corresponding to the first column of subcodes to the second value.
  • the switch-off identifier corresponding to the first column of subcodes is the second value, the first column of subcodes will be processed in the next decoding iteration.
  • the column sub-code performs soft-decision decoding.
  • the above-mentioned decoder 1100 further includes an obtaining module 1104:
  • the obtaining module 1104 is configured to obtain a second switch-off identifier corresponding to a second sub-code of the plurality of sub-codes, and the value indicated by the second switch-off identifier is the first value;
  • the obtaining module 1104 is further configured to obtain a second hard decision result of the second subcode, where the second hard decision result is an effective hard decision result obtained in a decoding iteration before the current decoding iteration;
  • the switching module 1102 is used to determine whether to jump out of the decoding iteration, when not jumping out of the decoding iteration:
  • the soft decision decoding module 1101 generates second soft information according to the above-mentioned second hard decision result, and the second soft information is used to perform soft decision decoding in the next decoding iteration of the second subcode;
  • the output module 1105 outputs the above-mentioned second hard decision result.
  • the second soft information is generated according to the symbol value corresponding to the second hard decision result and the bit width value of the second soft information.
  • the obtaining module 1104 is further configured to obtain a third switch-off identifier corresponding to a third sub-code of the plurality of sub-codes, and the value indicated by the third switch-off identifier is the second value;
  • the obtaining module 1104 is further configured to obtain third soft information corresponding to the third subcode
  • the soft decision decoding module 1101 is further configured to perform soft decision decoding on the third subcode according to the above third soft information to obtain a third hard decision result;
  • the soft decision decoding module 1101 is also used to determine whether the third hard decision result is valid. If the third hard decision result is valid:
  • the soft decision decoding module 1101 generates new third soft information, which is used for subsequent decoding iterations of the above-mentioned third subcode; the shut-off module 1103 updates the value indicated by the third shut-off identifier to The first value.
  • FIG. 12 is a decoding device disclosed in an embodiment of the application. As shown in FIG. 12, the decoding device includes:
  • the memory 1201 is used to store programs
  • the processor 1202 is configured to execute the program stored in the memory, and when the program is executed, the processor is configured to execute any method described in the foregoing method embodiment.
  • the decoding device is a chip or an integrated circuit.
  • the embodiment of the present application also discloses a computer-readable storage medium.
  • the computer-readable storage medium stores computer-readable instructions.
  • the computer reads and executes the computer-readable instructions, the computer executes the above-mentioned method embodiments. Any one of the methods described.
  • the embodiment of the present application also discloses a computer program product.
  • the computer reads and executes the computer program product, the computer executes any one of the methods described in the above method embodiments.
  • the embodiment of the present application provides a computer-readable storage medium, including computer-readable instructions, and when the computer reads and executes the computer-readable instructions, the computer is caused to execute the method executed by the above-mentioned processor.
  • the embodiment of the present application also provides a computer program product containing instructions, which when the computer program product runs on a computer, causes the computer to execute the method executed by the above-mentioned processor.
  • modules or steps of the present invention can be implemented by a general computing device, and they can be concentrated on a single computing device or distributed on a network composed of multiple computing devices.
  • they can be implemented with program codes executable by the computing device, so that they can be stored in a storage medium (ROM/RAM, magnetic disk, optical disk) and executed by the computing device, and in some cases
  • ROM/RAM read-only memory
  • magnetic disk magnetic disk
  • optical disk optical disk
  • the steps shown or described can be performed in a different order from here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them can be fabricated into a single integrated circuit module for implementation. Therefore, the present invention is not limited to any specific combination of hardware and software.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

本申请涉及通信领域，尤其涉及一种译码方法、译码器和译码装置。对多个子码中的第一子码进行软判决译码得到硬判决结果；判断是否跳出译码迭代，当不跳出译码迭代时：根据上述硬判决结果将第一子码对应的第一关断标识设置为第一数值，该第一关断标识用于指示在下一次译码迭代中是否对所述第一子码进行软判决译码，当第一关断标识表示的数值为第一数值时，则在下次译码迭代中不对所述第一子码进行软判决译码；保存上述硬判决结果。

Description

译码方法、译码器和译码装置
本申请要求于2019年12月30日提交中国国家知识产权局、申请号为201911393850.1、发明名称为“译码方法、译码器和译码装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种译码方法、译码器和译码装置。
背景技术
在高速光传输系统中，需要前向纠错(Forward error correction，FEC)技术来提升系统的传输性能，以支撑更远的传输距离。所谓FEC，指的是在发射端对所要传输的数据按照一定的规则进行编码，引入一定的冗余(即开销)；在接收端根据相应的编码规则进行译码，从而纠正传输过程中由噪声或信道损伤引入的数据传输错误。FEC按译码方式可分为硬判决FEC和软判决FEC两种。
其中，硬判决FEC是指输入FEC译码器的每比特数据只有0、1两种取值，该输入数据称为硬信息，译码器在译码过程中也只计算和更新硬信息，最终输出的是硬信息。软判决FEC是指输入FEC译码器的每比特数据均用浮点数值或量化为多种取值的定点数值表示，该数值的符号表示该比特的0、1取值，绝对值大小表示该取值的可信程度，该输入数据称为软信息，译码器在译码过程中计算和更新的是也是软信息，最终输出的是硬信息。
硬判决FEC的实现复杂度低，所需功耗低，但是对于传输系统的性能提升不如软判决FEC大，软判决FEC对传输系统的性能提升高于硬判决，但是实现复杂度高，功耗高。因此，需要根据应用场景的不同来选择不同译码方式，因此，在当前的FEC芯片设计中，希望能够在同一FEC芯片中能够支持多种应用场景下的译码，同时还要满足系统的功耗、延时等需求。
在一种现有技术中，直接采用软判决译码，在译码结果满足一定条件时跳出译码，然而一般在跳出译码前的若干次软判决译码中，残留误码已经很少，使用软判决译码会造成译码器的大部分性能处于浪费状态，会消耗大量不必要的功耗。
发明内容
鉴于此，本申请实施例提供了一种译码方法、译码器和译码装置，用于降低译码功耗。
第一方面，本申请实施例公开了一种译码方法，该译码方法包括：
对码字的多个子码中的第一行子码进行软判决译码得到第一硬判决结果；
判断是否跳出译码迭代，当不跳出译码迭代时：根据上述第一硬判决结果将第一行子码对应的第一关断标识设置为第一数值，该第一关断标识用于指示在下一次译码迭代中是否对第一行子码进行软判决译码，当第一关断标识表示的数值为第一数值时，则在下次译码迭代中不对所述第一行子码进行软判决译码，保存第一硬判决结果；
当跳出译码迭代时：输出第一硬判决结果。
这里，第一硬判决结果为第一行子码的有效硬判决结果，即有效子码。本申请公开的译码方法中通过为每个待译的子码添加关断标识，若第一子码已经生成有效的硬判决结果，则将该子码的关断标识表示的数值更新为第一数值，指示下一次译码迭代中不需要再对第一子码进行软判决译码，从而节省了译码功耗，提高了译码效率。
一种可能的设计中，第一硬判决结果与本次对第一行子码进行软判决译码之前保存的硬判决结果有至少一个第一比特位上的取值不同，该第一比特位对应有第一列子码，第一列子码与所述第一行子码在该第一比特位相交；将所述第一列子码对应的关断标识设置为第二数值，当第一列子码对应的关断标识表示的数值为第二数值时，则在下次译码迭代中对上述第一列子码进行软判决译码。
本次对第一行子码进行软判决译码之前保存的硬判决结果通常为上一次对第一行子码译码迭代得到的硬判决结果。在第一行子码存在比特位有误码的情况，不仅仅对第一行子码重新软判决译码，还对第一行子码关联的第一列子码也再进行译码，提高了译码的准确度和精度。
一种可能的设计中，获取上述码字的多个子码中的第二子码对应的第二关断标识，该第二关断标识表示的数值为第一数值；获取第二子码的第二硬判决结果，该第二硬判决结果为在本次译码迭代之前的译码迭代中得到的有效的硬判决结果；判断是否跳出译码迭代，当不跳出译码迭代时：根据第二硬判决结果生成第二软信息，该第二软信息用于在下一次对所述第二子码的译码迭代中进行软判决译码；当跳出译码迭代时：将所述第二硬判决结果输出。
本次对第二子码进行译码时，已经存储有第二子码对应的第二关断标识，且第二关断标识表示的数值为第二数字，故本次不需要对第二子码进行译码。
一种可能的设计中，上述根据第二硬判决结果生成第二软信息，包括：根据第二硬判决结果对应的符号值和第二软信息的位宽值生成第二软信息，优选软信息的最大位宽值或相对较大的位宽值。
一种可能的设计中，获取上述多个子码中的第三子码对应的第三关断标识，该第三关断标识表示的数值为第二数值，本次译码迭代中需要对第三子码进行译码；获取第三子码对应的第三软信息；根据该第三软信息对第三子码进行软判决译码得到第三硬判决结果；
判断第三硬判决结果是否有效，若第三硬判决结果有效：生成新的第三软信息，该新的第三软信息用于后续对所述第三子码的译码迭代；将上述第三关断标识表示的数值更新为所述第一数值。因为第三硬判决结果有效，下次译码迭代中不需要对第三子码再进行译码。
一种可能的设计中，上述根据第三软信息对第三子码进行软判决译码得到所述第三硬判决结果后，方法还包括：
判断当前译码迭代为预设次数的译码迭代中的最后一次译码迭代；
跳出译码迭代；
输出第三硬判决结果。
一种可能的设计中，所述判断第三硬判决结果是否有效，包括：
根据所述对第三子码得到的第三硬判决结果，计算所述第三子码对应的伴随式矩阵；
根据所述第三子码对应的伴随式矩阵的取值，确定所述第三硬判决结果是否有效。
第二方面，本申请实施例公开了一种译码器，该译码器包括：处理器、第一存储器和第二存储器；
处理器用于对码字的多个子码中的第一行子码进行软判决译码得到第一硬判决结果；
第一存储器用于存储第一行子码对应的第一关断标识；
第二存储器用于存储上述第一硬判决结果；
处理器还用于将第一关断标识设置为第一数值，该第一关断标识用于指示在下一次译码迭代中是否对所述第一行子码进行软判决译码，当第一关断标识表示的数值为第一数值时，则在下次译码迭代中不对所述第一行子码进行软判决译码；
处理器还用于将上述第一硬判决结果保存在第二存储器中。
一种可能的设计中，译码器还包括输出接口，该输出接口用于将对上述第一行子码译码得到的第一硬判决结果输出。
一种可能的设计中，所述处理器还用于判断第一硬判决结果与本次对第一行子码进行软判决译码之前保存的硬判决结果有至少一个第一比特位上的取值不同，该第一比特位对应有第一列子码，第一列子码与第一行子码在该第一比特位相交；
处理器还用于将第一列子码对应的关断标识设置为第二数值，当第一列子码对应的关断标识表示的数值为第二数值时，则在下一次译码迭代中对第一列子码进行软判决译码。
一种可能的设计中，译码器还包括输入接口，该输入接口用于获取多个子码中的第二子码对应的第二关断标识，该第二关断标识表示的数值为所述第一数值；
输入接口还用于获取第二子码的第二硬判决结果；
处理器用于判断是否跳出译码迭代，当不跳出译码迭代时：理器根据第二硬判决结果生成第二软信息，该第二软信息用于在下一次对第二子码的译码迭代中进行软判决译码；
当跳出译码迭代时：输出接口还用于将对第二子码译码得到的第二硬判决结果输出。
一种可能的设计中，输入接口还用于获取多个子码中的第三子码对应的第三关断标识，该第三关断标识表示的数值为所述第二数值；输入接口还用于获取第三子码对应的第三软信息；处理器还用于根据第三软信息对第三子码进行软判决译码得到第三硬判决结果；
当处理器判断第三硬判决结果有效：处理器还用于生成新的第三软信息，该新的第三软信息用于后续对所述第三子码的译码迭代；处理器还用于将第三关断标识表示的数值更新为所述第一数值。
一种可能的设计中，处理器根据第三软信息对第三子码进行软判决译码得到第三硬判决结果后，处理器还用于跳出译码迭代；输出接口还用于输出第三硬判决结果。
一种可能的设计中，处理器判断是否跳出译码迭代，包括：
处理器比较当前的迭代次数是否达到预设的迭代次数：
当当前的迭代次数达到预设的迭代次数，则跳出译码迭代；当前的迭代次数未达到预设的迭代次数，不跳出译码迭代。
第三方面，本申请实施例公开了一种译码装置，该译码装置包括：
存储器，用于存储程序；
处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行第一方面中任一种可能实现的方法。
一种可能的设计中，所述译码装置为芯片或集成电路。
第四方面，本申请实施例公开了一种计算机存储介质，所述计算机存储介质中存储有计算机可读指令，当计算机读取并执行所述计算机可读指令时，使得计算机执行第一方面中任一种可能实现的方法。
第五方面，本申请实施例还公开了一种计算机程序产品，当计算机读取并执行所述计算机程序产品时，使得计算机执行第一方面中任一种可能实现的方法。
附图说明
图1a为本申请实施例公开的一种编译码系统的结构示意图；
图1b为本申请实施例公开的一种TPC码字的结构示意图；
图2为本申请实施例公开的一种译码方法的流程图；
图3a为本申请实施例公开的一种码字的编码方案的示意图；
图3b为本申请实施例公开的一种码字的译码方案的示意图；
图4为本申请实施例公开的一种获取基本序列的方法示意图；
图5为本申请实施例公开的一种获取测试序列的方法示意图；
图6为本申请实施例公开的一种译码方法的流程图；
图7为本申请实施例公开的一种译码方法的流程图；
图8为本申请实施例公开的一种译码方法的流程图；
图9为本申请实施例公开的一种译码器的结构示意图；
图10为本申请实施例公开的一种译码装置的结构示意图；
图11为本申请实施例公开的一种译码器示意图；
图12为本申请实施例公开的一种译码装置示意图。
具体实施方式
本申请公开了一种译码方法、译码器和译码装置，用于降低译码功耗，以下进行详细说明。
本申请公开的译码方法、译码器和译码装置可以适用于通过校验矩阵定义的一类线性码，例如低密度奇偶校验码(Low Density Parity Check Code，LDPC)，同样更适用于二维码字， 例如TPC(Turbo Product Codes)码字。本申请公开的译码方法还适用于其他种类的二维或多维码字，本申请对此不做限制。
图1a是本申请实施例提供的一种编译码系统的示意图，参见图1a，该编译码系统100可以包括编码设备101以及译码设备102。其中，编码设备101用于对数据流中各个数据块，进行编码，得到每个数据块所对应的码字，并将码字组成码流发送给译码设备102。该数据流可以是视频流、音频流以及文本流等任一个数据流。一个码字也即是编码设备101对一个数据块进行编码的结果，每个码字可以视为一个帧，一个码字中的数据也即是一帧数据。一个码字为一个译码设备译码时的基本数据单元，一个码字可以包括多行多列的比特位，一列或一行比特位可以组成一个子码，也即是一个码字包括多个子码，每个子码包括多个比特位，属于同一个子码的比特位位于一个码字的同一行或同一列。例如，一个码字包括128*128个比特位，其中，每128个比特位为一行，每128个比特位为一列，也即是该码字可以包括128行子码或128列子码。该编码设备101可以采用阶梯(staircase)乘积(turbo product code，TPC)码的编码方案进行编码，该编码方案所得到的码字的比特位被一个横向的BCH(bose ray hocquenghem)子码和一个纵向的BCH子码保护。译码设备101以一帧数据(例如128bit*128bit)为基本单位进行编码，相邻的两个帧中的数据满足BCH(n，k)的编码关系，其中，n为一个BCH子码的码长，k为一个BCH子码的信息位。例如，译码设备101对一个数据流中第0帧和第1帧进行横向BCH(256,239)码字编码，也即是按照行，对第0帧和第1帧中每一行比特位上的数据进行编码，得到编码后的第0帧和编码后的第1帧；然后，译码设备101对编码后的第1帧以及第2帧进行纵向BCH(256,239)码字编码，也即是按照列，对编码后的第1帧以及第2帧的每一列比特位上的数据进行编码，得到2次编码后的第一帧和1次编码后的第2帧，从而2次编码后的第1帧中每个比特位被一个横向上的子码和一个纵向上的子码保护。
译码设备102，用于对接收到的码流中的码字进行译码。译码设备102每接收到一个码字时，均可以对目标个数的码字进行迭代译码，该目标个数的码字可以包括新接收的码字以及之前译码后的码字。
TPC码字是一种典型的二维分组代数码，两个维度可以采用相同或者不同的代数码子码联合编码，其码字构造如图1b所示(这里代数码子码以BCH码为例)。TPC码以一个矩形(多为正方形)的信息块为编码单元，首先对信息块的每一行使用BCH1码进行行编码，编码开销放在信息块右侧；然后再对信息块和行开销的每一列使用BCH2码进行列编码，编码开销放在信息块和行开销的下方。根据BCH码的内在数学原理，右下角部分由信息块和行开销部分编码出的列开销，从行的维度上看也会自动满足行BCH1的编码关系。编码后的信息块与行列开销组成一个更大的矩形数据块单元，即为一个TPC码字。
在译码端，以TPC码字为基本译码单元，进行行列迭代译码。在一定迭代次数内，译码性能随着迭代次数的增加而提升。迭代译码中的行/列译码内核既可以采用复杂度较低的硬判决译码内核，也可以采用性能更优的soft-in-soft-out(SISO)软判决译码内核，亦可设计成可根据条件切换的动态译码架构。
在采用硬判决译码内核时，只需要一个1位位宽的译码缓存RAM_HD。每次行/列译码后只需将RAM_HD中对应位置的比特按照译码结果翻转，在迭代中不断更新RAM_HD中的各个比特取值。在迭代译码完成后，RAM_HD的最终状态即作为译码结果输出。
在采用SISO译码内核时，需要两个多位位宽的译码缓存RAM_LLR和RAM_EX分别用于存 储从信道获取的每个比特的LLR(Log Likel ihood Rat io，对数似然比)值和每次行/列迭代译码后得到的外信息值。在每个TPC码字的译码过程中，RAM_LLR的内容保持不变，而RAM_EX则根据每次行/列译码后得到的外信息值对应更新。每次行/列译码的输入软信息由上一次列/行译码得到的外信息EX_info和LLR值共同计算得到。在迭代译码完成后，可简单的将最后一次译码的硬判决结果作为最终译码结果输出。
本申请公开的译码方法、译码器和译码装置是以子码为单元进行的，例如上述的TPC码字，假设一个n行n列的TPC码字，即总共存在2*n个子码，本申请的译码方法在译码时可以对该2*n子码中每个子码进行译码。
值得注意的是，本申请实施例下文所提到的关断标识缓存、硬判决结果缓存或软信息缓存可以是内存对象缓存系统或存储器，存储器可以包括寄存器、易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)；存储器也可以包括非易失性存储器(non-volatile memory)，例如快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)、云存储(cloud storage)、网络附接存储(Network Attached Storage，NAS)、网盘(network drive)等；存储器还可以包括上述种类的存储器的组合或者其他具有存储功能的任意形态的介质或产品。
为了使本领域技术人员能够更清楚地理解本申请实施例提供的技术方案，下面通过具体的实施例，对本申请的实施例提供的译码方法进行详细说明，示例性的，本实施例中待译码的码字可以采用staircase(阶梯)TPC(Turbo Product Code，Turbo乘积码)编码方案。在对多个子码进行译码时，通常会预设一定次数的译码迭代，在第N次译码迭代中(第N次译码迭代可以是预设次数软判决译码迭代中的除首次译码迭代外的任意一次译码迭代)本申请译码方法具体过程可以包括：
S201、从关断标识缓存中获取待译子码对应的关断标识，从硬判决结果缓存中获取之前存储的待译子码对应的硬判决结果。
译码端，选取待译子码进行译码，每一个待译子码都有对应的关断标识，该关断标识存储在关断标识缓存中，从关断标识缓存中获取待译子码对应的关断标识；同时，设置硬判决结果缓存用于存储译码迭代中的硬判决结果，从硬判决结果缓存中获取之前存储的待译子码对应的硬判决结果。
J201、判断待译子码对应的关断标识表示的数值是否为第二数值。
当待译子码对应的关断标识表示的数值为第二数值(例如为0)时，执行S202；当待译子码对应的关断标识表示的数值不为第二数值或者为第一数值时(例如为1)，执行J203；
待译子码对应的关断标识用于判断在本次译码迭代中是否需要进行待译子码的软判决译码：若待译子码对应的关断标识表示的数值为第二数值(例如为0)，则说明之前的软判决译码过程中尚未得到有效的硬判决结果，继续译码，提升译码性能；若待译子码对应的关断标识表示的数值不为第二数值或者为第一数值时(例如为1)，则说明之前的软判决译码过程中得到了有效的硬判决结果，本次译码迭代不需要再进行软判决译码，进而节省译码次数，降低译码功耗。
值得注意的是，当进行某一子码的第一次迭代译码时，可以直接从步骤S202开始，当进行第二次以及后续的译码迭代时，从步骤S201开始执行。
S202、获取待译子码对应的软信息。
从软信息缓存中获取待译子码在本次译码迭代中对应的软信息。
具体的，待译子码所在的码字采用上述staircase TPC编码方案可以如图3所示，采用该编码方案的每个比特被横向BCH(Bose Ray-Chaudhuri Hocquenghem)1和纵向BCH2两个BCH子码编码保护，故可以称为软判决BCH算法。示例性的，这里横向BCH1和纵向BCH2两个子码均采用BCH(512,491)纠三个错的码字(BCH1和BCH2也可以采用不同的BCH码字实现)。编码以一帧数据(256*256比特)为单位，相邻两帧数据用相同种类的BCH码字编码。如图3所示，第0帧和第1帧即采用横向BCH1(512，491)码字编码，编码后从横向看即为256个512比特长度的BCH码字。然后第1帧接着和第2帧用纵向的BCH2(512,491)码字编码(这里BCH1和2使用相同的BCH编码方案，也可以使用不同的)，编码后从纵向看也是256个512比特长度的BCH码字。
其中，待译子码的软信息，是指该待译子码的每个比特位取值的软信息，包括取值和取值的置信度，其数学表示为每个比特等于1的后验概率与其等于0的后验概率的比值的对数。其取值为正数表示该比特更可能等于1，取值为负数表示该比特更可能等于0，而其绝对值大小则可以表示相应取值的可信程度，绝对值越大该取值越可靠。
示例性的，子码中某一比特位的软信息可以通过以下算法获取：
APP N＝LLR+Ex_inof N-1*α   (1)
其中，APPN表示第N次译码迭代中，上述某一比特的软信息，LLR(Log Likelihood Ratio，对数似然比)表示信道输入的初始置信度，Ex_infoN-1为第(N-1)次迭代译码输出的外信息，α为权重系数，α随迭代过程慢慢增大。
根据上述算发可知，在第1次译码中，获取信道输入的每个子码中的每个比特位的LLR信息作为软信息；在第2次译码及后续软判决译码步骤中，根据信道输入的待译子码中的每个比特位的LLR信息，以及该比特位对应的外信息Ex_info获取该比特位的软信息。
S203、对待译子码进行软判决译码得到新的硬判决结果。
(1)根据待译子码中的每个比特位的软信息，为待译子码生成至少一个测试序列。
上述软判决BCH算法的核心思想是通过有限量的测试错误图样来尝试估计并纠正子码错误，因此测试序列的生成是其中的关键步骤，测试序列的数量也对算法性能有很大的影响。根据上文所述，某一比特位的软信息的绝对值可以表示该比特为取值的可靠程度，绝对值越小说明该比特位的取值越不可靠，其为错误比特的概率也就越大。因此，对于一个码字中的子码，首先选取该子码上软信息的绝对值最小的P个比特位，认为该子码的错误最有可能出现在该P个位置(P为大于零的整数，P的取值可以根据需要设置，此处不做限定)。而后，根据这P个位置构造2P个测试序列(Test Sequence，TS)。具体的构造方法，例如：
选出待译子码的P个比特位后，将待译子码的P个比特位依次遍历0和1取值，并将该子码中除了P个比特位之外的比特位取0，得到2P个基本序列(Basic Sequence，BS)。
示例性的，假设P＝2，并假设这2个位置为子码的第3位和第7位，则分别使上述第3位和第7位依次取值1和0，得到22＝4个BS(BS1-BS4)，如图4所示。
在得到BS后，获取对待译子码的软信息进行硬判决译码得到的待译子码的译码结果，记为D0，将待译子码的D0与该子码的2P个BS获取该子码的2P个TS。具体的，可以将待译子码的D0与该子码的2P个基本序列做模二加法，得到2P个TS。示例性的，利用图4所示的4个BS(BS1-BS4)构造TS，得到的TS(TS1-TS4)可以如图5所示。
(2)根据为待译子码生成的所有测试序列对待译子码进行软判决译码，得到待译子码的至少一个有效子码。
进行软判决译码后得到K个输出子码，即K个有效子码，K≤2P，这是因为有些TS可能超出译码能力从而不能正常译码。
(3)从待译子码的所有有效子码中选取最优有效子码，作为该子码的新的硬判决结果。
示例性的，从待译子码软判决译码后的K个有效子码中选取最优有效子码，可以通过：
首先，获取该子码K个有效子码与该子码软信息之间欧氏距离，这可以根据该子码每个有效子码的每个比特位的取值，以及该码字的每个比特位的软信息，利用欧氏距离公式获取，比如：
Figure PCTCN2020117022-appb-000001
其中，di表示一个子码的K个有效子码中的有效子码i与该子码软信息之间欧氏距离，有效子码i为该码字的K个有效子码中的任意一个，x1k表示有效子码i的第k位的取值，x2k表示该子码第k位的软信息的取值。
需要注意的是，在计算欧式距离时，需要将有效子码中的比特取值从(1,0)相应转化为(1，-1)从而与软信息的取值范围相对应。
根据上述算法，根据K个有效子码就可得到K个欧氏距离，而后选取最小的欧氏距离对应的有效子码为最优有效子码，作为待译子码的新的硬判决结果。
可选地，图3b所示的本申请实施例公开的一种迭代译码过程的示意图，图3b中的滑动窗口的维度为6，设滑动窗口内的码字包括第P-6个码字至第P-1个码字，其中，第P-1个码字为滑动窗口中的第1个码字，第P-6个码字为滑动窗口中的最后一个码字，第P-1个码字也即是第P-1帧数据；当译码设备接收到第P个码字时，滑动窗口向前滑动一个码字，使得第P个码字为该滑动窗口内的第1个码字，第P-6个码字从该滑动窗口滑出，第P-5个码字为滑动窗口的最后一个码字；译码设备开始对第P-5个码字至第P个码字进行迭代译码过程，该迭代译码过程包括迭代译码1-5；译码设备对第P-5个码字至第P个码字进行的迭代译码过程可以是：首先，译码设备102对第P个码字和第P-1个码字进行一次横向软判决译码，得到译码后的第P个码字以及译码后的第P-1个码字，记为迭代译码1；然后，译码设备对译码后的第P-1个码字以及第P-2个码字进行一次纵向软判决译码，得到再次译码后的第P-1个码字以及译码后的第P-2个码字，记为迭代译码2，依次类推译码设备进行迭代译码3-5，当迭代译码5完成后，译码设备将第P-5个码字的译码结果输出，也即是输出译码后的第P-5个码字。其中，横向软判决译码为按照行对码字中的各个子码进行软判决译码，例如，对于一个码字，译码设备先对该码字中的第一行子码进行软判决译码，再对该码字中的第二行子码进行软判决译码，当然，译码设备也可以并行对多行子码进行软判决译码。纵向软判决译码为按照列对码字中的各个子码进行软判决译码，例如，对于一个码字，译码设备102先对该码字中的第一列子码进行软判决译码，再对该码字中的第二列子码进行软判决译码，当然，译码设备可以并行对多列子码进行软判决译码。
J202、判断是否跳出译码迭代。
若本次对待译子码的译码迭代后的译码次数达到预设的最大译码次数，则跳出译码迭代，执行步骤S205；若本次对待译子码的译码迭代后的译码次数未达到预设的最大译码次数，则执行步骤S204。
S204、若新的硬判决结果有效，将新的硬判决结果存储，待译子码对应的关断标识设置 为第一数值；生成待译子码的下一次的软判决译码的软信息。之后执行步骤S207。
(1)判断上述得到的新的硬判决结果是否有效：若新的硬判决结果有效，将新的硬判决结果保存在硬判决结果缓存中，将关断标识缓存中待译子码对应的关断标识表示的数值更新为第一数值，这里关断标识表示的数值为第一数值，用于指示本次软判决译码过程中得到了有效的硬判决结果，下次译码迭代不需要再对本子码进行软判决译码，进而节省译码次数，降低译码功耗。
具体地，可以通过待译子码对应的新的硬判决结果和校验矩阵，来确定该子码的新的硬判决结果是否有效，在一种可能的实现方式中，计算校验矩阵与上述新的硬判决结果的积，当该积为0时，则认为新的硬判决结果有效。
可选地，在BCH译码中，通过计算BCH子码的伴随式来判断新的硬判决结果是否有效。例如，若一次软判决译码的纠错能力为t，也即是可以对t个比特位进行纠错，基于BCH子码的新的硬判决结果，计算2t个伴随式，若2t个伴随式的值全为0，则上述新的硬判决结果有效，若2t个伴随式的值出现非0值，则上述新的硬判决结果无效。这里，通过计算BCH子码的伴随式确定有效是在译码算法中默认的有效，即是译码算法设定的判断译码结果有效的方式，但实际可能存在一定的误码率。本申请对译码算法本身判断译码结果是否有效的方法并不限定。
(2)根据待译子码中的每个比特位的软信息、新的硬判决结果、次优有效子码获取该子码中的每个比特位的外信息，根据该外信息生成下一次的软判决译码的软信息。
由于所用FEC采用卷积编码+窗口译码的方式来提升性能，因此在完成当次软判决译码之后，还需要计算出本次译码获得的每个比特的外信息Ex_info并传递给下一次的软判决译码来生成下一次的软判决译码的软信息，从而实现置信度在译码过程中的有效传递。
示例性的，可以根据以下算法获取外信息：
Figure PCTCN2020117022-appb-000002
其中，wj表示一个子码第j比特位的外信息，R表示软判决译码的输入软信息，D为该子码的最优有效子码，即上述新的硬判决结果，C为次优有效子码(该子码的所有有效子码中除了最优有效子码外最优的有效子码，也可以称为竞争子码)，而dj为D中的第j比特位的取值(1/-1)。由于P的取值有限，所以有可能在K个输出结果中中找不到满足上述要求的C，这时，该比特位的外信息可以采用下面的近似算法获取：
w j＝βd j     (4)
其中，β为权重系数，随着译码流程取值慢慢增加，其具体取值可通过仿真优化得到。
由此可见，每一次软判决译码的译码结果通过外信息影响下一次软判决译码，所以上述某一子码的每一软判决译码也可以称为该子码的一次译码迭代。
可选地，新的硬判决结果与待译子码之前保存的硬判决结果有至少一个第一比特位上的取值不同，例如，本次译码迭代的待译子码为第一行子码，第一行子码上有第一比特位本次硬判决结果与之前保存的硬判决结果取值不同，第一比特位上还对应有第一列子码，第一列子码与第一行子码在第一比特位相交；则第一列子码对应的关断标识设置为第二数值(例如为0)，当关断标识表示的数值为第二数值时，则在下次译码迭代中需要对第一列子码进行软判决译码。
值得一提的是，本申请实施例所提及的第一行子码和第一列子码也可以是两个关联的子码，不需要严格遵循行列通常的排布方式；另外，子码上比特位也不一定都是遵循一排的排列方式，本申请对此并不限定。例如，如图6所示，第一行子码601和第一列子码602在第一比特位603(图6中半圆凸起处)相交，第一行子码601和第一列子码602通过第一比特位603关联，第一比特位603对应有第一行子码601和第一列子码602；第一行子码601和第一列子码602也可以以图6中弯折的形式排布。
S205、输出上述得到的待译子码的新的硬判决结果。之后执行步骤S207，直至进行到所有待译子码的最后一个子码的最后一次译码迭代。
J203、判断是否跳出译码迭代。
若本次对待译子码的译码迭代后的译码次数达到预设的最大译码次数，则跳出译码迭代，执行步骤S205；若本次对待译子码的译码迭代后的译码次数未达到预设的最大译码次数，则执行步骤S206。
S206、根据上次译码存储的硬判决结果生成新的软信息。之后执行步骤S207。
根据获取的上次译码迭代中的硬判决结果生成新的软信息，具体地，根据上次译码迭代中的硬判决结果对应的符号值(硬判决结果每比特数据一般只有0、1两种取值，例如1对应的符号值为正，0对应的符号值为负)和软信息的位宽值生成新的软信息，并将该新的软信息保存在软信息缓存中。一般将硬判决结果对应的符号值和软信息的位宽值的乘积作为输出的软信息；优选地，软信息的位宽值优先选取软信息位宽允许下的最大位宽值或相对较大的位宽值。
S207、转向下一个子码。
本次待译子码的本次译码迭代结束，转向下一个子码的译码迭代，下一个子码可以是行子码，也可以是列子码。
本申请公开的译码方法中，以一个码字中的子码为基本的译码单元，相对于现有技术中以码字为译码单元，提高了译码精度。现有技术中在以码字为译码单元的时候，当一个码字存在一个比特位需要软判决译码时，则需要对整个码字重新进行软判决译码，而本申请的技术方案中的只需要对该比特位所在的子码进行译码，大大节省了译码功耗。
本申请公开的译码方法中，为每个待译的子码添加关断标识，在每次译码迭代后，更新关断标识表示的数值，若有子码已经生成有效的硬判决结果，则将该子码的关断标识表示的数值更新为第一数值，指示下一次译码迭代中不需要再进行软判决译码；若有子码中尚有比特位还未得到有效译码结果，则将该子码的关断标识表示的数值更新为第二数值，指示下一次译码迭代中还需要再进行软判决译码。本申请公开的译码方法大大节省了译码功耗，提高了译码效率。
本申请的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序，应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以本申请未描述的顺序实施。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系。例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。方法实施例中的具体操作方法也可以应用于装置实施例中。此外，为了更加明显地体现不同实施例中的组件的关系，本申请采用相同的附图编号来表示不同实施例中功能相同或相似的组件。
需要说明的是，本申请实施例中所述的至少一个表示“一个”或“一个以上”。示例性的， 包括A、B、C中的至少一个，可能表示如下含义：
(1)包括A
(2)包括B
(3)包括C
(4)包括A和B
(5)包括A和C
(6)包括B和C
(7)包括A、B和C
还需要说明的是，除非特殊说明，一个实施例中针对一些技术特征的具体描述也可以应用于解释其他实施例提及对应的技术特征。例如，一个实施例中关于第二数值或第一数值表示的含义的限定也适用于其它实施例。
图7为本申请公开的一种译码方法的流程图，下述方法流程中以S表示执行类步骤，以J表示判断类步骤，如图7所示，该译码方法包括：
S701、对多个子码中的第一行子码进行软判决译码得到第一硬判决结果。
对码字中多个子码中的第一行子码进行软判决译码，软判决译码过程可参考上述步骤203的相关描述，得到第一硬判决结果。可选地，该第一硬判决结果为第一行子码有效子码，优先选取最优有效子码。
J701、判断是否跳出译码迭代：若是，则执行步骤S704；若否，则执行步骤S702。
若本次对第一行子码的译码迭代后的译码次数达到预设的最大译码次数，则跳出译码迭代，执行步骤S704；若本次第一行子码的译码迭代后的译码次数未达到预设的最大译码次数，则执行步骤S702。
S702、根据上述第一硬判决结果将第一行子码对应的第一关断标识设置为第一数值(例如为1)。
根据上述第一硬判决结果判断该第一硬判决结果是有效的译码结果。第一行子码对应有第一关断标识，第一关断标识存储在关断标识缓存中，将第一关断标识表示的数值设置为第一数值。第一关断标识用于指示在下一次译码迭代中是否对上述第一行子码进行软判决译码，当第一关断标识表示的数值为第一数值(例如为1)时，则在下次译码迭代中不对第一行子码进行软判决译码，因为在S701步骤中已经得到了有效的第一硬判决结果。
S703、保存上述第一硬判决结果。
将第一硬判决结果保存在硬判决结果缓存中。之后可以选择执行步骤S705。
S704、输出上述第一硬判决结果。
步骤S701-步骤S704为对某一子码第一次译码迭代所经历的步骤。
步骤S705、S706为可选步骤：
S705、将第一列子码对应的关断标识设置为第二数值。
在进行步骤S701之前，若硬判决结果缓存中，存储有在之前对第一行子码进行软判决译码保存的硬判决结果，本次一次译码迭代得到的第一硬判决结果与之前保存的第一行子码的硬判决结果有至少一个第一比特位上的取值不同，该第一比特位对应有第一列子码，第一列子码与第一行子码在该第一比特位相交；
将上述第一列子码对应的关断标识设置为第二数值(例如为0)，当第一关断标识表示的数值为第二数值时，则在下次译码迭代中需要对上述第一列子码进行软判决译码。
S706、对下一个子码进行译码迭代。
第一行子码的本次译码迭代(例如第五次)完成后，对下一个子码进行本次译码迭代(例如第五次)，下一个子码可以是行子码，也可以是列子码。
当码字中所有待译子码均进行完本次译码迭代后，再进行下一次译码迭代，直到码字的所有待译子码均完成预设次数的译码迭代后，译码完毕。
在一种可能的实施方式中，步骤S706中对下一个子码进行译码迭代可以包括如下步骤，如图8所示：
S801、获取多个子码中的第二子码对应的第二关断标识，该第二关断标识表示的数值为所述第一数值(例如为1)。
由于第二子码对应的第二关断标识表示的数值为第一数值，表明在之前的译码迭代中已经获得第二子码的有效的硬判决结果，所以在本次译码迭代中不需要对上述第二子码进行软判决译码。
S802、获取上述第二子码的第二硬判决结果，该第二硬判决结果为在当前的译码迭代之前的译码迭代中得到的有效的硬判决结果。
J801、判断是否跳出译码迭代，当不跳出译码迭代时，执行步骤S803；当跳出译码迭代时，执行步骤S804。
S803、根据上述第二硬判决结果生成第二软信息，该第二软信息用于在下一次对所述第二子码的译码迭代中进行软判决译码。
可选地，根据第二硬判决结果对应的符号值(硬判决结果每比特数据一般只有0、1两种取值，例如1对应的符号值为正，0对应的符号值为负)和第二软信息的位宽值生成第二软信息，并将该第二软信息保存在软信息缓存中。优选地，第二软信息的位宽值优先选取第二软信息的最大的位宽值或相对较大的位宽值。
S804、将上述第二硬判决结果输出。
步骤S801-S804展示了多个子码中有第二子码已经获得有效的硬判决结果后的译码过程。
在另一种可能的实施方式中，步骤S706中对下一个子码进行译码迭代还可以包括如下步骤，如图9所示：
S901、获取多个子码中的第三子码对应的第三关断标识，该第三关断标识表示的数值为上述第二数值(例如为0)。
由于第三子码对应的第三关断标识表示的数值为第二数值，表明在之前译码迭代中尚未得到第三子码的有效的硬判决结果，在本次译码迭代中，需要对第三子码进行软判决译码。
S902、获取第三子码对应的第三软信息，该第三软信息为在之前的译码迭代中保存的第三子码对应的第三软信息。
S903、根据上述第三软信息对第三子码进行软判决译码得到第三硬判决结果。
J901、判断上述第三硬判决结果是否有效，若该第三硬判决结果有效，执行步骤S904；若该第三硬判决结果无效，则可以选择执行步骤S905。
可选地，在BCH译码中，通过计算BCH子码的伴随式来判断新的硬判决结果是否有效。
S904、生成新的第三软信息，该新的第三软信息用于后续对第三子码的译码迭代；将第三子码对应的第三关断标识表示的数值更新为上述第一数值。
由于已经得到第三子码的有效的硬判决结果，下一次译码迭代中为了节省译码功耗不需要再对第三子码进行软判决译码，故将第三子码对应的第三关断标识表示的数值更新为第一 数值。
具体地，根据第三子码中的每个比特位的软信息、第三硬判决结果获取第三子码中的每个比特位的外信息，根据该外信息生成新的第三软信息。
可选地，若本次对第三子码的译码迭代为预设的最后一次译码迭代，则跳出译码迭代，输出上述第三硬判决结果。
S905、若第三硬判决结果无效，则第三关断标识表示的数值保持不变，同时若本次对第三子码的译码迭代为预设的最后一次译码迭代，则输出第三子码的译码失败指示信息。
步骤S901-S905展示了多个子码中有第三子码尚未获得有效的硬判决结果后的译码过程。
本实施例公开的译码方法中，分别公开了对子码进行第一次译码迭代的译码流程、对已经获得有效硬判决结果的子码的译码流程和对尚未获得有效硬判决结果的子码的译码流程。本申请公开的译码方法大大节省了译码功耗，提高了译码效率。
图10为本申请实施例公开的一种译码器，如图10所示，该译码器1000包括处理器1001、第一存储器1002、第二存储器1003；
处理器1001，用于对多个子码中的第一行子码进行软判决译码得到第一硬判决结果；
第二存储器1003，用于存储上述第一硬判决结果；
第一存储器1002，用于存储上述第一行子码对应的第一关断标识；
处理器1001，还用于将上述第一关断标识设置为第一数值，该第一关断标识用于指示在下一次译码迭代中是否对所述第一行子码进行软判决译码，当第一关断标识表示的数值为所述第一数值时，则在下次译码迭代中不对所述第一行子码进行软判决译码；
处理器1001，还用于将上述第一硬判决结果保存在第二存储器1003中。
第一存储器和第二存储器仅仅是为了区分存储不同的信息，在实际可能是同一个存储器的不同部分，例如可能是同一个存储器中的两个独立的缓存或RAM。
在一种可能的实施方式中，译码器1000还可以包括输出接口1005，输出接口1005用于将对上述第一行子码译码得到的第一硬判决结果输出。
在一种可能的设计中，处理器1001还用于判断上述第一硬判决结果与上述对第一行子码进行软判决译码之前保存的硬判决结果有至少一个第一比特位上的取值不同，该第一比特位对应有第一列子码，第一列子码与第一行子码在第一比特位上相交；
处理器1001还用于将上述第一列子码对应的关断标识设置为第二数值，当第一列子码对应的关断标识表示的数值为第二数值时，则在下一次译码迭代中需要对上述第一列子码进行软判决译码。
在另一种可能的实施方式中，译码器1000还包括输入接口1004，
输入接口1004，用于获取多个子码中的第二子码对应的第二关断标识，该第二关断标识表示的数值为第一数值；
输入接口1004，还用于获取第二子码的第二硬判决结果；
处理器1001，还用于判断是否跳出译码迭代，当不跳出译码迭代时：
处理器1001根据上述第二硬判决结果生成第二软信息，该第二软信息用于在下一次对所述第二子码的译码迭代中进行软判决译码；
当跳出译码迭代时：
输出接口1005还用于将上述第二硬判决结果输出。
在一种可能的设计中，输入接口1004还用于获取上述多个子码中的第三子码对应的第三 关断标识，该第三关断标识表示的数值为第二数值；
输入接口1004还用于获取第三子码对应的第三软信息；
处理器1001还用于根据上述第三软信息对第三子码进行软判决译码得到第三硬判决结果；
当处理器1001判断上述第三硬判决结果有效：处理器1001还用于生成新的第三软信息，该新的第三软信息用于后续对第三子码的译码迭代；处理器901还用于将上述第三关断标识表示的数值更新为第一数值。
进一步地，处理器1001根据上述第三软信息对第三子码进行软判决译码得到第三硬判决结果后，处理器1001还用于跳出译码迭代，输出接口1005还用于输出上述第三硬判决结果。
处理器1001判断是否跳出译码迭代，包括：
处理器1001比较当前的迭代次数是否达到预设的迭代次数：当当前的迭代次数达到预设的迭代次数，则跳出译码迭代；当前的迭代次数未达到预设的迭代次数，不跳出译码迭代。
图11为本申请实施例公开的一种译码器，如图11所示，该译码器1100包括：软判决译码模块1101、切换模块1102、关断模块1103和输出模块1105；
软判决译码模块1101，用于对多个子码中的第一行子码进行软判决译码得到第一硬判决结果；
切换模块1102，用于判断是否跳出译码迭代，当不跳出译码迭代时：
关断模块1103将第一行子码对应的第一关断标识设置为第一数值，该第一关断标识用于指示在下一次译码迭代中是否对上述第一行子码进行软判决译码，当第一关断标识表示的数值为上述第一数值时，则在下次译码迭代中不对所述第一行子码进行软判决译码；
当跳出译码迭代时：
输出模块1105将对所述第一行子码译码得到的所述第一硬判决结果输出。
在一种可能的实现方式中，上述第一硬判决结果与上述对第一行子码进行软判决译码之前保存的硬判决结果有至少一个第一比特位上的取值不同，该第一比特位对应有第一列子码，第一列子码与第一行子码在第一比特位相交；
关断模块1103将上述第一列子码对应的关断标识设置为第二数值，当第一列子码对应的关断标识表示的数值为第二数值时，则在下次译码迭代中对第一列子码进行软判决译码。
在一种可能的实现方式中，上述译码器1100还包括获取模块1104：
获取模块1104，用于获取多个子码中的第二子码对应的第二关断标识，该第二关断标识表示的数值为第一数值；
获取模块1104，还用于获取第二子码的第二硬判决结果，所述第二硬判决结果为在当前的译码迭代之前的译码迭代中得到的有效的硬判决结果；
切换模块1102，用于判断是否跳出译码迭代，当不跳出译码迭代时：
软判决译码模块1101根据上述第二硬判决结果生成第二软信息，该第二软信息用于在下一次对第二子码的译码迭代中进行软判决译码；
当跳出译码迭代时：
输出模块1105将上述第二硬判决结果输出。
可选地，根据所述第二硬判决结果对应的符号值和所述第二软信息的位宽值生成所述第二软信息。
在一种可能的实现方式中，获取模块1104，还用于获取多个子码中的第三子码对应的第 三关断标识，该第三关断标识表示的数值为第二数值；
获取模块1104，还用于获取所述第三子码对应的第三软信息；
软判决译码模块1101，还用于根据上述第三软信息对所述第三子码进行软判决译码得到第三硬判决结果；
软判决译码模块1101，还用于判断第三硬判决结果是否有效，若第三硬判决结果有效：
软判决译码模块1101生成新的第三软信息，该新的第三软信息用于后续对上述第三子码的译码迭代；关断模块1103将第三关断标识表示的数值更新为所述第一数值。
图12为本申请实施例公开的一种译码装置，如图12所示，该译码装置包括：
存储器1201，用于存储程序；
处理器1202，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如上述方法实施例中所描述的任意一种方法。
可选地，该译码装置为芯片或集成电路。
本申请实施例还公开了一种计算机可读存储介质，该计算机存储介质中存储有计算机可读指令，当计算机读取并执行所述计算机可读指令时，使得计算机执行如上述方法实施例中所描述的任意一种方法。
本申请实施例还公开了一种计算机程序产品，当计算机读取并执行所述计算机程序产品时，使得计算机执行如上述方法实施例中所描述的任意一种方法。
本申请实施例提供了一种计算机可读存储介质，包括计算机可读指令，当计算机读取并执行所述计算机可读指令时，使得计算机执行上述处理器所执行的方法。
本申请实施例还提供了一种包含指令的计算机程序产品，当计算机程序产品在计算机上运行时，使得计算机执行上述处理器所执行的方法。
本申请中的各个实施例之间相同相似的部分互相参见即可，尤其，对于图9-图10实施例而言，由于基于图2-图8对应的实施例，所以描述的比较简单，相关之处参见图2-图8对应实施例的部分说明即可。
显然，本领域的技术人员应该明白，上述本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储介质(ROM/RAM、磁碟、光盘)中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。所以，本发明不限制于任何特定的硬件和软件结合。
最后应说明的是：以上所述仅为本申请的具体实施方式，本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。

Claims (18)

  1. 一种译码方法，其特征在于，所述方法包括：
    对码字的多个子码中的第一行子码进行软判决译码得到第一硬判决结果；
    判断是否跳出译码迭代，当不跳出译码迭代时：
    根据所述第一硬判决结果将所述第一行子码对应的第一关断标识设置为第一数值，所述第一关断标识用于指示在下一次译码迭代中是否对所述第一行子码进行软判决译码，当所述第一关断标识表示的数值为所述第一数值时，则在下次译码迭代中不对所述第一行子码进行软判决译码；
    保存所述第一硬判决结果。
  2. 如权利要求1所述的方法，其特征在于，所述方法还包括：
    所述第一硬判决结果与所述对第一行子码进行软判决译码之前保存的硬判决结果有至少一个第一比特位上的取值不同，所述第一比特位对应有第一列子码，所述第一列子码与所述第一行子码在所述第一比特位相交；
    将所述第一列子码对应的关断标识设置为第二数值，当所述第一列子码对应的关断标识表示的数值为所述第二数值时，则在下次译码迭代中对所述第一列子码进行软判决译码。
  3. 如权利要求1或2任一所述的方法，其特征在于，所述方法还包括：
    获取所述多个子码中的第二子码对应的第二关断标识，所述第二关断标识表示的数值为所述第一数值；
    获取所述第二子码的第二硬判决结果，所述第二硬判决结果为在当前的译码迭代之前的译码迭代中得到的有效的硬判决结果；
    判断是否跳出译码迭代，当不跳出译码迭代时：
    根据所述第二硬判决结果生成第二软信息，所述第二软信息用于在下一次对所述第二子码的译码迭代中进行软判决译码；
    当跳出译码迭代时：
    将所述第二硬判决结果输出。
  4. 如权利要求3所述的方法，其特征在于，所述根据所述第二硬判决结果生成第二软信息，包括：
    根据所述第二硬判决结果对应的符号值和所述第二软信息的位宽值生成所述第二软信息。
  5. 如权利要求1至4任一所述的方法，其特征在于，所述方法还包括：
    获取所述多个子码中的第三子码对应的第三关断标识，所述第三关断标识表示的数值为所述第二数值；
    获取所述第三子码对应的第三软信息；
    根据所述第三软信息对所述第三子码进行软判决译码得到第三硬判决结果；
    判断所述第三硬判决结果是否有效，若所述第三硬判决结果有效：
    生成新的第三软信息，所述新的第三软信息用于后续对所述第三子码的译码迭代；
    将所述第三关断标识表示的数值更新为所述第一数值。
  6. 如权利要求5任一所述的方法，其特征在于，所述根据所述第三软信息对所述第三子码进行软判决译码得到所述第三硬判决结果后，所述方法还包括：
    判断当前译码迭代为预设次数的译码迭代中的最后一次译码迭代；
    跳出译码迭代；
    输出所述第三硬判决结果。
  7. 如权利要求5或6所述的方法，其特征在于，所述判断第三硬判决结果是否有效，包括：
    根据所述对第三子码得到的第三硬判决结果，计算所述第三子码对应的伴随式矩阵；
    根据所述第三子码对应的伴随式矩阵的取值，确定所述第三硬判决结果是否有效。
  8. 一种译码器，其特征在于，所述译码器包括：处理器、第一存储器和第二存储器；
    所述处理器用于对码字的多个子码中的第一行子码进行软判决译码得到第一硬判决结果；
    所述第一存储器用于存储所述第一行子码对应的第一关断标识；
    所述第二存储器用于存储所述第一硬判决结果；所述处理器还用于将所述第一关断标识设置为第一数值，所述第一关断标识用于指示在下一次译码迭代中是否对所述第一行子码进行软判决译码，当所述第一关断标识表示的数值为所述第一数值时，则在下次译码迭代中不对所述第一行子码进行软判决译码；
    所述处理器还用于将所述第一硬判决结果保存在所述第二存储器中。
  9. 如权利要求8所述的译码器，其特征在于，所述译码器还包括输出接口，所述输出接口用于将对所述第一行子码译码得到的所述第一硬判决结果输出。
  10. 如权利要求8或9任一所述的译码器，其特征在于，
    所述处理器还用于判断所述第一硬判决结果与所述对第一行子码进行软判决译码之前保存的硬判决结果有至少一个第一比特位上的取值不同，所述第一比特位对应有第一列子码，所述第一列子码与所述第一行子码在所述第一比特位相交；
    所述处理器还用于将所述第一列子码对应的关断标识设置为第二数值，当所述第一列子码对应的关断标识表示的数值为所述第二数值时，则在下一次译码迭代中对所述第一列子码进行软判决译码。
  11. 如权利要求8至10任一所述的译码器，其特征在于，所述译码器还包括输入接口，
    所述输入接口用于获取所述多个子码中的第二子码对应的第二关断标识，所述第二关断标识表示的数值为所述第一数值；
    所述输入接口还用于获取第二子码的第二硬判决结果；
    所处处理器用于判断是否跳出译码迭代，当不跳出译码迭代时：
    所述处理器根据所述第二硬判决结果生成第二软信息，所述第二软信息用于在下一次对所述第二子码的译码迭代中进行软判决译码；
    当跳出译码迭代时：
    所述输出接口还用于将对所述第二子码译码得到的所述第二硬判决结果输出。
  12. 如权利要求8至11任一所述的译码器，其特征在于，
    所述输入接口还用于获取所述多个子码中的第三子码对应的第三关断标识，所述第三关断标识表示的数值为所述第二数值；
    所述输入接口还用于获取所述第三子码对应的第三软信息；
    所述处理器还用于根据所述第三软信息对所述第三子码进行软判决译码得到第三硬判决结果；
    当所述处理器判断所述第三硬判决结果有效：
    所述处理器还用于生成新的第三软信息，所述新的第三软信息用于后续对所述第三子码 的译码迭代；
    所述处理器还用于将所述第三关断标识表示的数值更新为所述第一数值。
  13. 如权利要求12任一所述的译码器，其特征在于，所述处理器根据所述第三软信息对所述第三子码进行软判决译码得到所述第三硬判决结果后，
    所述处理器还用于跳出译码迭代；
    所述输出接口还用于输出所述第三硬判决结果。
  14. 如权利要求11所述的译码器，其特征在于，所述处理器判断是否跳出译码迭代，包括：
    所述处理器比较当前的迭代次数是否达到预设的迭代次数：
    当当前的迭代次数达到预设的迭代次数，则跳出译码迭代；当前的迭代次数未达到预设的迭代次数，不跳出译码迭代。
  15. 一种译码装置，其特征在于，所述译码装置包括：
    存储器，用于存储程序；
    处理器，用于执行所述存储器存储的所述程序，当所述程序被执行时，所述处理器用于执行如权利要求1-7任一项所述的方法。
  16. 如权利要求15所述的装置，其特征在于，所述译码装置为芯片或集成电路。
  17. 一种计算机可读存储介质，其特征在于，所述计算机存储介质中存储有计算机可读指令，当计算机读取并执行所述计算机可读指令时，使得计算机执行如权利要求1-7任意一项所述的方法。
  18. 一种计算机程序产品，其特征在于，当计算机读取并执行所述计算机程序产品时，使得计算机执行如权利要求1-7任意一项所述的方法。
PCT/CN2020/117022 2019-12-30 2020-09-23 译码方法、译码器和译码装置 WO2021135426A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP20908654.5A EP4072023A4 (en) 2019-12-30 2020-09-23 DECODING METHOD AND DECODER DEVICE
US17/852,218 US11750219B2 (en) 2019-12-30 2022-06-28 Decoding method, decoder, and decoding apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911393850.1A CN113131947B (zh) 2019-12-30 2019-12-30 译码方法、译码器和译码装置
CN201911393850.1 2019-12-30

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/852,218 Continuation US11750219B2 (en) 2019-12-30 2022-06-28 Decoding method, decoder, and decoding apparatus

Publications (1)

Publication Number Publication Date
WO2021135426A1 true WO2021135426A1 (zh) 2021-07-08

Family

ID=76686397

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/117022 WO2021135426A1 (zh) 2019-12-30 2020-09-23 译码方法、译码器和译码装置

Country Status (4)

Country Link
US (1) US11750219B2 (zh)
EP (1) EP4072023A4 (zh)
CN (1) CN113131947B (zh)
WO (1) WO2021135426A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114421976B (zh) * 2022-01-25 2023-09-08 电子科技大学 基于概率计算的tpc迭代译码方法及译码器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060045214A1 (en) * 2004-08-31 2006-03-02 Sanyo Electric Co., Ltd Receiving method and apparatus for variable rate
CN103503319A (zh) * 2013-04-03 2014-01-08 华为技术有限公司 一种译码方法、译码装置和通信系统
CN104092470A (zh) * 2014-07-25 2014-10-08 中国人民解放军国防科学技术大学 一种Turbo码译码装置及方法
CN104579369A (zh) * 2014-12-18 2015-04-29 中国科学院自动化研究所 一种Turbo迭代译码方法和译码装置
CN108347297A (zh) * 2017-01-25 2018-07-31 华为技术有限公司 一种编码方法、译码方法、编码装置及译码装置
CN106537787B (zh) * 2014-07-31 2019-10-22 华为技术有限公司 译码方法和译码器

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6460160B1 (en) * 2000-02-14 2002-10-01 Motorola, Inc. Chase iteration processing for decoding input data
KR20040086872A (ko) * 2003-03-22 2004-10-13 김환용 터보 복호기의 반복복호 횟수 제어장치 및 그 방법
US20080052594A1 (en) 2006-07-28 2008-02-28 Yedidia Jonathan S Method and system for replica group-shuffled iterative decoding of quasi-cyclic low-density parity check codes
US8341502B2 (en) * 2010-02-28 2012-12-25 Densbits Technologies Ltd. System and method for multi-dimensional decoding
CN102571108B (zh) * 2012-02-24 2014-02-26 清华大学深圳研究生院 一种应用于Turbo乘积码的自适应迭代译码方法
US9197365B2 (en) * 2012-09-25 2015-11-24 Nvidia Corporation Decoding a coded data block
US9755665B1 (en) * 2014-09-23 2017-09-05 Marvell International Ltd. Systems and methods for an iterative decoding scheme
KR20160046467A (ko) * 2014-10-21 2016-04-29 에스케이하이닉스 주식회사 컨트롤러, 반도체 메모리 시스템, 데이터 저장 시스템 및 그것의 동작 방법
US20160283321A1 (en) * 2015-03-28 2016-09-29 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and Methods for Flash Memory Access
US10419024B2 (en) * 2017-05-26 2019-09-17 SK Hynix Inc. Early termination of low-density parity-check (LDPC) decoding
CN113225091A (zh) * 2015-07-08 2021-08-06 北京忆芯科技有限公司 Ldpc解码方法及其装置
US10164656B2 (en) * 2016-03-30 2018-12-25 Silicon Motion Inc. Bit flipping algorithm for providing soft information during hard decision hard decoding
US10187086B2 (en) * 2017-03-15 2019-01-22 SK Hynix Inc. State-based decoding of product codes
JP6840591B2 (ja) * 2017-03-24 2021-03-10 キオクシア株式会社 復号装置
US10511326B2 (en) * 2017-11-14 2019-12-17 Nyquist Semiconductor Limited Systems and methods for decoding error correcting codes

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060045214A1 (en) * 2004-08-31 2006-03-02 Sanyo Electric Co., Ltd Receiving method and apparatus for variable rate
CN103503319A (zh) * 2013-04-03 2014-01-08 华为技术有限公司 一种译码方法、译码装置和通信系统
CN104092470A (zh) * 2014-07-25 2014-10-08 中国人民解放军国防科学技术大学 一种Turbo码译码装置及方法
CN106537787B (zh) * 2014-07-31 2019-10-22 华为技术有限公司 译码方法和译码器
CN104579369A (zh) * 2014-12-18 2015-04-29 中国科学院自动化研究所 一种Turbo迭代译码方法和译码装置
CN108347297A (zh) * 2017-01-25 2018-07-31 华为技术有限公司 一种编码方法、译码方法、编码装置及译码装置

Also Published As

Publication number Publication date
CN113131947B (zh) 2023-11-10
EP4072023A1 (en) 2022-10-12
CN113131947A (zh) 2021-07-16
US11750219B2 (en) 2023-09-05
EP4072023A4 (en) 2023-01-11
US20220329260A1 (en) 2022-10-13

Similar Documents

Publication Publication Date Title
US11784666B2 (en) Decoding signals by guessing noise
KR101535225B1 (ko) 디코딩 방법 및 그 방법을 이용하는 메모리 시스템 장치
US7853854B2 (en) Iterative decoding of a frame of data encoded using a block coding algorithm
WO2015139160A1 (zh) 一种动态阈值比特翻转的ldpc码硬判决译码方法
JP4777876B2 (ja) ターボデコーダの反復の早期終了
KR20110031092A (ko) 메모리 시스템 및 메모리 시스템의 제어 방법
WO2014075267A1 (zh) 译码处理方法及译码器
KR101261091B1 (ko) 반복 복호수 설정 방법, 반복 복호화 장치 및 그 방법
US20100146372A1 (en) Decoding of serial concatenated codes using erasure patterns
US9219501B2 (en) LDPC encoding/decoding method and device using same
WO2021135426A1 (zh) 译码方法、译码器和译码装置
WO2016015288A1 (zh) 译码方法和译码器
KR20200087211A (ko) 계단 코드의 디코딩 방법, 장치 및 기억매체
KR101206137B1 (ko) 모바일 와이맥스용 ｌｄｐｃ 복호기
WO2008134950A1 (fr) Procédé et dispositif permettant de décoder un code zigzag
RU2811072C1 (ru) Способ декодирования, декодер и устройство декодирования
US8402340B2 (en) Parity-check-code decoder and recording controller
KR101496052B1 (ko) 블록 단위 연접 bch 부호 성능 개선 및 오류마루 경감을 위해 순환 자리 이동을 활용하는 복호 기법 및 회로
KR101154923B1 (ko) 비씨에이치 디코더, 이를 포함하는 메모리 시스템 및 비씨에이치 디코딩 방법
WO2021120729A1 (zh) 译码方法、设备、可读存储介质、芯片及计算机程序产品
KR20140006444A (ko) 연접 비씨에이치 부호, 복호 및 다계층 복호 회로 및 방법, 이를 이용한 플래쉬 메모리 장치의 오류 정정 회로 및 플래쉬 메모리 장치
KR20120000040A (ko) 반복 복호수 설정 방법, ｌｄｐｃ 복호화 장치 및 그 방법
CN109245775B (zh) 一种译码器及其实现译码的方法
WO2011144161A1 (zh) 前向纠错方法、装置及系统
KR101190522B1 (ko) 비씨에이치 디코더, 이를 포함하는 메모리 시스템 및 비씨에이치 디코딩 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20908654

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020908654

Country of ref document: EP

Effective date: 20220708

NENP Non-entry into the national phase

Ref country code: DE