WO2021135014A1 - 单晶压电结构及具有其的电子设备 - Google Patents

单晶压电结构及具有其的电子设备 Download PDF

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Publication number
WO2021135014A1
WO2021135014A1 PCT/CN2020/088724 CN2020088724W WO2021135014A1 WO 2021135014 A1 WO2021135014 A1 WO 2021135014A1 CN 2020088724 W CN2020088724 W CN 2020088724W WO 2021135014 A1 WO2021135014 A1 WO 2021135014A1
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electrode
layer
single crystal
piezoelectric
pin
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PCT/CN2020/088724
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English (en)
French (fr)
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庞慰
张孟伦
杨清瑞
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诺思(天津)微系统有限责任公司
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/05—Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
    • H10N30/057—Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes by stacking bulk piezoelectric or electrostrictive bodies and electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/06—Forming electrodes or interconnections, e.g. leads or terminals
    • H10N30/063—Forming interconnections, e.g. connection electrodes of multilayered piezoelectric or electrostrictive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals
    • H10N30/871—Single-layered electrodes of multilayer piezoelectric or electrostrictive devices, e.g. internal electrodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0257—Microphones or microspeakers

Definitions

  • the embodiments of the present invention relate to the field of semiconductors, and in particular to a single crystal piezoelectric structure, and an electronic device with the structure.
  • MEMS Micro-Electro-Mechanical System
  • the internal structure size of MEMS devices is generally micron or nanometer level, and MEMS is an independent intelligent system.
  • MEMS devices can convert one form of energy into another form of energy, such as converting electrical energy into mechanical energy or mechanical energy into electrical energy.
  • the MEMS transducer involved in the present invention refers to a transducer that can mutually convert the mechanical energy of sound waves and electrical energy.
  • MEMS devices require piezoelectric materials to achieve different forms of energy conversion. When an alternating electric field is applied to the piezoelectric material, the piezoelectric material will vibrate according to the frequency of the applied alternating electric field.
  • the amplitude value will be greatly increased. Increase, have higher energy conversion efficiency at this frequency, and have greater emission sensitivity when the MEMS device is used as a transducer.
  • the sound wave when transmitted to the piezoelectric material, it will cause the vibration and deformation of the piezoelectric material. This vibration will cause alternating charge distribution on the electrodes at both ends of the piezoelectric material.
  • the frequency of the sound wave is in the MEMS At the resonant frequency of the device, it has higher energy conversion efficiency at this frequency, and when the MEMS device is used as a transducer, it has greater receiving sensitivity.
  • the piezoelectric film materials of traditional piezoelectric MEMS devices are mostly prepared by physical or chemical deposition techniques such as magnetron sputtering. They are polycrystalline piezoelectric films with poor piezoelectric properties (mainly reflected in low electromechanical coupling coefficient) and defects High density (mainly reflected in low quality factor), poor heat dissipation (mainly reflected in low power capacity), and limited choice of crystal orientation (the optimal crystal orientation and piezoelectric coefficient for device design cannot be selected). These defects lead to insufficient performance of polycrystalline piezoelectric MEMS devices, such as low Q value, low sensitivity, and high insertion loss.
  • a single crystal piezoelectric structure including:
  • each piezoelectric layer is a single crystal piezoelectric layer
  • a plurality of electrodes, electrodes are provided on the upper and lower sides of each piezoelectric layer, and the plurality of piezoelectric layers and the plurality of electrodes together form a laminated structure laminated in the thickness direction of the single crystal piezoelectric structure;
  • the base, the laminated structure is arranged on the base;
  • the overlapping area of the plurality of piezoelectric layers, the plurality of electrodes and the acoustic mirror in the thickness direction of the piezoelectric layer constitutes the effective area of the single crystal piezoelectric structure
  • Each electrode has an electrode connection part arranged on the same layer
  • the layer structure on the upper side of the electrode connection part of at least one of the other electrodes is removed to expose the electrode connection part.
  • the embodiment of the present invention also relates to an electronic device including the above-mentioned single crystal piezoelectric structure.
  • Fig. 1 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of a single crystal piezoelectric coupled resonant filter according to an exemplary embodiment of the present invention
  • Fig. 3 is a schematic top view of the single crystal piezoelectric coupling resonator filter in Fig. 2;
  • FIG. 4 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention, in which cross-electrode pins are provided;
  • FIG. 5 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention, in which cross-electrode pins are provided;
  • Fig. 6 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention, in which cross-electrode pins are provided;
  • FIG. 7 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention, in which cross-electrode pins are provided;
  • FIG. 8 is a schematic cross-sectional view of a single crystal piezoelectric coupled resonant filter according to an exemplary embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view of the single crystal piezoelectric coupled resonant filter taken along the A-A direction in FIG. 8;
  • Fig. 10 is a schematic cross-sectional view of a single crystal piezoelectric coupled resonant filter according to another exemplary embodiment of the present invention.
  • the present invention proposes a MEMS device structure using single crystal piezoelectric film material.
  • Single crystal piezoelectric film materials can make up for the shortcomings of traditional polycrystalline piezoelectric film materials.
  • Piezoelectric MEMS fabricated by it has a larger electromechanical coupling coefficient, a higher Q value, and a higher power capacity. Higher sensitivity, lower insertion loss, etc.
  • the device structure proposed in the present invention is a universal structure suitable for a variety of single crystal piezoelectric MEMS devices, and can be used for single crystal piezoelectric MEMS ultrasonic transducers (Ultrasonic Transducers), single crystal piezoelectric MEMS microphones (Microphone ), single crystal piezoelectric MEMS speaker (Speaker) and single crystal piezoelectric MEMS hydrophone (Hydrophone), single crystal piezoelectric coupled resonator filter (Coupled Resonator Filter), etc. Since the preparation method of the single crystal piezoelectric film is different from that of the traditional polycrystalline piezoelectric film, the manufacturing method and device structure of the single crystal piezoelectric MEMS device are also very different from the traditional polycrystalline piezoelectric MEMS device.
  • Fig. 1 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention.
  • 01 is the substrate of the device; 10 is the cavity structure at the bottom of the device. In this embodiment, the cavity structure is a through hole passing through the substrate, and 10 is the acoustic mirror structure of the device. It can also be other components.
  • Effect form 02 is the bottom electrode of the device; 03 is the first single crystal piezoelectric layer of the device; 04 is the middle electrode of the device; 05 is the second single crystal piezoelectric layer of the device; 06 is the top electrode of the device; A is The middle electrode connection part; B is the bottom electrode connection part.
  • the materials of the first single crystal piezoelectric layer and the second single crystal piezoelectric layer may both be single crystal lithium niobate (LiNbO 3 ) materials. It can also be other materials, such as single crystal lithium tantalate (LiTaO 3 ), single crystal aluminum nitride (AlN), quartz (Quartz), single crystal lead zirconate titanate (PZT), lead magnesium niobate-lead titanate ( At least one of PMN-PT).
  • the electrode constituent material may be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a composite or alloy of the above metals.
  • the substrate may be silicon (Si), single crystal lithium niobate (LiNbO3), silicon carbide (SiC), sapphire (Al 2 O 3 ), quartz (Quartz), and the like.
  • the area where the top electrode, the second single crystal piezoelectric layer, the middle electrode, the first single crystal piezoelectric layer, the bottom electrode and the cavity overlap in the vertical direction is the effective area of the device, as shown in Figure 1. Shown in the middle D area.
  • the area of the upper film structure is always less than or equal to the area of the lower film structure.
  • the top electrode 06 and a part of the right side of the second single crystal piezoelectric layer 05 can be removed by processing methods such as photolithography and etching, and a part of the middle electrode 04 is exposed as the middle electrode connecting portion A; then the top electrode 06 , The second single crystal piezoelectric layer 05, the middle electrode 04, and a part of the left side of the first single crystal piezoelectric layer 03 are etched away, and a part of the bottom electrode 02 is exposed as the bottom electrode connecting portion B.
  • a method similar to the above can also be used to expose each corresponding electrode connection part.
  • the bottom electrode connecting portion B is located on the left side of the effective area
  • the middle electrode connecting portion A is located on the right side of the effective area.
  • the electrode connecting portion is located on one side of the effective area, which means that it is outside the effective area, and, for example, in the figure shown, it is located on the left or right of the effective area.
  • the structure of the single crystal piezoelectric MEMS device is a five-layer thin-film stack structure, its energy conversion efficiency is twice as high as that of an ordinary three-layer structure.
  • the materials used in the first piezoelectric layer and the second piezoelectric layer are both single crystal piezoelectric materials, the electromechanical coupling coefficient of the device is much higher than that of ordinary polycrystalline piezoelectric materials. Therefore, the corresponding single crystal piezoelectric materials Electrical MEMS devices have higher transmit and receive sensitivity and lower insertion loss.
  • the energy conversion efficiency of the single-crystal piezoelectric MEMS device can be further optimized, and the crystal orientation of the first piezoelectric layer and the second piezoelectric layer are the same or opposite.
  • the crystal orientation here can be arbitrarily selected, because the characteristic of single crystal film is that it can provide films with any crystal orientation according to the device design needs; but the polycrystalline piezoelectric film is not the case, generally only in a fixed The piezoelectric properties of the thin film prepared in the direction of the crystal orientation can be guaranteed. Therefore, it is difficult for the polycrystalline piezoelectric film to provide the same or reverse piezoelectric film combination with the crystal orientation in any direction according to the design requirements.
  • Fig. 2 is a schematic cross-sectional view of a single crystal piezoelectric coupled resonant filter according to still another exemplary embodiment of the present invention.
  • the embodiment shown in Figure 2 is similar to the structure shown in Figure 1, except that in Figure 2, the middle electrode includes two metal layers (ie, electrodes 17 and 04) and a decoupling layer 16, forming a typical
  • the coupled resonator filter is formed by two resonators stacked in the vertical direction and acoustically decoupled.
  • 10 is a cavity structure, which is a through hole passing through the substrate 01;
  • 02 is the bottom electrode of the first resonator;
  • 03 is the single crystal piezoelectric layer of the first resonator;
  • 04 is the first resonator 16 is the decoupling layer, which can be a single passivation layer or a multilayer passivation layer composed of different acoustic impedance materials;
  • 17 is the bottom electrode of the second resonator;
  • 05 is the single crystal of the second resonator Piezoelectric layer;
  • 06 is the top electrode of the second resonator.
  • the area of the upper film is always less than or equal to the area of the lower film, which can expose the connection part of each electrode layer.
  • 07 is the electrode connection part of the top electrode of the second resonator
  • C is the electrode connection part of the bottom electrode of the second resonator
  • A is the electrode connection part of the top electrode of the first resonator
  • B is the electrode of the bottom electrode of the first resonator Connection part.
  • the piezoelectric layer materials of the first resonator and the second resonator are both single-crystal piezoelectric materials, they can improve the electromechanical coupling coefficient, quality factor, and power capacity of the resonator, and are formed by it.
  • the insertion loss of the coupled resonant filter and the suppression rate of adjacent frequency bands have also been greatly improved.
  • the single resonator is replaced by a pair of stacked resonators, the total area required for the filter is reduced, so the minimum size and manufacturing cost are reduced.
  • the introduction of the decoupling layer can make the bandwidth of the filter far larger. For other forms of filter architecture.
  • the structure of the embodiment in FIG. 2 is also applicable to other single crystal piezoelectric MEMS devices, such as ultrasonic transducers, microphones, speakers, hydrophones, etc.
  • the decoupling layer 16 can increase the strain of the piezoelectric layers 05 and 03, thereby improving the transmitting sensitivity and receiving sensitivity of the device.
  • FIG. 3 is a schematic top view of the single crystal piezoelectric coupling resonator filter in FIG. 2.
  • FIG. Fig. 3 clearly shows the schematic diagram of the electrode connection part of each resonator in the coupled resonator filter. It can be seen that from top to bottom, the area of the upper film is always less than or equal to the area of the lower film.
  • the left part of the top electrode 06 is the electrode connection part of the top electrode of the second resonator
  • C is the electrode connection part of the bottom electrode of the second resonator
  • A is the electrode connection part of the top electrode of the first resonator
  • B is the electrode connection part of the bottom electrode of the first resonator.
  • the electrode connecting portion B of the bottom electrode includes both a part on the left side of the effective area (in FIG. 2) and a part on the right side of the effective area.
  • the ends of the electrode connecting parts C and A are sequentially staggered on the right side of the effective area in the figure so that the top surfaces of the electrode connecting parts C and A form a stepped surface.
  • the order staggered here means that the end of the electrode connection part in the lower layer is located outside the end of the electrode connection part in the upper layer.
  • the outer side refers to the side farther from the center of the effective area in the lateral direction or the radial direction
  • the inner side refers to the side closer to the center of the effective area in the lateral direction or the radial direction.
  • the electrode connection parts of all the electrodes or the electrode connection parts of other electrodes except for the top electrode may be located on one side of the effective area.
  • the vertical direction is determined with the base 01 as the bottom and the top electrode 06 as the top.
  • the upward surface of each layer is the upper surface
  • the downward surface of each layer is the lower surface.
  • each piezoelectric layer and its upper and lower electrodes together form a thin film structure
  • each thin film structure has an upper electrode layer, a lower electrode layer, and a piezoelectric layer located between the upper electrode layer and the lower electrode layer.
  • two adjacent thin film structures in the thickness direction may share an electrode layer.
  • the lower electrode of the upper thin film structure may be used as the upper electrode of the lower thin film structure.
  • the area of at least one layer in the upper film structure is not larger than the corresponding layer in the lower film structure (here, corresponding, for example, the upper electrode layer is opposite to the upper electrode layer).
  • the area of the electrode layer, the piezoelectric layer to the piezoelectric layer, the lower electrode layer to the lower electrode layer), and/or the area of the upper film structure as a whole is not greater than the area of the lower film structure as a whole; and/or each In the thin film structure, the area of the upper electrode layer ⁇ the area of the piezoelectric layer ⁇ the area of the lower electrode layer.
  • the area of the piezoelectric layer in the upper film structure is smaller than the area of the piezoelectric layer in the lower film structure.
  • Fig. 4 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention, in which cross-electrode pins are provided.
  • 01 is a substrate
  • 10 is a cavity, which is a through-hole structure passing through the substrate.
  • 02 is the bottom electrode
  • 03 is the first single crystal piezoelectric layer
  • 04 is the middle electrode
  • 05 is the second single crystal piezoelectric layer
  • 06 is the top electrode
  • 07 is the electrode pin of the top electrode
  • 08 is the electrode of the middle electrode Pin.
  • 12 and 13 are structures formed by voids or non-conductive dielectric materials. The voids can be formed by etching the electrode layer with isotropic wet solution or dry gas.
  • the structure 12 separates the electrode pins of the top electrode and the middle electrode in the overlapping area in the vertical direction of the device, so as to avoid the influence of parasitic capacitance therein.
  • the structure 13 separates the electrode connection part of the middle electrode and the bottom electrode in the overlapping area in the vertical direction of the device, thus avoiding the influence of parasitic capacitance therein. It should be pointed out that in the design of some piezoelectric MEMS devices, the top electrode and the bottom electrode are electrically connected. In this case, there will be no parasitic capacitance in the right part of Figure 4, because the two layers of electrodes are electrically connected somewhere. Interconnected and at equal potential.
  • the upper end of the electrode pin 07 is electrically connected to the top electrode 06
  • the upper end of the electrode pin 08 is electrically connected to the middle electrode
  • the lower end of the electrode pin 07 is arranged on the same layer as the middle electrode and spaced apart from it.
  • the lower end of the electrode pin 08 and the bottom electrode are arranged in the same layer and spaced apart from it.
  • the lower end of the electrode pin 07 and the end of the middle electrode 04 define the boundary of the structure 12 in the lateral direction
  • the lower end of the electrode pin 08 and the end of the bottom electrode 02 are in the lateral direction.
  • the boundary of the structure 13 is defined.
  • Fig. 5 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention, in which cross-electrode pins are provided.
  • FIG. 5 and FIG. 4 there are structures 14 and 15 formed by voids or non-conductive dielectric materials.
  • the portion between the upper end and the lower end of the electrode pin 07/08 includes a vertical connection portion, and the gap exists in the lateral direction between the vertical connection portion and the edge of the laminated structure.
  • Fig. 6 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention, in which a jumper electrode pin is provided.
  • the difference between the structure shown in Fig. 6 and Fig. 5 is that in Fig. 6, in the process of forming air gaps or structures 14 and 15 of non-conductive dielectric material, there are multiple small steps, so that multiple small steps form multiple The step height is small and the height difference can effectively avoid the problem that the step directly crosses from the electrode connection part of the top electrode to the bottom and causes breakage.
  • the portion between the upper end and the lower end of the electrode pin 7/8 includes a plurality of stepped portions, and the gap is present in the lateral direction between the stepped portion and the edge of the laminated structure (corresponding structure 14 and 15).
  • Fig. 7 is a schematic cross-sectional view of a single crystal piezoelectric MEMS device according to an exemplary embodiment of the present invention, in which cross-electrode pins are provided. It is similar to the structure of FIG. 4, the electrode pin 07 is connected to the top electrode 06 and the bottom electrode 02. In the embodiment shown in FIG. 7, the top electrode and the middle electrode are separated from each other in the area overlapping in the vertical direction of the device, and the bottom electrode and the middle electrode are separated from each other in the area overlapping in the vertical direction of the device. It is separated from the bottom electrode in the area overlapping in the vertical direction of the device. This is beneficial to effectively reduce the influence of parasitic capacitance in the device and improve the performance of the device.
  • Fig. 8 is a schematic cross-sectional view of a single crystal piezoelectric coupled resonant filter according to an exemplary embodiment of the present invention.
  • Figure 8 is similar to the structure shown in Figure 4, the difference is that in Figure 8, the middle electrode includes two metal layers (ie 04 and 17) and a decoupling layer 16, forming a typical coupled resonant filter , Which is formed by two resonators stacked in the vertical direction and acoustically decoupled.
  • 01 is a cavity structure, which is a through hole passing through the substrate;
  • 02 is the bottom electrode of the first resonator,
  • 03 is the single crystal piezoelectric layer of the first resonator;
  • 04 is the top electrode of the first resonator;
  • 16 It is a decoupling layer, which can be a single passivation layer or a multilayer passivation layer composed of different acoustic impedance materials;
  • 17 is the bottom electrode of the second resonator;
  • 05 is the single crystal piezoelectric layer of the second resonator, 06 Is the top electrode of the second resonator;
  • 21 is the electrode pin of the top electrode of the second resonator;
  • 22 is a structure formed by voids or non-conductive dielectric materials.
  • the electrode pin 21 of the top electrode is separated from the bottom electrode of the second resonator, the top electrode of the first resonator, and the electrode of the first resonator by the structure 22, thereby reducing the overlap in the vertical direction of the device.
  • the influence of parasitic capacitance in the area improves the performance of the device.
  • Fig. 9 is a schematic cross-sectional view of the single crystal piezoelectric coupled resonator filter taken along the A-A direction in Fig. 8.
  • the electrode pin 23 of the bottom electrode of the second resonator is separated from the top electrode 04 of the first resonator and the bottom electrode 02 of the first resonator by the structure 24
  • the electrode pin of the top electrode of the first resonator 25 is separated from the bottom electrode 02 of the first resonator by the structure 26, thus avoiding the influence of parasitic capacitance generated in the overlapping area in the vertical direction on the performance of the device.
  • FIG. 10 is a schematic cross-sectional view of a single crystal piezoelectric coupled resonant filter according to another exemplary embodiment of the present invention.
  • the structure shown in FIG. 10 is similar to the structure shown in FIG. 8, except that, in FIG. 10, the electrode pin 29 and the electrode connecting portion of the bottom electrode 17 of the second resonator, the decoupling layer 16 and the first The electrode connection parts of the top electrode 04 of the resonator are all connected, and the structure 30 formed by a gap or a non-conductive dielectric material is isolated from the bottom electrode 02 of the first resonator; and the electrode pins of the top electrode 06 of the second resonator 27.
  • the structure 28 formed by a gap or a non-conductive dielectric material is isolated from the bottom electrode 17 of the second resonator, the decoupling layer 16, the top electrode 04 of the first resonator, and the bottom electrode 02 of the first resonator. This structure also helps to avoid the influence of parasitic capacitance in the overlapping area in the vertical direction.
  • the electrode pin is a jumper electrode pin
  • the upper end of the jumper electrode pin is electrically connected to the corresponding electrode
  • the upper end and the lower end of the jumper electrode pin are connected to each other.
  • At least one piezoelectric layer is provided.
  • the lower end of the cross-electrode pin is set on the same layer as the corresponding electrode or the corresponding piezoelectric layer.
  • the upper end of the cross electrode pin is connected to the corresponding electrode in the same layer and electrically connected.
  • the upper end of the cross electrode pin covers the top surface of the corresponding electrode and is electrically connected to the corresponding electrode.
  • a single crystal piezoelectric structure including:
  • each piezoelectric layer is a single crystal piezoelectric layer
  • a plurality of electrodes, electrodes are provided on the upper and lower sides of each piezoelectric layer, and the plurality of piezoelectric layers and the plurality of electrodes together form a laminated structure laminated in the thickness direction of the single crystal piezoelectric structure;
  • the base, the laminated structure is arranged on the base;
  • the overlapping area of the plurality of piezoelectric layers, the plurality of electrodes and the acoustic mirror in the thickness direction of the piezoelectric layer constitutes the effective area of the single crystal piezoelectric structure
  • Each electrode has an electrode connection part arranged on the same layer
  • the layer structure on the upper side of the electrode connection part of at least one of the other electrodes is removed to expose the electrode connection part.
  • the layer structure on the upper side of the electrode connection part of each of the other electrodes is removed to expose the electrode connection part.
  • the electrode connection parts of all the electrodes under the top electrode are located on the same side of the effective area or have parts on the same side of the effective area;
  • the ends of the electrode connection portion are sequentially staggered on the same side so that the top surface of the electrode connection portion constitutes a stepped surface.
  • the electrode connection portion of at least one electrode under the top electrode includes a portion located on one side of the effective area, while the electrode connection portion of other electrodes under the top electrode is located on the other side of the effective area or has a portion located on the other side of the effective area. part.
  • the ends of the electrode connection parts on the same side of the effective area are sequentially staggered and the top surfaces of the electrode connection parts on the same side constitute a stepped surface.
  • the electrode connection part of the bottom electrode in the lowermost layer of the plurality of electrodes is located on one side of the effective area or has a portion on the side of the effective area, and the other electrodes in the plurality of electrodes except for the top electrode and the bottom electrode
  • the electrode connection portion of the electrode is located on the other side of the effective area or has a portion on the other side of the effective area.
  • At least one jumper electrode pin the upper end of the jumper electrode pin is electrically connected to the corresponding electrode, and at least one piezoelectric layer is connected between the upper end and the lower end of the jumper electrode pin.
  • the lower end of the cross-electrode pin is arranged in the same layer as the corresponding electrode or the corresponding piezoelectric layer.
  • the upper end of the jumper electrode pin is electrically connected to the corresponding electrode in the same layer;
  • the upper end of the jumper electrode pin covers the top surface of the corresponding electrode and is electrically connected to the corresponding electrode.
  • the portion between the upper end and the lower end of the crossover electrode pin includes a plurality of stepped portions, and the gap exists between the stepped portion and the edge of the laminated structure in the lateral direction; or the crossover electrode pin
  • the portion between the upper end and the lower end includes a vertical connecting portion, and the gap exists in the lateral direction between the vertical connecting portion and the edge of the laminated structure;
  • the gap is a gap or a non-conductive medium gap.
  • the electrode electrically connected to the upper end of the cross electrode pin is the upper electrode
  • the electrode below the upper electrode and immediately adjacent to the upper electrode in the thickness direction is the lower electrode;
  • the end of the lower electrode is located inside the end of the upper electrode in the lateral direction to form an isolation layer on the lower side of the piezoelectric layer between the upper electrode and the lower electrode
  • the isolation layer is the same layer as the bottom electrode, and the isolation layer is a void layer or a non-conductive dielectric layer.
  • the end of the lower electrode and the jumper electrode pin define the boundary of the isolation layer in the lateral direction.
  • the plurality of piezoelectric layers includes a first piezoelectric layer and a second piezoelectric layer.
  • the plurality of electrodes includes a bottom electrode, a middle electrode, and a top electrode. The bottom electrode, the first piezoelectric layer, the middle electrode, and the second piezoelectric layer The electrical layer and the top electrode are stacked in sequence.
  • the at least one jumper electrode pin includes at least one of a middle electrode pin and a top electrode pin;
  • the upper end of the middle electrode pin is electrically connected to the electrode connection part of the middle electrode, and the lower end is spaced apart from the bottom electrode and arranged in the same layer as the bottom electrode;
  • the upper end of the top electrode pin is connected to the electrode connecting portion of the top electrode; and the lower end of the top electrode pin is spaced apart from the bottom electrode and arranged in the same layer as the bottom electrode, or the lower end of the top electrode pin is connected to the middle electrode Spaced apart and arranged in the same layer as the middle electrode, or the lower end of the top electrode and the top surface of the bottom electrode are connected to be electrically connected to each other.
  • the middle electrode pin and the top electrode pin are respectively arranged on both sides of the effective area.
  • the plurality of piezoelectric layers includes a first piezoelectric layer and a second piezoelectric layer;
  • the plurality of electrodes includes a bottom electrode, a first middle electrode, a second middle electrode, and a top electrode;
  • the single crystal piezoelectric structure further includes a coupling layer disposed between the first intermediate electrode and the second intermediate electrode;
  • the bottom electrode, the first piezoelectric layer, the first middle electrode, the coupling layer, the second middle electrode, the second piezoelectric layer, and the top electrode are sequentially stacked.
  • the at least one crossover electrode pin includes at least one of a first middle electrode pin, a second middle electrode pin, and a top electrode pin;
  • the upper end of the first middle electrode pin is electrically connected to the electrode connection part of the first middle electrode, and the lower end is spaced apart from the bottom electrode and arranged in the same layer as the bottom electrode;
  • the upper end of the second middle electrode pin is electrically connected to the electrode connection part of the second middle electrode, and the lower end is spaced apart from the bottom electrode and arranged in the same layer as the bottom electrode;
  • the upper end of the top electrode pin is connected to the electrode connection part of the top electrode; and the lower end of the top electrode pin is spaced apart from the bottom electrode and arranged in the same layer as the bottom electrode, or the lower end of the top electrode pin is connected to the first electrode.
  • the middle electrode is spaced apart and arranged in the same layer as the first middle electrode, or the lower end of the top electrode is connected to the top surface of the bottom electrode to be electrically connected to each other.
  • the first middle electrode pin and the second middle electrode pin are respectively arranged on both sides of the effective area.
  • the first middle electrode pin and the second middle electrode pin are common electrode pins that are simultaneously electrically connected to the first middle electrode and the second middle electrode.
  • Each piezoelectric layer and its upper and lower electrodes together form a thin film structure, and each thin film structure has an upper electrode layer, a lower electrode layer, and a piezoelectric layer located between the upper electrode layer and the lower electrode layer;
  • the area of at least one layer in the upper film structure is not greater than the area of the corresponding layer in the lower film structure; and/or the area of the upper film structure as a whole is not It is larger than the area of the thin film structure in the lower layer as a whole, and/or the area of the upper electrode layer in each thin film structure ⁇ the area of the piezoelectric layer ⁇ the area of the lower electrode layer.
  • the area of the piezoelectric layer located in the upper thin film structure is smaller than the area of the piezoelectric layer located in the lower thin film structure.
  • the crystal orientations of the first piezoelectric layer and the second piezoelectric layer are the same or opposite.
  • the materials of the piezoelectric layer include single crystal lithium niobate (LiNbO 3 ), single crystal lithium tantalate (LiTaO 3 ), single crystal aluminum nitride (AlN), quartz (Quartz), single crystal lead zirconate titanate (PZT), At least one of lead magnesium niobate-lead titanate (PMN-PT).
  • the electronic device includes at least one of a MEMS piezoelectric microphone, a MEMS ultrasonic transducer, a MEMS speaker, a MEMS hydrophone, and a single crystal coupled resonant filter.

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Abstract

本发明涉及单晶压电结构，以及具有该单晶压电结构的电子设备。所述单晶压电结构包括：多个压电层，每一个压电层为单晶压电层；多个电极，每个压电层的上下两侧设置有电极，多个压电层与多个电极共同形成在单晶压电结构的厚度方向上层叠的层叠结构；基底，层叠结构设置在基底上；声学镜，位于层叠结构的下方，其中：多个压电层、多个电极与声学镜在压电层的厚度方向上的重叠区域构成有效区域；每一个电极具有与其同层布置的电极连接部；多个电极中除了位于顶层的顶电极之外，其他电极中的至少一个电极的电极连接部上侧的层结构被移除以露出该电极连接部。其还可包括跨接电极引脚，其上端与对应电极电连接且上端与下端之间跨接了至少一个压电层。

Description

单晶压电结构及具有其的电子设备 技术领域
本发明的实施例涉及半导体领域，尤其涉及一种单晶压电结构，以及一种具有该结构的电子设备。
背景技术
MEMS(Micro-Electro-Mechanical System)是微机电系统的简称。MEMS器件内部结构尺寸一般是微米或纳米级别，同时MEMS是一个独立的智能系统。MEMS器件能够将一种形式的能量转换为另一种形式的能量，如将电能转化为机械能或者机械能转化为电能。本发明中所涉及到的MEMS换能器是指能将声波的机械能和电能相互转换的换能器。一般来说，MEMS器件需要压电材料实现不同形式的能量转换。当在压电材料上施以交变电场时，压电材料将按所施交变电场的频率而振动，若所施交变电场的频率刚好是该MEMS器件的谐振频率，则振幅值将大大增加，在该频率处具有更高的能量转换效率，当MEMS器件作为换能器时具有较大的发射灵敏度。另一方面，当声波传至压电材料上，将引起压电材料的振动和形变，这一振动又将在压电材料的两端电极上引起交变的电荷分布，当声波频率是在MEMS器件的谐振频率点时，在该频率处具有更高的能量转换效率，当MEMS器件作为换能器时具有较大的接收灵敏度。
传统的压电MEMS器件的压电薄膜材料大多采用磁控溅射等物理或化学沉积技术制备，为多晶压电薄膜，其压电特性较差(主要体现为机电耦合系数较低)，缺陷密度较高(主要体现为品质因数较低)，散热性不佳(主要体现为功率容量较低)，而且晶向选择有限(无法选择器件设计的最优晶向和压电系数)。这些缺陷导致多晶压电MEMS器件性能不够好，如Q值不高、灵敏度不高、插入损耗较高等。
此外，如何合理连接不同电极、电学隔离电极，例如如何在隔离中间电极的情况下电学连接顶电极和底电极，也需要解决。
发明内容
为缓解或解决现有技术中的上述问题的至少一个方面，提出本发明。
根据本发明的实施例的一个方面，提出了一种单晶压电结构，包括：
多个压电层，每一个压电层为单晶压电层；
多个电极，每个压电层的上下两侧设置有电极，所述多个压电层与所述多个电极共同形成在单晶压电结构的厚度方向上层叠的层叠结构；
基底，层叠结构设置在基底上；
声学镜，位于层叠结构的下方，
其中：
所述多个压电层、多个电极与声学镜在压电层的厚度方向上的重叠区域构成所述单晶压电结构的有效区域；
每一个电极具有与其同层布置的电极连接部；
多个电极中除了位于顶层的顶电极之外，其他电极中的至少一个电极的电极连接部上侧的层结构被移除以露出该电极连接部。
本发明的实施例还涉及一种电子设备，包括上述的单晶压电结构。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图；
图2为根据本发明的一个示例性实施例的单晶压电耦合谐振滤波器的剖面示意图；
图3为图2中的单晶压电耦合谐振滤波器的示意性俯视图；
图4为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图，其中设置有跨接电极引脚；
图5为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图，其中设置有跨接电极引脚；
图6为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图，其中设置有跨接电极引脚；
图7为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图，其中设置有跨接电极引脚；
图8为根据本发明的一个示例性实施例的单晶压电耦合谐振滤波器的剖面示意图；
图9为沿图8中的A-A向获得的单晶压电耦合谐振滤波器的剖面示意图；
图10为根据本发明的另一个示例性实施例的单晶压电耦合谐振滤波器的剖面示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。
本发明提出了一种利用单晶压电薄膜材料的MEMS器件结构。单晶压电薄膜材料能够弥补传统多晶压电薄膜材料中所存在的不足，由其加工制作的压电MEMS其具有更大的机电耦合系数、更高的Q值、更高的功率容量、更高的灵敏度、更低的插入损耗等。本发明中所提出的器件结构是一种适用于多种单晶压电MEMS器件的通用性结构，可用于单晶压电MEMS超声波换能器(Ultrasonic Transducers)、单晶压电MEMS麦克风(Microphone)、单晶压电MEMS扬声器(Speaker)和单晶压电MEMS水听器(Hydrophone)、单晶压电耦合谐振滤波器(Coupled Resonator Filter)等。由于单晶压电薄膜的制备方式与传统多晶压电薄膜不同，单晶压电MEMS器件的制造方法、器件结构等也与传统多晶压电MEMS器件有很大区别。
图1为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图。图1中，01为器件的基底；10为器件底部的空腔结构，在本实施例中，空腔结构为穿过基底的通孔，10为器件的声学镜结构，其也可以是其他等效形式；02为器件的底电极；03为器件的第一单晶压电层；04为器件的中间电极；05为器件的第二单晶压电层；06为器件的顶电极；A为中间电极连接部；B为底电极连接部。
在本发明中，第一单晶压电层和第二单晶压电层的材料可以都为单晶铌酸锂(LiNbO 3)材料。也可以为其他材料，例如单晶钽酸锂(LiTaO 3)、单晶氮化铝(AlN)、石英(Quartz)、单晶锆钛酸铅(PZT)、铌镁酸铅-钛酸铅(PMN-PT)中的至少一种。在本发明中，电极组成材料可以是钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。基底可以为硅(Si)、单晶铌酸锂(LiNbO3)、碳化硅(SiC)、蓝宝石(Al 2O 3)、石英(Quartz)等。
此外，在图1中，顶电极、第二单晶压电层、中间电极、第一单晶压电层、底电极和空腔在垂直方向上重叠的区域为器件的有效区域，如图1中D区域所示。
为了提高单晶压电MEMS器件的性能，如提高能量转化效率，也为了便于合理连接电极等，在本发明中，上层薄膜结构的面积始终小于等于下层薄膜结构的面积。可以通过光刻、刻蚀等加工方法，先将顶电极06、第二单晶压电层05右侧的一部分去除掉，露出中间电极04的一部分作为中间电极连接部A；再将顶电极06、第二单晶压电层05、中间电极04和第一单晶压电层03左侧的一部分刻蚀掉，露出底电极02的一部分作为底电极连接部B。此外，对于图2中所示的结构，也可以采用与上面类似的方法露出各个相应的电极连接部分。
在本发明中，参见图1，底电极连接部B位于有效区域的左侧，而中间电极连接部A位于有效区域的右侧。在本发明中，电极连接部位于有效区域的一侧，表示其在有效区域的外侧，且在例如图示的图中，位于有效区域的左边或者右边。
在本发明实施例中，由于单晶压电MEMS器件的结构为五层薄膜堆叠结构，其能量转化效率比普通三层结构高一倍。而且由于第一压电层和第 二压电层所用的材料都是单晶压电材料，使得器件的机电耦合系数也要比普通多晶压电材料的要高很多，因此对应的单晶压电MEMS器件的发射、接收灵敏度更高、插入损耗更低。从压电层晶向选择角度可以进一步优化单晶压电MEMS器件的能量转化效率，第一压电层和第二压电层的晶向为同向或反向。需要指出的是，这里的晶向可以为任意选定的方向，因为单晶薄膜的特点为可以根据器件设计需要提供任意晶向的薄膜；而多晶压电薄膜则不然，一般只有在一个固定的晶向方向上其制备的薄膜压电特性才能得到保证，因此多晶压电薄膜很难根据设计要求提供晶向在任意方向下的同向或反向压电薄膜组合。
图2为根据本发明的还一个示例性实施例的单晶压电耦合谐振滤波器的剖面示意图。图2所示的实施例与图1中所示的结构相似，不同之处在于，图2中，中间电极包括了两层金属层(即电极17与04)和解耦层16，形成了典型的耦合谐振滤波器，即由两个谐振器在垂直方向上重叠放置并声学解耦形成。在图4中，10为空腔结构，其为穿过基底01的通孔；02为第一谐振器的底电极；03为第一谐振器的单晶压电层；04为第一谐振器的顶电极；16为解耦层，其可以为单层钝化层或者不同声阻抗材料构成的多层钝化层；17为第二谐振器的底电极；05为第二谐振器的单晶压电层；06为第二谐振器的顶电极。
另外，在本实施例中，如图2所示，上层薄膜的面积始终要小于等于下层薄膜的面积，这可以将各电极层的连接部分裸露出来。其中07为第二谐振器顶电极的电极连接部分，C为第二谐振器底电极的电极连接部分，A为第一谐振器顶电极的电极连接部分，B为第一谐振器底电极的电极连接部分。
在本实施例中，由于第一谐振器和第二谐振器的压电层材料都是单晶压电材料，所以其可以提高谐振器的机电耦合系数、品质因数和功率容量，以及由其形成的耦合谐振滤波器的插入损耗、相邻频带的抑制率等性能也大幅提高。并且，由于单谐振器被一对堆叠谐振器所代替，实现滤波器所需的总面积减小，因此实现了最小尺寸和制造成本的降低，同时解耦层的引入可以让滤波器的带宽远大于其他形式的滤波器构架。
另一方面，图2的实施例结构也适用于其他单晶压电MEMS器件，如超声换能器、麦克风、扬声器、水听器等。解耦层16可以起到增大压电层05和03应变的作用，进而提高器件的发射灵敏度和接收灵敏度。
图3为图2中的单晶压电耦合谐振滤波器的示意性俯视图。在图3中清楚的表现出了耦合谐振器滤波器中各个谐振器的电极连接部分示意图，可以看到从上到下，上层薄膜的面积始终小于等于下层薄膜的面积。其中，顶电极06的左侧部分为第二谐振器的顶电极的电极连接部分，C为第二谐振器的底电极的电极连接部分，A为第一谐振器的顶电极的电极连接部分，B为第一谐振器的底电极的电极连接部分。
在图3中，可以看到，底电极的电极连接部B既包括了在有效区域的左侧(图2中)的一部分，也包括在有效区域的右侧的一部分。
从图2可以看出，电极连接部分C和A的端部在图中有效区域的右侧依次错开以使得电极连接部分C和A的顶面组成台阶面。这里的依次错开，表示在下层的电极连接部分的端部位于在上层的电极连接部分的端部的外侧。在本发明中，外侧是指在横向方向或者径向方向上更远离有效区域的中心的一侧，而内侧是指在横向方向或者径向方向上更靠近有效区域的中心的一侧。
虽然没有示出，所有电极的电极连接部分或者除了顶电极的之外的其他电极的电极连接部分都可以位于有效区域的一侧。
在本发明中，在图中结构中，以基底01为下、顶电极06为上确定上下方向，此外，各层朝上的表面为上表面，各层朝下的表面为下表面。
在本发明中，每个压电层及其上下两侧的电极一起构成一个薄膜结构，每一个薄膜结构具有上电极层、下电极层以及位于上电极层与下电极层之间的压电层。如能够理解的，两个在厚度方向上相邻的薄膜结构可以共用电极层，例如上薄膜结构的下电极可以作为下薄膜结构的上电极。
在本发明中，在单晶压电结构的厚度方向上，位于上层的薄膜结构中的至少一层的面积不大于位于下层的薄膜结构中的对应层(这里的对应，例如上电极层对上电极层，压电层对压电层，下电极层对下电极层)的面积，和/或上层的薄膜结构作为一个整体其面积不大于下层的薄膜结构作 为整体的面积；和/或每一个薄膜结构中上电极层的面积≤压电层的面积≤下电极层的面积。进一步的，在单晶压电结构的厚度方向上，位于上层薄膜结构中的压电层的面积小于位于下层薄膜结构中的压电层的面积。
图4为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图，其中设置有跨接电极引脚。图4中，01为基底，10为空腔，其为穿过基底的通孔结构。02为底电极，03为第一单晶压电层，04为中间电极，05为第二单晶压电层，06为顶电极，07为顶电极的电极引脚，08为中间电极的电极引脚。12和13为空隙或不导电介质材料形成的结构，空隙可以由各项同性的湿法溶液或干法气体刻蚀电极层形成。
在本实施例中，结构12将顶电极的电极引脚与中间电极在器件的垂直方向上的重叠区域中隔开，这样避免了其中寄生电容的影响。结构13将中间电极的电极连接部分与底电极在器件的垂直方向上的重叠区域中隔开，这样避免了其中寄生电容的影响。需要指出的是，在有些压电MEMS器件的设计中顶电极和底电极电学连接，在这种情况下图4右侧部分就不会有寄生电容的存在，因为这两层电极在某处电学互连、处于等电势。
在图4中，电极引脚07的上端实现与顶电极06的电连接，电极引脚08的上端实现与中间电极的电连接，电极引脚07的下端与中间电极同层布置且与之间隔开，电极引脚08的下端与底电极同层布置且与之间隔开。在图4所示的示例中，电极引脚07的下端与中间电极04的端部在横向方向上限定了结构12的边界，电极引脚08的下端与底电极02的端部在横向方向上限定了结构13的边界。
图5为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图，其中设置有跨接电极引脚。图5与图4的不同在于，在图5所示的实施例中，存在空隙或不导电介质材料形成的结构14和15。换言之，电极引脚07/08与层叠结构(顶电极、第二压电层、中间电极、第一压电层和底电极层叠形成)的边缘之间在横向方向上存在间隙，所述间隙从跨接电极引脚的上端延伸到下端，这里的间隙是结构14和15。在图5中，电极引脚07/08的上端与下端之间的部分包括竖直连接部，所述竖直连接部与层叠结构的边缘之间在横向方向上存在所述间隙。
图6为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图，其中设置有跨接电极引脚。图6与图5所示的结构不同的是，在图6中，在形成空气隙或不导电介质材料的结构14和15过程中，有多个小台阶，这样多个小台阶形成了多个台阶高度较小的高度差，从而能够有效避免台阶直接从顶电极的电极连接部跨越到底部而产生断裂的问题。如图6所示，电极引脚7/8的上端与下端之间的部分包括多个台阶部，所述台阶部与层叠结构的边缘之间在横向方向上存在所述间隙(对应结构14和15)。
图7为根据本发明的一个示例性实施例的单晶压电MEMS器件的剖面示意图，其中设置有跨接电极引脚。其与图4结构相似，电极引脚07连接着顶电极06和底电极02。在图7所示的实施例中，顶电极和中间电极在器件的垂直方向上重叠的区域中相隔开，底电极和中间电极在器件的垂直方向上重叠的区域中相隔开，中间电极和底电极在器件的垂直方向上重叠的区域中相隔开。这有利于有效降低器件中寄生电容的影响，提升器件的性能。
图8为根据本发明的一个示例性实施例的单晶压电耦合谐振滤波器的剖面示意图。图8与图4中所示的结构相似，不同之处在于，在图8中，中间电极包括了两层金属层(即04和17)和解耦层16，形成了典型的耦合谐振滤波器，即由两个谐振器在垂直方向上重叠放置并声学解耦形成。其中01为空腔结构，其为穿过基底的通孔；02为第一谐振器的底电极，03为第一谐振器的单晶压电层；04为第一谐振器的顶电极；16为解耦层，其可以为单层钝化层或者不同声阻抗材料构成的多层钝化层；17为第二谐振器的底电极；05为第二谐振器的单晶压电层，06为第二谐振器的顶电极；21为第二谐振器顶部电极的电极引脚；22为空隙或不导电介质材料形成的结构。在实施例中，顶电极的电极引脚21通过结构22与第二谐振器的底电极、第一谐振器的顶电极和第一谐振器的电极隔离开，从而降低了在器件垂直方向上重叠区域中寄生电容的影响，提高了器件的性能。
图9为沿图8中的A-A向获得的单晶压电耦合谐振滤波器的剖面示意图。图9中，23为第二谐振器底电极的电极引脚；25为第一谐振器顶 电极的电极引脚；24和26为空隙或不导电介质材料形成的结构。由于第二谐振器的底部电极的电极引脚23通过结构24将其与第一谐振器的顶电极04和第一谐振器的底部电极02隔离开，第一谐振器的顶电极的电极引脚25通过结构26将其与第一谐振器的底电极02间隔开，因而避免了在垂直方向上重叠区域中产生的寄生电容对器件性能的影响。
图10为根据本发明的另一个示例性实施例的单晶压电耦合谐振滤波器的剖面示意图。图10所示的结构与图8中所示结构相似，不同之处在于，在图10中，电极引脚29与第二谐振器的底电极17的电极连接部、解耦层16以及第一谐振器的顶电极04的电极连接部均相连，且通过空隙或不导电介质材料形成的结构30与第一谐振器的底电极02隔离开；并且第二谐振器的顶电极06的电极引脚27，通过空隙或不导电介质材料形成的结构28与第二谐振器的底电极17、解耦层16、第一谐振器的顶电极04和第一谐振器的底电极02隔离开。此结构也有利于避免在垂直方向上重叠区域中寄生电容的影响。
在图4-10所示的示例中，电极引脚为跨接电极引脚，所述跨接电极引脚的上端与对应电极电连接，跨接电极引脚的上端与下端之间跨接了至少一个压电层。
如图4-10所示，跨接电极引脚的下端与对应电极或对应压电层同层设置。
如图10所示，跨接电极引脚的上端与所述对应电极同层相接而电连接。
如图4-7所示，跨接电极引脚的上端覆盖所述对应电极的顶面而与所述对应电极电连接。
基于以上，本发明提出了如下技术方案：
1、一种单晶压电结构，包括：
多个压电层，每一个压电层为单晶压电层；
多个电极，每个压电层的上下两侧设置有电极，所述多个压电层与所述多个电极共同形成在单晶压电结构的厚度方向上层叠的层叠结构；
基底，层叠结构设置在基底上；
声学镜，位于层叠结构的下方，
其中：
所述多个压电层、多个电极与声学镜在压电层的厚度方向上的重叠区域构成所述单晶压电结构的有效区域；
每一个电极具有与其同层布置的电极连接部；
多个电极中除了位于顶层的顶电极之外，其他电极中的至少一个电极的电极连接部上侧的层结构被移除以露出该电极连接部。
2、根据1所述的单晶压电结构，其中：
所述其他电极中的每个电极的电极连接部上侧的层结构均被移除以露出该电极连接部。
3、根据2所述的单晶压电结构，其中：
顶电极之下的所有电极的电极连接部分均位于有效区域的同一侧或具有在有效区域的同一侧的部分；
电极连接部分的端部在所述同一侧依次错开以使得电极连接部分的顶面组成台阶面。
4、根据2所述的单晶压电结构，其中：
顶电极之下的至少一个电极的电极连接部分包括位于有效区域的一侧的部分，而顶电极之下的其他电极的电极连接部分位于有效区域的另一侧或具有在有效区域的另一侧的部分。
5、根据4所述的单晶压电结构，其中：
在有效区域的同侧的电极连接部分的个数不小于二的情况下，在有效区域的同侧的电极连接部分的端部依次错开且在同侧的电极连接部分顶面组成台阶面。
6、根据4所述的单晶压电结构，其中：
所述多个电极中位于最下层的底电极的电极连接部分位于有效区域的一侧或具有在有效区域的一侧的部分，而所述多个电极中除了顶电极与底电极之外的其他电极的电极连接部分位于有效区域的另一侧或具有在有效区域的另一侧的部分。
7、根据2-6中任一项所述的单晶压电结构，还包括：
至少一个跨接电极引脚，所述跨接电极引脚的上端与对应电极电连接，跨接电极引脚的上端与下端之间跨接了至少一个压电层。
8、根据7所述的单晶压电结构，其中：
所述跨接电极引脚的下端与对应电极或对应压电层同层设置。
9、根据7所述的单晶压电结构，其中：
所述跨接电极引脚的上端与所述对应电极同层相接而电连接；或者
所述跨接电极引脚的上端覆盖所述对应电极的顶面而与所述对应电极电连接。
10、根据7-9中任一项所述的单晶压电结构，其中：
所述跨接电极引脚与层叠结构的边缘之间在横向方向上存在间隙，所述间隙从跨接电极引脚的上端延伸到下端。
11、根据10所述的单晶压电结构，其中：
所述跨接电极引脚的上端与下端之间的部分包括多个台阶部，所述台阶部与层叠结构的边缘之间在横向方向上存在所述间隙；或者所述跨接电极引脚的上端与下端之间的部分包括竖直连接部，所述竖直连接部与层叠结构的边缘之间在横向方向上存在所述间隙；
所述间隙为空隙或者不导电介质间隙。
12、根据9-11中任一项所述的单晶压电结构，其中：
所述跨接电极引脚的上端所电连接的电极为上电极；
在所述上电极下方且与所述上电极在所述厚度方向上紧邻的电极为下电极；
在所述有效区域的一侧，所述下电极的端部在横向方向上位于所述上电极的端部的内侧，以在上电极与下电极之间的压电层的下侧形成隔离层，所述隔离层与所述下电极同层，所述隔离层为空隙层或者不导电介质层。
13、根据12所述的单晶压电结构，其中：
所述下电极的端部与所述跨接电极引脚限定所述隔离层在横向方向上的边界。
14、根据7-13中任一项所述的单晶压电结构，其中：
所述多个压电层包括第一压电层与第二压电层，所述多个电极包括底电极、中间电极和顶电极，底电极、第一压电层、中间电极、第二压电层、顶电极依次叠置。
15、根据14所述的单晶压电结构，其中：
所述至少一个跨接电极引脚包括中间电极引脚和顶电极引脚中的至少一个；
所述中间电极引脚的上端电连接到中间电极的电极连接部，下端与底电极间隔开且与底电极同层布置；
所述顶电极引脚的上端连接到顶电极的电极连接部；且所述顶电极引脚的下端与底电极间隔开且与底电极同层布置，或者所述顶电极引脚的下端与中间电极间隔开且与中间电极同层布置，或者所述顶电极的下端与底电极的顶面相接而彼此电连接。
16、根据15所述的单晶压电结构，其中：
所述中间电极引脚与所述顶电极引脚分别设置在有效区域的两侧。
17、根据7-13中任一项所述的单晶压电结构，其中：
所述多个压电层包括第一压电层与第二压电层；
所述多个电极包括底电极、第一中间电极、第二中间电极和顶电极；
所述单晶压电结构还包括耦合层，耦合层设置在第一中间电极与第二中间电极之间；且
底电极、第一压电层、第一中间电极、耦合层、第二中间电极、第二压电层、顶电极依次叠置。
18、根据17所述的单晶压电结构，其中：
所述至少一个跨接电极引脚包括第一中间电极引脚、第二中间电极引脚和顶电极引脚中的至少一个；
所述第一中间电极引脚的上端电连接到第一中间电极的电极连接部，下端与底电极间隔开且与底电极同层布置；
所述第二中间电极引脚的上端电连接到第二中间电极的电极连接部，下端与底电极间隔开且与底电极同层布置；
所述顶电极引脚的上端连接到顶电极的电极连接部；且所述顶电极引脚的下端与底电极间隔开且与底电极同层布置，或者所述顶电极引脚的下端与第一中间电极间隔开且与第一中间电极同层布置，或者所述顶电极的下端与底电极的顶面相接而彼此电连接。
19、根据18所述的单晶压电结构，其中：
所述第一中间电极引脚、第二中间电极引脚分别设置在有效区域的两 侧。
20、根据18所述的单晶压电结构，其中：
第一中间电极引脚与第二中间电极引脚为同时与第一中间电极和第二中间电极电连接的共用电极引脚。
21、根据2-20中任一项所述的单晶压电结构，其中：
每个压电层及其上下两侧的电极一起构成一个薄膜结构，每一个薄膜结构具有上电极层、下电极层以及位于上电极层与下电极层之间的压电层；
在单晶压电结构的厚度方向上，位于上层的薄膜结构中的至少一层的面积不大于位于下层的薄膜结构中的对应层的面积；和/或位于上层的薄膜结构作为整体的面积不大于位于下层的薄膜结构作为整体的面积，和/或每一个薄膜结构中上电极层的面积≤压电层的面积≤下电极层的面积。
22、根据21所述的单晶压电结构，其中：
在单晶压电结构的厚度方向上，位于上层薄膜结构中的压电层的面积小于位于下层薄膜结构中的压电层的面积。
23、根据1所述的单晶压电结构，其中：
第一压电层和第二压电层的晶向为同向或反向。
24、根据1-23中任一项所述的单晶压电结构，其中：
压电层的材料包括单晶铌酸锂(LiNbO 3)、单晶钽酸锂(LiTaO 3)、单晶氮化铝(AlN)、石英(Quartz)、单晶锆钛酸铅(PZT)、铌镁酸铅-钛酸铅(PMN-PT)中的至少一种。
25、一种电子设备，包括根据1-24中任一项所述的单晶压电结构。
26、根据25所述的电子设备，其中：
所述电子设备包括MEMS压电麦克风、MEMS超声换能器、MEMS扬声器、MEMS水听器、单晶耦合谐振滤波器中的至少一种。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (26)

  1. 一种单晶压电结构，包括：
    多个压电层，每一个压电层为单晶压电层；
    多个电极，每个压电层的上下两侧设置有电极，所述多个压电层与所述多个电极共同形成在单晶压电结构的厚度方向上层叠的层叠结构；
    基底，层叠结构设置在基底上；
    声学镜，位于层叠结构的下方，
    其中：
    所述多个压电层、多个电极与声学镜在压电层的厚度方向上的重叠区域构成所述单晶压电结构的有效区域；
    每一个电极具有与其同层布置的电极连接部；
    多个电极中除了位于顶层的顶电极之外，其他电极中的至少一个电极的电极连接部上侧的层结构被移除以露出该电极连接部。
  2. 根据权利要求1所述的单晶压电结构，其中：
    所述其他电极中的每个电极的电极连接部上侧的层结构均被移除以露出该电极连接部。
  3. 根据权利要求2所述的单晶压电结构，其中：
    顶电极之下的所有电极的电极连接部分均位于有效区域的同一侧或具有在有效区域的同一侧的部分；
    电极连接部分的端部在所述同一侧依次错开以使得电极连接部分的顶面组成台阶面。
  4. 根据权利要求2所述的单晶压电结构，其中：
    顶电极之下的至少一个电极的电极连接部分包括位于有效区域的一侧的部分，而顶电极之下的其他电极的电极连接部分位于有效区域的另一侧或具有在有效区域的另一侧的部分。
  5. 根据权利要求4所述的单晶压电结构，其中：
    在有效区域的同侧的电极连接部分的个数不小于二的情况下，在有效区域的同侧的电极连接部分的端部依次错开且在同侧的电极连接部分顶面组成台阶面。
  6. 根据权利要求4所述的单晶压电结构，其中：
    所述多个电极中位于最下层的底电极的电极连接部分位于有效区域的一侧或具有在有效区域的一侧的部分，而所述多个电极中除了顶电极与底电极之外的其他电极的电极连接部分位于有效区域的另一侧或具有在有效区域的另一侧的部分。
  7. 根据权利要求2-6中任一项所述的单晶压电结构，还包括：
    至少一个跨接电极引脚，所述跨接电极引脚的上端与对应电极电连接，跨接电极引脚的上端与下端之间跨接了至少一个压电层。
  8. 根据权利要求7所述的单晶压电结构，其中：
    所述跨接电极引脚的下端与对应电极或对应压电层同层设置。
  9. 根据权利要求7所述的单晶压电结构，其中：
    所述跨接电极引脚的上端与所述对应电极同层相接而电连接；或者
    所述跨接电极引脚的上端覆盖所述对应电极的顶面而与所述对应电极电连接。
  10. 根据权利要求7-9中任一项所述的单晶压电结构，其中：
    所述跨接电极引脚与层叠结构的边缘之间在横向方向上存在间隙，所述间隙从跨接电极引脚的上端延伸到下端。
  11. 根据权利要求10所述的单晶压电结构，其中：
    所述跨接电极引脚的上端与下端之间的部分包括多个台阶部，所述台阶部与层叠结构的边缘之间在横向方向上存在所述间隙；或者所述跨接电极引脚的上端与下端之间的部分包括竖直连接部，所述竖直连接部与层叠结构的边缘之间在横向方向上存在所述间隙；
    所述间隙为空隙或者不导电介质间隙。
  12. 根据权利要求9-11中任一项所述的单晶压电结构，其中：
    所述跨接电极引脚的上端所电连接的电极为上电极；
    在所述上电极下方且与所述上电极在所述厚度方向上紧邻的电极为下电极；
    在所述有效区域的一侧，所述下电极的端部在横向方向上位于所述上电极的端部的内侧，以在上电极与下电极之间的压电层的下侧形成隔离层，所述隔离层与所述下电极同层，所述隔离层为空隙层或者不导电介质层。
  13. 根据权利要求12所述的单晶压电结构，其中：
    所述下电极的端部与所述跨接电极引脚限定所述隔离层在横向方向上的边界。
  14. 根据权利要求7-13中任一项所述的单晶压电结构，其中：
    所述多个压电层包括第一压电层与第二压电层，所述多个电极包括底电极、中间电极和顶电极，底电极、第一压电层、中间电极、第二压电层、顶电极依次叠置。
  15. 根据权利要求14所述的单晶压电结构，其中：
    所述至少一个跨接电极引脚包括中间电极引脚和顶电极引脚中的至少一个；
    所述中间电极引脚的上端电连接到中间电极的电极连接部，下端与底电极间隔开且与底电极同层布置；
    所述顶电极引脚的上端连接到顶电极的电极连接部；且所述顶电极引脚的下端与底电极间隔开且与底电极同层布置，或者所述顶电极引脚的下端与中间电极间隔开且与中间电极同层布置，或者所述顶电极的下端与底电极的顶面相接而彼此电连接。
  16. 根据权利要求15所述的单晶压电结构，其中：
    所述中间电极引脚与所述顶电极引脚分别设置在有效区域的两侧。
  17. 根据权利要求7-13中任一项所述的单晶压电结构，其中：
    所述多个压电层包括第一压电层与第二压电层；
    所述多个电极包括底电极、第一中间电极、第二中间电极和顶电极；
    所述单晶压电结构还包括耦合层，耦合层设置在第一中间电极与第二中间电极之间；且
    底电极、第一压电层、第一中间电极、耦合层、第二中间电极、第二压电层、顶电极依次叠置。
  18. 根据权利要求17所述的单晶压电结构，其中：
    所述至少一个跨接电极引脚包括第一中间电极引脚、第二中间电极引脚和顶电极引脚中的至少一个；
    所述第一中间电极引脚的上端电连接到第一中间电极的电极连接部，下端与底电极间隔开且与底电极同层布置；
    所述第二中间电极引脚的上端电连接到第二中间电极的电极连接部， 下端与底电极间隔开且与底电极同层布置；
    所述顶电极引脚的上端连接到顶电极的电极连接部；且所述顶电极引脚的下端与底电极间隔开且与底电极同层布置，或者所述顶电极引脚的下端与第一中间电极间隔开且与第一中间电极同层布置，或者所述顶电极的下端与底电极的顶面相接而彼此电连接。
  19. 根据权利要求18所述的单晶压电结构，其中：
    所述第一中间电极引脚、第二中间电极引脚分别设置在有效区域的两侧。
  20. 根据权利要求18所述的单晶压电结构，其中：
    第一中间电极引脚与第二中间电极引脚为同时与第一中间电极和第二中间电极电连接的共用电极引脚。
  21. 根据权利要求2-20中任一项所述的单晶压电结构，其中：
    每个压电层及其上下两侧的电极一起构成一个薄膜结构，每一个薄膜结构具有上电极层、下电极层以及位于上电极层与下电极层之间的压电层；
    在单晶压电结构的厚度方向上，位于上层的薄膜结构中的至少一层的面积不大于位于下层的薄膜结构中的对应层的面积；和/或位于上层的薄膜结构作为整体的面积不大于位于下层的薄膜结构作为整体的面积，和/或每一个薄膜结构中上电极层的面积≤压电层的面积≤下电极层的面积。
  22. 根据权利要求21所述的单晶压电结构，其中：
    在单晶压电结构的厚度方向上，位于上层薄膜结构中的压电层的面积小于位于下层薄膜结构中的压电层的面积。
  23. 根据权利要求1所述的单晶压电结构，其中：
    第一压电层和第二压电层的晶向为同向或反向。
  24. 根据权利要求1-23中任一项所述的单晶压电结构，其中：
    压电层的材料包括单晶铌酸锂(LiNbO 3)、单晶钽酸锂(LiTaO 3)、单晶氮化铝(AlN)、石英(Quartz)、单晶锆钛酸铅(PZT)、铌镁酸铅-钛酸铅(PMN-PT)中的至少一种。
  25. 一种电子设备，包括根据权利要求1-24中任一项所述的单晶压电结构。
  26. 根据权利要求25所述的电子设备，其中：
    所述电子设备包括MEMS压电麦克风、MEMS超声换能器、MEMS扬声器、MEMS水听器、单晶耦合谐振滤波器中的至少一种。
PCT/CN2020/088724 2019-12-31 2020-05-06 单晶压电结构及具有其的电子设备 WO2021135014A1 (zh)

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