WO2021135013A1 - 具有叠置单元的半导体结构及制造方法、电子设备 - Google Patents

具有叠置单元的半导体结构及制造方法、电子设备 Download PDF

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Publication number
WO2021135013A1
WO2021135013A1 PCT/CN2020/088723 CN2020088723W WO2021135013A1 WO 2021135013 A1 WO2021135013 A1 WO 2021135013A1 CN 2020088723 W CN2020088723 W CN 2020088723W WO 2021135013 A1 WO2021135013 A1 WO 2021135013A1
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unit
substrate
bonding
semiconductor structure
conductive
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PCT/CN2020/088723
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English (en)
French (fr)
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张兰月
庞慰
温攀
张巍
杨清瑞
张孟伦
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诺思(天津)微系统有限责任公司
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Priority to EP20911018.8A priority Critical patent/EP4086955A4/en
Publication of WO2021135013A1 publication Critical patent/WO2021135013A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/1014—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H03H9/0547—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a vertical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02157—Dimensional parameters, e.g. ratio between two dimension parameters, length, width or thickness

Definitions

  • the embodiments of the present invention relate to the field of semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof, and an electronic device having the semiconductor structure.
  • filter components such as filters and duplexers based on, for example, Film Bulk Acoustic Resonator (FBAR) have become more and more popular in the market.
  • FBAR Film Bulk Acoustic Resonator
  • ESD anti-electrostatic discharge
  • the prior art proposes a method of vertically stacking semiconductor devices, which requires wafer-level packaging and bonding.
  • Metal bonding is a common method. This bonding process is simple and has good sealing properties.
  • the isotropy of the wet solution will cause severe lateral etching, so the control of the pattern size is poor, leading to the problem of poor bonding and sealing.
  • the present invention proposes a structure and method for bonding alignment during vertical stack packaging.
  • a semiconductor structure with stacked units including at least two units stacked in a thickness direction of the semiconductor structure, the at least two units are provided with at least one chip, And includes at least one unit pair, the unit pair includes an upper unit and a lower unit adjacent in the thickness direction of the semiconductor structure, the upper unit is above the lower unit, wherein:
  • Both the upper unit and the lower unit include a base
  • the lower surface of the base of the upper unit is provided with a plurality of convex structures protruding downward, and the convex structures are covered with a bonding layer to form a bonding-protrusion structure together with the convex structures;
  • the upper surface of the base of the lower unit is provided with conductive bumps protruding upward, the bonding-protrusion structure and the corresponding conductive bumps are aligned with each other and connected by bonding, and the lower surface of the base of the upper unit is connected to the base of the lower unit.
  • a first accommodation space is defined between the upper surfaces.
  • the embodiment of the present invention also relates to a method of manufacturing a semiconductor structure with stacked units, including the steps:
  • the first unit having a first substrate and a plurality of first holes passing through the first substrate;
  • the first substrate is thinned from the lower surface of the first substrate to form a first new lower surface to expose the first hole, and a first protruding structure is formed around the first hole, and the first protruding structure is self-exposed.
  • the first new lower surface is protruding;
  • the second unit having a second substrate, and a plurality of second bonding protrusions are provided on the upper surface of the second substrate;
  • the first bonding-protrusion structure and the corresponding second bonding protrusion are bonded to each other to form a first accommodating space between the first substrate and the second substrate.
  • the embodiment of the present invention also relates to an electronic device having the above-mentioned semiconductor structure.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure with stacked cells according to an exemplary embodiment of the present invention, wherein the semiconductor structure has only three substrates;
  • FIG. 1A is a schematic cross-sectional view further exemplarily showing the bonding-protrusion structure provided on the underside of the substrate;
  • FIG. 2A-2G are schematic diagrams exemplarily showing the manufacturing process of the semiconductor structure in FIG. 1;
  • FIG. 3 is a schematic cross-sectional view of a semiconductor structure with stacked cells according to an exemplary embodiment of the present invention, wherein the semiconductor structure has a five-layer substrate;
  • 4A-4C are respectively schematic cross-sectional views showing protrusion structures of a semiconductor structure according to an exemplary embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view of a semiconductor structure with stacked cells according to an exemplary embodiment of the present invention, wherein the semiconductor structure has only three substrates, and conductive vias pass through the first substrate;
  • FIG. 6 is a schematic cross-sectional view of a semiconductor structure with stacked cells in the prior art.
  • an acoustic wave filter is taken as an example to illustrate the semiconductor structure.
  • the acoustic wave filter can adopt a multi-substrate method for electrical connection in the vertical direction, which can reduce the area of the filter, duplexer, and quadruplexer by more than 30%.
  • the overall external electrical input and output are on the top surface of the protective layer of the semiconductor structure or the upper surface of the first substrate 10 (mentioned later), and the lower surface of the corresponding semiconductor structure does not need to be provided as an electrical lead.
  • the substrate 30 located on the lower side of the semiconductor structure is not provided with conductive vias, and conductive vias and conductive pads 110 are provided on the upper surface of the protective layer 10.
  • the metal bonded to each other between adjacent substrates can have two functions. One is to ensure electrical connection, and the other is to ensure sealing. In the drawings of the present invention, only the metal bonding structure that plays the role of electrical connection is shown. .
  • the protective layer or the first substrate 10 is used as the uppermost substrate of the semiconductor structure.
  • the upwardly facing surface of each substrate is the upper surface
  • the downwardly facing surface of each substrate is the lower surface.
  • FIG. 6 is a schematic cross-sectional view of a semiconductor structure with stacked cells in the prior art.
  • the reference signs are as follows:
  • the bonding metal 60 is dry etched, the cost is very high; if the metal liftoff process is used, the metal thickness is relatively thick (generally, the thickness of the bonding metal 60 is in the range of 3-6 microns Inside), the metal peeling off is not clean, and the process is difficult; if wet etching is used, it is difficult to control the patterned morphology of the metal, and the phenomenon of over-etching and falling off occurs.
  • the present invention optimizes the structure and increases the protruding structure during bonding and packaging, which can not only solve the above-mentioned problems, but also improve the sealing effect.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure with stacked cells according to an exemplary embodiment of the present invention, wherein the semiconductor structure has only three substrates.
  • the components denoted by the reference numerals are as follows:
  • the first substrate can be used as a protective layer or a protective sealing layer.
  • the optional materials are monocrystalline silicon, gallium arsenide, sapphire, quartz, etc.
  • the second substrate, the optional materials are monocrystalline silicon, gallium arsenide, sapphire, quartz, etc.
  • the third substrate, optional materials are monocrystalline silicon, gallium arsenide, sapphire, quartz, etc.
  • Bonding metal, set on the first substrate, and its material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a combination of the above metals or their alloys.
  • Bonding metal, set on the second substrate, and its material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a combination of the above metals or their alloys.
  • the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or their alloys. Wait.
  • Bonding metal, set on the third substrate, and its material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a combination of the above metals or their alloys.
  • the acoustic wave resonator includes but is not limited to: an acoustic mirror, which can be a cavity, or a Bragg reflective layer and other equivalent forms;
  • the top electrode (electrode pin) the material can be molybdenum, ruthenium, gold, aluminum, and magnesium , Tungsten, copper, titanium, iridium, osmium, chromium or a combination of the above metals or their alloys, etc.; piezoelectric film layer, optional aluminum nitride, zinc oxide, PZT and other materials and contain a certain atomic ratio of rare earth elements of the above materials Doped material; top electrode (electrode pin), the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium
  • Protruding structure which is set on the lower surface of the second substrate in the figure, and is integrally formed with the second substrate.
  • the via structure 100 can be filled with a conductive material to form a conductive via.
  • the upwardly facing surface of each substrate is the upper surface
  • the downwardly facing surface of each substrate is the lower surface
  • FIG. 1 the conductive via 100 passing through the first substrate 10, the bonding metal 40, the bonding metal 50, the second substrate 20, the protrusion structure 90 and the bonding metal 60 is shown.
  • a protective layer bonding structure (ie, bonding metal 40) is provided on the lower surface of the first substrate 10 under the through hole 100; a second substrate upper key is provided on the upper surface of the second substrate 20
  • the bonding structure (ie bonding metal 50) is provided with a second substrate bonding structure (ie, bonding metal 60) on the lower surface of the second substrate 20; a third substrate bonding structure (ie, bonding metal 60) is provided on the upper surface of the third substrate 30 Bonded structure (ie bonding metal 70).
  • the conductive via 100 passes through the corresponding bonding structure until it is electrically connected to the bonding structure on the corresponding substrate (the substrate where the unit to be electrically connected to the conductive via is located).
  • the bonding between adjacent substrates or adjacent layers is achieved through the adjacent bonding structure, and in addition, the connection through holes provided between the adjacent layers may be formed by the bonding structure.
  • the upper ends of the conductive vias are opened or located on the upper surface of the first substrate 10.
  • the conductive pad 110 is electrically connected to the upper end of the conductive via on the upper surface of the first substrate 10.
  • the lower surface of the second substrate 20 is provided with a convex structure 90 protruding downward, the through hole 100 passes through the convex structure 90, and the bonding metal 60 surrounds the through hole to cover the outside of the convex structure 90.
  • the bonding metal 60 covers the convex structure 90 and covers a part of the lower surface of the second substrate on both sides of the convex structure in the lateral direction, as also mentioned later Shown in Figure 1A.
  • the width of the bonding metal 60 in the lateral direction can be greater than the width of the raised structure 90 by 1 um or more to ensure that the bonding size is defined by the raised structure 90, which can reduce the alignment of the time engraving when the bonding metal 60 is formed.
  • the height of the raised structure 90 increases the sacrificial length of the lateral etching of the bonding metal 60, which can ultimately ensure that the top or end surface of the raised structure 90 is covered by the bonding metal 60.
  • the bonding-bump structure formed by the combination of the convex structure 90 and the bonding metal 60 realizes that the size of the bonding metal is determined by the convex structure 90 with higher dimensional accuracy control, which reduces the alignment accuracy requirements and is also beneficial Solve the problem of poor sealing performance of the bonding metal 60.
  • the purpose of providing the protruding structure 90 is at least to maintain a good morphology for the bonding metal 60 on the substrate 20 and to easily form a self-aligned structure with the substrate 30.
  • FIG. 1A is a schematic cross-sectional view further showing that a bonding-protrusion structure is provided on the underside of the substrate.
  • the bonding layer 60 has portions a, b, and c.
  • the wet etching generally needs to increase the excess of 50%. Etching, as shown in Figure 1A, the metal in area b is easily over-etched.
  • the metal in area a will not be etched clean even if the etching time is increased by 50%, so The patterning of the metal structure in the area c remains intact, which lays a good foundation for the next step of bonding and self-alignment, and ensures the tightness of the product.
  • the height t1 may be 2-10 ⁇ m, and the width d1 may be 20-300 ⁇ m. Specifically, the width may be 20 ⁇ m, 100 ⁇ m, 300 ⁇ m, and the height may be 2 ⁇ m, 5 ⁇ m, and 10 ⁇ m.
  • the raised structure 90 may be made of the same material as the base 20 (obtained by thinning the base 20), and the raised structure 90 may be made of a different material from the base 20.
  • FIGS. 4A-4C are respectively schematic cross-sectional views showing a semiconductor structure of a bump structure according to an exemplary embodiment of the present invention.
  • the protruding structure 90 is a comb-shaped structure; in FIG. 4B, the protruding structure 90 is a semi-comb-shaped structure; in FIG. 4C, the protruding structure 90 is a concave wedge-shaped structure.
  • the through hole 100 passes through the protruding structure and the protruding structures are all arranged around the through hole 100.
  • 4A-4C are only examples in which the end surface of the convex structure can be configured as a concave-convex structure.
  • the configuration of the bonding end surface of the convex structure 90 as a concave-convex structure is beneficial to prevent the bonding metal 60 from falling off, and it is also beneficial to improve the sealing performance between the bonding metal 60 and the bonding metal 70.
  • FIGS. 2A-2F a method of forming the semiconductor structure with a plurality of stacked units shown in FIG. 1 by using a vertical stacking process will be exemplified.
  • a first substrate 10 is provided, and a bonding metal 40 is provided on the first substrate;
  • a second substrate 20 is provided.
  • the upper surface of the second substrate is provided with a bonding metal 50.
  • the second substrate 20 is also provided with a second through hole 100B, which penetrates the bonding metal 50 and partially enters the second substrate.
  • a substrate 20, a semiconductor device 80 is arranged on the second substrate;
  • the first substrate 10 and the second substrate 20 are opposed to each other and the bonding metal 40 and the corresponding bonding metal 50 are bonded to each other;
  • the second substrate is thinned from the lower surface of the second substrate to expose the second through hole 100B;
  • a convex structure 90 is formed on the lower surface of the second substrate 20 by means of etching or the like, and the convex structure 90 protrudes from the lower surface of the second substrate;
  • the bonding metal 60 is covered on the protrusion structure 90, and the second through hole 100B penetrates the bonding metal 60;
  • a third substrate 30 is provided.
  • the upper surface of the third substrate is provided with a bonding metal 70 and a semiconductor device 80, and then the third substrate 30 and the second substrate 20 are opposed to each other so that the bonding metal 70 corresponds to The bonding metals 60 are bonded to each other.
  • the wall thickness of the conductive metal post in the through hole gradually decreases from top to bottom as a whole.
  • the conductive vias can be obtained by one-time filling and molding to form an integrated conductive post.
  • the integrated conductive post means that the conductive post is formed integrally based on one-time filling of conductive material, rather than after two conductive vias are filled separately , Perform the bonding operation again to make the two conductive vias conductive. Because the conductive pillars are integrally formed, in the present invention, the conductive pillars do not have the problems of easy formation of holes, virtual connections, and contamination defects at the two metal-filled contacts caused by the bonding operation.
  • Fig. 3 is a schematic cross-sectional view of a semiconductor structure with stacked cells according to an exemplary embodiment of the present invention, wherein the semiconductor structure has a five-layer substrate.
  • the specific number of layers here is only exemplary, and the semiconductor structure may also have other number of layers.
  • the third substrate 30 has a plurality of third holes 100C passing through the corresponding bonding metal 70 and partially entering the third substrate 30;
  • the second through hole 100B and the third through hole 100C are aligned and communicated;
  • the third substrate can be thinned from the lower surface of the third substrate 30 to form a new To expose the third through hole 100C on the lower surface, and another raised structure 90A is formed around the third through hole 100C, and the additional raised structure 90A protrudes from the new lower surface;
  • the bonding metal 60A is covered on the other raised structure 90A (a second bonding-protruding structure can be formed);
  • a fourth substrate 120 is provided, at least one of the fourth substrate 120 and the third substrate 30 may be provided with a chip, and the upper surface of the fourth substrate 120 is provided with a plurality of corresponding bonding metals 70A;
  • the bonding metal 60A and the corresponding bonding metal 70A on the fourth substrate 120 are bonded to each other to form a receiving space between the third substrate 30 and the fourth substrate 120.
  • a fifth substrate 130 is also stacked, the fourth substrate 120 is provided with a fourth through hole 100D, and the protrusion structure 90B is covered with a bonding metal 60B (a third bonding-protrusion structure can be formed);
  • the second substrate 130 is provided with a bonding metal 70B, and the bonding metal 70B can be bonded to the corresponding bonding metal 60B.
  • the second through hole 100B, the third through hole 100C, and the fourth through hole 100D may be aligned with and communicate with each other.
  • the first substrate 10 serves as a protective layer, and no through holes are provided therethrough.
  • the first substrate 10 may also be provided with a first through hole.
  • the first substrate 10 is provided with a first through hole 100A, which is aligned with and communicates with the second through hole 100B to form a conductive through hole 100.
  • the upper surface of the first substrate 10 is also provided with a conductive pad 110, the material of which may be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a combination of the above metals or their alloys.
  • the lower surface of the first substrate 10 may also be provided with a bonding-protrusion structure.
  • an electroplating process may be used to form an effective electrical connection in the first through hole 100A and the second through hole 100B at one time (ie, the conductive through hole 100 is formed).
  • This one-time filling can effectively solve or alleviate the problems of poor second bonding effect and poor sealing performance caused by the separate filling of the through holes.
  • the electrical conduction performance is better, and the process steps are also saved.
  • the conductive pad 110 to which the conductive via 100 is electrically connected can be formed.
  • the corresponding conductive through holes of each layer may not penetrate each other axially, but may be staggered in the radial direction.
  • the conductive via electrically connected to the upper layer is inside the conductive via electrically connected to the lower layer.
  • a semiconductor structure with stacked units comprising at least two units stacked in a thickness direction of the semiconductor structure, the at least two units are provided with at least one chip and include at least one unit pair, the unit For the upper unit and the lower unit that are adjacent in the thickness direction of the semiconductor structure, the upper unit is above the lower unit, where:
  • Both the upper unit and the lower unit include a base
  • the lower surface of the base of the upper unit is provided with a plurality of convex structures protruding downward, and the convex structures are covered with a bonding layer to form a bonding-protrusion structure together with the convex structures;
  • the upper surface of the base of the lower unit is provided with conductive bumps protruding upward, the bonding-protrusion structure and the corresponding conductive bumps are aligned with each other and connected by bonding, and the lower surface of the base of the upper unit is connected to the base of the lower unit.
  • a first accommodation space is defined between the upper surfaces.
  • the semiconductor structure further includes a conductive through hole that passes through at least one substrate to form an electrical connection under the substrate, and the conductive through hole passes through or its axis passes through the corresponding bonding-protrusion structure.
  • the conductive vias include conductive vias that pass through the base of the upper unit and are electrically connected to the corresponding bond-protrusion structure.
  • the at least one unit pair includes at least two unit pairs, and the two unit pairs include a first unit, a second unit, and a third unit that are sequentially stacked from top to bottom in the thickness direction of the semiconductor structure, wherein the first unit The unit and the second unit form a first unit pair, and the second unit and the third unit form a second unit pair.
  • the conductive vias include conductive vias that pass through at least one substrate of the two unit pairs to be electrically connected to the corresponding bond-protrusion structure.
  • the conductive pillars in the conductive through holes are integrally formed conductive pillars.
  • the integrally formed conductive column is a conductive column whose wall thickness gradually decreases from top to bottom.
  • the two uppermost units of the semiconductor structure constitute an uppermost unit pair, and the base of the topmost unit of the semiconductor structure constitutes a protective layer, and the protective layer has an upper surface and a lower surface;
  • the conductive via includes a conductive via that extends from the upper surface of the protective layer through the protective layer and extends downward through the corresponding substrate in the thickness direction of the protective layer to be electrically connected to the bonding-protrusion structure of the corresponding unit .
  • the conductive vias include conductive vias that are only electrically connected to the bond-protrusion structure of a corresponding unit under the protective layer.
  • the conductive vias include conductive vias electrically connected to the bonding-protrusion structures of at least two corresponding units under the protective layer.
  • the conductive vias include conductive vias that are electrically connected to the corresponding bond-protrusion structures of all units provided with the bond-protrusion structure.
  • the two uppermost units of the semiconductor structure constitute an uppermost unit pair, and the base of the topmost unit of the semiconductor structure constitutes a protective layer, and the protective layer has an upper surface and a lower surface;
  • the conductive vias include conductive vias that extend from the upper surface of the protective layer through the protective layer and extend downward in the thickness direction of the protective layer, and are only electrically connected to the lower unit of the uppermost pair of units.
  • the conductive via electrically connected to the upper unit is located inside the conductive via electrically connected to the lower unit.
  • the semiconductor structure further includes a conductive pad located on the upper surface of the protective layer and electrically connected to the conductive via.
  • the protruding structure is integrally formed with the base on which it is provided.
  • the bonding layer covers the convex structure and covers a part of the lower surface of the substrate on both sides of the convex structure in the lateral direction.
  • the conductive vias include conductive vias passing through the corresponding bond-protrusion structure.
  • the end surface of the convex structure is provided with a concave-convex shape arranged around the conductive through hole.
  • the concave-convex shape includes a comb-shaped structure or a concave wedge-shaped structure.
  • the protrusion height t1 of the protrusion structure is in the range of 2 ⁇ m-10 ⁇ m; and/or
  • the width d1 of the annular structure formed by the protruding structure surrounding the through hole is in the range of 20 ⁇ m-300 ⁇ m.
  • the semiconductor structure is a thin film bulk acoustic wave resonator or a thin film bulk acoustic wave filter, or a duplexer, or a quadruple.
  • a method for manufacturing a semiconductor structure with stacked units including the steps:
  • the first unit having a first substrate and a plurality of first holes passing through the first substrate;
  • the first substrate is thinned from the lower surface of the first substrate to form a first new lower surface to expose the first hole, and a first protruding structure is formed around the first hole, and the first protruding structure is self-exposed
  • the first new lower surface is protruding
  • the second unit having a second substrate, and a plurality of second bonding protrusions are provided on the upper surface of the second substrate;
  • the first bonding-protrusion structure and the corresponding second bonding protrusion are bonded to each other to form a first accommodating space between the first substrate and the second substrate.
  • the second unit has a plurality of second holes passing through the corresponding second bonding protrusions and partially into the second substrate;
  • the first hole and the second hole are aligned and communicated;
  • the method also includes the steps:
  • the second substrate is thinned from the lower surface of the second substrate to form a second new lower surface to expose the second hole, and a second convex structure is formed around the second hole, the second convex structure is The second new lower surface is protruding;
  • the third unit having a third substrate, and a plurality of third bonding protrusions are provided on the upper surface of the third substrate;
  • the second bonding-protrusion structure and the corresponding third bonding protrusion are bonded to each other to form a second accommodating space between the second substrate and the third substrate.
  • the upper surface of the first unit is provided with a plurality of first bonding protrusions
  • the method further includes the steps of: providing a fourth unit, the fourth unit having a fourth substrate, a lower surface of the fourth substrate is provided with a plurality of fourth bonding protrusions; and making the first bonding protrusions and the corresponding fourth The bonding protrusions are bonded to each other to form a third receiving space between the first substrate and the fourth substrate.
  • the first hole is a conductive through hole that is electrically connected to the corresponding bonding-protrusion structure.
  • the fourth unit has a plurality of fourth holes passing through the corresponding fourth bonding protrusions and partially entering the fourth substrate;
  • the first hole and the fourth hole are aligned and communicated;
  • the method also includes the steps:
  • a conductive pad electrically connected to the corresponding conductive via is formed on the upper surface of the fourth substrate.
  • the protruding structure is formed by etching the corresponding substrate.
  • An electronic device comprising the semiconductor structure according to any one of 1-21 or the semiconductor structure manufactured according to any one of 22-27.
  • the semiconductor structure may be a thin film bulk acoustic wave resonator, or a thin film bulk acoustic wave filter, or a duplexer, or a quadruplexer.
  • the semiconductor structure may also be other structures based on the different chips provided in the unit.
  • the chip may include semiconductor devices, such as microelectromechanical devices, active or passive semiconductor devices, and the like.
  • the electronic equipment here includes but is not limited to intermediate products such as radio frequency front-ends, filter amplification modules, and terminal products such as mobile phones, WIFI, and drones.

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Abstract

本发明涉及具有叠置单元的半导体结构，包括沿半导体结构的厚度方向上叠置的至少两个单元，所述至少两个单元设置有至少一个芯片、且包括至少一个单元对，所述单元对包括在半导体结构的厚度方向上相邻的上单元和下单元，上单元在下单元上方，其中：上单元与下单元均包括基底；上单元的基底下表面设置有向下凸出的多个凸起结构，所述凸起结构覆盖有键合层而与凸起结构一起形成键合-凸起结构；下单元的基底上表面设置有向上凸出的导电凸块，所述键合-凸起结构与对应的导电凸块彼此相对对齐且键合连接，上单元的基底的下表面与下单元的基底的上表面之间限定第一容纳空间。本发明还涉及具有叠置单元的半导体结构的制造方法及具有该结构的电子设备。

Description

具有叠置单元的半导体结构及制造方法、电子设备 技术领域
本发明的实施例涉及半导体领域，尤其涉及一种半导体结构及其制造方法，以及一种具有该半导体结构的电子设备。
背景技术
随着当今无线通讯技术的飞速发展，小型化便携式终端设备的应用也日益广泛，因而对于高性能、小尺寸的射频前端模块和器件的需求也日益迫切。近年来，以例如为薄膜体声波谐振器(Film Bulk Acoustic Resonator，简称FBAR)为基础的滤波器、双工器等滤波器件越来越为市场所青睐。一方面是因为其插入损耗低、过渡特性陡峭、选择性高、功率容量高、抗静电放电(ESD)能力强等优异的电学性能，另一方面也是因为其体积小、易于集成的特点所致。
不过，现实中对于滤波器件的尺寸存在进一步减小的需要。
发明内容
为进一步减小例如滤波器件的尺寸，已有技术提出了半导体器件垂直叠置的方法，这需要进行晶圆级封装键合。金属键合是常用的方式，此种键合工艺简单、密封性好。但由于金属图形化需要湿法刻蚀形成，湿法溶液的各项同性会导致侧向刻蚀严重，因此对图形尺寸的控制性差，导致键合密封性差的问题。为解决或缓解键合密封性差的问题，本发明提出一种垂直叠层封装时键合对准的结构和方法。
根据本发明的实施例的一个方面，提出了一种具有叠置单元的半导体结构，包括沿半导体结构的厚度方向上叠置的至少两个单元，所述至少两个单元设置有至少一个芯片、且包括至少一个单元对，所述单元对包括在半导体结构的厚度方向上相邻的上单元和下单元，上单元在下单元上方，其中：
上单元与下单元均包括基底；
上单元的基底下表面设置有向下凸出的多个凸起结构，所述凸起结构覆盖有键合层而与凸起结构一起形成键合-凸起结构；
下单元的基底上表面设置有向上凸出的导电凸块，所述键合-凸起结构与对应的导电凸块彼此相对对齐且键合连接，上单元的基底的下表面与下单元的基底的上表面之间限定第一容纳空间。
本发明的实施例还涉及一种具有叠置单元的半导体结构的制造方法，包括步骤：
提供第一单元，第一单元具有第一基底，以及穿过第一基底的多个第一孔；
从第一基底的下表面减薄第一基底而形成第一新下表面以露出所述第一孔，且围绕所述第一孔形成第一凸起结构，所述第一凸起结构自所述第一新下表面凸出；
在所述第一凸起结构上覆盖键合层以形成第一键合-凸起结构；
提供第二单元，第二单元具有第二基底，所述第二基底的上表面设置有多个第二键合凸起；
使得第一键合-凸起结构与对应的第二键合凸起彼此键合以在第一基底与第二基底之间形成第一容纳空间。
本发明的实施例还涉及一种电子设备，具有上述的半导体结构。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1为根据本发明的一个示例性实施例的具有叠置单元的半导体结构的示意性剖视图，其中该半导体结构仅有三层基底；
图1A为进一步示例性示出基底下侧设置键合-凸起结构的示意性剖视图；
图2A-2G为示例性示出图1中的半导体结构的制造过程的示意图；
图3为根据本发明的一个示例性实施例的具有叠置单元的半导体结构的示意性剖视图，其中该半导体结构具有五层基底；
图4A-4C分别为示出根据本发明的示例性实施例的半导体结构的凸起结构的示意性剖视图；
图5为根据本发明的一个示例性实施例的具有叠置单元的半导体结构的示意性剖视图，其中该半导体结构仅有三层基底，且导电通孔贯穿过第一基底；
图6为已知技术中的具有叠置单元的半导体结构的示意性剖视图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。
在本发明中，以声波滤波器为例说明半导体结构。声波滤波器可采用多基底的方式，进行垂直方向电连接，可以降低滤波器、双工器、四工器等面积达30％以上。
在本发明中，整体对外的电学输入输出均在作为半导体结构的最顶层的保护层或第一基底10(后面提及)的上表面，相应的半导体结构的下表面不需要设置起电学引线作用的通孔，例如在图5中，位于半导体结构的下侧的基底30并未设置导电通孔，导电通孔以及导电焊盘(pad)110设置在保护层10的上表面。
相邻基底之间相互键合的金属可以有两种作用，一是保证电学连接，二是保证密封性，在本发明的附图中，仅示出了起到电学连接作用的金属键合结构。
在本发明中，以保护层或第一基底10作为半导体结构的最上层基底。例如，在图中，在半导体结构中，各个基底朝上的表面为上表面，各个基底朝下的表面为下表面。
图6为已知技术中的具有叠置单元的半导体结构的示意性剖视图。其中的附图标记如下：
10：第一基底；20：第二基底；30：第三基底；40：键合金属；50：键合金属；60：键合金属；70：键合金属；80：芯片或半导体器件；100：导电通孔。
在图6所示的结构中，在图形化键合金属60的时候，可能出现过刻蚀或者金属脱落现象，导致键合密封性差。
此外，键合金属60若采用干法刻蚀方式，成本很高；若采用金属剥离(Liftoff)工艺，则金属厚度比较厚(一般而言，键合金属60的厚度在3-6微米的范围内)，出现金属剥离不干净情况，工艺难度大；若采用湿法刻蚀，则金属图形化形貌很难控制，出现过刻蚀、脱落的现象。
本发明从结构上进行优化，增加键合封装时的凸起结构，不但可以解决上述问题，而且能够提高密封的效果。
图1为根据本发明的一个示例性实施例的具有叠置单元的半导体结构的示意性剖视图，其中该半导体结构仅有三层基底。在图1中，各附图标记表示的部件如下：
10：第一基底，可作为保护层或保护密封层，可选材料为单晶硅、砷化镓、蓝宝石、石英等。
20：第二基底，可选材料为单晶硅、砷化镓、蓝宝石、石英等。
30：第三基底，可选材料为单晶硅、砷化镓、蓝宝石、石英等。
40：键合金属，设置于第一基底，其材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
50：键合金属，设置于第二基底，其材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
60：键合金属，设置于第二基底的凸起结构上，其材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
70：键合金属，设置于第三基底，其材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
80：芯片或半导体器件，例如为单个声波谐振器或多个声波谐振器电学连接结构。其中，声波谐振器包含但不限于：声学镜，可为空腔，也可采用布拉格反射层及其他等效形式；顶电极(电极引脚)，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等；压电薄膜层，可选氮化铝，氧化锌，PZT等材料并包含上述材料的一定原子比的稀土元素掺杂材料；顶电极(电极引脚)，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
90：凸起结构，图中设置在第二基底的下表面，与第二基底一体形成。
100：通孔结构，其中设置有导电材料，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。如本领域技术人员能够理解的，通孔结构100中填充导电材料可以形成导电通孔。
在本发明中，在图中半导体结构中，各个基底朝上的表面为上表面，各个基底朝下的表面为下表面。
在图1中，示出了穿过第一基底10、键合金属40、键合金属50、第二基底20、凸起结构90及键合金属60的导电通孔100。
如图1所示，在第一基底10的下表面在通孔100的下方设置有保护层键合结构(即键合金属40)；在第二基底20的上表面设置有第二基底上键合结构(即键合金属50)，在第二基底20的下表面设置有第二基底上键合结构(即键合金属60)；在第三基底30的上表面设置有第三基底上键合结构(即键合金属70)。在第一基底10、第二基底20和第三基底30叠置时，相应的键合结构彼此键合。如图1所示，导电通孔100穿过对应的键合结构直至与对应基底(导电通孔所要电连接的单元所在的基底)上的键合结构电连接。换言之，如本领域技术人员能够理解的，相邻基底或相邻层之间的键合经由相邻键合结构实现，此外，相邻层之间设置的连接通孔可以由键合结构形成。
如图1所示，导电通孔的上端开口于或者位于第一基底10的上表面。如图1所示，导电焊盘110在第一基底10的上表面与导电通孔的上端电连接。
在图1中，第二基底20的下表面设置有向下凸出的凸起结构90，通孔100穿过凸起结构90，且键合金属60围绕通孔覆盖凸起结构90的外侧。在进一步的实施例中，如图1所示，键合金属60覆盖凸起结构90且覆盖凸起结构在横向方向上的两侧的第二基底的下表面的一部分，也如后续提及的图1A所示。键合金属60在横向上的宽度，可大于凸起结构90的宽度1um及以上，以保证键合大小由凸起结构90定义，这可以降低在形成键合金属60时光刻对准的对准精度。此外，凸起结构90的高度增加了键合金属60横向刻蚀可牺牲长度，最终可以保证凸起结构90的顶部或端面被键合金属60覆盖。凸起结构90与键合金属60的结合形成的键合-凸起结构，实现了键合金属尺寸由尺寸精度控制更高的凸起结构90来决定，减少了对准精度要求，也有利于解决键合金属60键合密封性差的问题。在本发明中，设置凸起结构90的目的至少在于为基底20上的键合金属60保持良好形貌以及易于与基底30形成自对准结构。
图1A为进一步示出基底下侧设置键合-凸起结构的示意性剖视图。如图1A所示，键合层60具有部分a、b和c。在对键合层或键合金属60进行湿法刻蚀时，因湿法刻蚀的各向同性原理和为了将图形化以外的金属刻蚀干净，湿法刻蚀一般需要增加50％的过刻蚀，如图1A中所示，区域b的金属很容易过刻蚀，因凸起结构90的存在，区域a的金属在刻蚀时间增加50％的情况也不会被刻蚀干净，所以区域c的金属结构图形化完整保留，对下一步的键合和自对准打下良好的基础，保证了产品的密封性。
如图1A所示，在可选的实施例中，高度t1可为2-10μm，宽度d1可为20-300μm。具体的，宽度可以是20μm，100μm，300μm，高度可以是2μm，5μm和10μm。
在本发明中，凸起结构90可以为与基底20材质一致(通过减薄基底20得到)，凸起结构90页可以为不同于基底20的材质。
图4A-4C分别为示出根据本发明的示例性实施例的凸起结构的半导体结构的示意性剖视图。在图4A中，凸起结构90为梳状结构；在图4B中，凸起结构90为半梳状结构；在图4C中，凸起结构90为凹入的楔形结构。在图4A-4C中，通孔100穿过凸起结构且凸起结构均围绕通孔100 设置。图4A-4C仅仅是凸起结构的端面可以设置为凹凸结构的示例。凸起结构90的键合端面设置为凹凸结构有利于防止键合金属60脱落，也有利于提高键合金属60与键合金属70之间的密封性。
下面参照附图2A-2F，示例性说明采用垂直叠层工艺形成图1所示的具有多个叠置单元的半导体结构的方法。
如图2A所示，提供第一基底10，第一基底上设置有键合金属40；
如图2B所示，提供第二基底20，第二基底上表面设置有键合金属50，第二基底20还设置有第二通孔100B，其穿过键合金属50且部分进入到第二基底20，第二基底上设置有半导体器件80；
如图2C所示，将第一基底10与第二基底20对置且使得键合金属40与对应的键合金属50彼此键合；
如图2D所示，从第二基底的下表面减薄第二基底，以露出第二通孔100B；
接着如图2E所示，利用刻蚀等手段在第二基底20的下表面形成凸起结构90，凸起结构90从第二基底的下表面凸出；
如图2F所示，在凸起结构90上覆盖键合金属60，且第二通孔100B穿过键合金属60；
如图2G所示，提供第三基底30，第三基底上表面设置有键合金属70和半导体器件80，然后将第三基底30与第二基底20对置且使得键合金属70与对应的键合金属60彼此键合。
在本发明中，通孔中的导电金属柱的壁厚总体上从上而下逐渐降低。
在本发明中，导电通孔可以通过一次填充成型而获得，从而形成一体成型的导电柱，导电柱一体成型表示导电柱基于一次填充导电材料而一体形成，而非两个导电通孔分别填充后、再执行键合操作而使得两个导电通孔导通。因为导电柱为一体成型，所以在本发明中，导电柱不存在所谓的因为键合操作而导致的两次金属填充接触处易形成孔洞、虚连接、沾污缺陷等问题。
图3为根据本发明的一个示例性实施例的具有叠置单元的半导体结 构的示意性剖视图，其中该半导体结构具有五层基底。这里的具体的层数仅仅是示例性的，半导体结构也可以是其他的层数。
为了在第三基底的下表面在层叠或叠置第四基底，虽然没有图示出具体的步骤，但本领域技术人员在上面描述的基础上能够理解：
在“提供第三基底”的步骤中，第三基底30具有穿过对应的键合金属70以及部分进入第三基底30的多个第三孔100C；
在使得键合金属70与对应的键合金属60彼此键合的步骤中，第二通孔100B与第三通孔100C对齐且相通；
与在第二基底20的下表面形成凸起结构90与键合金属60(可形成第一键合-凸起结构)类似，可以从第三基底30的下表面减薄第三基底而形成新的下表面以露出第三通孔100C，且围绕所述第三通孔100C形成另外的凸起结构90A，该另外的凸起结构90A自所述新的下表面凸出；
之后，在所述另外的凸起结构90A上覆盖键合金属60A(可以形成第二键合-凸起结构)；
然后，提供第四基底120，第四基底120和第三基底30中的至少一个可设置有芯片，且所述第四基底120的上表面设置有对应的多个键合金属70A；
使得键合金属60A与第四基底120上对应的键合金属70A彼此键合以在第三基底30与第四基底120之间形成容纳空间。
如此重复，可以叠置更多的层。在图3中，还叠置有第五基底130，第四基底120设置有第四通孔100D，以及凸起结构90B上覆盖键合金属60B(可以形成第三键合-凸起结构)；第二基底130上设置有键合金属70B，键合金属70B可以与对应的键合金属60B键合。
在图3中，第二通孔100B，第三通孔100C和第四通孔100D可以彼此对齐且相通。
在本发明图1-图4C所示的上述实施例中，第一基底10作为保护层，并未设置穿过其的通孔。但是，本发明不限于此。第一基底10也可以设置有第一通孔。如图5所示，第一基底10设置有第一通孔100A，其与第二通孔100B彼此对齐且相通以形成导电通孔100。第一基底10的上表面还设置有导电焊盘110，其材料可选钼、钌、金、铝、镁、钨、铜，钛、 铱、锇、铬或以上金属的复合或其合金等。
虽然没有示出，第一基底10的下表面也可以设置有键合-凸起结构。
可以在第一通孔和第二通孔对齐且相通之后，利用电镀工艺一次性使第一通孔100A和第二通孔100B中形成有效电连接(即形成导电通孔100)。此一次性填充，可有效解决或缓解通孔单独填充时带来的第二次键合效果不佳、密封性差的问题，同时电学导通性能更佳，也节省了工艺步骤。最后，可形成导电通孔100电连接的导电焊盘110。
在本发明中，各层的对应导电通孔也可以不是彼此轴向贯通的，而是可以在径向方向上错开。例如，虽然没有示出，对于在厚度方向上相邻叠置的两层，在径向方向或横向方向上，与上层电连接的导电通孔处于与下层电连接的导电通孔的内侧。
基于以上，本发明提出了如下技术方案：
1、一种具有叠置单元的半导体结构，包括沿半导体结构的厚度方向上叠置的至少两个单元，所述至少两个单元设置有至少一个芯片、且包括至少一个单元对，所述单元对包括在半导体结构的厚度方向上相邻的上单元和下单元，上单元在下单元上方，其中：
上单元与下单元均包括基底；
上单元的基底下表面设置有向下凸出的多个凸起结构，所述凸起结构覆盖有键合层而与凸起结构一起形成键合-凸起结构；
下单元的基底上表面设置有向上凸出的导电凸块，所述键合-凸起结构与对应的导电凸块彼此相对对齐且键合连接，上单元的基底的下表面与下单元的基底的上表面之间限定第一容纳空间。
2、根据1所述的半导体结构，其中：
所述半导体结构还包括穿过至少一个基底而与基底下方形成电连接的导电通孔，所述导电通孔穿过或者其轴线穿过对应的键合-凸起结构。
3、根据2所述的半导体结构，其中：
所述导电通孔包括穿过上单元的基底而与对应的键合-凸起结构电连接的导电通孔。
4、根据2所述的半导体结构，其中：
所述至少一个单元对至少包括两个单元对，所述两个单元对包括在半导体结构的厚度方向上从上往下依次叠置的第一单元、第二单元和第三单元，其中第一单元与第二单元形成第一单元对，第二单元与第三单元形成第二单元对。
5、根据4所述的半导体结构，其中：
所述导电通孔包括穿过所述两个单元对的至少一个基底而与对应的键合-凸起结构电连接的导电通孔。
6、根据5所述的半导体结构，其中：
所述导电通孔内的导电柱为一体成型导电柱。
7、根据6所述的半导体结构，其中：
所述一体成型导电柱为壁厚从上到下逐渐变细的导电柱。
8、根据2-7中任一项所述的半导体结构，其中：
所述半导体结构的最上侧的两个单元构成最上侧单元对，且半导体结构的最顶层的单元的基底构成保护层，保护层具有上表面与下表面；
所述导电通孔包括自所述保护层的上表面穿过所述保护层沿保护层的厚度方向向下延伸穿过对应基底而与对应单元的键合-凸起结构电连接的导电通孔。
9、根据8所述的半导体结构，其中：
所述导电通孔包括仅与保护层下方一个对应的单元的键合-凸起结构电连接的导电通孔。
10、根据8所述的半导体结构，其中：
所述导电通孔包括与保护层下方至少两个对应的单元的键合-凸起结构电连接的导电通孔。
11、根据10所述的半导体结构，其中：
所述导电通孔包括与所有设置有键合-凸起结构的单元的对应键合-凸起结构电连接的导电通孔。
12、根据2所述的半导体结构，其中：
所述半导体结构的最上侧的两个单元构成最上侧单元对，且半导体结构的最顶层的单元的基底构成保护层，保护层具有上表面与下表面；
所述导电通孔包括自所述保护层的上表面穿过所述保护层沿保护层 的厚度方向向下延伸而仅与最上侧单元对的下单元电连接的导电通孔。
13、根据2所述的半导体结构，其中：
对于所述单元对，在径向方向上，与上单元电连接的导电通孔处于与下单元电连接的导电通孔的内侧。
14、根据8所述的半导体结构，其中：
所述半导体结构还包括位于保护层的上表面与导电通孔电连接的导电焊盘。
15、根据1-14中任一项所述的半导体结构，其中：
所述凸起结构与其所设置的基底一体形成。
16、根据15所述的半导体结构，其中：
所述键合层覆盖所述凸起结构且覆盖所述凸起结构在横向方向上的两侧的部分基底的下表面。
17、根据15所述的半导体结构，其中：
所述导电通孔包括穿过对应的键合-凸起结构的导电通孔。
18、根据17所述的半导体结构，其中：
所述凸起结构的端面设置有围绕所述导电通孔布置的凹凸形状。
19、根据18所述的半导体结构，其中：
所述凹凸形状包括梳状结构或者凹入楔形结构。
20、根据2-14中任一项所述的半导体结构，其中：
所述凸起结构的凸出高度t1在2μm-10μm的范围内；和/或
所述凸起结构围绕所述通孔形成的环状结构的宽度d1在20μm-300μm的范围内。
21、根据1所述的半导体结构，其中：
半导体结构为薄膜体声波谐振器或薄膜体声波滤波器，或双工器，或四工器。
22、一种具有叠置单元的半导体结构的制造方法，包括步骤：
提供第一单元，第一单元具有第一基底，以及穿过第一基底的多个第一孔；
从第一基底的下表面减薄第一基底而形成第一新下表面以露出所述第一孔，且围绕所述第一孔形成第一凸起结构，所述第一凸起结构自所述 第一新下表面凸出；
在所述第一凸起结构上覆盖键合层以形成第一键合-凸起结构；
提供第二单元，第二单元具有第二基底，所述第二基底的上表面设置有多个第二键合凸起；
使得第一键合-凸起结构与对应的第二键合凸起彼此键合以在第一基底与第二基底之间形成第一容纳空间。
23、根据22所述的方法，其中：
在“提供第二单元”的步骤中，第二单元具有穿过对应第二键合凸起以及部分进入第二基底的多个第二孔；
在“使得第一键合-凸起结构与对应的第二键合凸起彼此键合”的步骤中，第一孔与第二孔对齐且相通；
所述方法还包括步骤：
从第二基底的下表面减薄第二基底而形成第二新下表面以露出所述第二孔，且围绕所述第二孔形成第二凸起结构，所述第二凸起结构自所述第二新下表面凸出；
在所述第二凸起结构上覆盖键合层以形成第二键合-凸起结构；
提供第三单元，第三单元具有第三基底，所述第三基底的上表面设置有多个第三键合凸起；
使得第二键合-凸起结构与对应的第三键合凸起彼此键合以在第二基底与第三基底之间形成第二容纳空间。
24、根据22或23所述的方法，其中：
在“提供第一单元”的步骤中，所述第一单元的上表面设置有多个第一键合凸起；
所述方法还包括步骤：提供第四单元，第四单元具有第四基底，第四基底的下表面设置有多个第四键合凸起；以及使得第一键合凸起与对应的第四键合凸起彼此键合以在第一基底与第四基底之间形成第三容纳空间。
25、根据22或23所述的方法，还包括步骤：
使得第一孔为与对应键合-凸起结构电导通的导电通孔。
26、根据24所述的方法，其中：
在“提供第四单元”的步骤中，所述第四单元具有穿过对应第四键合 凸起以及部分进入第四基底的多个第四孔；
在“使得第一键合凸起与对应的第四键合凸起彼此键合”的步骤中，第一孔与第四孔对齐且相通；
所述方法还包括步骤：
从第四基底的上表面减薄第四基底而形成新上表面以露出所述第四孔；
在第四孔以及与第四孔对齐且导通的对应孔内填充导电金属而形成导电通孔；和
在第四基底的上表面形成与对应导电通孔电连接的导电焊盘。
27、根据22-26中任一项所述的方法，其中：
形成凸起结构的步骤中，通过刻蚀对应基底而形成所述凸起结构。
28、一种电子设备，包括根据1-21中任一项所述的半导体结构或根据22-27中任一项所述的方法制造的半导体结构。
在本发明中，半导体结构可以是薄膜体声波谐振器，或薄膜体声波滤波器，或双工器，或四工器等。如能理解的，基于单元设置的芯片的不同，半导体结构也可以是其他结构。在本发明中，芯片可以包括半导体器件，如微机电器件、有源或无源半导体器件等。
这里的电子设备，包括但不限于射频前端、滤波放大模块等中间产品，以及手机、WIFI、无人机等终端产品。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (28)

  1. 一种具有叠置单元的半导体结构，包括沿半导体结构的厚度方向上叠置的至少两个单元，所述至少两个单元设置有至少一个芯片、且包括至少一个单元对，所述单元对包括在半导体结构的厚度方向上相邻的上单元和下单元，上单元在下单元上方，其中：
    上单元与下单元均包括基底；
    上单元的基底下表面设置有向下凸出的多个凸起结构，所述凸起结构覆盖有键合层而与凸起结构一起形成键合-凸起结构；
    下单元的基底上表面设置有向上凸出的导电凸块，所述键合-凸起结构与对应的导电凸块彼此相对对齐且键合连接，上单元的基底的下表面与下单元的基底的上表面之间限定第一容纳空间。
  2. 根据权利要求1所述的半导体结构，其中：
    所述半导体结构还包括穿过至少一个基底而与基底下方形成电连接的导电通孔，所述导电通孔穿过或者其轴线穿过对应的键合-凸起结构。
  3. 根据权利要求2所述的半导体结构，其中：
    所述导电通孔包括穿过上单元的基底而与对应的键合-凸起结构电连接的导电通孔。
  4. 根据权利要求2所述的半导体结构，其中：
    所述至少一个单元对至少包括两个单元对，所述两个单元对包括在半导体结构的厚度方向上从上往下依次叠置的第一单元、第二单元和第三单元，其中第一单元与第二单元形成第一单元对，第二单元与第三单元形成第二单元对。
  5. 根据权利要求4所述的半导体结构，其中：
    所述导电通孔包括穿过所述两个单元对的至少一个基底而与对应的键合-凸起结构电连接的导电通孔。
  6. 根据权利要求5所述的半导体结构，其中：
    所述导电通孔内的导电柱为一体成型导电柱。
  7. 根据权利要求6所述的半导体结构，其中：
    所述一体成型导电柱为壁厚从上到下逐渐变细的导电柱。
  8. 根据权利要求2-7中任一项所述的半导体结构，其中：
    所述半导体结构的最上侧的两个单元构成最上侧单元对，且半导体结构的最顶层的单元的基底构成保护层，保护层具有上表面与下表面；
    所述导电通孔包括自所述保护层的上表面穿过所述保护层沿保护层的厚度方向向下延伸穿过对应基底而与对应单元的键合-凸起结构电连接的导电通孔。
  9. 根据权利要求8所述的半导体结构，其中：
    所述导电通孔包括仅与保护层下方一个对应的单元的键合-凸起结构电连接的导电通孔。
  10. 根据权利要求8所述的半导体结构，其中：
    所述导电通孔包括与保护层下方至少两个对应的单元的键合-凸起结构电连接的导电通孔。
  11. 根据权利要求10所述的半导体结构，其中：
    所述导电通孔包括与所有设置有键合-凸起结构的单元的对应键合-凸起结构电连接的导电通孔。
  12. 根据权利要求2所述的半导体结构，其中：
    所述半导体结构的最上侧的两个单元构成最上侧单元对，且半导体结构的最顶层的单元的基底构成保护层，保护层具有上表面与下表面；
    所述导电通孔包括自所述保护层的上表面穿过所述保护层沿保护层的厚度方向向下延伸而仅与最上侧单元对的下单元电连接的导电通孔。
  13. 根据权利要求2所述的半导体结构，其中：
    对于所述单元对，在径向方向上，与上单元电连接的导电通孔处于与下单元电连接的导电通孔的内侧。
  14. 根据权利要求8所述的半导体结构，其中：
    所述半导体结构还包括位于保护层的上表面与导电通孔电连接的导电焊盘。
  15. 根据权利要求1-14中任一项所述的半导体结构，其中：
    所述凸起结构与其所设置的基底一体形成。
  16. 根据权利要求15所述的半导体结构，其中：
    所述键合层覆盖所述凸起结构且覆盖所述凸起结构在横向方向上的两侧的部分基底的下表面。
  17. 根据权利要求15所述的半导体结构，其中：
    所述导电通孔包括穿过对应的键合-凸起结构的导电通孔。
  18. 根据权利要求17所述的半导体结构，其中：
    所述凸起结构的端面设置有围绕所述导电通孔布置的凹凸形状。
  19. 根据权利要求18所述的半导体结构，其中：
    所述凹凸形状包括梳状结构或者凹入楔形结构。
  20. 根据权利要求2-14中任一项所述的半导体结构，其中：
    所述凸起结构的凸出高度t1在2μm-10μm的范围内；和/或
    所述凸起结构围绕所述通孔形成的环状结构的宽度d1在20μm-300μm的范围内。
  21. 根据权利要求1所述的半导体结构，其中：
    半导体结构为薄膜体声波谐振器或薄膜体声波滤波器，或双工器，或四工器。
  22. 一种具有叠置单元的半导体结构的制造方法，包括步骤：
    提供第一单元，第一单元具有第一基底，以及穿过第一基底的多个第一孔；
    从第一基底的下表面减薄第一基底而形成第一新下表面以露出所述第一孔，且围绕所述第一孔形成第一凸起结构，所述第一凸起结构自所述第一新下表面凸出；
    在所述第一凸起结构上覆盖键合层以形成第一键合-凸起结构；
    提供第二单元，第二单元具有第二基底，所述第二基底的上表面设置有多个第二键合凸起；
    使得第一键合-凸起结构与对应的第二键合凸起彼此键合以在第一基底与第二基底之间形成第一容纳空间。
  23. 根据权利要求22所述的方法，其中：
    在“提供第二单元”的步骤中，第二单元具有穿过对应第二键合凸起以及部分进入第二基底的多个第二孔；
    在“使得第一键合-凸起结构与对应的第二键合凸起彼此键合”的步骤中，第一孔与第二孔对齐且相通；
    所述方法还包括步骤：
    从第二基底的下表面减薄第二基底而形成第二新下表面以露出所述第二孔，且围绕所述第二孔形成第二凸起结构，所述第二凸起结构自所述第二新下表面凸出；
    在所述第二凸起结构上覆盖键合层以形成第二键合-凸起结构；
    提供第三单元，第三单元具有第三基底，所述第三基底的上表面设置有多个第三键合凸起；
    使得第二键合-凸起结构与对应的第三键合凸起彼此键合以在第二基底与第三基底之间形成第二容纳空间。
  24. 根据权利要求22或23所述的方法，其中：
    在“提供第一单元”的步骤中，所述第一单元的上表面设置有多个第一键合凸起；
    所述方法还包括步骤：提供第四单元，第四单元具有第四基底，第四基底的下表面设置有多个第四键合凸起；以及使得第一键合凸起与对应的第四键合凸起彼此键合以在第一基底与第四基底之间形成第三容纳空间。
  25. 根据权利要求22或23所述的方法，还包括步骤：
    使得第一孔为与对应键合-凸起结构电导通的导电通孔。
  26. 根据权利要求24所述的方法，其中：
    在“提供第四单元”的步骤中，所述第四单元具有穿过对应第四键合凸起以及部分进入第四基底的多个第四孔；
    在“使得第一键合凸起与对应的第四键合凸起彼此键合”的步骤中，第一孔与第四孔对齐且相通；
    所述方法还包括步骤：
    从第四基底的上表面减薄第四基底而形成新上表面以露出所述第四孔；
    在第四孔以及与第四孔对齐且导通的对应孔内填充导电金属而形成导电通孔；和
    在第四基底的上表面形成与对应导电通孔电连接的导电焊盘。
  27. 根据权利要求22-26中任一项所述的方法，其中：
    形成凸起结构的步骤中，通过刻蚀对应基底而形成所述凸起结构。
  28. 一种电子设备，包括根据权利要求1-21中任一项所述的半导体 结构或根据权利要求22-27中任一项所述的方法制造的半导体结构。
PCT/CN2020/088723 2019-12-31 2020-05-06 具有叠置单元的半导体结构及制造方法、电子设备 WO2021135013A1 (zh)

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