WO2021134653A1 - 电力载波信号识别电路、方法和集成电路芯片 - Google Patents

电力载波信号识别电路、方法和集成电路芯片 Download PDF

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Publication number
WO2021134653A1
WO2021134653A1 PCT/CN2019/130874 CN2019130874W WO2021134653A1 WO 2021134653 A1 WO2021134653 A1 WO 2021134653A1 CN 2019130874 W CN2019130874 W CN 2019130874W WO 2021134653 A1 WO2021134653 A1 WO 2021134653A1
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WIPO (PCT)
Prior art keywords
circuit
data
power
signal
level
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PCT/CN2019/130874
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English (en)
French (fr)
Inventor
邹云根
卢玉玲
乔世成
蔡荣怀
陈孟邦
张丹丹
曹进伟
Original Assignee
宗仁科技(平潭)有限公司
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Application filed by 宗仁科技(平潭)有限公司 filed Critical 宗仁科技(平潭)有限公司
Priority to CN201980003540.6A priority Critical patent/CN111226506B/zh
Priority to US17/789,062 priority patent/US20230049359A1/en
Priority to PCT/CN2019/130874 priority patent/WO2021134653A1/zh
Publication of WO2021134653A1 publication Critical patent/WO2021134653A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/54—Systems for transmission via power distribution lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/355—Power factor correction [PFC]; Reactive power compensation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2513—Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2203/00—Indexing scheme relating to line transmission systems
    • H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404—Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/5412—Methods of transmitting or receiving signals via power distribution lines by modofying wave form of the power source
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/175—Controlling the light source by remote control
    • H05B47/185—Controlling the light source by remote control via power line carrier transmission

Definitions

  • This application belongs to the technical field of electronic circuits, and in particular relates to a power carrier signal identification circuit, method, and integrated circuit chip.
  • the purpose of the present application is to provide a power carrier signal identification circuit, method, and integrated circuit chip, which aims to solve the problem of low reliability of the traditional power carrier using a fixed comparison point to identify data.
  • the first aspect of the embodiments of the present application provides a power carrier signal identification circuit, which includes:
  • the voltage amplitude detection circuit is configured to be connected to the power line, and is used to detect the voltage amplitude change and duration caused by modulating the data of each data frame on the power line in the form of a carrier signal on the power line and generate a corresponding level signal;
  • the decoding circuit is connected to the voltage amplitude detection circuit and is configured to convert the level signal to obtain the data of the current data frame.
  • the second aspect of the embodiments of the present application provides a power carrier signal identification method, including:
  • the level signal is converted to obtain the data of the current data frame.
  • the third aspect of the embodiments of the present application provides an integrated circuit chip including the power carrier signal identification circuit described above.
  • the fourth aspect of the embodiments of the present application provides an integrated circuit chip, including a memory, a processor, and a computer program stored in the memory and running on the processor, and the processor executes the computer program When implementing the steps of the method described above.
  • the beneficial effects of the power carrier signal identification circuit and method provided by the embodiments of the present application are: when the signal is transmitted on the power line, the amplitude change and duration of the voltage signal on the power line are identified, and then decoded into corresponding data, reducing signal identification Depending on the power supply voltage, the increase in the transmission distance will not reduce the signal recognition rate, thereby reducing the requirements for the system power supply.
  • FIG. 1 is a schematic structural diagram of a power carrier signal identification circuit provided by the first embodiment of this application;
  • FIG. 2 is a schematic structural diagram of a power carrier signal identification circuit provided by a second embodiment of this application.
  • FIG. 3 is a schematic structural diagram of a power carrier signal identification circuit provided by a third embodiment of this application.
  • Fig. 4 is a waveform diagram of three different modes of the power carrier signal of the application.
  • FIG. 5 is a schematic circuit diagram of an example of a voltage amplitude detection circuit in the power carrier signal identification circuit shown in FIG. 1;
  • FIG. 6 is a specific flowchart of the power carrier signal identification method provided by the first embodiment of this application.
  • FIG. 7 is a specific flowchart of the power carrier signal identification method provided by the second embodiment of this application.
  • FIG. 8 is a schematic diagram of an integrated circuit chip provided by an embodiment of the present invention.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • FIG. 1 shows a schematic structural diagram of a power carrier signal identification circuit provided by a preferred embodiment of the present application. For ease of description, only the parts related to this embodiment are shown, and the details are as follows:
  • the power carrier signal identification circuit in this embodiment can be integrated in the chip, for example, used to drive RGB full-color LED lights, and the LED lights can also be integrated in the chip.
  • the power carrier signal identification circuit includes a voltage amplitude detection circuit 11 and a decoding circuit 12.
  • the control system modulates the data signal on the power line, and the voltage amplitude detection circuit 11 is configured to be connected to the power line to detect the voltage amplitude change caused by modulating the data of each data frame on the power line in the form of a carrier signal on the power line And the duration and generate a corresponding level signal;
  • the decoding circuit 12 is connected to the voltage amplitude detection circuit 11 and is configured to convert the level signal to obtain the data of the current data frame.
  • the voltage amplitude detection circuit 11 performs level conversion on the voltage variation amplitude on the power line and compares it with the reference voltage to obtain a level signal that can be identified by the decoding circuit 12, and the decoding circuit 12 uses the system clock to convert the level signal into carrier data. ; At this point, the data signal loaded on the power supply voltage is decoded and separated to obtain the carrier data.
  • the amplitude change and duration of the voltage signal on the power line are recognized, and then decoded into corresponding data, reducing the dependence on the power supply voltage during signal recognition, and increasing the transmission distance will not reduce the signal recognition rate , Thereby reducing the requirements for system power.
  • a control circuit 13 needs to be configured in the circuit.
  • the control circuit 13 is connected to the decoding circuit 12, and the control circuit 13 is configured to start from the current data frame.
  • the drive signal is extracted from the data to drive the load.
  • the voltage amplitude detection circuit 11 also needs to perform counting statistics based on the preset identification code (such as the RESET code) in the data of the current data frame.
  • the control circuit 13 determines that the chip addresses match
  • the driving signal is extracted from the data of the current data frame.
  • the control circuit 13 includes an address setting circuit 131, a data frame counting circuit 132 and a logic control circuit 134.
  • the address setting circuit 131 is configured to set address information;
  • the data frame counting circuit 132 is configured to perform counting statistics according to the preset identification code in the data;
  • the logic control circuit 134, the address setting circuit 131, and the logic control circuit 134 is connected to the load, configured to compare the address information with the count value of the current data frame, and when the address information matches the count value, extract a driving signal from the data of the current data frame to drive the load .
  • the address setting circuit 131 is connected to the logic control circuit 134, and the address setting control signal is received through the power line to burn the polysilicon fuse to set the chip address information.
  • the address setting terminal is 9 bits.
  • the data frame counting circuit 132 counts the preset identification codes of the carrier data, and when it is judged that a data frame is completed, the data frame counter value is increased by one.
  • the data frame counting circuit 132 is further configured to receive an initial value setting instruction, set the initial value of the count value of the data frame counting register according to the initial value setting instruction, and accumulate the count value after the circuit works normally.
  • control circuit 13 should also include a conversion circuit 135 and a drive circuit 136.
  • the conversion circuit 135 converts the control data in the carrier data into drive signals with different duty cycles, and the drive circuit 135 is connected to the outside
  • the LED drive terminal is used to drive the LED module to work according to the drive signal.
  • the voltage amplitude detection circuit 11 determines whether there is a valid carrier signal based on the peak-to-peak voltage on the power line and the duration of the peak-to-peak value greater than a preset value. There is no need to set a fixed comparison point to identify data. Even if the power supply voltage decreases as the transmission distance increases, the voltage peak-to-peak value will not change accordingly. As long as the voltage peak-to-peak value on the source line is greater than the preset value, it can be identified The carrier signal has high reliability, and the chip far away from the main control can also identify the data sent by the control system.
  • the voltage on the power line is detected, and the corresponding level signal is output according to the peak-to-peak value of the voltage and the duration of the peak-to-peak value greater than the preset value. If the peak value is greater than the preset value and the duration matches the first preset duration, the first level signal of the second preset duration is output, and when the peak-to-peak value is greater than the preset value and the duration matches the third preset duration, the output is The second level signal with the opposite level signal and the fourth preset duration, when the peak-to-peak value of the voltage is greater than the preset value and the duration matches the fifth preset duration, the preset duration identification voltage of the sixth preset duration is output Level, the identification level is a first level signal or a second level signal.
  • the decoding circuit 12 converts the first level signal of the second preset duration and the second level signal of the fourth preset duration into data 0 and 1, respectively, and converts the data of the sixth preset duration
  • the identification level is converted to a preset identification code. It is understandable that the first preset duration and the second preset duration may be equal, or may be unequal; similarly, the third preset duration and the fourth preset duration may be equal, or may be If they are not equal, the fifth preset duration and the sixth preset duration may be equal, or may be unequal.
  • the decoding circuit 12 sets a low level for 1us. Converted to data 0; when it lasts for 2us, it outputs a high level of 2us, and the decoding circuit 12 converts a high level of 2us to data 1. When it lasts for 4us, it outputs a low or high level for a preset duration (such as 4us) , The decoding circuit 12 converts the low or high level of the preset duration into a RESET code.
  • the RESET code indicates that the data frame transmission is finished, and the chip whose address matches the data frame on the multi-chip cascade system will refresh the brightness display.
  • the data of each data frame on the power line is represented by a combination of high voltage and low voltage with different durations.
  • the data of each data frame on the power line includes control code and control data (such as driving three Color LED's first data, second data, third data), RESET code.
  • the control code includes two working mode selection bits, the first data, the second data, and the third data each include eight bits, indicating different brightness of the LED, and the RESET code is the preset identification code, which represents the end of the data frame.
  • the end of frame information is indicated by the low voltage duration within the set time range.
  • the internal address of the chip is not limited to laser fuse, metal fuse, poly fuse, otp, mtp, etc.
  • the data of each data frame on the power line is separated from the power supply voltage.
  • the working mode control code is two bits.
  • the working mode control code selection bit is 11, the power carrier signal identification circuit enters the data In the frame count setting working mode, the data frame counting circuit 132 is ready to receive the initial value setting instruction to set the initial value of the count value of the data frame counter.
  • the operating mode control code selection bit is 01
  • the address information of the address setting circuit 131 of the logic control circuit 134 is compared with the count value of the data frame counting circuit 132.
  • the logic control circuit 134 obtains data from the current data frame.
  • the conversion circuit 135 converts the control data into brightness driving signals with different duty cycles, and the driving circuit 136 drives the LED module to work according to the brightness driving signals with different duty cycles.
  • the control system does not need to include the chip address when sending the data frame.
  • the data frame counting circuit 132 counts the RESET code in the decoded carrier data on the power line, and automatically matches the internal address of the chip and sends out an output signal, reducing the amount of data sent and the chip
  • the bit error rate of the received data makes the entire system control more stable, and at the same time reduces the cost of the chip and the control system.
  • the voltage amplitude detection circuit 11 includes a level conversion unit 111 and a comparator 112.
  • the level conversion unit 111 is configured to be connected to the power line for connecting to a voltage signal on the power line, and to generate a preset amplitude detection level according to the voltage signal; one input terminal of the comparator 112 is connected to the detection level, and the other One input terminal is connected to a reference voltage, and the comparator 112 compares the detection level with the reference voltage and outputs it as a comparison result of the level signal.
  • the above-mentioned voltage amplitude detection circuit 11 provides a way to identify the carrier signal. After level conversion and comparison, a level signal that can be identified by the subsequent decoding circuit 12 is obtained.
  • the level conversion unit 111 includes a capacitive device M0, a first NMOS tube M1, and a diode D1; the gate of the first NMOS tube M1 is used to connect to a power line, and the first NMOS tube
  • the drain of M1 serves as the output of the level conversion unit 111 and is connected to the first terminal of the capacitive device M0, the second terminal of the capacitive device M0 is connected to the power terminal of the comparator 112, and the first NMOS
  • the source of the tube M1 is grounded, the diode D1 is connected between the source and the drain of the first NMOS tube M1, and the anode is grounded.
  • the capacitive device M0 includes a capacitor; or the capacitive device M0 includes a PMOS tube, wherein the gate of the PMOS tube serves as the first end of the capacitive device M0, and the drain and source of the PMOS tube The pole and the substrate are connected together as the second end of the capacitive device M0.
  • the level conversion unit 111 it can be known that the detection level and the level state of the power supply voltage are opposite.
  • the voltage amplitude detection circuit 11 further includes an output unit 113; the output unit 113 is connected to the output terminal of the comparator 112 and is configured to enhance the driving capability of the level signal.
  • the output unit 113 includes two inverters I1 and I2 connected in series. In other embodiments, the output unit 113 may be an RC circuit.
  • the voltage amplitude detection circuit 11 further includes a power-on protection circuit 113.
  • the input terminal of the power-on protection circuit 113 is used to connect the power-on reset signal POR1, and the power-on protection circuit 113 is configured to The output of the voltage amplitude detection circuit 11 is clamped at a high level or a low level under the control of the power-on reset signal POR1.
  • the power-on protection circuit 113 includes a first inverter U3 and a second NMOS transistor M2, the input terminal of the first inverter U3 is used as the input terminal of the power-on protection circuit 113, and the output terminal is connected to the The gate of the second NMOS tube M2, the drain of the second NMOS tube M2 is connected to the output terminal of the comparator 112 or the output terminal of the output unit 113, and the source of the second NMOS tube M2 is grounded .
  • FIG. 5 discloses a general structure of the comparator 112. In other embodiments, other comparator structures may be used, which will not be repeated here.
  • the power-on reset signal POR1 provides an initial state for the voltage amplitude detection circuit 11 (which can be a chip). After power-on, the power-on reset signal POR1 is low, and after passing through the inverter I3, it is high. The second NMOS The tube M2 is turned on, and the output of the comparator 112 is forced to be low, the output terminal DOUT is output as 0, and the chip is in the power-on reset state. After the chip power-on reset is successful, the power-on reset signal POR1 is high, and after the inverter I3 is low, the second NMOS transistor is turned off, the output terminal DOUT is the output value of the comparator 112, and the chip enters normal operation.
  • the reference voltage VREF is provided by the reference module, for example 1.2V
  • the signal NBIAS is a current source provided by the reference module as the tail current of the comparator 112.
  • the power supply voltage VCC is divided by the capacitive device M0 and the resistive device-the first NMOS tube M1 and then input to the N terminal of the comparator 112 (the gate of the NMOS tube M4), and the P terminal of the comparator 112 (the gate of the NMOS tube M5) Gate) to compare the reference voltage VREF.
  • the capacitive device M0 After the power supply voltage VCC (such as 5V) is powered on, the capacitive device M0 has no charge.
  • the power supply voltage VCC charges the capacitive device M0 through the NMOS tube M1. After a certain period of time, the capacitive device M0 is fully charged and the charging current is zero, and the comparator 112
  • the voltage at the N terminal is 0V.
  • the source voltage VCC drops from 5V to 3V, the 5V voltage drop across the capacitive device M0 cannot be changed suddenly.
  • the voltage value of the P terminal is 1.2V greater than the voltage value of the N terminal -0.7V, and the output of the comparator 112 is high. After passing through the two inverters I1 and I2, the output terminal DOUT is high.
  • the output of the comparator 112 is low level. After passing through the two inverters I4 and I3, the output terminal DOUT is low level.
  • the voltage amplitude detection and detection work is repeated in this way.
  • the decoding circuit 12 recognizes the DOUT output of the voltage amplitude detection module according to the level signal and its duration, decodes it into corresponding data and stores it in a shift register.
  • the decoding circuit 12 may be a mode conversion circuit.
  • the format of the data frame signal is control code+first data+second data+third data+RESET code.
  • the control code has a total of 2 bits, which are the working mode selection bits.
  • the first data, the second data, and the third data are set to 8 bits respectively,
  • C1 C0 2-bit working mode selection bit.
  • the first data, the second data, and the third data respectively represent the brightness data information of the three-color LED lamp.
  • the control system sends data, the low bit is first sent, and then the high bit is sent. The control code is sent first, and then the first data, the second data, and the third data are sent sequentially from low to high.
  • the conversion circuit 135 converts the control signal in the data signal into a luminance drive signal with different duty cycles.
  • the 8-bit data information represents 0-255 different values, and different values correspond to different brightness of the LED lamp. When the value is 0, the LED The brightness of the lamp is the smallest, and the lamp is off. When the data is 255, the brightness of the LED lamp is the largest. When the data is a certain value in the middle, such as 128, the PWM output is 128/256 duty cycle output brightness.
  • the logic control circuit 134 includes multiple XOR gates.
  • C1 and C0 correspond to I56_Q and I52_Q in the shift register.
  • the value of each address of the address setting circuit and the value of each data frame counter in the data frame counting circuit are respectively XORed. After the matching signal is outputted by the AND operation.
  • the shift registers of the two control codes are operated by the XOR gate. When C1C0 is 01, it enters the chip address and data frame count matching mode. When C1C0 is 01, the output of the two control code shift registers is ANDed by the output of the XOR gate operation and the matching signal, and the output enable signal of the logic control circuit 134 is obtained.
  • the logic control circuit 134 After receiving the end code RESET, when the output enable signal is 1 at the same time, the logic control circuit 134 outputs the first data, the second data, and the third data in the carrier data to the conversion circuit 135, and at the same time updates the output of the driving circuit 136; , The output display is not refreshed.
  • a power carrier signal identification method including:
  • Step S110 detecting the voltage amplitude change and duration caused by modulating the data of each data frame on the power line in the form of a carrier signal on the power line and generating a corresponding level signal;
  • Step S120 Convert the level signal to obtain data of the current data frame.
  • the detecting the data of each data frame on the power line modulates the voltage amplitude change and duration caused by the power line in the form of a carrier signal and generates the corresponding level signal, including:
  • the second preset duration is output For the first level signal, when the peak-to-peak value is greater than the preset value and the duration matches the third preset duration, the second level signal of the fourth preset duration opposite to the level signal is output, and the peak-to-peak value is greater than the preset duration. If the value is set and the duration matches the fifth preset duration, the identification level of the sixth preset duration is output, and the identification level is the first level signal or the second level signal.
  • the converting the level signal to obtain the data of the current data frame includes:
  • the data of each data frame includes the control code, the control data, and the preset identification code arranged in sequence.
  • step S130 extracting a driving signal from the data of the current data frame to drive the load.
  • the extracting the driving signal from the data of the current data frame to control the work of the load includes;
  • the control data is converted into a driving signal and output to drive the load.
  • the method further includes: receiving an initial value setting instruction, and setting the initial value of the count value according to the initial value setting instruction.
  • FIG. 8 is a schematic diagram of an integrated circuit chip provided by an embodiment of the present application.
  • the integrated circuit chip 6 of this embodiment includes: a processor 60, a memory 61, and a computer program 62 that is stored in the memory 61 and can run on the processor 60.
  • the processor 60 When the computer program 62 is executed, the steps in the above embodiments of the power carrier signal identification method are implemented, for example, steps 110 to 130 shown in FIG. 5.
  • the processor 60 executes the computer program 62, the function of each module/unit in the foregoing device embodiments, for example, the function of each module shown in FIG. 2 is realized.
  • the computer program 62 may be divided into one or more modules/units, and the one or more modules/units are stored in the memory 61 and executed by the processor 60 to complete This application.
  • the one or more modules/units may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program 62 in the integrated circuit core 6.
  • the computer program 62 can be divided into a synchronization module, a summary module, an acquisition module, and a return module (modules in the virtual device), and the specific functions of each module are as follows:
  • the so-called processor 60 may be a central processing unit (Central Processing Unit, CPU), other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the memory 61 may be an internal storage unit of the integrated circuit core 6, for example, a hard disk or a memory of the integrated circuit core 6.
  • the memory 61 may also be an external storage device of the integrated circuit core 6, such as a plug-in hard disk equipped on the integrated circuit core 6, a smart memory card (Smart Media Card, SMC), or a secure digital (Secure Digital, SD) card, flash memory card (Flash Card) and so on.
  • the memory 61 may also include both an internal storage unit of the integrated circuit core 6 and an external storage device.
  • the memory 61 is used to store the computer program and other programs and data required by the integrated circuit core.
  • the memory 61 can also be used to temporarily store data that has been output or will be output.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

本申请公开一种电力载波信号识别电路，其包括信号在电源线上传输时，对电源线上电压信号的幅度变化和持续时间进行识别，进而解码成相应数据，减少信号识别时对电源电压的依赖，传输距离增加也不会减低信号识别率，从而降低对系统电源的要求。

Description

电力载波信号识别电路、方法和集成电路芯片 技术领域
本申请属于电子电路技术领域，尤其涉及一种电力载波信号识别电路、方法和集成电路芯片。
 背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。如今市面上有很多电力载波LED控制芯片应用在3D灯、圣诞灯、窗帘灯等场合，相比以前的四线传输系统，简化了安装流程和大幅节约了线缆成本，同时也降低了产品的故障率，没有了维修的麻烦。但是这些产品由于采用电源线传输数据，在电源线本身干扰较大的前提下，电源电压会随着传输距离增加而下降，信号传输幅度也变小，采用固定比较点的方式识别数据，当电源的低电平点或者高电平点靠近或者比较点时，芯片数据识别将会失败，可靠性低，导致距离主控较远的芯片无法识别控制系统发送的数据，从而无法根据系统数据做出正确反应。
 技术问题
本申请的目的在于提供一种电力载波信号识别电路、方法和集成电路芯片，旨在解决传统电力载波采用固定比较点的方式识别数据可靠性低的问题。
 技术解决方案
为解决上述技术问题，本申请实施例采用的技术方案是：
本申请实施例的第一方面提了一种电力载波信号识别电路，包括：
电压幅度检测电路，配置为连接电源线，用于检测电源线上每一数据帧的数据以载波信号的形式调制在电源线上所引起的电压幅度变化和持续时间并生成对应的电平信号；
解码电路，与所述电压幅度检测电路连接，配置为将所述电平信号进行转换得到当前数据帧的数据。
本申请实施例的第二方面提了一种电力载波信号识别方法，包括：
检测电源线上每一数据帧的数据以载波信号的形式调制在电源线上所引起的电压幅度变化和持续时间并生成对应的电平信号；
将所述电平信号进行转换得到当前数据帧的数据。
本申请实施例的第三方面提了一种集成电路芯片，包括如上所述的电力载波信号识别电路。
本申请实施例的第四方面提了一种集成电路芯片，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如上所述方法的步骤。
 有益效果
本申请实施例提供的电力载波信号识别电路和方法的有益效果在于：信号在电源线上传输时，对电源线上电压信号的幅度变化和持续时间进行识别，进而解码成相应数据，减少信号识别时对电源电压的依赖，传输距离增加也不会减低信号识别率，从而降低对系统电源的要求。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请第一实施例提供的电力载波信号识别电路结构示意图；
图2为本申请第二实施例提供的电力载波信号识别电路结构示意图；
图3为本申请第三实施例提供的电力载波信号识别电路结构示意图；
图4为本申请的电力载波信号的三种不同方式的波形图；
图5为图1所示的电力载波信号识别电路中电压幅度检测电路的示例电路原理图；
图6为本申请第一实施例提供的电力载波信号识别方法的具体流程图；
图7为本申请第二实施例提供的电力载波信号识别方法的具体流程图；
图8是本发明实施例提供的一种集成电路芯片的示意图。
 本发明的实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本申请。
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
需要说明的是，当元件被称为“固定于”或“设置于”另一个元件，它可以直接在另一个元件上或者间接在该另一个元件上。当一个元件被称为是“连接于”另一个元件，它可以是直接连接到另一个元件或间接连接至该另一个元件上。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
请参阅图1  ，图1示出了本申请较佳实施例提供的电力载波信号识别电路的结构示意图，为了便于说明，仅示出了与本实施例相关的部分，详述如下：
本实施例中的电力载波信号识别电路可以被集成在芯片中，比如用于驱动RGB全彩LED灯，LED灯也可以被一同集成在改芯片中。电力载波信号识别电路包括电压幅度检测电路11和解码电路12。控制系统将数据信号调制在电源线上，电压幅度检测电路11配置为连接电源线，用于检测电源线上每一数据帧的数据以载波信号的形式调制在电源线上所引起的电压幅度变化和持续时间并生成对应的电平信号；解码电路12与所述电压幅度检测电路11连接，配置为将所述电平信号进行转换得到当前数据帧的数据。
电压幅度检测电路11将电源线上的电压变化幅值进行电平转换后与基准电压进行比较得到解码电路12可以识别的电平信号，解码电路12利用系统时钟将该电平信号转化为载波数据；至此，将加载在电源电压上的数据信号解码分离出来，得到载波数据。
载波信号在电源线上传输时，对电源线上电压信号的幅度变化和持续时间进行识别，进而解码成相应数据，减少信号识别时对电源电压的依赖，传输距离增加也不会减低信号识别率，从而降低对系统电源的要求。
在其中一些实施例中，请参阅图2，如需要根据载波数据驱动负载，那么电路中还需要配置一个控制电路13，控制电路13与解码电路12连接，控制电路13配置为从当前数据帧的数据中提取驱动信号以驱动负载。进一步地，当控制系统需要同时控制多个芯片时，电压幅度检测电路11还需要根据当前数据帧的数据中的预设标示码（比如RESET码）进行计数统计，当控制电路13判断芯片地址匹配当前数据帧计数值时，从当前数据帧的数据中提取驱动信号。
在其中一些实施例中，请参阅图3，控制电路13包括地址设置电路131、数据帧计数电路132及逻辑控制电路134。地址设置电路131配置为设定地址信息；数据帧计数电路132，配置为根据所述数据中的预设标识码进行计数统计；逻辑控制电路134与所述地址设置电路131、所述逻辑控制电路134及所述负载连接，配置为将所述地址信息与当前数据帧的计数值进行比较，当所述地址信息与所述计数值匹配时，从当前数据帧的数据中提取驱动信号以驱动负载。
本实施例中，地址设置电路131连接逻辑控制电路134，通过电源线接收地址设置控制信号来烧多晶硅熔丝设定芯片地址信息，本实施例中，地址设置端是9位。数据帧计数电路132统计载波数据的预设标示码，当判断一个数据帧完成时，数据帧计数器值加一。可选地，数据帧计数电路132还被配置为接收初值设置指令，根据所述初值设置指令设置数据帧计数寄存器的计数值的初值，电路正常工作后在此计数值上累加。
如上述，比如负载时全彩LED灯，控制电路13应还包括转换电路135和驱动电路136，转换电路135将载波数据中的控制数据转化为不同占空比的驱动信号，驱动电路135连接外部LED驱动端，用于根据驱动信号驱动所述LED模组工作。
本实施例中，电压幅度检测电路11是根据电源线上的电压峰峰值以及大于预设值的峰峰值持续时间来确定是否有有效载波信号。不需要设置采用固定比较点的方式识别数据，即使电源电压会随着传输距离增加而下降，电压峰峰值也不会随之改变，只要源线上的电压峰峰值大于预设值即能识别出载波信号，可靠性高，距离主控较远的芯片也能识别控制系统发送的数据。
请参阅图3和图4，具体地，检测电源线上的电压，并根据该电压的峰峰值及大于预设值的峰峰值的持续时间输出对应的电平信号，其中，在电压的该峰峰值大于预设值且持续时间匹配第一预设时长则输出第二预设时长的第一电平信号，在该峰峰值大于预设值且持续时间匹配第三预设时长则输出与所述电平信号相反的、第四预设时长的第二电平信号，在该电压的峰峰值大于预设值且持续时间匹配第五预设时长则输出第六预设时长的预设时长标识电平，所述标识电平为第一电平信号或第二电平信号。此后，解码电路12将所述第二预设时长的第一电平信号、所述第四预设时长的第二电平信号分别转换为数据0、1，将所述第六预设时长的标识电平转换为预设标识码。可以理解的是，第一预设时长和第二预设时长可以是相等的，或可以是不相等的；同样的，第三预设时长和第四预设时长可以是相等的，或可以是不相等的，第五预设时长和第六预设时长可以是相等的，或可以是不相等的。
请参阅图4，比如电压幅度检测电路11接入的电压信号符合条件的电压峰峰值（可以为任何电平）持续1us时，则输出1us低电平，此后，解码电路12将1us低电平转换为数据0；持续2us时，则输出2us高电平，解码电路12将2us高电平转换为数据1；持续4us时，则输出预设时长（比如4us）的低电平或高电平，解码电路12将预设时长的低电平或高电平转换为RESET码，RESET码说明该数据帧发送结束，多芯片级联系统上的地址与数据帧匹配的芯片将刷新辉度显示。
在一个实施例中，电源线上的每一数据帧的数据是以高电压与低电压不同持续时间组合表示，电源线上的每一数据帧的数据包括控制码、控制数据（比如分别驱动三色LED的第一数据、第二数据、第三数据）、RESET码。可选地，控制码包括两个工作模式选择位，第一数据、第二数据、第三数据分别包括八位，表示LED不同的辉度，RESET码为预设标识码，代表数据帧结束信息，帧结束信息以低电压持续时间在设定时间范围内表示。芯片内部地址不局限于laser fuse、metal fuse 、poly fuse、otp 、mtp等方式.
在一个实施例中，电源线上的每一数据帧的数据从电源电压中分离出来，比如工作模式控制码为两位，当工作模式控制码选择位为11时，电力载波信号识别电路进入数据帧计数设置的工作模式，数据帧计数电路132准备接收初值设置指令设置数据帧计数器的计数值的初值。当工作模式控制码选择位为01时，逻辑控制电路134地址设置电路131的地址信息与数据帧计数电路132的计数值进行比对，当数据相同时，逻辑控制电路134从当前数据帧的数据中提取控制数据，转换电路135将控制数据转化为不同占空比的辉度驱动信号，驱动电路136根据不同占空比的辉度驱动信号驱动所述LED模组工作。
控制系统在发送数据帧时不需要包含芯片地址，数据帧计数电路132对电源线上解码后的载波数据中RESET码进行统计，自动匹配芯片内部地址后发出输出信号，减少数据发送量，降低芯片接收数据的误码率，使整个系统控制更加稳定，同时降低了芯片和控制系统成本。
在一个实施例中，请参阅图5，电压幅度检测电路11包括电平转换单元111和比较器112。电平转换单元111配置为连接电源线，用于接入电源线上电压信号，并根据该电压信号生成预设幅值检测电平；比较器112的一个输入端连接所述检测电平，另一个输入端连接基准电压，比较器112将所述检测电平与基准电压比较输出作为所述电平信号的比较结果。上述电压幅度检测电路11提供了一种载波信号的识别方式，通过电平转换和比较后得到后续解码电路12能识别的电平信号。
在一个实施例中，电平转换单元111包括一容性器件M0、第一NMOS管M1以及一二极管D1；所述第一NMOS管M1的栅极用于连接电源线，所述第一NMOS管M1的漏极作为电平转换单元111的输出、连接所述容性器件M0的第一端，所述容性器件M0的第二端连接所述比较器112的电源端，所述第一NMOS管M1的源极接地，所述二极管D1连接在所述第一NMOS管M1的源极和漏极之间，且正极接地。
可选地，容性器件M0包括一电容器；或者容性器件M0包括一PMOS管，其中，该PMOS管的栅极作为所述容性器件M0的第一端，该PMOS管的漏极、源极及衬底共接作为所述容性器件M0的第二端。本实施例中，根据电平转换单元111的工作原理可知检测电平和电源电压的电平状态是相反的。
在一个实施例中，电压幅度检测电路11还包括输出单元113；输出单元113与所述比较器112的输出端连接，配置为用于加强所述电平信号的驱动能力。本实施例中，输出单元113包括串联连接的两个反相器I1、I2。在其他实施例中，可以输出单元113可以是RC电路。
在一个实施例中，电压幅度检测电路11还包括上电保护电路113，所述上电保护电路113的输入端用于连接上电复位信号POR1，所述上电保护电路113配置为在所述上电复位信号POR1的控制控制下使所述电压幅度检测电路11的输出钳位在高电平或低电平。可选地，上电保护电路113包括第一反相器U3和第二NMOS管M2，所述第一反相器U3的输入端作为所述上电保护电路113的输入端，输出端连接所述第二NMOS管M2的栅极，所述第二NMOS管M2的漏极连接所述比较器112的输出端或所述输出单元113的输出端，所述第二NMOS管M2的源极接地。
另外，图5中公开的是比较器112通用架构，在其他实施方式中，可以采用其他比较器架构，这里不再赘述。
具体地，上电复位信号POR1给电压幅度检测电路11（可以是芯片）提供初始状态，上电后上电复位信号POR1为低电平，经过反相器I3后为高电平，第二NMOS管M2打开，强制把比较器112输出置为低，输出端DOUT输出为0，芯片处于上电复位状态。芯片上电复位成功后上电复位信号POR1为高，经过反相器I3后为低电平，第二NMOS管关闭，输出端DOUT值为比较器112输出值，芯片进入正常工作。基准电压VREF为基准模块提供，例如1.2V，信号NBIAS为基准模块提供的电流源，作为比较器112的尾电流。电源电压VCC用容性器件M0和阻性器件-第一NMOS管M1分压后输入到比较器112的N端（NMOS管M4的栅极），与比较器112的P端（NMOS管M5的栅极）的基准电压VREF比较。
电源电压VCC（比如5V）上电后，容性器件M0没有电荷，电源电压VCC经过NMOS管M1对容性器件M0充电，经过一定时间后，容性器件M0充满充电电流为零，比较器112的N端的电压为0V。当源电压VCC由5V降到3V时，容性器件M0两端的压降5V不能突变，N端电压为3-5=-2V，由于二极管D1的钳位作用，N端电压为-0.7V，P端电压值1.2V大于N端电压值-0.7V，比较器112输出为高电平，经过两个反相器I1、I2后，输出端DOUT为高电平。当当源电压VCC由3V升到5V时，容性器件M0两端的压降-2V不能突变，N端电压为-0.7+2=1.3V，P端电压值1.2V小于N端电压值1.3V，比较器112输出为低电平，经过两个反相器I4、I3后，输出端DOUT为低电平。电压幅度检测检测工作如此反复进行，解码电路12对电压幅度检测模块的DOUT输出根据电平信号及其持续时间进行识别，解码成对应数据并以移位寄存器的方式存储。解码电路12可以是模式转换电路。
本实施例中，数据帧信号的格式为控制码+第一数据+第二数据+第三数据+RESET码，在本实施例中，控制码共2位，为工作模式选择位。第一数据、第二数据、第三数据分别设为8位，
C1 C0 : 2位工作模式选择位，C1C0=11时，芯片进入数据帧计数设置的工作模式；C1C0=01时，芯片地址与数据帧计数进行匹配，输出驱动信号。在驱动全彩LED灯时，第一数据、第二数据、第三数据分别代表三色LED灯的亮度数据信息，控制系统发送数据时先发低位，再发高位。先发控制码，然后按第一数据、第二数据、第三数据的顺序从低到高位依次发送。
转换电路135将数据信号中的控制信号转化为不同占空比的辉度驱动信号，8位数据信息表示0-255个不同数值，不同数值对应LED灯不同的亮度，当数值为0时，LED灯的亮度最小，灯灭，当数据为255时，LED灯的亮度最大，当数据为中间某一数值时，比如128时，表现PWM输出为128/256的占空比输出亮度。
逻辑控制电路134包括多个同或门，C1、C0对应移位寄存器中的I56_Q、I52_Q，地址设置电路的各个地址的值与数据帧计数电路中的各数据帧计数器的值分别做同或运算后经过与运算输出的匹配信号。两个控制码的移位寄存器通过同或门运算，C1C0为01时，进入芯片地址与数据帧计数匹配模式。C1C0为01时，两个控制码的移位寄存器通过同或门运算的输出与匹配信号经过与的结果，得到逻辑控制电路134的输出使能信号。收到结束码RESET后，同时输出使能信号为1时，逻辑控制电路134把载波数据中第一数据、第二数据、第三数据输出到转换电路135，同时更新驱动电路136的输出；反之，则不刷新输出显示。
请参阅图6，本申请还公开了一种电力载波信号识别方法，包括：
步骤S110，检测电源线上每一数据帧的数据以载波信号的形式调制在电源线上所引起的电压幅度变化和持续时间并生成对应的电平信号；
步骤S120，将所述电平信号进行转换得到当前数据帧的数据。
在其中一个实施例中，所述检测电源线上每一数据帧的数据以载波信号的形式调制在电源线上所引起的电压幅度变化和持续时间并生成对应的电平信号，包括：
检测电源线上的电压，并根据该电压的峰峰值及持续时间输出对应的电平信号，其中，在峰峰值大于预设值且持续时间匹配第一预设时长则输出第二预设时长的第一电平信号，在峰峰值大于预设值且持续时间匹配第三预设时长则输出与所述电平信号相反的、第四预设时长的第二电平信号，在峰峰值大于预设值且持续时间匹配第五预设时长则输出第六预设时长的标识电平，所述标识电平为第一电平信号或第二电平信号。
在其中一个实施例中，所述将所述电平信号进行转换得到当前数据帧的数据，包括：
将所述第二预设时长的第一电平信号、第四预设时长的第二电平信号分别转换为数据0、1，将所述第六预设时长标识电平转换为预设标识码；
其中，每一数据帧的数据包括依次排列的控制码、控制数据、预设标识码。
在其中一个实施例中，请参阅图7，还包括步骤S130，从当前数据帧的数据中提取驱动信号以驱动负载。
在其中一个实施例中，所述从当前数据帧的数据中提取驱动信号以控制负载工作，包括；
将所述地址信息与当前数据帧的计数值进行比较，其中，所述计数值是根据所述数据中的预设标识码进行计数统计；
当所述地址信息与所述计数值匹配时，从当前数据帧的数据中提取控制数据；
将所述控制数据转换为驱动信号并输出以驱动所述负载。
在其中一个实施例中，还包括：接收初值设置指令，根据所述初值设置指令设置计数值的初值。
图8是本申请一实施例提供的集成电路芯片的示意图。如图8所示，该实施例的集成电路芯片6包括：处理器60、存储器61以及存储在所述存储器61中并可在所述处理器60上运行的计算机程序62，所述处理器60执行所述计算机程序62时实现上述各个电力载波信号识别方法实施例中的步骤，例如图5所示的步骤110至130。或者，所述处理器60执行所述计算机程序62时实现上述各装置实施例中各模块/单元的功能，例如图2所示各模块的功能。
示例性的，所述计算机程序62可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器61中，并由所述处理器60执行，以完成本申请。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述所述计算机程序62在所述集成电路芯6中的执行过程。例如，所述计算机程序62可以被分割成同步模块、汇总模块、获取模块、返回模块（虚拟装置中的模块），各模块具体功能如下：
所称处理器60可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器 (Digital Signal Processor，DSP)、专用集成电路 (Application Specific Integrated Circuit，ASIC)、现成可编程门阵列 (Field-Programmable Gate Array，FPGA) 或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述存储器61可以是所述集成电路芯6的内部存储单元，例如集成电路芯6的硬盘或内存。所述存储器61也可以是所述集成电路芯6的外部存储设备，例如所述集成电路芯6上配备的插接式硬盘，智能存储卡（Smart Media Card, SMC），安全数字（Secure Digital, SD）卡，闪存卡（Flash Card）等。进一步地，所述存储器61还可以既包括所述集成电路芯6的内部存储单元也包括外部存储设备。所述存储器61用于存储所述计算机程序以及所述集成电路芯所需的其他程序和数据。所述存储器61还可以用于暂时地存储已经输出或者将要输出的数据。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种电力载波信号识别电路，其特征在于，包括：
    电压幅度检测电路，配置为连接电源线，用于检测电源线上每一数据帧的数据以载波信号的形式调制在电源线上所引起的电压幅度变化和持续时间并生成对应的电平信号；
    解码电路，与所述电压幅度检测电路连接，配置为将所述电平信号进行转换得到当前数据帧的数据。
  2. 如权利要求1所述的电力载波信号识别电路，其特征在于，所述电压幅度检测电路具体用于：
    检测电源线上的电压，并根据该电压的峰峰值及持续时间输出对应的电平信号，其中：
    在峰峰值大于预设值且持续时间匹配第一预设时长则输出第二预设时长的第一电平信号；
    在峰峰值大于预设值且持续时间匹配第三预设时长则输出与所述第一电平信号相反的、第四预设时长的第二电平信号；
    在峰峰值大于预设值且持续时间匹配第五预设时长则输出第六预设时长的标识电平，所述标识电平为第一电平信号或第二电平信号。
  3. 如权利要求1或2所述的电力载波信号识别电路，其特征在于，所述电压幅度检测电路包括：
    电平转换单元，配置为连接电源线，用于接入电源线上电压信号，并根据该电压信号生成预设幅值的检测电平；
    比较器，一输入端连接所述检测电平，另一输入端连接基准电压，所述比较器将所述检测电平与基准电压比较输出作为所述电平信号的比较结果。
  4. 如权利要求3所述的电力载波信号识别电路，其特征在于，所述电平转换单元包括一容性器件、第一NMOS管以及一二极管；所述第一NMOS管的栅极用于连接电源线，所述第一NMOS管的漏极作为电平转换单元的输出、连接所述容性器件的第一端，所述容性器件的第二端连接所述比较器的电源端，所述第一NMOS管的源极接地，所述二极管连接在所述第一NMOS管的源极和漏极之间，且正极接地。
  5. 如权利要求4所述的电力载波信号识别电路，其特征在于，所述容性器件包括一电容器；或者
    所述容性器件包括一PMOS管，其中，该PMOS管的栅极作为所述容性器件的第一端，该PMOS管的漏极、源极及衬底共接作为所述容性器件的第二端。
  6. 如权利要求3所述的电力载波信号识别电路，其特征在于，所述电压幅度检测电路还包括上电保护电路，所述上电保护电路的输入端用于连接上电复位信号，所述上电保护电路配置为在所述上电复位信号的控制控制下使所述电压幅度检测电路的输出钳位在高电平或低电平。
  7. 如权利要求6所述的电力载波信号识别电路，其特征在于，所述上电保护电路包括第一反相器和第二NMOS管，所述第一反相器的输入端作为所述上电保护电路的输入端，输出端连接所述第二NMOS管的栅极，所述第二NMOS管的漏极连接所述比较器的输出端或所述输出单元的输出端，所述第二NMOS管的源极接地。
  8. 如权利要求2所述的电力载波信号识别电路，其特征在于，所述解码电路将所述第二预设时长的第一电平信号、所述第四预设时长的第二电平信号分别转换为数据0、1，将所述第六预设时长的标识电平转换为预设标识码；
    其中，每一数据帧的数据包括依次排列的控制码、控制数据、预设标识码。
  9. 如权利要求1或2所述的电力载波信号识别电路，其特征在于，还包括控制电路，所述控制电路与所述解码电路连接，配置为从当前数据帧的数据中提取驱动信号以驱动负载。
  10. 如权利要求9所述的电力载波信号识别电路，其特征在于，所述控制电路包括：
    地址设置电路，配置为设定地址信息；
    数据帧计数电路，配置为根据所述数据中的预设标识码进行计数统计；
    逻辑控制电路，与所述地址设置电路、所述逻辑控制电路及所述负载连接，配置为将所述地址信息与当前数据帧的计数值进行比较，当所述地址信息与所述计数值匹配时，从当前数据帧的数据中提取驱动信号以驱动负载。
  11. 如权利要求10所述的电力载波信号识别电路，其特征在于，所述数据帧计数电路还被配置为接收初值设置指令，根据所述初值设置指令设置数据帧计数器的计数值的初值。
  12. 如权利要求10所述的电力载波信号识别电路，其特征在于，所述地址设置电路通过芯片内部多晶硅熔丝的通断设置设定地址信息。
  13. 一种电力载波信号识别方法，其特征在于，包括：
    检测电源线上每一数据帧的数据以载波信号的形式调制在电源线上所引起的电压幅度变化和持续时间并生成对应的电平信号；
    将所述电平信号进行转换得到当前数据帧的数据。
  14. 如权利要求13所述的电力载波信号识别方法，其特征在于，所述检测电源线上每一数据帧的数据以载波信号的形式调制在电源线上所引起的电压幅度变化和持续时间并生成对应的电平信号，包括：
    检测电源线上的电压，并根据该电压的峰峰值及持续时间输出对应的电平信号，其中；
    在峰峰值大于预设值且持续时间匹配第一预设时长则输出第二预设时长的第一电平信号；
    在峰峰值大于预设值且持续时间匹配第三预设时长则输出与所述电平信号相反的、第四预设时长的第二电平信号；
    在峰峰值大于预设值且持续时间匹配第五预设时长则输出第六预设时长的标识电平，所述标识电平为第一电平信号或第二电平信号。
  15. 如权利要求14所述的电力载波信号识别方法，其特征在于，所述将所述电平信号进行转换得到当前数据帧的数据，包括：
    将所述第二预设时长的第一电平信号、所述第四预设时长的第二电平信号分别转换为数据0、1，将所述第六预设时长的预设时长标识电平转换为预设标识码；
    其中，每一数据帧的数据包括依次排列的控制码、控制数据、预设标识码。
  16. 如权利要求13至15任一项所述的电力载波信号识别方法，其特征在于，还包括从当前数据帧的数据中提取驱动信号以驱动负载。
  17. 如权利要求16所述的电力载波信号识别方法，其特征在于，所述从当前数据帧的数据中提取驱动信号以驱动负载，包括；
    将地址信息与当前数据帧的计数值进行比较，其中，所述计数值是根据所述数据中的预设标识码进行计数统计；
    当所述地址信息与所述计数值匹配时，从当前数据帧的数据中提取控制数据；
    将所述控制数据转换为驱动信号并输出以驱动所述负载。
  18. 如权利要求17所述的电力载波信号识别方法，其特征在于，还包括：
    接收初值设置指令，根据所述初值设置指令设置计数值的初值。
  19. 一种集成电路芯片，其特征在于，包括权利要求1至12任一项所述的电力载波信号识别电路。
  20. 一种集成电路芯片，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现如权利要求13至18任一项所述方法的步骤。
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