WO2021134200A1 - 芯片设计方法、芯片设计装置、芯片及电子设备 - Google Patents

芯片设计方法、芯片设计装置、芯片及电子设备 Download PDF

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Publication number
WO2021134200A1
WO2021134200A1 PCT/CN2019/129895 CN2019129895W WO2021134200A1 WO 2021134200 A1 WO2021134200 A1 WO 2021134200A1 CN 2019129895 W CN2019129895 W CN 2019129895W WO 2021134200 A1 WO2021134200 A1 WO 2021134200A1
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Prior art keywords
power
domain
state
chip
power domain
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PCT/CN2019/129895
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English (en)
French (fr)
Inventor
王毓千
姚水音
梁洪昌
唐志敏
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成都海光集成电路设计有限公司
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Priority to PCT/CN2019/129895 priority Critical patent/WO2021134200A1/zh
Priority to US17/254,242 priority patent/US11775717B2/en
Priority to CN201980006491.1A priority patent/CN113330388B/zh
Publication of WO2021134200A1 publication Critical patent/WO2021134200A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present disclosure relate to the field of chip technology, and in particular to a chip design method, a chip design device, a chip, and an electronic device.
  • EDA Electronics Design Automation
  • VHDL hardware description languages
  • the embodiments of the present disclosure provide a chip design method, a chip design device, a chip, and an electronic device.
  • the method can determine the timing dependence of the power domain during the verification stage of the register conversion level of the chip, so as to ensure the circuit performance when the power domain is turned off. Stability provides the possibility.
  • An embodiment of the present disclosure provides a chip design method, which is applied to the register transfer level (RTL) verification stage of the chip, and the chip design method includes:
  • At least one power state of the chip wherein one of the at least one power state includes the switching state of each power domain on the chip in a chip working mode, and the at least one power state
  • the state includes the first power state
  • determining the at least one power state of the chip includes:
  • the power state table of the unified power supply format file is analyzed to determine the at least one power state of the chip; the power state table describes the switching state of each power domain on the chip in each chip working mode.
  • analyzing the timing dependence between the control signals, and determining the timing dependence between the power domains affected by the control signal in the first power state includes:
  • the power supply relationship includes: the power supply domain supplied by the power supply, and the domain cross-line connection mode of the power supply domain supplied by the power supply;
  • the chip design method further includes:
  • determining the power source corresponding to the control signal includes:
  • the power source corresponding to the power source control line can be traced back through the power source control line.
  • determining the power control line corresponding to the domain crossing line includes:
  • Backtracking the power supply corresponding to the power control line through the power control line includes:
  • the power supply corresponding to the power control line is determined through the mode information of the power management unit.
  • the chip design method further includes:
  • the domain crossover line is affected by the switching state of the power supply, and an isolation unit is designed in the power domain connected to the output end of the domain crossover line, wherein the isolation unit is used at the input end of the domain crossover line Before the connected power domain is turned off, isolate the power domain connected to the input end of the domain crossing line and the power domain connected to the output end of the domain crossing line.
  • the at least one power state further includes a second power state
  • the control signal sent by the changed power domain in each power domain includes:
  • the switch states of the power domains in the second power state and the switch states of the power domains in the first power state it is determined that the power state of the chip changes from the second power state The changed power domain when switching to the first power state;
  • the embodiment of the present disclosure also provides a chip design device, including:
  • a power state determination circuit for determining at least one power state of the chip, wherein one power state in the at least one power state includes the switching state of each power domain on the chip in a chip working mode , The at least one power state includes a first power state;
  • the control signal determining circuit is used to determine the control signal sent by the power domain of the change in each power domain when the power state of the chip is switched to the first power state, wherein the power state of the chip is switched When the first power state is reached, the switch state of the changing power domain changes;
  • An analysis circuit is used to analyze the timing dependence between the control signals, and determine the timing dependence between the power domains that the control signals act on in the first power state.
  • the embodiment of the present disclosure also provides a chip, including:
  • a power management unit configured to obtain the timing dependency between the first power domain and the second power domain
  • a first power source and a second power source connected to the power management unit
  • the first power domain connected to the first power source, where the first power source supplies power to the first power domain;
  • the second power source supplies power to the second power domain; wherein, the timing dependency indicates that in the current power state, the second power domain is Depends on the first power domain in timing;
  • the second power domain includes an isolation unit configured to isolate the first power domain from the second power domain before the first power domain is turned off.
  • the first input terminal of the isolation unit is connected to a control line between the first power supply domain and the second power supply domain, and the control line is a crossover from the first power supply domain to the second power supply The domain crossing line of the domain; the second input terminal of the isolation unit is connected to the power management unit.
  • the power management unit is configured to send an isolation signal to the isolation unit before sending a power-down signal to the first power source to turn off the first power domain based on the timing dependency, So that the isolation unit isolates the control line between the first power domain and the second power domain; and the control line between the first power domain and the second power domain After isolation, a power-down signal is sent to the first power source to turn off the first power domain.
  • the embodiments of the present disclosure also provide an electronic device, including the chip described in any of the above embodiments.
  • the embodiments of the present disclosure can determine at least one power state of the chip during the RTL verification stage of the chip design, where one power state in the at least one power source includes that each power domain on the chip works in one chip.
  • the at least one power state includes the first power state; thus, it is determined that when the power state of the chip is switched to the first power state, the change power domain in each power domain sends control Signal, wherein when the power state of the chip is switched to the first power state, the switch state of the changing power domain changes; further, the timing dependence between the control signals is analyzed to determine the control signal According to the timing dependence between the control signals, determine the timing dependence between the power domains that each control signal acts on in the first power state, so as to realize that the power domain is determined in each power state Timing dependency between.
  • the embodiments of the present disclosure can analyze the timing dependence between the control signals sent by the power domain whose switch state changes when the power state is switched, so as to determine the power domain under the switched power state.
  • the timing dependence between the power domains can be used to determine the timing dependence of the power domain; and the embodiments of the present disclosure can analyze and determine the timing dependency of the power domain during the RTL verification stage, without having to implement it at the gate-level stage of the chip design. Therefore, the embodiments of the present disclosure can relatively simply implement the analysis and determination of the timing dependence of the power domain.
  • Figure 1 is a schematic diagram of a power management unit with a power domain to manage power
  • Figure 2 is a schematic diagram of the structure of a chip
  • FIG. 3 is a schematic diagram of turning off the first power domain according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of signals corresponding to turning off the first power domain according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of another structure of a chip provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of another signal corresponding to turning off the first power domain according to an embodiment of the present disclosure
  • FIG. 7 is a flowchart of a chip design method provided by an embodiment of the present disclosure.
  • FIG. 8 is an exemplary diagram of a power state provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a method for implementing step S120 in the process shown in FIG. 7;
  • FIG. 10 is a block diagram of a chip design device provided by an embodiment of the present disclosure.
  • FIG. 11 is another block diagram of a chip design apparatus provided by an embodiment of the disclosure.
  • chip design In addition to considering performance and cost, chip design also needs to consider chip-level or system-level power consumption requirements. Therefore, chip low-power design is also a key task of chip design; current chip low-power design can use multiple power domains (Power Domain ) Design and implementation, by running certain power domains under a lower power supply voltage, or turning off the power domains in an idle state, thereby reducing the power consumption of the chip.
  • Power Domain power domains
  • the inventor of the present invention found that: based on the current chip low-power design, when the power domain needs to be turned off, if the timing dependency of the power domain is not considered, it is very likely to cause the instability of the chip circuit; therefore, how to determine the power domain The timing dependence becomes very important.
  • the power domain of the chip can be turned off by the PMU (Power Management Unit).
  • the PMU can be connected to the power source, and the power source can be connected to the power domain.
  • the power domain can refer to a group of design elements that share power in the chip.
  • the power domain may include, for example, Host Interface and CGC (Clock Gating Control) modules, Processor and Baseband Subsystem modules, For the RF subsystem (radio frequency subsystem) module, it should be noted that there may also be connections between power domains (not shown in Figure 1); the form of the power domain shown in Figure 1 is only an optional example.
  • Embodiments Any power domain described below can be any of the multiple forms of power domains; of course, the embodiments of the present disclosure also support any power domain described below as other forms of power domains, and are not limited to the above Example.
  • FIG. 2 an example of a chip may be shown in FIG. 2.
  • the chip may include: PMU1, first power supply 2, first power supply domain 3, second power supply 4, and second power supply domain 5; for example, first power supply 2 Output voltage Vdd1 to the first power domain 3 to supply power to the first power domain 3, and the second power source 4 outputs voltage Vdd2 to the second power domain 5 to supply power to the second power domain 5; Power-up and power-down can be controlled by PMU1.
  • Figure 3 shows an optional schematic diagram of turning off the first power domain 3.
  • the PMU1 can output PD ( Power Down signal, the first power supply 2 is powered off (correspondingly, the voltage Vdd1 output by the first power supply 2 to the first power supply domain 3 becomes 0 volts), so that the first power supply domain 3 is turned off.
  • PD Power Down signal
  • the PMU1 can output a PD signal to the second power source 4, and the second power source 4 is powered down (correspondingly, the voltage Vdd2 output by the second power source 4 to the second power domain 5 changes Is 0 volts), so that the second power domain 5 is turned off.
  • the PMU1 can output a power-on signal to the first power source 2, and the first power source 2 is powered on (correspondingly, the voltage Vdd1 output by the first power source 2 to the first power domain 3 changes Is a positive value), so that the first power domain 3 is turned on;
  • the PMU1 can output a power-on signal to the second power source 4, and the second power source 4 is powered on (correspondingly, the second The voltage Vdd2 output by the power supply 4 to the second power domain 5 becomes a positive value), so that the second power domain 5 is turned on;
  • the power-on signal and the power-off signal are power control signals for the PMU1 to control the power supply (for example, the first power supply 2 and the second power supply 4 shown in FIG. 2).
  • FIG. 4 shows a schematic diagram of signal changes in the process of turning off the first power domain. ; It can be seen from Figure 4 that if the PMU1 outputs the PD signal to the first power supply 2, the first power supply domain 3 is turned off immediately, then the signal a output from the first power supply domain 3 to the second power supply domain 5 will be determined by The value becomes unknown.
  • Vdd2 maintains the power-on state (positive value), the PD signal is in a low-level state to indicate that the PD signal is not activated, and the PD signal is in a high-level state to indicate that the PD signal is activated, and Vdd1 is in a low-power state
  • the flat state indicates that the first power supply 2 is powered off, that is, the first power supply domain 3 is off, and the Vdd1 is in a high state indicates that the first power supply 2 is powered on, that is, the first power supply domain 3 is turned on.
  • the power domain (for example, the first power domain 3 or the second power domain 5 shown in FIG. 2) will change between an on state and an off state ; And there are generally timing dependencies between multiple power domains. If the power domain is not considered when the PMU1 turns off the power domain, it is very easy to cause the instability of the chip circuit.
  • the embodiments of the present disclosure provide an improved chip and a corresponding solution for turning off the power domain; alternatively, the chip provided in the embodiments of the present disclosure may As shown in FIG. 5, referring to FIG. 5, the chip may include: PMU1, first power supply 2, first power supply domain 3, second power supply 4, second power supply domain 5, and an isolation unit arranged in the second power supply domain 5. 6. The first power domain 3 to which the first power source 2 is connected, and the first power source 2 provides power to the first power domain 3; the second power domain 4 to which the second power source 3 is connected, and the second power source 3 is the second power domain 5 powered by. The isolation unit 6 is used to isolate the first power domain 3 and the second power domain 5 before the first power domain 3 is turned off.
  • PMU1 is used to obtain the timing dependency between the first power domain and the second power domain.
  • the timing dependence is determined based on the chip design method described below.
  • Timing dependency means that in the current power state, the second power domain 5 depends on the first power domain 3 in timing; optionally, the isolation unit 6 may be a power gate (for example, a logic gate such as a NAND gate).
  • the embodiment of the present disclosure may first pass through the isolation unit in the second power domain 5 6 Isolate the first power domain 3 and the second power domain 5, for example, isolate the control line connected between the first power domain 3 and the second power domain 5, and then turn off the first power domain 3, so that the first power domain 3 After the power domain 3 is turned off, the instability of the second power domain 5 that depends on the first power domain 3 is reduced, thereby achieving the purpose of reducing the instability of the chip circuit when the first power domain 3 is turned off.
  • the first input terminal of the isolation unit 6 provided in the second power domain 5 can be connected to the control line between the first power domain 3 and the second power domain 5, and the control line can be the first power domain 3 to the second power domain.
  • Domain Crossing of power domain 5, the second input terminal of isolation unit 6 is connected to PMU1, the second input terminal of isolation unit 6 can detect the isolation signal, that is, receive the isolation signal, and the output terminal of isolation unit 6 can be connected to The second power domain 5, and the output terminal of the isolation unit 6 can output signal b;
  • the embodiment of the present disclosure can be set: PMU1 based on the timing dependence, before sending the PD signal to the first power supply 2, can be set to the second power supply
  • the isolation unit 6 in the domain 5 sends out an isolation signal, so that the isolation unit 6 can isolate the control line connected between the first power domain 3 and the second power domain 5 to realize the isolation of the first power domain 3 and the second power domain 5 , And then the PMU1 sends a PD signal to the first power supply 2 to switch off the first
  • FIG. 6 shows a schematic diagram of signal changes in the process of turning off the first power domain in the embodiment of the present disclosure.
  • the isolation signal acts before the PD signal, that is, the first power domain 3 and the second power domain 3
  • the signal a becomes unknown, that is, The signal a may cause the second power domain 5 to be unstable, but since the first power domain 3 and the second power domain 5 have been isolated in advance, the unknown state of the signal a will have a smaller impact on the second power domain 5, so The instability of the second power domain 5 that depends on the first power domain 3 can be reduced, and the purpose of reducing the instability of the chip circuit when the first power domain 3 is turned off is realized.
  • the core idea of turning off the power domain in the embodiment of the present disclosure is: when the first power domain 3 on which the second power domain 5 depends needs to be turned off, the embodiment of the present disclosure can be isolated by the second power domain 5
  • the unit first isolates the first power domain 3 and the second power domain 5, and then turns off the first power domain 3 on which the second power domain 5 depends, thereby reducing the instability of the chip circuit when the first power domain 3 is turned off
  • the first power domain 3 and the second power domain 5 are any two power domains in the chip that are dependent on timing, and the second power domain 5 depends on the first power domain 3.
  • the solution for shutting down the power domain provided by the embodiments of the present disclosure, it is necessary to determine the timing dependency between the power domains, that is, there are some timing requirements for the power supply control signal of the PMU1 to shut down the power supply domain.
  • the PMU shuts down the power domain
  • the solution of turning off the power domain provided by the embodiments of the present disclosure is implemented; however, in the chip design process, the analysis of the timing dependency is generally at the gate-level stage of the chip, such as by using SDF( Standard Delay format) gate-level simulation determines the timing dependence between power domains; however, the circuit scale of the gate-level stage is undoubtedly very complex and huge.
  • SDF gate-level simulation to determine the timing dependence between power domains is undoubtedly extremely complex.
  • mainstream chip design is mainly divided into specifications, algorithm-level description, RTL-level (register transfer level, register transfer level) description, gate-level netlist, layout and other design processes.
  • RTL-level and gate-level design are chip designs. Two key stages: RTL level uses hardware description language (such as Verilog or VHDL) to describe chip functions, RTL level is logically synthesized to obtain gate level (such as gate-level netlist), and gate level uses specific logic units (depending on Cell library) to implement chip functions.
  • the gate level introduces timing relationships (including timing dependencies between power domains referred to in the embodiments of the present disclosure).
  • RTL-level simulation and gate-level simulation are respectively for the RTL-level and gate-level simulation verification stages; RTL-level simulation is to verify the syntax and basic functions of the chip function described by the hardware description language (not including timing information); Level simulation is mainly for the simulation verification of the gate-level timing after logic synthesis; it can be seen that although the timing verification can be achieved at the gate-level simulation, the gate-level is represented by specific logic units, and the circuit scale is very complex and large, so Using SDF gate-level simulation to analyze the timing dependence between power domains is undoubtedly extremely complicated.
  • the embodiment of the present disclosure provides a novel chip design method to determine the timing dependency between power domains in a relatively simple manner, so that the PMU can be based on
  • the timing dependence between power domains realizes the solution of turning off the power domain provided in the embodiments of the present disclosure, and further, when the designed chip needs to turn off the power domain, it is possible to ensure the stability of the circuit.
  • FIG. 7 shows an optional process of the chip design method provided by the embodiment of the present disclosure, and the chip design method can be applied in the RTL verification stage of the chip design;
  • a tool for implementing the chip design method provided by the embodiment of the present disclosure can be configured in a chip design tool (for example, EDA), so that the tool can be executed to implement the chip design method provided by the embodiment of the present disclosure.
  • a chip design tool for example, EDA
  • the chip design method may include:
  • Step S100 Determine at least one power state of the chip, where one power state of the at least one power state includes the switching state of each power domain on the chip in a chip working mode.
  • the at least one power state includes a first power state.
  • the chip may have multiple chip working modes, such as power off (power off), standby (standby), sleep (sleep), etc.
  • the chip may also have other chip working modes not shown, which will not be shown here. Expand the explanation; in different chip working modes, the on-off state of each power domain on the chip is also different. For example, in the power-off chip working mode, most of the power domains corresponding to the power supply are powered off, so most of the power domains It is the off state. In the standby chip working mode, the power supply corresponding to some power domains is powered on, and the power supply of some power domains is powered off. Therefore, some power domains are in the on state, and some power domains are in the off state.
  • PDA Power Domain A
  • PDB Power Domain B
  • PDC Power Domain C
  • RF subsystem modules as an example, as shown in Fig. 8 exemplarily An example diagram of each power state is shown, and each power state can represent the switch state of the power domain in each chip working mode.
  • the switching state of each power domain can constitute a power state (power state): on, off, off; in the chip working mode of standby, the switching state of each power domain can be constituted Power state: on, off, off; that is to say, for any chip working mode, the set of switch states of each power domain in the chip working mode can be used as the power state of the chip working mode; that is, the analyzed A power state includes the switching state of each power domain in a chip working mode.
  • the embodiments of the present disclosure may determine the switching states of each power domain in each chip working mode, respectively, so as to aggregate the switching states of each power domain in each chip working mode to obtain at least one power state of the chip.
  • the switch state of the power domain in any chip working mode can be described by a UPF (United Power Format) file, and the embodiment of the present disclosure may determine the switch state of each power domain in each chip working mode according to the UPF file.
  • UPF United Power Format
  • the UPF file is a standard power format file widely used in the IEEEl801 standard for low-power design and verification.
  • the UPF file consists of a set of commands similar to Tool Command Language (tool command language) to describe the chip Low power intent in the design.
  • Step S110 It is determined that when the power state of the chip is switched to the first power state, the changed power domain in each power domain sends a control signal.
  • variable power domain may be a part of the power domain on the chip, that is, each power domain includes a variable power domain.
  • the switch state of the changing power domain changes.
  • the determined control signal can be multiple; optionally, the first power state and the second power state can be set as two power states of the power state of the chip That is, at least one power state further includes a second power state.
  • the embodiments of the present disclosure can determine that the switch state changes when the second power state is switched to the first power state. Power domain, and determine the control signal sent by the power domain of the switch state change.
  • the power state switching referred to in step S110 should be a legal power state switching, that is, the allowed power state switching during chip design.
  • the at least one power state further includes a second power state.
  • Step S110 includes: determining the switching state of each power domain in the second power state; determining the switching state of each power domain in the first power state; according to the switching state of each power domain in the second power state and the switching state of each power domain in the first power state; The switch state of each power domain in the state determines the changed power domain when the power state of the chip is switched from the second power state to the first power state; determines the control signal sent by the changed power domain.
  • the switch state for example, the on state
  • the switch state for example, the off state
  • Step S120 Analyze the timing dependence between the control signals, and determine the timing dependence between the power domains that each control signal acts on in the first power state (that is, the power state switched to).
  • the embodiment of the present disclosure may use a static timing analysis (Timing Analysis, STA) method to analyze the timing dependence between the control signals, and determine the power state to which the power domains acted by the control signals are switched.
  • STA Timing Analysis
  • the timing dependence under.
  • the power domain to which each control signal acts includes the power domain that sends the control signal and the power domain to which the control signal crosses.
  • the embodiments of the present disclosure can determine at least one power state of the chip during the RTL verification stage of the chip design, where one power state of the at least one power state includes the switching state of each power domain in a chip working mode; Therefore, when the power state is switched, the control signal sent by the power domain (that is, the changing power domain) of the switch state is determined; further, the timing dependence between the control signals is analyzed, and the power domain that each control signal acts on is determined to be between the power domains. The timing dependence of the switched power state is realized in each power state, and the timing dependence between power domains is determined.
  • the embodiments of the present disclosure can analyze the timing dependence between the control signals sent by the power domains whose switch state changes when the power state is switched, so as to determine the power state between the power domains when the power state is switched to.
  • Timing dependence is to realize the determination of the timing dependence of the power domain; and the embodiment of the present disclosure is to analyze and determine the timing dependence of the power domain in the RTL verification stage, without having to implement it at the gate-level stage of the chip design.
  • the example can be relatively simple to realize the analysis and determination of the timing dependence of the power domain.
  • FIG. 9 shows the flow of an optional implementation method of step S120 in the flow shown in FIG. 7.
  • the flow may include:
  • Step S200 Determine the domain crossing line corresponding to the control signal.
  • Domain Crossing is a domain crossing line between power domains, indicating the control signal crossing from one power domain to another power domain; for example, as shown in FIG. 5, the first power source
  • the connection between the domain and the second power domain can be considered as a domain crossing line.
  • the embodiment of the present disclosure may determine the domain crossing line from the power domain that sends the control signal to the power domain to which the control signal crosses.
  • Step S210 Determine the power control line corresponding to the domain crossover line.
  • the embodiments of the present disclosure can combine the Power State Table and PMU model information to determine the power control line corresponding to the domain crossing line, and the power control line corresponding to the domain crossing line
  • the line can be considered as the power control line of the power domain that outputs the control signal connected to the domain crossing line.
  • Step S220 through the power control line, trace back the power corresponding to the power control line.
  • the embodiments of the present disclosure can determine the power supply corresponding to the power control line.
  • Step S230 Determine the power supply relationship of the power supply according to the characteristics of the power supply; the power supply relationship includes: the power supply domain supplied by the power supply and the cross-line connection mode of all domains of the power supply domain supplied by the power supply.
  • Step S240 According to the power supply relationship of the power supply, it is determined whether the domain crossing line of the power supply domain supplied by the power supply is affected by the switching state of the power supply. If so, step S250 is executed, and if not, step S260 is executed.
  • the switching state of the power supply includes a power-on state and a power-off state.
  • the domain crossing line of the power domain supplied by the power supply is affected by the switch state of the power supply, indicating that when the power supply changes between the power-on state and the power-down state, the corresponding control signal of the domain crossing line of the power domain supplied by the power supply will change.
  • Step S250 Determine that the power domain connected to the domain crossover line affected by the switching state of the power source has a timing dependency in the first power state.
  • the power domain connected to the domain crossing line includes the power domain connected to the input end of the domain crossing line and the power domain connected to the output end of the domain crossing line, and the power domain to which the domain crossing line is affected by the switching state of the power source is connected.
  • the control signal spans from the power domain connected to the input end of the domain crossing line to the power domain connected to the output end of the domain crossing line.
  • the embodiment of the present disclosure may provide an isolation unit in the power domain connected to the output end of the domain crossing line, and the isolation unit may be connected to the power source at the input end of the domain crossing line.
  • the power domain connected to the input end of the isolation domain crossover line and the power domain connected to the output end of the domain crossover line are used to realize the solution of shutting down the power domain provided by the embodiments of the present disclosure;
  • the power domains that are affected by the switching state of the domain crossover line are the first power domain and the second power domain, and the second power domain depends on the first power domain as an example (that is, the power domain connected to the input end of the domain crossover line is In the first power domain, the power domain connected to the output end of the domain crossing line is the second power domain), when it is necessary to turn off the first power domain on which the second power domain depends, the embodiment of the present disclosure can pass through the second power domain
  • the isolation unit first isolates the first power domain and the second power domain, and then turns off the first power domain on which the second power domain depends, thereby reducing the instability of the chip circuit when the first power domain is turned off.
  • Step S260 It is determined that the power domain connected to the domain crossover line that is not affected by the switching state of the power source does not have a timing dependency in the first power state.
  • the power consumption intent of the chip design described in the UPF file may cover the power supply network, the isolation unit, and the power switch unit managed by the PMU.
  • the UPF file can specify how to establish the power supply network, the behavior between each power line, and additional logic functions to support the design of dynamic power domain shutdown.
  • the UPF file can define the power domain; the UPF file can accurately describe the power network of each power domain according to the power distribution, and define the power supply of each power domain in detail Line name and the connection relationship with the original power input port of the chip, etc.; in a design with power domain shutdown, UPF can define the power domain shutdown unit (Power Gating cell), describing the power domain input and output of the power domain shutdown unit As well as the connection relationship of the control signal, the power domain shutdown unit can be inserted in the physical realization stage of the chip design.
  • Power Gating cell Power Gating cell
  • the chip design device provided by the embodiment of the present disclosure is introduced below.
  • the chip design device described below can be considered as a functional module required by a chip design tool (such as EDA) to implement the chip design method provided by the embodiment of the present disclosure.
  • the content of the chip design device described below can be referred to correspondingly with the content of the chip design method described above.
  • FIG. 10 is a block diagram of a chip design apparatus provided by an embodiment of the disclosure.
  • the chip design apparatus may include:
  • the power state determining circuit 100 is used to determine at least one power state of the chip, wherein one of the at least one power state includes the switching state of each power domain on the chip in a chip working mode, and at least one One power state includes the first power state.
  • the control signal determining circuit 110 is used to determine the control signal sent by the changing power domain in each power domain when the power state of the chip is switched to the first power state, wherein, when the power state of the chip is switched to the first power state, The switch state of the power domain changes.
  • the analysis circuit 120 is configured to analyze the timing dependence between the control signals, and determine the timing dependence between the power domains that each control signal acts on in the first power state (that is, the power state switched to).
  • the power state determining circuit 100 is specifically configured to: analyze the PST of the UPF file to determine at least one power state of the chip; the PST describes each of the chip The switch state of the power domain in the working mode of each chip.
  • the analysis circuit 120 when performing an analysis of the timing dependence between the control signals to determine the timing dependence operation between the power domains that the control signals act on in the first power state, the analysis circuit 120 is specifically configured to:
  • the power supply relationship includes: the power supply domain supplied by the power supply and the cross-line connection mode of the power supply domain supplied by the power supply;
  • the analysis circuit 120 when performing an analysis of the timing dependence between the control signals to determine the timing dependence operation between the power domains that the control signals act on in the first power state, the analysis circuit 120 may also be used to:
  • the analysis circuit 120 is specifically configured to:
  • the power control line corresponding to the domain crossover line is determined.
  • the analysis circuit 120 when performing the operation of tracing the power supply corresponding to the power control line through the power control line, the analysis circuit 120 is specifically configured to:
  • the power supply corresponding to the power control line is determined.
  • FIG. 11 shows another block diagram of a chip design apparatus provided by an embodiment of the present disclosure.
  • the chip design apparatus may further include:
  • the isolation design circuit 130 is used to design an isolation unit in the power domain connected to the output end of the domain crossover line if the domain crossover line is affected by the switching state of the power supply; the isolation unit is used for the power supply connected at the input end of the domain crossover line Before the domain is turned off, the power domain connected to the input end of the isolation domain crossover line and the power domain connected to the output end of the domain crossover line.
  • the above-mentioned chip design apparatus may be a program module in a chip design tool (such as EDA).
  • the embodiments of the present disclosure also provide an electronic device, and the electronic device may include the chip shown in FIG. 5 above. That is, the electronic device may include a chip, and the chip includes: a power management unit for obtaining the timing dependency between the first power domain and the second power domain; the first power source and the second power source connected to the power management unit Power supply; a first power supply domain connected to the first power supply, the first power supply supplying power for the first power supply domain; a second power supply domain connected to the second power supply, the second power supply supplying power for the second power supply domain, wherein the timing depends It means that in the current power state, the second power domain depends on the first power domain in time sequence; the second power domain includes an isolation unit, and the isolation unit is used to isolate the first power domain from the first power domain before the first power domain is turned off. Two power domain.
  • the first input terminal of the isolation unit is connected to the control line between the first power domain and the second power domain, and the control line is a domain crossing line from the first power domain to the second power domain; the second input terminal of the isolation unit is connected Power management unit.
  • the power management unit is used to send an isolation signal to the isolation unit before sending a power-down signal to the first power source to turn off the first power domain, so that the isolation unit separates the first power domain from the second power domain.
  • the control lines between the power domains are isolated; and after the control lines between the first power domain and the second power domain are isolated, a power-down signal is sent to the first power source to turn off the first power domain.
  • the electronic device may be a terminal device or a server device, and the electronic device may include the chip described in the embodiments of the present disclosure.

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Abstract

一种芯片设计方法、装置、芯片及电子设备，方法包括：确定芯片的至少一种电源状态，其中，一种电源状态包括各电源域在一种芯片工作模式下的开关状态（S100），至少一种电源状态包括第一电源状态；确定在芯片的电源状态切换到第一电源状态时，各电源域中的变化电源域发送的控制信号（S110），其中，在芯片的电源状态切换到第一电源状态时，变化电源域的开关状态发生变化；对控制信号间的时序依赖进行分析，确定控制信号所作用的电源域之间在第一电源状态下的时序依赖性（S120）；可在芯片的寄存器转换级验证阶段确定电源域的时序依赖性，从而在关断电源域时，保障电路的稳定性。

Description

芯片设计方法、芯片设计装置、芯片及电子设备 技术领域
本公开实施例涉及芯片技术领域，具体涉及一种芯片设计方法、芯片设计装置、芯片及电子设备。
背景技术
EDA(Electronics Design Automation，电子设计自动化)是芯片设计的常用技术，EDA是以计算机为工具，根据硬件描述语言(例如Verilog、VHDL等)完成设计文件，然后由计算机自动地完成逻辑编译、化简、分割、综合、优化、布局、布线和仿真，直至完成对于特定目标芯片的适配编译、逻辑映射和编程下载等工作。使用EDA技术，可以极大地提高芯片设计的效率，减轻设计者的劳动强度。
发明内容
本公开实施例提供一种芯片设计方法、芯片设计装置、芯片及电子设备，该方法可以在芯片的寄存器转换级验证阶段确定电源域的时序依赖性，从而在关断电源域时，保障电路的稳定性提供可能。
本公开的一实施例提供一种芯片设计方法，应用于芯片的寄存器转换级(register transfer level，RTL)验证阶段，所述芯片设计方法包括：
确定芯片的至少一种电源状态，其中，所述至少一种电源状态中的一种电源状态包括所述芯片上的各电源域在一种芯片工作模式下的开关状态，所述至少一种电源状态包括第一电源状态；
确定在所述芯片的电源状态切换到所述第一电源状态时，所述各电源域中的变化电源域发送的控制信号，其中，在所述芯片的电源状态切换到所述第一电源状态时，所述变化电源域的开关状态发生变化；
对所述控制信号间的时序依赖进行分析，确定所述控制信号所作用的电源域之间在所述第一电源状态下的时序依赖性。
可选的，确定所述芯片的所述至少一种电源状态包括：
分析统一电源格式文件的电源状态表，确定所述芯片的所述至少一种电源状态；所述电源状态表描述有所述芯片上的各电源域在各芯片工作模式下的开 关状态。
可选的，对所述控制信号间的时序依赖进行分析，确定所述控制信号所作用的电源域之间在所述第一电源状态下的所述时序依赖性包括：
确定所述控制信号相应的电源；
根据所述电源的特性，确定所述电源的供电关系，其中，所述供电关系包括：所述电源所供电的电源域，以及所述电源所供电的所述电源域的域跨越线连接方式；
根据所述电源的供电关系，确定所述电源所供电的所述电源域的所述域跨越线是否受所述电源的开关状态影响；
确定受所述电源的开关状态影响的域跨越线所连接的电源域在所述第一电源状态下存在时序依赖性。
可选的，所述芯片设计方法还包括：
确定未受所述电源的开关状态影响的域跨越线所连接的电源域在所述第一电源状态下不存在时序依赖性。
可选的，确定所述控制信号相应的所述电源包括：
确定所述控制信号相应的所述域跨越线；
确定所述域跨越线所对应的电源控制线；
通过所述电源控制线，回溯所述电源控制线相应的所述电源。
可选的，确定所述域跨越线所对应的所述电源控制线包括：
根据所述电源状态表与电源管理单元的模式信息，确定所述域跨越线所对应的所述电源控制线；
通过所述电源控制线，回溯所述电源控制线相应的所述电源包括：
通过所述电源管理单元的模式信息，确定所述电源控制线相应的所述电源。
可选的，所述芯片设计方法还包括：
确定所述域跨越线受所述电源的开关状态影响，在所述域跨越线的输出端连接的电源域中设计隔离单元，其中，所述隔离单元用于在所述域跨越线的输入端连接的电源域关断前，隔离所述域跨越线的输入端连接的所述电源域和所述域跨越线的输出端连接的所述电源域。
可选的，所述至少一种电源状态还包括第二电源状态；
确定在所述芯片的电源状态切换到所述第一电源状态时，所述各电源域中的变化电源域发送的控制信号包括：
确定在所述第二电源状态时所述各电源域的开关状态；
确定在所述第一电源状态时所述各电源域的开关状态；
根据在所述第二电源状态时所述各电源域的开关状态和在所述第一电源状态时所述各电源域的开关状态，确定在所述芯片的电源状态从所述第二电源状态切换到所述第一电源状态时的所述变化电源域；
确定所述变化电源域发送的控制信号。
本公开实施例还提供一种芯片设计装置，包括：
电源状态确定电路，用于确定芯片的至少一种电源状态，其中，所述至少一种电源状态中的一种电源状态包括所述芯片上的各电源域在一种芯片工作模式下的开关状态，所述至少一种电源状态包括第一电源状态；
控制信号确定电路，用于确定在所述芯片的电源状态切换到所述第一电源状态时，所述各电源域中的变化电源域发送的控制信号，其中，在所述芯片的电源状态切换到所述第一电源状态时，所述变化电源域的开关状态发生变化；
分析电路，用于对所述控制信号间的时序依赖进行分析，确定所述控制信号所作用的电源域之间在所述第一电源状态下的时序依赖性。
本公开实施例还提供一种芯片，包括：
电源管理单元，用于获取所述第一电源域和所述第二电源域之间的时序依赖性；
与所述电源管理单元连接的第一电源和第二电源；
与所述第一电源连接的所述第一电源域，所述第一电源为所述第一电源域供电；
与所述第二电源连接的所述第二电源域，所述第二电源为所述第二电源域供电；其中，所述时序依赖性表示在当前电源状态下，所述第二电源域在时序上依赖于所述第一电源域；
所述第二电源域包括隔离单元，所述隔离单元用于在所述第一电源域关断前，隔离所述第一电源域和所述第二电源域。
可选的，所述隔离单元的第一输入端连接所述第一电源域和所述第二电源域间的控制线，所述控制线为所述第一电源域跨越到所述第二电源域的域跨越线；所述隔离单元的第二输入端连接所述电源管理单元。
可选的，所述电源管理单元用于基于所述时序依赖性，在向所述第一电源发送掉电信号以使所述第一电源域关断前，向所述隔离单元发送隔离信号，以 使所述隔离单元将所述第一电源域和所述第二电源域间的所述控制线进行隔离；及在所述第一电源域和所述第二电源域间的所述控制线隔离后，向所述第一电源发送掉电信号，以使所述第一电源域关断。
本公开实施例还提供一种电子设备，包括上述任一实施例所述的芯片。
本公开实施例可在芯片设计的RTL验证阶段，确定芯片的至少一种电源状态，其中，所述至少一种电源中的一种电源状态包括所述芯片上的各电源域在一种芯片工作模式下的开关状态，所述至少一种电源状态包括第一电源状态；从而确定在所述芯片的电源状态切换到所述第一电源状态时，所述各电源域中的变化电源域发送控制信号，其中，在所述芯片的电源状态切换到所述第一电源状态时，所述变化电源域的开关状态发生变化；进而，对各控制信号间的时序依赖进行分析，确定各控制信号间的时序依赖性，根据各控制信号间的时序依赖性，确定各控制信号所作用的电源域之间在所述第一电源状态下的时序依赖性，从而实现在各电源状态下，确定电源域间的时序依赖性。本公开实施例可在芯片设计的RTL验证阶段，分析在电源状态切换时，对开关状态变化的电源域发送的控制信号间的时序依赖进行分析，从而在切换到的电源状态下，确定电源域之间的时序依赖性，实现电源域的时序依赖性的确定；并且本公开实施例是可在RTL验证阶段，实现分析确定电源域的时序依赖性，而不必在芯片设计的门级阶段实现，因此本公开实施例可相对较为简便的实现电源域的时序依赖性的分析确定。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为一种具有电源域的电源管理单元管理电源的示意图；
图2为一种芯片的结构示意图；
图3为本公开一实施例提供的关断第一电源域的示意图；
图4为本公开一实施例提供的关断第一电源域相应的信号示意图；
图5为本公开一实施例提供的一种芯片的另一结构示意图；
图6为本公开一实施例提供的关断第一电源域相应的另一信号示意图；
图7为本公开一实施例提供的一种芯片设计方法的流程图；
图8为本公开一实施例提供的一种电源状态的示例图；
图9为图7所示流程中步骤S120的实现方法流程图；
图10为本公开一实施例提供的一种芯片设计装置的框图；
图11为本公开一实施例提供的一种芯片设计装置的另一框图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
芯片设计除了考虑性能、成本外，还需考虑芯片级或系统级的功耗要求，因此芯片低功耗设计也是芯片设计的关键工作；目前的芯片低功耗设计可以采用多电源域(Power Domain)设计实现，通过在较低电源电压下运行某些电源域，或者关断处于空闲状态的电源域，从而实现降低芯片功耗。本发明的发明人发现：基于目前的芯片低功耗设计，在需要关断电源域时，如果不考虑电源域的时序依赖性，极可能导致芯片电路的不稳定性；因此，如何确定电源域的时序依赖性变得非常重要。
芯片的电源域可由PMU(Power Management Unit，电源管理单元)控制关断，如图1所示，PMU可连接电源，电源可连接电源域，电源域可以是指芯片中共用电源的一组设计元素；示例的，如图1所示，电源域可以包括例如：Host Interface(主机接口)与CGC(Clock Gating Control，时钟门控)模块、Processor(处理器)与Baseband Subsystem(基带子系统)模块、RF subsystem(射频子系统)模块，需要说明的是，电源域之间还可存在连线(图1未示出)；图1所示的电源域的形式仅是一种可选示例，本公开实施例下文描述的任一电源域可以是该多种形式的电源域中的任一种；当然，本公开实施例也支持下文描述的任一电源域为其他形式的电源域，并不限于上述示例。
可选的，一种芯片的示例可如图2所示，芯片可以包括：PMU1、第一电源2、第一电源域3、第二电源4和第二电源域5；例如，第一电源2向第一电源域3输出电压Vdd1，为第一电源域3供电，第二电源4向第二电源域5输出电压Vdd2，为第二电源域5供电；第一电源2和第二电源4的上电和掉电 可受PMU1控制。
示例的，基于图2所示芯片的结构，图3示出了关断第一电源域3的可选示意图，在需要关断第一电源域3时，PMU1可向第一电源2输出PD(Power Down，掉电)信号，第一电源2掉电(相应的，第一电源2输出给第一电源域3的电压Vdd1变为0伏特)，从而第一电源域3关断。
同理，在需要关断第二电源域5时，PMU1可向第二电源4输出PD信号，第二电源4掉电(相应的，第二电源4输出给第二电源域5的电压Vdd2变为0伏特)，从而第二电源域5关断。
示例的，在需要开启第一电源域3时，PMU1可向第一电源2输出上电信号，第一电源2上电(相应的，第一电源2输出给第一电源域3的电压Vdd1变为正值)，从而第一电源域3开启；同理，在需要开启第二电源域5时，PMU1可向第二电源4输出上电信号，第二电源4上电(相应的，第二电源4输出给第二电源域5的电压Vdd2变为正值)，从而第二电源域5开启；
可以理解的是，上电信号和掉电信号为PMU1控制电源(例如，图2所示的第一电源2和第二电源4)的电源控制信号。
示例的，以第二电源域5在时序上依赖于第一电源域3为例，以图3所示的示例为基础，图4示出了关断第一电源域的过程中的信号变化示意；从图4可以看出，如果PMU1向第一电源2输出PD信号时，立刻进行第一电源域3的关断，那么第一电源域3输出给第二电源域5的信号a将由可确定值变得unknown(未知)，由于第二电源域5在时序上依赖于第一电源域3，这将使得第二电源域5由于第一电源域3的突然关断变得不稳定，从而导致芯片电路的不稳定性；图4中，Vdd2维持上电状态(正值)，PD信号处于低电平状态表示PD信号未激活，PD信号处于高电平状态表示PD信号激活，Vdd1处于低电平状态表示第一电源2掉电，即第一电源域3关断，Vdd1处于高电平状态表示第一电源2上电，即第一电源域3开启。
可以理解的是，随着PMU1的控制，电源域(例如，图2所示的第一电源域3或第二电源域5)会在开启(on)状态和关断(off)状态之间变化；而多个电源域之间一般存在时序依赖性，如果在PMU1关断电源域时，不考虑电源域的时序依赖性，那么极易导致芯片电路的不稳定。
基于此，为降低关断电源域时芯片电路的不稳定性，本公开实施例提供一种改进的芯片及相适应的关断电源域的方案；可选的，本公开实施例提供的芯 片可以如图5所示，参照图5，该芯片可以包括：PMU1、第一电源2、第一电源域3、第二电源4、第二电源域5和设置于第二电源域5内的隔离单元6，第一电源2连接的第一电源域3，第一电源2为第一电源域3供电；第二电源3连接的第二电源域4，所述第二电源3为第二电源域5供电。隔离单元6用于在第一电源域3关断前，隔离第一电源域3和第二电源域5。
例如，PMU1用于获取第一电源域和第二电源域之间的时序依赖性。时序依赖性基于下面将要描述的芯片设计方法而确定。
时序依赖性表示在当前电源状态下，第二电源域5在时序上依赖于第一电源域3；可选的，隔离单元6可以是电门(例如与非门等逻辑门)。
可选的，为实现在关断第一电源域3时，降低芯片电路的不稳定性，在关断第一电源域3前，本公开实施例可先通过第二电源域5内的隔离单元6隔离第一电源域3和第二电源域5，例如，将第一电源域3和第二电源域5之间连接的控制线进行隔离，进而再关断第一电源域3，使得第一电源域3关断后，降低依赖于第一电源域3的第二电源域5的不稳定性，从而实现在关断第一电源域3时，降低芯片电路不稳定性的目的。
例如，设置于第二电源域5的隔离单元6的第一输入端可连接第一电源域3和第二电源域5间的控制线，该控制线可以是第一电源域3跨越到第二电源域5的域跨越线(Domain Crossing)，隔离单元6的第二输入端连接PMU1，隔离单元6的第二输入端可检测隔离信号，即接收隔离信号，隔离单元6的输出端可连接至第二电源域5，且隔离单元6的输出端可输出信号b；本公开实施例可设置：PMU1基于时序依赖性，在向第一电源2发出PD信号前，可先向设置于第二电源域5内的隔离单元6发出隔离信号，从而隔离单元6可将第一电源域3和第二电源域5之间连接的控制线进行隔离，实现隔离第一电源域3和第二电源域5，进而PMU1再向第一电源2发出PD信号，实现关断第一电源域3。
示例的，图6示出了本公开实施例关断第一电源域的过程中的信号变化示意，可以看出，隔离信号先于PD信号起作用，即先将第一电源域3和第二电源域5之间连接的控制线进行隔离后，PD信号再激活，虽然第一电源2掉电后(即Vdd1处于低电平状态后)，信号a变得unknown(未知)，也就是说，信号a可能导致第二电源域5不稳定，但由于第一电源域3和第二电源域5已事先进行了隔离，因此信号a的unknown状态对第二电源域5的影响将变小， 从而可降低依赖于第一电源域3的第二电源域5的不稳定性，实现在关断第一电源域3时，降低芯片电路不稳定性的目的。
可以看出，本公开实施例实现关断电源域的核心思路为：当需要关断第二电源域5所依赖的第一电源域3时，本公开实施例可通过第二电源域5的隔离单元先隔离第一电源域3和第二电源域5，然后再关断第二电源域5所依赖的第一电源域3，从而在关断第一电源域3时，降低芯片电路的不稳定性；例如，第一电源域3和第二电源域5为芯片内任意两个在时序上相依赖的电源域，且第二电源域5依赖于第一电源域3。
实现本公开实施例提供的关断电源域的方案，需要确定电源域之间的时序依赖性，即PMU1关断电源域供电的电源控制信号存在一些时序要求，PMU在关断电源域时，需基于电源域之间的时序依赖性，实现本公开实施例提供的关断电源域的方案；然而，在芯片设计过程中，时序依赖性的分析一般在芯片的门级阶段，如通过使用SDF(Standard Delay format，标准延迟格式)门级仿真确定电源域间的时序依赖性；但是，门级阶段的电路规模无疑非常复杂和庞大，使用SDF门级仿真来确定电源域间的时序依赖性无疑极为复杂。
可选的，主流的芯片设计主要分为规范、算法级描述、RTL级(register transfer level，寄存器传输级)描述、门级网表、版图等设计过程，其中RTL级和门级设计是芯片设计的两个关键阶段：RTL级使用硬件描述语言(例如Verilog或VHDL)描述芯片功能，RTL级经过逻辑综合后得到门级(例如门级网表Netlist)，门级则使用具体的逻辑单元(依赖单元库)来实现芯片功能，此时，门级引入时序关系(包括本公开实施例所指的电源域之间的时序依赖性)。
相应的，RTL级仿真和门级仿真分别是针对RTL级和门级的仿真验证阶段；RTL级仿真是对硬件描述语言描述的芯片功能的语法和基本功能进行验证(不含时序信息)；门级仿真则主要针对逻辑综合后的门级的时序进行仿真验证；可见，在门级仿真虽然可以实现时序验证，但门级是使用具体的逻辑单元来表现，其电路规模非常复杂和庞大，因此使用SDF门级仿真来分析电源域之间的时序依赖性无疑极为的复杂。
基于此，为适应本公开实施例提供的关断电源域的方案，本公开实施例提供一种新型的芯片设计方法，以较为简便的方式确定电源域间的时序依赖性，从而使得PMU可根据电源域间的时序依赖性，实现本公开实施例提供的关断电源域的方案，进而在设计的芯片需要关断电源域时，为保障电路的稳定性提 供了可能。
作为本公开实施例公开内容的一种可选实现，图7示出了本公开实施例提供的芯片设计方法的一种可选流程，该芯片设计方法可应用在芯片设计的RTL验证阶段；
可选的，本公开实施例可在芯片设计工具(例如EDA)中配置实现本公开实施例提供的芯片设计方法的tool(工具)，从而可由该tool执行实现本公开实施例提供的芯片设计方法；参照图7，该芯片设计方法可以包括：
步骤S100、确定芯片的至少一种电源状态，其中，至少一种电源状态中的一种电源状态包括芯片上的各电源域在一种芯片工作模式下的开关状态。
例如，至少一种电源状态包括第一电源状态。
可选的，芯片可以具有多种芯片工作模式，例如power off(电源关闭)、standby(待机)、sleep(休眠)等，当然芯片还可以具有其他未示出的芯片工作模式，此处不再展开说明；在不同的芯片工作模式下，芯片上的各电源域的开关状态也是不同的，例如，在power off的芯片工作模式下，大部分电源域对应的电源掉电，因此大部分电源域是关断状态，在standby的芯片工作模式下，部分电源域对应的电源上电，部分电源域的电源掉电，因此部分电源域是开启状态，部分电源域是关断状态。
示例的，以PDA(Power Domain A)包括Host Interface与CGC模块，PDB(Power Domain B)包括Processor与Baseband Subsystem模块，PDC(Power Domain C)包括RF subsystem模块为例，图8示例性的示出了各电源状态的示例图，各电源状态可以表示各芯片工作模式下电源域的开关状态。
可以看出，在power off的芯片工作模式下，各电源域的开关状态可构成电源状态(power state)：on、off、off；在standby的芯片工作模式下，各电源域的开关状态可构成电源状态：on、off、off；也就是说，对于任一芯片工作模式，各电源域在该芯片工作模式下的开关状态的集合，可作为该芯片工作模式下的电源状态；即，所分析的一种电源状态包括各电源域在一种芯片工作模式下的开关状态。
可选的，本公开实施例可分别确定各芯片工作模式下各电源域的开关状态，从而分别在各芯片工作模式下，集合各电源域的开关状态，得到芯片的至少一种电源状态。
可选的，电源域在任一芯片工作模式下的开关状态可由UPF(United Power  Format，统一电源格式)文件描述，本公开实施例可根据UPF文件确定各芯片工作模式下各电源域的开关状态。
UPF文件是IEEEl801标准中被广泛使用的用于低功耗设计和验证的一种标准功耗格式文件，UPF文件由一组类似于Tool Command Language(工具命令语言)的命令组成，用于描述芯片设计中的低功耗意图。
示例的，可通过分析UPF文件的PST(Power State Table，电源状态表)描述的各个电源域在各芯片工作模式下的开关状态，从而得到芯片的至少一种电源状态。
步骤S110、确定在芯片的电源状态切换到第一电源状态时，各电源域中的变化电源域发送控制信号。
例如，变化电源域可以为芯片上的部分电源域，即各电源域包括变化电源域。在芯片的电源状态切换到第一电源状态时，变化电源域的开关状态发生变化。
确定芯片的至少一种电源状态后，在本公开实施例中，芯片可在不同的电源状态之间发生切换时，并在切换过程中，确定开关状态变化的电源域，即变化电源域，并分析出对开关状态变化的电源域发送的控制信号，所确定的控制信号可以是多个；可选的，可设第一电源状态和第二电源状态为芯片的电源状态中的两个电源状态，即至少一种电源状态还包括第二电源状态，在第二电源状态切换到第一电源状态时，本公开实施例可确定在从第二电源状态切换到第一电源状态时，开关状态变化的电源域，并确定开关状态变化的电源域发送的控制信号。
例如，在从芯片工作模式standby对应的电源状态切换到芯片工作模式sleep对应的电源状态时，可分析从standby对应的电源状态切换到sleep对应的电源状态时，开关状态变化的电源域，并分析出开关状态变化的电源域发送的控制信号。
可选的，步骤S110所指的电源状态切换应是合法的电源状态切换，即在芯片设计时，允许的电源状态切换。
例如，在一些示例中，至少一种电源状态还包括第二电源状态。步骤S110包括：确定在第二电源状态时各电源域的开关状态；确定在第一电源状态时各电源域的开关状态；根据在第二电源状态时各电源域的开关状态和在第一电源状态时各电源域的开关状态，确定在芯片的电源状态从第二电源状态切换到第 一电源状态时的变化电源域；确定变化电源域发送的控制信号。
例如，当某电源域在第二电源状态中的开关状态(例如，开启状态)与该电源域在第一电源状态中的开关状态(例如，关断状态)不相同，则该电源域为变化电源域。
步骤S120、对各控制信号间的时序依赖进行分析，确定各控制信号所作用的电源域之间在第一电源状态(即切换到的电源状态)下的时序依赖性。
可选的，本公开实施例可使用静态时序分析(Timing Analysis,STA)方法，对各控制信号间的时序依赖进行分析，确定出各控制信号所作用的电源域之间在切换到的电源状态下的时序依赖性。需要说明的是，在本公开的实施例中，每个控制信号所作用的电源域包括发送该控制信号的电源域和该控制信号跨越到的电源域。
本公开实施例可在芯片设计的RTL验证阶段，确定芯片的至少一种电源状态，其中，至少一种电源状态中的一种电源状态包括各电源域在一种芯片工作模式下的开关状态；从而确定在电源状态切换时，开关状态变化的电源域(即变化电源域)发送的控制信号；进而，对各控制信号间的时序依赖进行分析，确定各控制信号所作用的电源域之间在切换到的电源状态下的时序依赖性，实现在各电源状态下，确定电源域间的时序依赖性。在芯片设计的RTL验证阶段，本公开实施例可在电源状态切换时，分析开关状态变化的电源域发送的控制信号间的时序依赖，从而在切换到的电源状态下，确定电源域之间的时序依赖性，实现电源域的时序依赖性的确定；并且本公开实施例是在RTL验证阶段，实现分析确定电源域的时序依赖性，而不必在芯片设计的门级阶段实现，因此本公开实施例可相对较为简便的实现电源域的时序依赖性的分析确定。
作为一种可选实现，图9示出了图7所示流程中步骤S120的一种可选实现方法流程，参照图9，该流程可以包括：
步骤S200、确定控制信号相应的域跨越线。
在本公开实施例中，Domain Crossing为电源域之间的域跨越线，指示的是控制信号从一个电源域跨越到另一个电源域的控制线；示例的，如图5所示，第一电源域和第二电源域之间的连线可以认为是域跨越线。
作为一种可选实现，本公开实施例可在确定控制信号后，确定发送控制信号的电源域至该控制信号跨越到的电源域之间的域跨越线。
步骤S210、确定域跨越线所对应的电源控制线。
在分析域跨越线后，本公开实施例可结合Power State Table(电源状态表)与PMU的模式(model)信息，确定出域跨越线所对应的电源控制线，域跨越线所对应的电源控制线可以认为是，域跨越线所连接的输出控制信号的power domain的电源控制线。
步骤S220、通过电源控制线，回溯电源控制线相应的电源。
通过PMU的模式信息，本公开实施例可确定出电源控制线相应的电源。
步骤S230、根据所述电源的特性，确定电源的供电关系；所述供电关系包括：电源所供电的电源域，以及电源所供电的电源域的所有域跨越线连接方式。
步骤S240、根据所述电源的供电关系，确定电源所供电的电源域的域跨越线是否受电源的开关状态影响，若是，执行步骤S250，若否，执行步骤S260。
可选的，电源的开关状态包括电源上电状态和电源掉电状态。电源所供电的电源域的域跨越线受电源的开关状态影响，说明电源在上电状态和掉电状态之间变化时，电源所供电的电源域的域跨越线相应的控制信号将发生变化。
步骤S250、确定受电源的开关状态影响的域跨越线所连接的电源域在第一电源状态下存在时序依赖性。
可选的，域跨越线所连接的电源域包括域跨越线的输入端连接的电源域和域跨越线的输出端连接的电源域，受电源的开关状态影响的域跨越线所连接的电源域中，控制信号从域跨越线的输入端连接的电源域跨越到域跨越线的输出端连接的电源域。
进一步，当确定域跨越线受电源的开关状态影响，则本公开实施例可在域跨越线的输出端连接的电源域中设置隔离单元，该隔离单元可在域跨越线的输入端连接的电源域关断前，隔离域跨越线的输入端连接的电源域和域跨越线的输出端连接的电源域，以实现本公开实施例提供的关断电源域的方案；可选的，以受电源的开关状态影响的域跨越线所连接的电源域为第一电源域和第二电源域，且第二电源域依赖于第一电源域为例(即域跨越线的输入端连接的电源域为第一电源域，域跨越线的输出端连接的电源域为第二电源域)，则当需要关断第二电源域所依赖的第一电源域时，本公开实施例可通过第二电源域的隔离单元先隔离第一电源域和第二电源域，然后再关断第二电源域所依赖的第一电源域，从而在关断第一电源域时，降低芯片电路的不稳定性。
步骤S260、确定未受电源的开关状态影响的域跨越线所连接的电源域在第一电源状态下不存在时序依赖性。
可选的，在本公开实施例中，UPF文件描述的芯片设计的功耗意图可以涵盖PMU管理的供电网络、隔离单元、电源开关单元等方面。UPF文件可以指定如何建立供电网络、各个电源线之间的行为、以及用来支持设计动态电源域关断的额外的逻辑功能等。
可选的，在本公开实施例中，UPF文件可对电源域进行定义；UPF文件可根据电源分布，准确地描述各个电源域的电源网络(Power Network)，详细的定义每个电源域的电源线名称以及与芯片原始电源输入端口的连接关系等；在有电源域关断的设计中，UPF可定义电源域关断单元(Power Gating cell)，描述电源域关断单元的电源域输入、输出以及控制信号的连接关系，电源域关断单元可以在芯片设计的物理实现阶段插入。
上文描述了本公开实施例提供的多个实施例方案，各实施例方案介绍的各可选方式可在不冲突的情况下相互结合、交叉引用，从而延伸出多种可能的实施例方案，这些均可认为是本公开实施例披露、公开的实施例方案。
下面对本公开实施例提供的芯片设计装置进行介绍，下文描述的芯片设计装置可以认为是芯片设计工具(如EDA)为实现本公开实施例提供的芯片设计方法所需设置的功能模块。下文描述的芯片设计装置的内容，可与上文描述的芯片设计方法的内容，相互对应参照。
图10为本公开实施例提供的芯片设计装置的框图，参照图10，该芯片设计装置可以包括：
电源状态确定电路100，用于确定芯片的至少一种电源状态，其中，至少一种电源状态中的一种电源状态包括芯片上的各电源域在一种芯片工作模式下的开关状态，至少一种电源状态包括第一电源状态。
控制信号确定电路110，用于确定在芯片的电源状态切换到第一电源状态时，各电源域中的变化电源域发送的控制信号，其中，在芯片的电源状态切换到第一电源状态时，变化电源域的开关状态发生变化。
分析电路120，用于对各控制信号间的时序依赖进行分析，确定各控制信号所作用的电源域之间在第一电源状态(即切换到的电源状态)下的时序依赖性。
可选的，执行确定芯片的至少一种电源状态的操作时，电源状态确定电路100具体用于：分析UPF文件的PST，确定芯片的至少一种电源状态；所述PST描述有芯片上的各个电源域在各芯片工作模式下的开关状态。
可选的，执行对控制信号间的时序依赖进行分析，确定控制信号所作用的电源域之间在第一电源状态下的所述时序依赖性的操作时，分析电路120具体用于：
确定所述控制信号相应的域跨越线；
确定所述域跨越线所对应的电源控制线；
通过所述电源控制线，回溯所述电源控制线相应的电源；
根据所述电源的特性，确定所述电源的供电关系，其中，所述供电关系包括：电源所供电的电源域，以及电源所供电的电源域的域跨越线连接方式；
根据所述电源的供电关系，确定所述电源所供电的电源域的域跨越线是否受所述电源的开关状态影响；
确定受电源的开关状态影响的域跨越线所连接的电源域在第一电源状态下存在时序依赖性。
可选的，执行对控制信号间的时序依赖进行分析，确定控制信号所作用的电源域之间在第一电源状态下的所述时序依赖性的操作时，分析电路120还可用于：
确定未受电源的开关状态影响的域跨越线所连接的电源域在第一电源状态下不存在时序依赖性。
可选的，执行确定所述域跨越线所对应的电源控制线的操作时，分析电路120具体用于：
根据电源状态表与PMU的模式信息，确定所述域跨越线所对应的电源控制线。
可选的，执行通过所述电源控制线，回溯所述电源控制线相应的电源的操作时，分析电路120具体用于：
通过所述PMU的模式信息，确定电源控制线相应的电源。
可选的，图11示出了本公开实施例提供的芯片设计装置的另一框图，结合图10和图11所示，该芯片设计装置还可以包括：
隔离设计电路130，用于若域跨越线受电源的开关状态影响，在域跨越线的输出端连接的电源域中设计隔离单元；所述隔离单元用于在域跨越线的输入端连接的电源域关断前，隔离域跨越线的输入端连接的电源域和域跨越线的输出端连接的电源域。
可选的，在一种可选实现中，上述芯片设计装置可以是芯片设计工具(如 EDA)中的程序模块。
本公开实施例还提供一种电子设备，电子设备可以包括上述图5所示的芯片。也就是说，电子设备可以包括芯片，且该芯片包括：电源管理单元，用于获取第一电源域和第二电源域之间的时序依赖性；与电源管理单元连接的第一电源和第二电源；与第一电源连接的第一电源域，第一电源为所述第一电源域供电；与第二电源连接的第二电源域，第二电源为第二电源域供电，其中，时序依赖性表示在当前电源状态下，第二电源域在时序上依赖于第一电源域；第二电源域包括隔离单元，隔离单元用于在第一电源域关断前，隔离第一电源域和第二电源域。
例如，隔离单元的第一输入端连接第一电源域和第二电源域间的控制线，控制线为第一电源域跨越到第二电源域的域跨越线；隔离单元的第二输入端连接电源管理单元。
例如，电源管理单元用于基于时序依赖性，在向第一电源发送掉电信号以使第一电源域关断前，向隔离单元发送隔离信号，以使隔离单元将第一电源域和第二电源域间的控制线进行隔离；及在第一电源域和第二电源域间的控制线隔离后，向第一电源发送掉电信号，以使第一电源域关断。
该电子设备可以是终端设备，也可以是服务器设备，该电子设备可以包括本公开实施例所述的芯片。
虽然本公开实施例披露如上，但本公开并非限定于此。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各种更动与修改，因此本公开的保护范围应当以权利要求所限定的范围为准。

Claims (15)

  1. 一种芯片设计方法，应用于芯片的寄存器转换级验证阶段，其中，所述芯片设计方法包括：
    确定芯片的至少一种电源状态，其中，所述至少一种电源状态中的一种电源状态包括所述芯片上的各电源域在一种芯片工作模式下的开关状态，所述至少一种电源状态包括第一电源状态；
    确定在所述芯片的电源状态切换到所述第一电源状态时，所述各电源域中的变化电源域发送的控制信号，其中，在所述芯片的电源状态切换到所述第一电源状态时，所述变化电源域的开关状态发生变化；
    对所述控制信号间的时序依赖进行分析，确定所述控制信号所作用的电源域之间在所述第一电源状态下的时序依赖性。
  2. 根据权利要求1所述的芯片设计方法，其中，确定所述芯片的所述至少一种电源状态包括：
    分析统一电源格式文件的电源状态表，确定所述芯片的所述至少一种电源状态，
    其中，所述电源状态表描述有所述芯片上的各电源域在各芯片工作模式下的开关状态。
  3. 根据权利要求2所述的芯片设计方法，其中，对所述控制信号间的时序依赖进行分析，确定所述控制信号所作用的电源域之间在所述第一电源状态下的所述时序依赖性包括：
    确定所述控制信号相应的电源；
    根据所述电源的特性，确定所述电源的供电关系，其中，所述供电关系包括：所述电源所供电的电源域，以及所述电源所供电的所述电源域的域跨越线连接方式；
    根据所述电源的供电关系，确定所述电源所供电的所述电源域的所述域跨越线是否受所述电源的开关状态影响；
    确定受所述电源的开关状态影响的域跨越线所连接的电源域在所述第一电源状态下存在时序依赖性。
  4. 根据权利要求3所述的芯片设计方法，还包括：
    确定未受所述电源的开关状态影响的域跨越线所连接的电源域在所述第 一电源状态下不存在时序依赖性。
  5. 根据权利要求3所述的芯片设计方法，其中，确定所述控制信号相应的所述电源包括：
    确定所述控制信号相应的所述域跨越线；
    确定所述域跨越线所对应的电源控制线；
    通过所述电源控制线，回溯所述电源控制线相应的所述电源。
  6. 根据权利要求5所述的芯片设计方法，其中，确定所述域跨越线所对应的所述电源控制线包括：
    根据所述电源状态表与电源管理单元的模式信息，确定所述域跨越线所对应的所述电源控制线；
    通过所述电源控制线，回溯所述电源控制线相应的所述电源包括：
    通过所述电源管理单元的模式信息，确定所述电源控制线相应的所述电源。
  7. 根据权利要求3所述的芯片设计方法，还包括：
    确定所述域跨越线受所述电源的开关状态影响，在所述域跨越线的输出端连接的电源域中设计隔离单元；其中，所述隔离单元用于在所述域跨越线的输入端连接的电源域关断前，隔离所述域跨越线的输入端连接的所述电源域和所述域跨越线的输出端连接的所述电源域。
  8. 根据权利要求1所述的芯片设计方法，其中，所述至少一种电源状态还包括第二电源状态；
    确定在所述芯片的电源状态切换到所述第一电源状态时，所述各电源域中的变化电源域发送的控制信号包括：
    确定在所述第二电源状态时所述各电源域的开关状态；
    确定在所述第一电源状态时所述各电源域的开关状态；
    根据在所述第二电源状态时所述各电源域的开关状态和在所述第一电源状态时所述各电源域的开关状态，确定在所述芯片的电源状态从所述第二电源状态切换到所述第一电源状态时的所述变化电源域；
    确定所述变化电源域发送的所述控制信号。
  9. 一种芯片设计装置，包括：
    电源状态确定电路，用于确定芯片的至少一种电源状态，其中，所述至少一种电源状态中的一种电源状态包括所述芯片上的各电源域在一种芯片工作模式下的开关状态，所述至少一种电源状态包括第一电源状态；
    控制信号确定电路，用于确定在所述芯片的电源状态切换到所述第一电源状态时，所述各电源域中的变化电源域发送的控制信号，其中，在所述芯片的电源状态切换到所述第一电源状态时，所述变化电源域的开关状态发生变化；
    分析电路，用于对所述控制信号间的时序依赖进行分析，确定所述控制信号所作用的电源域之间在所述第一电源状态下的时序依赖性。
  10. 一种芯片，包括：
    电源管理单元，用于获取所述第一电源域和所述第二电源域之间的时序依赖性；
    与所述电源管理单元连接的第一电源和第二电源；
    与所述第一电源连接的所述第一电源域，所述第一电源为所述第一电源域供电；
    与所述第二电源连接的所述第二电源域，所述第二电源为所述第二电源域供电，其中，所述时序依赖性表示在当前电源状态下，所述第二电源域在时序上依赖于所述第一电源域；
    所述第二电源域包括隔离单元，所述隔离单元用于在所述第一电源域关断前，隔离所述第一电源域和所述第二电源域。
  11. 根据权利要求10所述的芯片，其中，所述隔离单元的第一输入端连接所述第一电源域和所述第二电源域间的控制线，所述控制线为所述第一电源域跨越到所述第二电源域的域跨越线；所述隔离单元的第二输入端连接所述电源管理单元。
  12. 根据权利要求11所述的芯片，其中，所述电源管理单元用于基于所述时序依赖性，在向所述第一电源发送掉电信号以使所述第一电源域关断前，向所述隔离单元发送隔离信号，以使所述隔离单元将所述第一电源域和所述第二电源域间的所述控制线进行隔离；及在所述第一电源域和所述第二电源域间的所述控制线隔离后，向所述第一电源发送掉电信号，以使所述第一电源域关断。
  13. 一种电子设备，包括权利要求10所述的芯片。
  14. 根据权利要求13所述的电子设备，其中，所述隔离单元的第一输入端连接所述第一电源域和所述第二电源域间的控制线，所述控制线为所述第一电源域跨越到所述第二电源域的域跨越线；所述隔离单元的第二输入端连接所述电源管理单元。
  15. 根据权利要求14所述的电子设备，其中，所述电源管理单元用于基于 所述时序依赖性，在向所述第一电源发送掉电信号以使所述第一电源域关断前，向所述隔离单元发送隔离信号，以使所述隔离单元将所述第一电源域和所述第二电源域间的所述控制线进行隔离；及在所述第一电源域和所述第二电源域间的所述控制线隔离后，向所述第一电源发送掉电信号，以使所述第一电源域关断。
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