WO2021131192A1 - Wiring structure - Google Patents

Wiring structure Download PDF

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Publication number
WO2021131192A1
WO2021131192A1 PCT/JP2020/036178 JP2020036178W WO2021131192A1 WO 2021131192 A1 WO2021131192 A1 WO 2021131192A1 JP 2020036178 W JP2020036178 W JP 2020036178W WO 2021131192 A1 WO2021131192 A1 WO 2021131192A1
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WO
WIPO (PCT)
Prior art keywords
pad
region
trench
wiring structure
signal line
Prior art date
Application number
PCT/JP2020/036178
Other languages
French (fr)
Japanese (ja)
Inventor
正人 石▲崎▼
久保 昇
Original Assignee
Ngkエレクトロデバイス株式会社
日本碍子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ngkエレクトロデバイス株式会社, 日本碍子株式会社 filed Critical Ngkエレクトロデバイス株式会社
Priority to JP2021566821A priority Critical patent/JP7223170B2/en
Priority to CN202080065866.4A priority patent/CN114424678B/en
Publication of WO2021131192A1 publication Critical patent/WO2021131192A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/025Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/0245Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09036Recesses or grooves in insulating substrate

Definitions

  • the present invention relates to a wiring structure, and more particularly to a wiring structure to be mounted on a circuit board using a ball grid array (BGA).
  • BGA ball grid array
  • BGA technology is one of the technologies for mounting wiring structures such as packages for electronic components. According to this technique, spherical conductive balls arranged in a grid pattern, typically solder balls, are used.
  • Patent Document 1 discloses a multilayer dielectric substrate connected by BGA technology. The multilayer dielectric substrate has a pad for mounting solder balls and a columnar conductor connected to the pad and passing through the multilayer dielectric substrate.
  • the wiring structure is mainly made of ceramics and the circuit board is mainly made of resin
  • the difference in the coefficient of thermal expansion between the two is large, so that it is highly necessary to relax the thermal stress. Therefore, there is a limit to the miniaturization of the conductive ball as compared with the miniaturization in the wiring structure. Therefore, as the density increases, the size of the conductive ball tends to be relatively large compared to the cross section of the signal line in the wiring structure. Therefore, the distance between the conductive balls tends to be narrower than the distance between the signal line in the wiring structure and the signal line or the grounding portion adjacent to the signal line.
  • the wiring structure and the characteristic impedance of the circuit board on which it is mounted are usually almost the same.
  • the characteristic impedance at the BGA junction composed of the conductive balls is higher than the characteristic impedance of the wiring structure and the circuit board. It will decrease locally. This local drop causes a mismatch in the characteristic impedance.
  • the mismatch of the characteristic impedance adversely affects the transmission characteristics as the signal frequency becomes higher.
  • the present invention has been made to solve the above problems, and an object of the present invention is to provide a wiring structure capable of obtaining good high frequency transmission characteristics while maintaining mounting reliability.
  • the wiring structure of one embodiment is to be mounted on a circuit board using a ball grid array.
  • the wiring structure includes a substrate, a first differential line, a second differential line, a grounding area, a first pad, a second pad, a third pad, and a fourth pad.
  • the substrate is made of a dielectric and has a facing surface that faces the circuit board.
  • the first differential line is provided in the substrate, reaches the facing surface, and has a first signal line and a second signal line.
  • the second differential line is provided in the substrate, reaches the facing surface, and has a third signal line and a fourth signal line.
  • the grounding region is provided on the facing surface, and a grounding potential is applied.
  • the first pad is provided on the facing surface and is connected to the first signal line.
  • the second pad is provided on the facing surface and is connected to the second signal line.
  • the third pad is provided on the facing surface, is adjacent to the second pad via the grounding region, and is connected to the third signal line.
  • the fourth pad is provided on the facing surface and is connected to the fourth signal line.
  • the ground contact area includes an intervening portion between the second pad and the third pad, and a non-intervening portion deviating from the intervening portion.
  • the facing surfaces of the substrate are the first region between the first pad and the second pad, the second region between the second pad and the intervening portion, and each of the first pad and the second pad and the non-intervening portion. Includes a third region between and.
  • the facing surface of the substrate has a trench in at least one of a first region, a second region, and a third region.
  • the characteristic impedance of the wiring increases near the trench.
  • TDR Time Domain Reflectometry
  • FIG. 1 is a cross-sectional view schematically showing the configuration of the electronic device 900 according to the first embodiment.
  • the electronic device 900 includes a package 100 (wiring structure), a BGA 90, a printed circuit board 200 (circuit board), an electronic component 300, an optical fiber 310, and a lid 400.
  • the BGA 90 is for an electrical and mechanical connection between the package 100 and the printed circuit board 200 and includes solder balls 91 (conductive balls) arranged in a grid pattern.
  • the package 100 will be mounted on the printed circuit board 200 using the BGA 90.
  • the package 100 has a substrate made of a dielectric (details will be described later), and this substrate has a bottom portion 101 and a frame portion 102.
  • the bottom 101 has a mounting surface SM on which the electronic component 300 will be mounted.
  • the frame portion 102 surrounds the space CV on the mounting surface SM.
  • the frame portion 102 has a through hole portion 110 for passing the optical fiber 310.
  • a light transmitting portion may be provided instead of the through hole portion 110.
  • the translucent portion is a window portion made of a translucent material.
  • the electronic component 300 includes an integrated circuit (IC) 301 and an optical component 302 that are electrically connected to each other.
  • the operating frequency of the IC 301 may be a high frequency, for example 55 GHz or higher.
  • the optical component 302 is, for example, a photodiode.
  • the optical fiber 310 is connected to the optical component 302 and extends out of the space CV through the through hole 110.
  • FIG. 2 is a circuit diagram of a partial configuration of the package 100 (FIG. 1).
  • FIG. 3 is a partial cross-sectional view corresponding to the broken line portion III-III (FIG. 1).
  • FIG. 4 is a partial plan view schematically showing the configuration of the package 100.
  • Package 100 has a substrate 80 made of a dielectric material.
  • the substrate 80 is made of a dielectric, for example ceramics.
  • the substrate 80 has a mounting surface SM and a facing surface SP.
  • the facing surface SP faces the printed circuit board 200 via the BGA 90 when the package 100 is mounted on the printed circuit board 200.
  • the electronic component 300 (FIG. 1) will be mounted on the mounting surface SM.
  • the package 100 has a differential line 131 (first differential line), a differential line 132 (second differential line), and a grounding portion 10 in the substrate 80, and these have a facing surface SP and a grounding portion 10. It has reached each of the mounting surfaces SM.
  • the grounding portion 10 is for the electric shield of each of the differential line 131 and the differential line 132, and a ground potential (reference potential) is applied. The ground potential may be applied when the electronic device 900 is used.
  • the differential line 131 has a signal line 11 (first signal line) and a signal line 12 (second signal line), and the differential line 132 has a signal line 13 (third signal line) and a signal line 14. It has (4th signal line).
  • the package 100 has a ground contact area 20, a pad 21 (first pad), a pad 22 (second pad), a pad 23 (third pad), and a pad 24 (fourth pad) on the facing surface SP of the substrate 80. ), Which are connected to the grounding portion 10, the signal line 11, the signal line 12, the signal line 13, and the signal line 14, respectively.
  • the pad 23 is adjacent to the pad 22 via the ground contact area 20.
  • a ground potential is applied to the ground region 20.
  • the ground contact area 20 includes an intervening portion 20i between the pad 22 and the pad 23, and a non-intervening portion 20n separated from the intervening portion.
  • the facing surface SP of the substrate 80 has a region R1 (first region) between the pad 21 and the pad 22 and a region R2 (first region) between the pad 22 and the intervening portion 20i. 2 regions) and a region R3 (third region) between each of the pads 21 and 22 and the non-intervening portion 20n.
  • the facing surface SP of the substrate 80 has a trench TR in at least one of the region R1, the region R2, and the region R3.
  • the trench TR may be located at least in region R1. Further, the trench TR may be located at least in the region R2.
  • the trench TR is located at least in regions R1 and R2. More preferably, as shown in FIG. 4, the trench TR is located at least in region R1, region R2 and region R3.
  • the portion of the trench TR adjacent to the pad 21 and the pad 22 is perpendicular to the edge ED and with respect to a virtual line passing through the midpoint between the pad 21 and the pad 22. It has line symmetry. More preferably, the portion of the trench TR adjacent to the pads 21 to 24 is perpendicular to the edge ED and has line symmetry with respect to the virtual line passing through the midpoint between the pad 22 and the pad 23.
  • the trench TR preferably has a depth of 100 ⁇ m or more and 300 ⁇ m or less.
  • the dielectric constant of the space in the trench TR is lower than the dielectric constant of the substrate 80, typically about 1.
  • the trench TR is filled with gas or is evacuated.
  • the trench TR does not have to reach the edge ED of the facing surface SP as shown in FIG. In that case, in the production of the substrate 80, it becomes easy to apply the construction method using a green sheet having punch holes corresponding to the trench TR. If the trench TR reaches the edge ED, the portion of the green sheet corresponding to the pad 21 is separated from the other surrounding portions, making it difficult to handle a single green sheet before laminating. When the trench is formed by, for example, laser processing after laminating the green sheet, the above problem does not occur even if the trench reaches the edge ED.
  • each of the pad 21, the pad 22, the pad 23 and the pad 24 is adjacent to the edge ED on the facing surface SP.
  • the fact that a certain pad is adjacent to the edge ED means that there is no other pad between the pad and the edge ED, as shown in FIG.
  • each of the pad 21, the pad 22, the pad 23, and the pad 24 is arranged on the outer periphery of the facing surface SP among the pads arranged in a grid pattern on the facing surface SP corresponding to the BGA 90. is there.
  • the pads 21, pads 22, pads 23 and pads 24 are the pads closest to the edge ED of all the pads on the facing surface SP.
  • the package 100 has a connection end 30, a connection end 31, a connection end 32, a connection end 33, and a connection end 34 on the mounting surface SM of the substrate 80. These may be connected to the grounding portion 10, the signal line 11, the signal line 12, the signal line 13, and the signal line 14, respectively.
  • the connection end 30, the connection end 31, the connection end 32, the connection end 33, and the connection end 34 are used for electrical connection of the package 100 to the electronic component 300 (FIG. 1).
  • the printed circuit board 200 (FIG. 3) has a substrate 280 and a circuit pattern.
  • the substrate 280 may be made of resin.
  • the printed circuit board 200 may be a resin substrate.
  • the circuit pattern includes, for example, a circuit pattern 220, a circuit pattern 221 and a circuit pattern 230, and a circuit pattern 231.
  • the printed circuit board 200 may have a via electrode 210 that connects the circuit pattern 220 and the circuit pattern 230 in the thickness direction, and a via electrode 211 that connects the circuit pattern 221 and the circuit pattern 231 in the thickness direction.
  • the solder balls 91 constituting the BGA 90 are arranged on each of the pad 21, the pad 22, the pad 23, the pad 24, and the ground contact area 20. Has been done. Therefore, when the electronic device 900 is manufactured, a package 100 in which the solder balls 91 constituting the BGA 90 are mounted is prepared on each of the pad 21, the pad 22, the pad 23, the pad 24, and the ground contact area 20. Ru. Then, the package 100 is mounted on the printed circuit board 200 using the BGA 90. For example, in the field of view shown in FIG. 3, the grounding region 20 and the circuit pattern 220 and the pad 21 and the circuit pattern 221 are joined by the solder balls 91.
  • the solder ball 91 is deformed at the time when it is mounted on the pad 21, the pad 22, the pad 23, the pad 24, the ground contact area 20, etc., and then when it is sandwiched between the package 100 and the printed circuit board 200. receive. As shown in FIG. 3, the solder ball 91 has a shape deformed from a spherical shape due to this deformation.
  • the trench TR preferably has a depth of 1/3 or more of the ball diameter and less than or equal to the ball diameter.
  • the ball diameter is preferably larger than 200 ⁇ m from the viewpoint of mounting reliability, and preferably smaller than 400 ⁇ m from the viewpoint of high density, for example, about 300 ⁇ m.
  • the distance between the centers of the adjacent solder balls 91 is, for example, about 500 ⁇ m.
  • the gap between adjacent solder balls (horizontal gap in FIG. 3) is usually smaller than the gap between adjacent pads (gap between pads 20 and 21 in FIG. 3), and the balls as described above.
  • the diameter is 300 ⁇ m and the center-to-center distance is 500 ⁇ m, it is less than 200 ⁇ m.
  • the characteristic impedance of the wiring increases in the vicinity of the trench TR.
  • the distance between the solder ball 91 and the trench TR is preferably small, and this distance is, for example, less than or equal to the ball diameter.
  • the trench TR may be located at least in the area R1 (FIG. 4).
  • the capacitive coupling between the wiring including the signal line 11 and the pad 21 and the wiring including the signal line 12 and the pad 22 becomes small. Therefore, the characteristic impedance of both wirings increases in the vicinity of the trench TR. Therefore, it is possible to suppress an adverse effect due to a local decrease in the characteristic impedance due to the proximity of the solder balls 91 on the pad 21 and the solder balls 91 on the pad 22. Therefore, the high frequency transmission characteristics of the wiring including the signal line 11 and the wiring including the signal line 12 can be improved. In other words, the high frequency transmission characteristics of the differential line 131 (FIG. 2) can be enhanced.
  • the trench TR may be located at least in the area R2 (FIG. 4).
  • the capacitive coupling between the wiring including the signal line 12 and the pad 22 and the member including the grounding portion 10 and the grounding region 20 is reduced. Therefore, the characteristic impedance of the wiring increases in the vicinity of the trench TR. Therefore, it is possible to suppress an adverse effect due to a local decrease in the characteristic impedance due to the proximity of the solder balls 91 on the pad 22 and the solder balls 91 on the grounding region 20. Therefore, the high frequency transmission characteristics of the wiring can be improved.
  • the capacitive coupling between the wiring including the signal line 12 and the pad 22 and the wiring including the signal line 13 and the pad 23 becomes small. Therefore, crosstalk between the differential line 131 including the signal line 12 (FIG. 2) and the differential line 132 including the signal line 13 (FIG. 2) is suppressed.
  • the trench TR is located not only in the region R1 and the region R2 but also in the region R3, the room for impedance matching by the trench TR is further secured.
  • each of the pad 21, the pad 22, the pad 23 and the pad 24 is adjacent to the edge ED.
  • the pads for the differential line 131 and the differential line 132 are arranged adjacent to the edge ED on the facing surface SP. Therefore, no other pad is arranged between the pad for these differential lines and the edge ED. Therefore, in the portion of the printed circuit board 200 (FIG. 3) near the edge ED, the wiring from the pad for the differential line can be arranged without being hindered by the wiring from these other pads.
  • the printed circuit board 200 is often a resin substrate, and in that case, when the substrate 80 of the package 100 is made of ceramics, the difference in the coefficient of thermal expansion between the printed circuit board 200 and the package 100 is large, and therefore thermal stress is likely to occur. According to this embodiment, since it is not necessary to make the solder balls 91 excessively small, this thermal stress can be sufficiently relaxed. This prevents the two from coming off due to thermal stress.
  • solder ball 91 is used as the conductive ball of the BGA. This allows typical BGA techniques to be used.
  • the depth of the trench TR When the depth of the trench TR is 1/3 or more of the ball diameter, it becomes easy to sufficiently secure the effect of reducing the capacitive coupling by the trench TR.
  • the depth of the trench TR When the depth of the trench TR is equal to or less than the ball diameter, it is possible to prevent the length of the portion of the wiring of the package 100 where the characteristic impedance is increased by the trench TR from becoming excessive. Therefore, it is possible to prevent the characteristic impedance from being increased even at a position far from the solder ball 91. Therefore, it is possible to prevent the mismatch of the characteristic impedance from being worsened due to the trench TR.
  • the depth of the trench TR When the depth of the trench TR is 100 ⁇ m or more, it becomes easy to sufficiently secure the effect of reducing the capacitive coupling by the trench TR. When the depth of the trench TR is 300 ⁇ m or less, it is possible to prevent the length of the portion of the wiring in which the characteristic impedance is increased by the trench TR from becoming excessive. Therefore, it is possible to prevent the characteristic impedance from being increased even at a position far from the solder ball 91. Therefore, it is possible to prevent the mismatch of the characteristic impedance from being worsened due to the trench TR.
  • the package 100 can form a sealed space CV together with the lid 400.
  • the electronic component 300 can be sealed in the space CV.
  • the through hole 110 of the frame 102 can be used to transmit light related to the optical component 302. Packages on which the optics 302 are mounted often require high frequency transmission. According to this embodiment, the characteristics of high frequency transmission can be enhanced.
  • the electronic component 300 (FIG. 1) mounted on the package 100 includes an optical component 302 to which the optical fiber 310 is connected.
  • the electronic component may not include an optical component and an optical fiber.
  • the package 100 has the frame portion 102, but as a modification, the wiring structure may not have the frame portion.
  • the solder ball 91 which is a typical conductive ball in the BGA connection, is used, but the conductive ball is not limited to the solder ball.
  • FIG. 5 is a partial plan view schematically showing the configuration of the package 100V (wiring structure) according to the second embodiment.
  • the trench TR of the substrate 80 includes trenches TR1, trenches TR2 and trenches TR3 located in regions R1, regions R2 and regions R3, respectively.
  • the trench TR of the package 100 (FIG. 4: Embodiment 1) corresponds to one configured by connecting the trench TR1, the trench TR2, and the trench TR3 to each other.
  • the package 100V has trenches TR1, trench TR2 and trench TR3 separated from each other, as shown in FIG.
  • a form in which one of the trench TR1 and the trench TR2 is connected to the trench TR3 and the other is not connected may be used. Further, as another modification, only one or two of the trench TR1, the trench TR2, and the trench TR3 may be provided.
  • the same effect as that of the first embodiment can be obtained by the present embodiment. Further, since the trench TR1, the trench TR2 and the trench TR3 are separated from each other, a green sheet having punch holes corresponding to the trench TR1, the trench TR2 and the trench TR3 in the production of the substrate 80 is obtained. The method used can be easily applied.
  • the wire E2a corresponds to the condition that the ball diameter is 300 ⁇ m and the depths of the trenches TR1 and TR2 are 200 ⁇ m and there is no trench TR3, and the wire E2b has a ball diameter of 300 ⁇ m and the depths of the trenches TR1 and TR2 are 300 ⁇ m and the trench.
  • the line E3a corresponds to the condition of the ball diameter of 300 ⁇ m and the depth of the trenches TR1 to TR3 of 200 ⁇ m
  • the line E3b corresponds to the condition of the ball diameter of 300 ⁇ m and the depth of the trenches TR1 and TR2 of 300 ⁇ m and the depth of the trench TR3. It corresponds to the condition of 200 ⁇ m.
  • FIG. 6 is a graph showing a simulation result showing the characteristic impedance as a time domain reflection (TDR: Time Domain Reflectometry).
  • TDR Time Domain Reflectometry
  • the time axis of TDR can be regarded as the spatial axis, and in the figure, the range of about 50 to 65 ps corresponds to the position near BGA90.
  • line E0a ball diameter 300 ⁇ m and no trench
  • a significant local drop in characteristic impedance is seen at approximately 50-65 ps, which leads to a significant mismatch in characteristic impedance.
  • This inconsistency is mitigated by reducing the ball diameter from 300 ⁇ m to 200 ⁇ m with reference to line E0b (ball diameter 200 ⁇ m and no trench) as a comparative example.
  • FIG. 7 is a graph showing the simulation results of the relationship between the reflection coefficient and the frequency.
  • the comparative example line E0a (ball diameter 300 ⁇ m and no trench) has a higher reflectance in the range of approximately 20-60 GHz than any other example, which is unsuitable for transmission. Means a characteristic.
  • line E0b (ball diameter 200 ⁇ m and no trench) as a comparative example, the reflectance coefficient is reduced by reducing the ball diameter from 300 ⁇ m to 200 ⁇ m.
  • the ball diameter is small, there is a concern that the mounting reliability may be lowered.
  • the reflectance coefficient is reduced while using a ball diameter of 300 ⁇ m. It is considered that the reduction of the reflectance coefficient is due to the characteristic impedance being more matched in the vicinity of BGA90.
  • FIG. 8 is a graph showing the simulation results of the relationship between the transmission coefficient and the frequency.
  • the wire E0a ball diameter 300 ⁇ m and no trench
  • the wire E0b ball diameter 200 ⁇ m and no trench
  • the transmission coefficient is increased by reducing the ball diameter from 300 ⁇ m to 200 ⁇ m.
  • the ball diameter is small, there is a concern that the mounting reliability may be lowered.
  • the transmission coefficient is increased while using a ball diameter of 300 ⁇ m.
  • the increase in the transmission coefficient is considered to be due to the reduction of signal reflection in the vicinity of BGA90.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A wiring structure (100) is implemented using a ball grid array (90). A substrate (80) is made of a dielectric. A first differential line (131) is provided in the substrate (80), and includes a first signal line (11) and a second signal line (12). The second differential line (132) is provided in the substrate (80) and includes a third signal line (13) and a fourth signal line (14). A first pad (21) is connected to the first signal line (11). A second pad (22) is connected to the second signal line (12). A third pad (23) is adjacent to the second pad (22) with a ground region (20) therebetween, and is connected to the third signal line (13). A fourth pad is connected to the fourth signal line. The ground region (20) includes an interposed portion (20i) between the second pad (22) and the third pad (23), and a non-interposed portion (20n) away from the interposed portion (20i). The substrate (80) has a trench (TR).

Description

配線構造Wiring structure
 本発明は、配線構造に関し、特に、回路基板上へボールグリッドアレイ(BGA)を用いて実装されることになる配線構造に関するものである。 The present invention relates to a wiring structure, and more particularly to a wiring structure to be mounted on a circuit board using a ball grid array (BGA).
 電子部品用のパッケージなどの配線構造を実装する技術のひとつとしてBGA技術がある。この技術によれば、格子状に配列された球状の導電性ボール、典型的にははんだボール、が用いられる。例えば、特開2008-283622号公報(特許文献1)は、BGA技術によって接続される多層誘電体基板を開示している。多層誘電体基板は、はんだボール搭載用のパッドと、このパッドに接続され多層誘電体基板内を通る柱状導体とを有している。 BGA technology is one of the technologies for mounting wiring structures such as packages for electronic components. According to this technique, spherical conductive balls arranged in a grid pattern, typically solder balls, are used. For example, Japanese Patent Application Laid-Open No. 2008-283622 (Patent Document 1) discloses a multilayer dielectric substrate connected by BGA technology. The multilayer dielectric substrate has a pad for mounting solder balls and a columnar conductor connected to the pad and passing through the multilayer dielectric substrate.
特開2008-283622号公報Japanese Unexamined Patent Publication No. 2008-283622
 近年、配線構造の高密度化が要請されている。すなわち、配線構造内の、信号が供される信号線路、および、接地電位が供される接地部に対して、微細化が要求されている。この微細化に対応して仮に、配線構造を回路基板に実装するための導電性ボールも同様に小さくされたとすると、導電性ボールによる配線構造の実装信頼性が確保できない可能性がある。具体的には、第1に、導電性ボールのサイズが過小であれば、接合強度が低下してしまう。第2に、導電性ボールが配線構造と回路基板との間で応力を緩和する機能が低下してしまう。特に、配線構造が主にセラミックスからなり回路基板が主に樹脂からなる場合、両者の間での熱膨張係数の差異が大きいので、熱応力の緩和の必要性が高い。よって、配線構造内の微細化に比して、導電性ボールの小型化には限界がある。よって、高密度化が進むほど、導電性ボールのサイズは、配線構造中の信号線路の断面に比して相対的に大きくなりやすい。よって、配線構造における信号線路とそれに隣り合う信号線路または接地部との間の間隔に比して、導電性ボール間の間隔が狭くなりやすい。 In recent years, there has been a demand for higher density wiring structures. That is, miniaturization is required for the signal line to which the signal is provided and the ground portion to which the ground potential is provided in the wiring structure. If the conductive balls for mounting the wiring structure on the circuit board are also made smaller in response to this miniaturization, there is a possibility that the mounting reliability of the wiring structure by the conductive balls cannot be ensured. Specifically, first, if the size of the conductive ball is too small, the joint strength will decrease. Second, the conductive balls reduce the ability to relieve stress between the wiring structure and the circuit board. In particular, when the wiring structure is mainly made of ceramics and the circuit board is mainly made of resin, the difference in the coefficient of thermal expansion between the two is large, so that it is highly necessary to relax the thermal stress. Therefore, there is a limit to the miniaturization of the conductive ball as compared with the miniaturization in the wiring structure. Therefore, as the density increases, the size of the conductive ball tends to be relatively large compared to the cross section of the signal line in the wiring structure. Therefore, the distance between the conductive balls tends to be narrower than the distance between the signal line in the wiring structure and the signal line or the grounding portion adjacent to the signal line.
 配線構造およびそれが実装される回路基板の特性インピーダンスは、通常、ほぼ共通とされる。配線構造における配線間隔が十分である一方で導電性ボール間の間隔が過小である場合、配線構造および回路基板の特性インピーダンスに比して、導電性ボールによって構成されたBGA接合部において特性インピーダンスが局所的に低下してしまう。この局所的な低下によって、特性インピーダンスの不整合が生じる。特性インピーダンスの不整合は、信号周波数が高くなるほど伝送特性に悪影響を及ぼす。 The wiring structure and the characteristic impedance of the circuit board on which it is mounted are usually almost the same. When the wiring spacing in the wiring structure is sufficient but the spacing between the conductive balls is too small, the characteristic impedance at the BGA junction composed of the conductive balls is higher than the characteristic impedance of the wiring structure and the circuit board. It will decrease locally. This local drop causes a mismatch in the characteristic impedance. The mismatch of the characteristic impedance adversely affects the transmission characteristics as the signal frequency becomes higher.
 本発明は以上のような課題を解決するためになされたものであり、その目的は、実装信頼性を維持しつつ良好な高周波伝送特性を得ることができる配線構造を提供することである。 The present invention has been made to solve the above problems, and an object of the present invention is to provide a wiring structure capable of obtaining good high frequency transmission characteristics while maintaining mounting reliability.
 一実施の形態の配線構造は、回路基板上へボールグリッドアレイを用いて実装されることになるものである。配線構造は、基体と、第1差動線路と、第2差動線路と、接地領域と、第1パッドと、第2パッドと、第3パッドと、第4パッドとを有している。基体は、誘電体からなり、回路基板に対向することになる対向面を有している。第1差動線路は、基体中に設けられており、対向面に達しており、第1信号線路および第2信号線路を有している。第2差動線路は、基体中に設けられており、対向面に達しており、第3信号線路および第4信号線路を有している。接地領域は、対向面上に設けられており、接地電位が付与されることになる。第1パッドは、対向面上に設けられており、第1信号線路に接続されている。第2パッドは、対向面上に設けられており、第2信号線路に接続されている。第3パッドは、対向面上に設けられており、接地領域を介して第2パッドと隣り合っており、第3信号線路に接続されている。第4パッドは、対向面上に設けられており、第4信号線路に接続されている。接地領域は、第2パッドと第3パッドとの間の介在部と、介在部から外れた非介在部とを含む。基体の対向面は、第1パッドと第2パッドとの間の第1領域と、第2パッドと介在部との間の第2領域と、第1パッドおよび第2パッドの各々と非介在部との間の第3領域とを含む。基体の対向面は、第1領域、第2領域および第3領域の少なくともいずれかにトレンチを有している。 The wiring structure of one embodiment is to be mounted on a circuit board using a ball grid array. The wiring structure includes a substrate, a first differential line, a second differential line, a grounding area, a first pad, a second pad, a third pad, and a fourth pad. The substrate is made of a dielectric and has a facing surface that faces the circuit board. The first differential line is provided in the substrate, reaches the facing surface, and has a first signal line and a second signal line. The second differential line is provided in the substrate, reaches the facing surface, and has a third signal line and a fourth signal line. The grounding region is provided on the facing surface, and a grounding potential is applied. The first pad is provided on the facing surface and is connected to the first signal line. The second pad is provided on the facing surface and is connected to the second signal line. The third pad is provided on the facing surface, is adjacent to the second pad via the grounding region, and is connected to the third signal line. The fourth pad is provided on the facing surface and is connected to the fourth signal line. The ground contact area includes an intervening portion between the second pad and the third pad, and a non-intervening portion deviating from the intervening portion. The facing surfaces of the substrate are the first region between the first pad and the second pad, the second region between the second pad and the intervening portion, and each of the first pad and the second pad and the non-intervening portion. Includes a third region between and. The facing surface of the substrate has a trench in at least one of a first region, a second region, and a third region.
 上記配線構造によれば、配線の特性インピーダンスがトレンチ近傍で増大する。これにより、導電性ボール同士の接近による特性インピーダンスの局所的低下に起因しての高周波伝送特性への悪影響を抑えることができる。よって、導電性ボール同士の接近を避けるために導電性ボールのサイズを過度に小さくする必要がなく、これにより実装信頼性が維持される。以上から、実装信頼性を維持しつつ良好な高周波伝送特性を得ることができる。 According to the above wiring structure, the characteristic impedance of the wiring increases near the trench. As a result, it is possible to suppress an adverse effect on the high-frequency transmission characteristic due to a local decrease in the characteristic impedance due to the proximity of the conductive balls to each other. Therefore, it is not necessary to make the size of the conductive balls excessively small in order to avoid the conductive balls from approaching each other, thereby maintaining the mounting reliability. From the above, good high-frequency transmission characteristics can be obtained while maintaining mounting reliability.
 この発明の目的、特徴、局面、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。 The objectives, features, aspects, and advantages of the present invention will be made clearer by the following detailed description and accompanying drawings.
本発明の実施の形態1における電子機器の構成を概略的に示す断面図である。It is sectional drawing which shows schematic the structure of the electronic device in Embodiment 1 of this invention. 本発明の実施の形態1における配線構造の一部構成の回路図である。It is a circuit diagram of a part of the wiring structure in Embodiment 1 of this invention. 図1の破線部III-IIIに対応する部分断面図である。It is a partial cross-sectional view corresponding to the broken line part III-III of FIG. 本発明の実施の形態1における配線構造の構成を概略的に示す部分平面図である。It is a partial plan view which shows roughly the structure of the wiring structure in Embodiment 1 of this invention. 本発明の実施の形態2における配線構造の構成を概略的に示す部分平面図である。It is a partial plan view which shows roughly the structure of the wiring structure in Embodiment 2 of this invention. 特性インピーダンスを時間領域反射(TDR:Time Domain Reflectometry)として示すシミュレーション結果を示すグラフ図である。It is a graph which shows the simulation result which shows the characteristic impedance as time domain reflection (TDR: Time Domain Reflectometry). 反射係数と周波数との関係のシミュレーション結果を示すグラフ図である。It is a graph which shows the simulation result of the relationship between a reflection coefficient and a frequency. 伝送係数と周波数との関係のシミュレーション結果を示すグラフ図である。It is a graph which shows the simulation result of the relationship between a transmission coefficient and a frequency.
 以下、図面に基づいて本発明の実施の形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
 <実施の形態1>
 図1は、本実施の形態1における電子機器900の構成を概略的に示す断面図である。電子機器900は、パッケージ100(配線構造)と、BGA90と、プリント基板200(回路基板)と、電子部品300と、光ファイバ310と、蓋体400とを有している。BGA90は、パッケージ100とプリント基板200との間の電気的かつ機械的接続のためのものであり、格子状に配列されたはんだボール91(導電性ボール)を含む。
<Embodiment 1>
FIG. 1 is a cross-sectional view schematically showing the configuration of the electronic device 900 according to the first embodiment. The electronic device 900 includes a package 100 (wiring structure), a BGA 90, a printed circuit board 200 (circuit board), an electronic component 300, an optical fiber 310, and a lid 400. The BGA 90 is for an electrical and mechanical connection between the package 100 and the printed circuit board 200 and includes solder balls 91 (conductive balls) arranged in a grid pattern.
 パッケージ100は、図示されているように、プリント基板200上へBGA90を用いて実装されることになるものである。パッケージ100は、誘電体からなる基体(詳しくは後述する)を有しており、この基体は底部101および枠部102を有している。底部101は、電子部品300が実装されることになる実装面SMを有している。枠部102は、実装面SM上の空間CVを囲んでいる。枠部102は、光ファイバ310を通すための貫通孔部110を有している。変形例として、貫通孔部110に代わって透光部が設けられてもよい。透光部は、透光性材料からなる窓部である。 As shown in the figure, the package 100 will be mounted on the printed circuit board 200 using the BGA 90. The package 100 has a substrate made of a dielectric (details will be described later), and this substrate has a bottom portion 101 and a frame portion 102. The bottom 101 has a mounting surface SM on which the electronic component 300 will be mounted. The frame portion 102 surrounds the space CV on the mounting surface SM. The frame portion 102 has a through hole portion 110 for passing the optical fiber 310. As a modification, a light transmitting portion may be provided instead of the through hole portion 110. The translucent portion is a window portion made of a translucent material.
 本実施の形態においては、電子部品300は、互いに電気的に接続された集積回路(IC)301および光学部品302を含む。IC301の動作周波数は高周波であってよく、例えば55GHz以上であってよい。光学部品302は、例えば、フォトダイオードである。光ファイバ310は、光学部品302に接続されており、貫通孔部110を通って空間CVの外へ延びている。 In this embodiment, the electronic component 300 includes an integrated circuit (IC) 301 and an optical component 302 that are electrically connected to each other. The operating frequency of the IC 301 may be a high frequency, for example 55 GHz or higher. The optical component 302 is, for example, a photodiode. The optical fiber 310 is connected to the optical component 302 and extends out of the space CV through the through hole 110.
 図2は、パッケージ100(図1)の一部構成の回路図である。図3は、破線部III-III(図1)に対応する部分断面図である。図4は、パッケージ100の構成を概略的に示す部分平面図である。 FIG. 2 is a circuit diagram of a partial configuration of the package 100 (FIG. 1). FIG. 3 is a partial cross-sectional view corresponding to the broken line portion III-III (FIG. 1). FIG. 4 is a partial plan view schematically showing the configuration of the package 100.
 パッケージ100は、誘電体からなる基体80を有している。基体80は、誘電体からなり、例えばセラミックスからなる。基体80は、実装面SMと、対向面SPとを有している。対向面SPは、パッケージ100がプリント基板200へ実装される際に、BGA90を介してプリント基板200に対向することになる。実装面SM上には、電子部品300(図1)が実装されることになる。 Package 100 has a substrate 80 made of a dielectric material. The substrate 80 is made of a dielectric, for example ceramics. The substrate 80 has a mounting surface SM and a facing surface SP. The facing surface SP faces the printed circuit board 200 via the BGA 90 when the package 100 is mounted on the printed circuit board 200. The electronic component 300 (FIG. 1) will be mounted on the mounting surface SM.
 パッケージ100は基体80中に、差動線路131(第1差動線路)と、差動線路132(第2差動線路)と、接地部10とを有しており、これらは対向面SPおよび実装面SMの各々に達している。接地部10は、差動線路131および差動線路132の各々の電気的シールドのためのものであり、接地電位(基準電位)が付与されることになる。なお接地電位は、電子機器900が使用される際に付与されていればよい。差動線路131は、信号線路11(第1信号線路)および信号線路12(第2信号線路)を有しており、差動線路132は、信号線路13(第3信号線路)および信号線路14(第4信号線路)を有している。 The package 100 has a differential line 131 (first differential line), a differential line 132 (second differential line), and a grounding portion 10 in the substrate 80, and these have a facing surface SP and a grounding portion 10. It has reached each of the mounting surfaces SM. The grounding portion 10 is for the electric shield of each of the differential line 131 and the differential line 132, and a ground potential (reference potential) is applied. The ground potential may be applied when the electronic device 900 is used. The differential line 131 has a signal line 11 (first signal line) and a signal line 12 (second signal line), and the differential line 132 has a signal line 13 (third signal line) and a signal line 14. It has (4th signal line).
 パッケージ100は基体80の対向面SP上に、接地領域20と、パッド21(第1パッド)と、パッド22(第2パッド)と、パッド23(第3パッド)と、パッド24(第4パッド)とを有しており、これらはそれぞれ、接地部10と、信号線路11と、信号線路12と、信号線路13と、信号線路14とに接続されている。パッド23は、接地領域20を介してパッド22と隣り合っている。接地領域20には接地電位が付与されることになる。接地領域20は、パッド22とパッド23との間の介在部20iと、介在部から外れた非介在部20nとを含む。 The package 100 has a ground contact area 20, a pad 21 (first pad), a pad 22 (second pad), a pad 23 (third pad), and a pad 24 (fourth pad) on the facing surface SP of the substrate 80. ), Which are connected to the grounding portion 10, the signal line 11, the signal line 12, the signal line 13, and the signal line 14, respectively. The pad 23 is adjacent to the pad 22 via the ground contact area 20. A ground potential is applied to the ground region 20. The ground contact area 20 includes an intervening portion 20i between the pad 22 and the pad 23, and a non-intervening portion 20n separated from the intervening portion.
 基体80の対向面SPは、図4に示されているように、パッド21とパッド22との間の領域R1(第1領域)と、パッド22と介在部20iとの間の領域R2(第2領域)と、パッド21およびパッド22の各々と非介在部20nとの間の領域R3(第3領域)とを含む。基体80の対向面SPは、領域R1、領域R2および領域R3の少なくともいずれかにトレンチTRを有している。トレンチTRは少なくとも領域R1に位置していてよい。またトレンチTRは少なくとも領域R2に位置していてよい。好ましくは、トレンチTRは少なくとも領域R1および領域R2に位置している。より好ましくは、図4に示されているように、トレンチTRは少なくとも領域R1、領域R2および領域R3に位置している。 As shown in FIG. 4, the facing surface SP of the substrate 80 has a region R1 (first region) between the pad 21 and the pad 22 and a region R2 (first region) between the pad 22 and the intervening portion 20i. 2 regions) and a region R3 (third region) between each of the pads 21 and 22 and the non-intervening portion 20n. The facing surface SP of the substrate 80 has a trench TR in at least one of the region R1, the region R2, and the region R3. The trench TR may be located at least in region R1. Further, the trench TR may be located at least in the region R2. Preferably, the trench TR is located at least in regions R1 and R2. More preferably, as shown in FIG. 4, the trench TR is located at least in region R1, region R2 and region R3.
 平面レイアウト(図4参照)において、好ましくは、トレンチTRのうちパッド21およびパッド22に隣接する部分は、縁EDに垂直であってパッド21とパッド22との中点を通る仮想線に対して線対称性を有している。より好ましくは、トレンチTRのうちパッド21~24に隣接する部分は、縁EDに垂直であってパッド22とパッド23との中点を通る仮想線に対して線対称性を有している。 In a planar layout (see FIG. 4), preferably, the portion of the trench TR adjacent to the pad 21 and the pad 22 is perpendicular to the edge ED and with respect to a virtual line passing through the midpoint between the pad 21 and the pad 22. It has line symmetry. More preferably, the portion of the trench TR adjacent to the pads 21 to 24 is perpendicular to the edge ED and has line symmetry with respect to the virtual line passing through the midpoint between the pad 22 and the pad 23.
 トレンチTRは100μm以上かつ300μm以下の深さを有していることが好ましい。トレンチTR内の空間の誘電率は、基体80の誘電率よりも低く、典型的には約1である。典型的には、トレンチTR内は、気体によって充填されているか、または真空である。 The trench TR preferably has a depth of 100 μm or more and 300 μm or less. The dielectric constant of the space in the trench TR is lower than the dielectric constant of the substrate 80, typically about 1. Typically, the trench TR is filled with gas or is evacuated.
 トレンチTRは、図4に示されているように対向面SPの縁EDに達していなくてよい。その場合、基体80の製造においてトレンチTRに対応するパンチ孔を有するグリーンシートを用いた工法の適用が容易となる。トレンチTRが縁EDに達しているとすると、グリーンシートのパッド21に対応する部分が周囲の他の部分から分離されてしまうので、積層前の単一のグリーンシートのハンドリングが困難となる。なお、グリーンシートの積層後にトレンチが、例えばレーザ加工で形成される場合は、トレンチが縁EDに達していても、上記の問題は生じない。 The trench TR does not have to reach the edge ED of the facing surface SP as shown in FIG. In that case, in the production of the substrate 80, it becomes easy to apply the construction method using a green sheet having punch holes corresponding to the trench TR. If the trench TR reaches the edge ED, the portion of the green sheet corresponding to the pad 21 is separated from the other surrounding portions, making it difficult to handle a single green sheet before laminating. When the trench is formed by, for example, laser processing after laminating the green sheet, the above problem does not occur even if the trench reaches the edge ED.
 対向面SP上において、パッド21、パッド22、パッド23およびパッド24の各々は縁EDに隣接していることが好ましい。ここで、あるパッドが縁EDに隣接しているということは、図4に示されているように、当該パッドと縁EDとの間に他のパッドがないことを意味する。具体的には、パッド21、パッド22、パッド23およびパッド24の各々は、BGA90に対応して対向面SP上に格子状に配列されたパッドのうち対向面SPの外周に配置されたものである。典型的には、パッド21、パッド22、パッド23およびパッド24は、対向面SP上の全パッドのうち、縁EDから最も近くに位置するパッドである。 It is preferable that each of the pad 21, the pad 22, the pad 23 and the pad 24 is adjacent to the edge ED on the facing surface SP. Here, the fact that a certain pad is adjacent to the edge ED means that there is no other pad between the pad and the edge ED, as shown in FIG. Specifically, each of the pad 21, the pad 22, the pad 23, and the pad 24 is arranged on the outer periphery of the facing surface SP among the pads arranged in a grid pattern on the facing surface SP corresponding to the BGA 90. is there. Typically, the pads 21, pads 22, pads 23 and pads 24 are the pads closest to the edge ED of all the pads on the facing surface SP.
 パッケージ100は、図2に示されているように、基体80の実装面SM上に、接続端30と、接続端31と、接続端32と、接続端33と、接続端34とを有していてよく、これらはそれぞれ、接地部10と、信号線路11と、信号線路12と、信号線路13と、信号線路14とに接続されている。接続端30と、接続端31と、接続端32と、接続端33と、接続端34とは、電子部品300(図1)へのパッケージ100の電気的接続に用いられる。 As shown in FIG. 2, the package 100 has a connection end 30, a connection end 31, a connection end 32, a connection end 33, and a connection end 34 on the mounting surface SM of the substrate 80. These may be connected to the grounding portion 10, the signal line 11, the signal line 12, the signal line 13, and the signal line 14, respectively. The connection end 30, the connection end 31, the connection end 32, the connection end 33, and the connection end 34 are used for electrical connection of the package 100 to the electronic component 300 (FIG. 1).
 プリント基板200(図3)は、基体280と、回路パターンとを有している。基体280は樹脂からなってよい。言い換えれば、プリント基板200は樹脂基板であってよい。回路パターンは、例えば、回路パターン220と、回路パターン221と、回路パターン230と、回路パターン231とを含む。またプリント基板200は、回路パターン220と回路パターン230とを厚み方向においてつなぐビア電極210と、回路パターン221と回路パターン231とを厚み方向においてつなぐビア電極211とを有していてよい。 The printed circuit board 200 (FIG. 3) has a substrate 280 and a circuit pattern. The substrate 280 may be made of resin. In other words, the printed circuit board 200 may be a resin substrate. The circuit pattern includes, for example, a circuit pattern 220, a circuit pattern 221 and a circuit pattern 230, and a circuit pattern 231. Further, the printed circuit board 200 may have a via electrode 210 that connects the circuit pattern 220 and the circuit pattern 230 in the thickness direction, and a via electrode 211 that connects the circuit pattern 221 and the circuit pattern 231 in the thickness direction.
 電子機器900(図1)においては、図4に示されているように、パッド21、パッド22、パッド23、パッド24および接地領域20の各々の上に、BGA90を構成するはんだボール91が配置されている。よって、電子機器900が製造される際には、パッド21、パッド22、パッド23、パッド24および接地領域20の各々の上に、BGA90を構成するはんだボール91が搭載されたパッケージ100が準備される。そしてBGA90を用いてパッケージ100がプリント基板200に実装される。例えば図3に示された視野においては、接地領域20と回路パターン220との間、および、パッド21と回路パターン221との間が、はんだボール91によって接合される。 In the electronic device 900 (FIG. 1), as shown in FIG. 4, the solder balls 91 constituting the BGA 90 are arranged on each of the pad 21, the pad 22, the pad 23, the pad 24, and the ground contact area 20. Has been done. Therefore, when the electronic device 900 is manufactured, a package 100 in which the solder balls 91 constituting the BGA 90 are mounted is prepared on each of the pad 21, the pad 22, the pad 23, the pad 24, and the ground contact area 20. Ru. Then, the package 100 is mounted on the printed circuit board 200 using the BGA 90. For example, in the field of view shown in FIG. 3, the grounding region 20 and the circuit pattern 220 and the pad 21 and the circuit pattern 221 are joined by the solder balls 91.
 はんだボール91は、パッド21、パッド22、パッド23、パッド24および接地領域20等の上に搭載される時点と、その後においてパッケージ100とプリント基板200との間に挟まれる時点とで、変形を受ける。この変形によってはんだボール91は、図3に示されているように、球形から変形した形状を有している。はんだボール91の体積と等しい体積を有する球の直径をボール径と定義したとき、トレンチTRはボール径の1/3以上かつボール径以下の深さを有していることが好ましい。ボール径は、実装信頼性の観点で200μmよりも大きいことが好ましく、高密度化の観点で400μmよりも小さいことが好ましく、例えば300μm程度である。隣接するはんだボール91の中心間距離は、例えば、500μm程度である。隣接するはんだボール間の隙間(図3における横方向の隙間)は、通常、隣接するパッド間の隙間(図3におけるパッド20とパッド21との間の隙間)よりも小さく、上記のようにボール径が300μmであって中心間距離が500μmである場合は200μm未満である。 The solder ball 91 is deformed at the time when it is mounted on the pad 21, the pad 22, the pad 23, the pad 24, the ground contact area 20, etc., and then when it is sandwiched between the package 100 and the printed circuit board 200. receive. As shown in FIG. 3, the solder ball 91 has a shape deformed from a spherical shape due to this deformation. When the diameter of a sphere having a volume equal to the volume of the solder ball 91 is defined as the ball diameter, the trench TR preferably has a depth of 1/3 or more of the ball diameter and less than or equal to the ball diameter. The ball diameter is preferably larger than 200 μm from the viewpoint of mounting reliability, and preferably smaller than 400 μm from the viewpoint of high density, for example, about 300 μm. The distance between the centers of the adjacent solder balls 91 is, for example, about 500 μm. The gap between adjacent solder balls (horizontal gap in FIG. 3) is usually smaller than the gap between adjacent pads (gap between pads 20 and 21 in FIG. 3), and the balls as described above. When the diameter is 300 μm and the center-to-center distance is 500 μm, it is less than 200 μm.
 本実施の形態によれば、配線の特性インピーダンスがトレンチTR近傍で増大する。これにより、はんだボール91同士の接近による特性インピーダンスの局所的低下に起因しての高周波伝送特性への悪影響を抑えることができる。よって、はんだボール91同士の接近を避けるために導電性ボール91のサイズを過度に小さくする必要がなく、これにより実装信頼性が維持される。以上から、実装信頼性を維持しつつ良好な高周波伝送特性を得ることができる。 According to this embodiment, the characteristic impedance of the wiring increases in the vicinity of the trench TR. As a result, it is possible to suppress an adverse effect on the high frequency transmission characteristics due to a local decrease in the characteristic impedance due to the proximity of the solder balls 91 to each other. Therefore, it is not necessary to make the size of the conductive balls 91 excessively small in order to avoid the solder balls 91 from approaching each other, thereby maintaining the mounting reliability. From the above, good high-frequency transmission characteristics can be obtained while maintaining mounting reliability.
 具体的には、はんだボール91同士の接近によって特性インピーダンスが局所的に低下した箇所と、トレンチTRによって特性インピーダンスが局所的に増加した箇所とが十分に近ければ、信号周波数が極端に高くない限り、これら低下と増加とが実質的に相殺することによって特性インピーダンスの整合を図ることができる。よって、はんだボール91とトレンチTRとの間の距離は小さいことが好ましく、この距離は、例えばボール径以下である。 Specifically, if the location where the characteristic impedance locally decreases due to the proximity of the solder balls 91 and the location where the characteristic impedance locally increases due to the trench TR are sufficiently close, unless the signal frequency is extremely high. , The characteristic impedance can be matched by substantially canceling these decrease and increase. Therefore, the distance between the solder ball 91 and the trench TR is preferably small, and this distance is, for example, less than or equal to the ball diameter.
 トレンチTRは少なくとも領域R1(図4)に位置していてよい。これにより、信号線路11およびパッド21を含む配線と、信号線路12およびパッド22を含む配線との間の容量結合が小さくなる。よって、トレンチTR近傍で両配線の特性インピーダンスが増大する。よって、パッド21上のはんだボール91とパッド22上のはんだボール91との接近に起因しての特性インピーダンスの局所的低下による悪影響を抑えることができる。よって、信号線路11を含む配線と、信号線路12を含む配線との各々の高周波伝送特性を高めることができる。言い換えれば、差動線路131(図2)の高周波伝送特性を高めることができる。 The trench TR may be located at least in the area R1 (FIG. 4). As a result, the capacitive coupling between the wiring including the signal line 11 and the pad 21 and the wiring including the signal line 12 and the pad 22 becomes small. Therefore, the characteristic impedance of both wirings increases in the vicinity of the trench TR. Therefore, it is possible to suppress an adverse effect due to a local decrease in the characteristic impedance due to the proximity of the solder balls 91 on the pad 21 and the solder balls 91 on the pad 22. Therefore, the high frequency transmission characteristics of the wiring including the signal line 11 and the wiring including the signal line 12 can be improved. In other words, the high frequency transmission characteristics of the differential line 131 (FIG. 2) can be enhanced.
 トレンチTRは少なくとも領域R2(図4)に位置していてよい。これにより第1に、信号線路12およびパッド22を含む配線と、接地部10および接地領域20を含む部材との間の容量結合が小さくなる。よって、トレンチTR近傍で配線の特性インピーダンスが増大する。よって、パッド22上のはんだボール91と、接地領域20上のはんだボール91との接近に起因しての特性インピーダンスの局所的低下による悪影響を抑えることができる。よって、配線の高周波伝送特性を高めることができる。第2に、信号線路12およびパッド22を含む配線と、信号線路13およびパッド23を含む配線との間の容量結合が小さくなる。よって、信号線路12を含む差動線路131(図2)と、信号線路13を含む差動線路132(図2)との間でのクロストークが抑制される。 The trench TR may be located at least in the area R2 (FIG. 4). As a result, firstly, the capacitive coupling between the wiring including the signal line 12 and the pad 22 and the member including the grounding portion 10 and the grounding region 20 is reduced. Therefore, the characteristic impedance of the wiring increases in the vicinity of the trench TR. Therefore, it is possible to suppress an adverse effect due to a local decrease in the characteristic impedance due to the proximity of the solder balls 91 on the pad 22 and the solder balls 91 on the grounding region 20. Therefore, the high frequency transmission characteristics of the wiring can be improved. Secondly, the capacitive coupling between the wiring including the signal line 12 and the pad 22 and the wiring including the signal line 13 and the pad 23 becomes small. Therefore, crosstalk between the differential line 131 including the signal line 12 (FIG. 2) and the differential line 132 including the signal line 13 (FIG. 2) is suppressed.
 トレンチTRが領域R1および領域R2だけでなく領域R3にも位置していることによって、トレンチTRによるインピーダンス整合の余地が、より確保される。 Since the trench TR is located not only in the region R1 and the region R2 but also in the region R3, the room for impedance matching by the trench TR is further secured.
 対向面SP上において、図4に示されているように、パッド21、パッド22、パッド23およびパッド24の各々が縁EDに隣接していることが好ましい。これにより、差動線路131および差動線路132用のパッドが対向面SP上において縁EDに隣接して配置される。よって、これら差動線路用のパッドと縁EDとの間に他のパッドが配置されない。よって、プリント基板200(図3)の、縁ED近傍部分において、これら他のパッドからの配線に妨げられることなく、差動線路用のパッドからの配線を配置することができる。 On the facing surface SP, as shown in FIG. 4, it is preferable that each of the pad 21, the pad 22, the pad 23 and the pad 24 is adjacent to the edge ED. As a result, the pads for the differential line 131 and the differential line 132 are arranged adjacent to the edge ED on the facing surface SP. Therefore, no other pad is arranged between the pad for these differential lines and the edge ED. Therefore, in the portion of the printed circuit board 200 (FIG. 3) near the edge ED, the wiring from the pad for the differential line can be arranged without being hindered by the wiring from these other pads.
 プリント基板200はしばしば樹脂基板であり、その場合、パッケージ100の基体80がセラミックスからなると、プリント基板200とパッケージ100との間での熱膨張係数の差異が大きく、よって熱応力が生じやすい。本実施の形態によれば、はんだボール91を過度に小さくする必要がないので、この熱応力を十分に緩和することができる。これにより、熱応力に起因して両者の接合が外れることが防止される。 The printed circuit board 200 is often a resin substrate, and in that case, when the substrate 80 of the package 100 is made of ceramics, the difference in the coefficient of thermal expansion between the printed circuit board 200 and the package 100 is large, and therefore thermal stress is likely to occur. According to this embodiment, since it is not necessary to make the solder balls 91 excessively small, this thermal stress can be sufficiently relaxed. This prevents the two from coming off due to thermal stress.
 BGAの導電性ボールとして、本実施の形態においては、はんだボール91が用いられる。これにより、典型的なBGA技術を用いることができる。 In the present embodiment, the solder ball 91 is used as the conductive ball of the BGA. This allows typical BGA techniques to be used.
 トレンチTRの深さがボール径の1/3以上であることによって、トレンチTRによる、容量結合の低減効果を十分に確保しやすくなる。トレンチTRの深さがボール径以下であることによって、パッケージ100の配線のうち、特性インピーダンスがトレンチTRによって増大される部分の長さが過大になることが避けられる。よって、はんだボール91から遠い位置においてまで特性インピーダンスが増大されてしまうことが避けられる。よって、トレンチTRに起因して特性インピーダンスの不整合がかえって悪化することを避けることができる。 When the depth of the trench TR is 1/3 or more of the ball diameter, it becomes easy to sufficiently secure the effect of reducing the capacitive coupling by the trench TR. When the depth of the trench TR is equal to or less than the ball diameter, it is possible to prevent the length of the portion of the wiring of the package 100 where the characteristic impedance is increased by the trench TR from becoming excessive. Therefore, it is possible to prevent the characteristic impedance from being increased even at a position far from the solder ball 91. Therefore, it is possible to prevent the mismatch of the characteristic impedance from being worsened due to the trench TR.
 トレンチTRの深さが100μm以上であることによって、トレンチTRによる、容量結合の低減効果を十分に確保しやすくなる。トレンチTRの深さが300μm以下であることによって、配線のうち、特性インピーダンスがトレンチTRによって増大される部分の長さが過大になることが避けられる。よって、はんだボール91から遠い位置においてまで特性インピーダンスが増大されてしまうことが避けられる。よって、トレンチTRに起因して特性インピーダンスの不整合がかえって悪化することを避けることができる。 When the depth of the trench TR is 100 μm or more, it becomes easy to sufficiently secure the effect of reducing the capacitive coupling by the trench TR. When the depth of the trench TR is 300 μm or less, it is possible to prevent the length of the portion of the wiring in which the characteristic impedance is increased by the trench TR from becoming excessive. Therefore, it is possible to prevent the characteristic impedance from being increased even at a position far from the solder ball 91. Therefore, it is possible to prevent the mismatch of the characteristic impedance from being worsened due to the trench TR.
 基体80が枠部102(図1)を有することによって、パッケージ100は蓋体400と共に、封止された空間CVを構成することができる。これにより、空間CV内に電子部品300を封止することができる。 Since the base 80 has the frame portion 102 (FIG. 1), the package 100 can form a sealed space CV together with the lid 400. As a result, the electronic component 300 can be sealed in the space CV.
 枠部102の貫通孔部110は、光学部品302に関連した光を透過させるのに用いることができる。光学部品302が搭載されたパッケージは、しばしば高周波伝送を要する。本実施の形態によれば、高周波伝送の特性を高めることができる。 The through hole 110 of the frame 102 can be used to transmit light related to the optical component 302. Packages on which the optics 302 are mounted often require high frequency transmission. According to this embodiment, the characteristics of high frequency transmission can be enhanced.
 なお、本実施の形態においては、パッケージ100上に実装される電子部品300(図1)は、光ファイバ310が接続された光学部品302を含む。変形例として、電子部品は光学部品および光ファイバを含まなくてもよい。また本実施の形態においてはパッケージ100が枠部102を有しているが、変形例として、配線構造は枠部を有していなくてもよい。また本実施の形態においては、BGA接続における典型的な導電性ボールであるはんだボール91が用いられているが、導電性ボールははんだボールに限定されるものではない。 In the present embodiment, the electronic component 300 (FIG. 1) mounted on the package 100 includes an optical component 302 to which the optical fiber 310 is connected. As a modification, the electronic component may not include an optical component and an optical fiber. Further, in the present embodiment, the package 100 has the frame portion 102, but as a modification, the wiring structure may not have the frame portion. Further, in the present embodiment, the solder ball 91, which is a typical conductive ball in the BGA connection, is used, but the conductive ball is not limited to the solder ball.
 <実施の形態2>
 図5は、本実施の形態2におけるパッケージ100V(配線構造)の構成を概略的に示す部分平面図である。パッケージ100Vにおいては、基体80のトレンチTRは、領域R1、領域R2および領域R3のそれぞれに位置するトレンチTR1、トレンチTR2およびトレンチTR3を含む。パッケージ100(図4:実施の形態1)のトレンチTRは、これらトレンチTR1、トレンチTR2およびトレンチTR3が互いにつながることで構成されたものに相当する。一方、パッケージ100Vは、図5に示されているように、互いに分離されたトレンチTR1、トレンチTR2およびトレンチTR3を有している。なお変形例として、トレンチTR3へトレンチTR1およびトレンチTR2の一方がつながり他方がつながらない形態が用いられてもよい。また他の変形例として、トレンチTR1、トレンチTR2およびトレンチTR3のうちの1つまたは2つのみが設けられてもよい。
<Embodiment 2>
FIG. 5 is a partial plan view schematically showing the configuration of the package 100V (wiring structure) according to the second embodiment. In package 100V, the trench TR of the substrate 80 includes trenches TR1, trenches TR2 and trenches TR3 located in regions R1, regions R2 and regions R3, respectively. The trench TR of the package 100 (FIG. 4: Embodiment 1) corresponds to one configured by connecting the trench TR1, the trench TR2, and the trench TR3 to each other. On the other hand, the package 100V has trenches TR1, trench TR2 and trench TR3 separated from each other, as shown in FIG. As a modification, a form in which one of the trench TR1 and the trench TR2 is connected to the trench TR3 and the other is not connected may be used. Further, as another modification, only one or two of the trench TR1, the trench TR2, and the trench TR3 may be provided.
 なお、上記以外の構成については、上述した実施の形態1の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。 Since the configurations other than the above are almost the same as the configurations of the first embodiment described above, the same or corresponding elements are designated by the same reference numerals, and the description thereof will not be repeated.
 本実施の形態によっても、実施の形態1とほぼ同様の効果が得られる。さらに、本実施の形態によれば、トレンチTR1、トレンチTR2およびトレンチTR3が互いに分離されていることによって、基体80の製造においてトレンチTR1、トレンチTR2およびトレンチTR3に対応するパンチ孔を有するグリーンシートを用いた工法の適用が容易となる。 The same effect as that of the first embodiment can be obtained by the present embodiment. Further, according to the present embodiment, since the trench TR1, the trench TR2 and the trench TR3 are separated from each other, a green sheet having punch holes corresponding to the trench TR1, the trench TR2 and the trench TR3 in the production of the substrate 80 is obtained. The method used can be easily applied.
 <シミュレーション>
 トレンチTR(図5参照)の構成とはんだボールのボール径とが高周波伝送特性へ及ぼす影響についてのシミュレーション結果について、図6~図8を参照して、以下に説明する。なお各図において、比較例を示すものとして、線E0aはボール径300μmかつトレンチなしの条件に対応し、線E0bはボール径200μmかつトレンチなしの条件に対応する。また実施例を示すものとして、線E2aはボール径300μmかつトレンチTR1,TR2の深さ200μmかつトレンチTR3なしの条件に対応し、線E2bはボール径300μmかつトレンチTR1,TR2の深さ300μmかつトレンチTR3なしの条件に対応し、線E3aはボール径300μmかつトレンチTR1~TR3の深さ200μmの条件に対応し、線E3bはボール径300μmかつトレンチTR1,TR2の深さ300μmかつトレンチTR3の深さ200μmの条件に対応する。
<Simulation>
The simulation results of the influence of the structure of the trench TR (see FIG. 5) and the ball diameter of the solder balls on the high-frequency transmission characteristics will be described below with reference to FIGS. 6 to 8. In each figure, as a comparative example, the line E0a corresponds to the condition of the ball diameter of 300 μm and no trench, and the line E0b corresponds to the condition of the ball diameter of 200 μm and no trench. Further, as an example, the wire E2a corresponds to the condition that the ball diameter is 300 μm and the depths of the trenches TR1 and TR2 are 200 μm and there is no trench TR3, and the wire E2b has a ball diameter of 300 μm and the depths of the trenches TR1 and TR2 are 300 μm and the trench. Corresponding to the condition without TR3, the line E3a corresponds to the condition of the ball diameter of 300 μm and the depth of the trenches TR1 to TR3 of 200 μm, and the line E3b corresponds to the condition of the ball diameter of 300 μm and the depth of the trenches TR1 and TR2 of 300 μm and the depth of the trench TR3. It corresponds to the condition of 200 μm.
 図6は、特性インピーダンスを時間領域反射(TDR:Time Domain Reflectometry)として示すシミュレーション結果を示すグラフ図である。TDRの時間軸は空間軸とみなすことができ、図中、おおよそ50~65psの範囲がBGA90近傍の位置に相当する。比較例としての線E0a(ボール径300μmかつトレンチなし)を参照して、おおよそ50~65psで特性インピーダンスの著しい局所的低下が見られ、これは特性インピーダンスの著しい不整合につながっている。比較例としての線E0b(ボール径200μmかつトレンチなし)を参照して、ボール径を300μmから200μmに低減することで、この不整合が緩和されている。しかしながら、前述したように、ボール径が小さいと実装信頼性の低下が懸念される。これに対して実施例(線E2a、線E2b、線E3aおよび線E3b)によれば、300μmのボール径を用いつつも特性インピーダンスの不整合が緩和されている。 FIG. 6 is a graph showing a simulation result showing the characteristic impedance as a time domain reflection (TDR: Time Domain Reflectometry). The time axis of TDR can be regarded as the spatial axis, and in the figure, the range of about 50 to 65 ps corresponds to the position near BGA90. With reference to line E0a (ball diameter 300 μm and no trench) as a comparative example, a significant local drop in characteristic impedance is seen at approximately 50-65 ps, which leads to a significant mismatch in characteristic impedance. This inconsistency is mitigated by reducing the ball diameter from 300 μm to 200 μm with reference to line E0b (ball diameter 200 μm and no trench) as a comparative example. However, as described above, if the ball diameter is small, there is a concern that the mounting reliability may be lowered. On the other hand, according to the embodiment (line E2a, line E2b, line E3a and line E3b), the mismatch of the characteristic impedance is alleviated while using the ball diameter of 300 μm.
 図7は、反射係数と周波数との関係のシミュレーション結果を示すグラフ図である。比較例としての線E0a(ボール径300μmかつトレンチなし)は、おおよそ20~60GHzの範囲で、他のいずれの例に比しても、より大きな反射係数を有しており、これは好適でない伝送特性を意味する。比較例としての線E0b(ボール径200μmかつトレンチなし)を参照して、ボール径を300μmから200μmに低減することで反射係数が低減されている。しかしながら、前述したように、ボール径が小さいと実装信頼性の低下が懸念される。これに対して実施例(線E2a、線E2b、線E3aおよび線E3b)によれば、300μmのボール径を用いつつも反射係数が低減されている。反射係数の低減は、BGA90近傍で特性インピーダンスがより整合されたためと考えられる。 FIG. 7 is a graph showing the simulation results of the relationship between the reflection coefficient and the frequency. The comparative example line E0a (ball diameter 300 μm and no trench) has a higher reflectance in the range of approximately 20-60 GHz than any other example, which is unsuitable for transmission. Means a characteristic. With reference to line E0b (ball diameter 200 μm and no trench) as a comparative example, the reflectance coefficient is reduced by reducing the ball diameter from 300 μm to 200 μm. However, as described above, if the ball diameter is small, there is a concern that the mounting reliability may be lowered. On the other hand, according to Examples (Line E2a, Line E2b, Line E3a and Line E3b), the reflectance coefficient is reduced while using a ball diameter of 300 μm. It is considered that the reduction of the reflectance coefficient is due to the characteristic impedance being more matched in the vicinity of BGA90.
 図8は、伝送係数と周波数との関係のシミュレーション結果を示すグラフ図である。比較例としての線E0a(ボール径300μmかつトレンチなし)は、おおよそ60GHz以下の範囲で、他のいずれの例に比しても、より小さな伝送係数を有しており、これは好適でない伝送特性を意味する。比較例としての線E0b(ボール径200μmかつトレンチなし)を参照して、ボール径を300μmから200μmに低減することで伝送係数が増大されている。しかしながら、前述したように、ボール径が小さいと実装信頼性の低下が懸念される。これに対して実施例(線E2a、線E2b、線E3aおよび線E3b)によれば、300μmのボール径を用いつつも伝送係数が増大されている。伝送係数の増大は、BGA90近傍での信号反射が低減されたためと考えられる。 FIG. 8 is a graph showing the simulation results of the relationship between the transmission coefficient and the frequency. The wire E0a (ball diameter 300 μm and no trench) as a comparative example has a smaller transmission coefficient than any other example in the range of about 60 GHz or less, which is an unsuitable transmission characteristic. Means. With reference to line E0b (ball diameter 200 μm and no trench) as a comparative example, the transmission coefficient is increased by reducing the ball diameter from 300 μm to 200 μm. However, as described above, if the ball diameter is small, there is a concern that the mounting reliability may be lowered. On the other hand, according to Examples (Line E2a, Line E2b, Line E3a and Line E3b), the transmission coefficient is increased while using a ball diameter of 300 μm. The increase in the transmission coefficient is considered to be due to the reduction of signal reflection in the vicinity of BGA90.
 この発明は詳細に説明されたが、上記した説明は、すべての局面において、例示であって、この発明がそれに限定されるものではない。例示されていない無数の変形例が、この発明の範囲から外れることなく想定され得るものと解される。 Although the present invention has been described in detail, the above description is exemplary in all aspects and the invention is not limited thereto. It is understood that innumerable variations not illustrated can be assumed without departing from the scope of the present invention.
 10 :接地部
 11 :第1信号線路
 12 :第2信号線路
 13 :第3信号線路
 14 :第4信号線路
 20 :接地領域
 20i :介在部
 20n :非介在部
 21 :第1パッド
 22 :第2パッド
 23 :第3パッド
 24 :第4パッド
 30~34 :接続端
 80 :基体
 90 :BGA
 91 :はんだボール(導電性ボール)
 100 :配線構造
 100,100V :パッケージ(配線構造)
 101 :底部
 102 :枠部
 110 :貫通孔部
 131 :第1差動線路
 132 :第2差動線路
 200 :プリント基板(回路基板)
 210,211 :ビア電極
 220,221,230,231 :回路パターン
 280 :基体
 300 :電子部品
 302 :光学部品
 310 :光ファイバ
 400 :蓋体
 900 :電子機器
 CV :空間
 ED :縁
 R1 :第1領域
 R2 :第2領域
 R3 :第3領域
 SM :実装面
 SP :対向面
 TR,TR1~TR3 :トレンチ
10: Grounding part 11: 1st signal line 12: 2nd signal line 13: 3rd signal line 14: 4th signal line 20: Grounding area 20i: Intervening part 20n: Non-intervening part 21: 1st pad 22: 2nd Pad 23: 3rd pad 24: 4th pad 30 to 34: Connection end 80: Base 90: BGA
91: Solder ball (conductive ball)
100: Wiring structure 100, 100V: Package (wiring structure)
101: Bottom 102: Frame 110: Through hole 131: First differential line 132: Second differential line 200: Printed circuit board (circuit board)
210, 211: Via electrode 220, 211,230,231: Circuit pattern 280: Base 300: Electronic component 302: Optical component 310: Optical fiber 400: Lid 900: Electronic device CV: Spatial ED: Edge R1: First region R2: 2nd area R3: 3rd area SM: Mounting surface SP: Facing surface TR, TR1 to TR3: Trench

Claims (13)

  1.  回路基板上へボールグリッドアレイを用いて実装されることになる配線構造であって、
     誘電体からなり、前記回路基板に対向することになる対向面を有する基体と、
     前記基体中に設けられ、前記対向面に達し、第1信号線路および第2信号線路を有する第1差動線路と、
     前記基体中に設けられ、前記対向面に達し、第3信号線路および第4信号線路を有する第2差動線路と、
     前記対向面上に設けられ、接地電位が付与されることになる接地領域と、
     前記対向面上に設けられ、前記第1信号線路に接続された第1パッドと、
     前記対向面上に設けられ、前記第2信号線路に接続された第2パッドと、
     前記対向面上に設けられ、前記接地領域を介して前記第2パッドと隣り合い、前記第3信号線路に接続された第3パッドと、
     前記対向面上に設けられ、前記第4信号線路に接続された第4パッドと、
    を備え、
     前記接地領域は、前記第2パッドと前記第3パッドとの間の介在部と、前記介在部から外れた非介在部とを含み、
     前記基体の前記対向面は、前記第1パッドと前記第2パッドとの間の第1領域と、前記第2パッドと前記介在部との間の第2領域と、前記第1パッドおよび前記第2パッドの各々と前記非介在部との間の第3領域とを含み、
     前記基体の前記対向面は、前記第1領域、前記第2領域および前記第3領域の少なくともいずれかにトレンチを有している、
    配線構造。
    It is a wiring structure that will be mounted on a circuit board using a ball grid array.
    A substrate made of a dielectric and having an opposing surface that faces the circuit board,
    A first differential line provided in the substrate, reaching the opposite surface, and having a first signal line and a second signal line.
    A second differential line provided in the substrate, reaching the opposite surface, and having a third signal line and a fourth signal line.
    A grounding region provided on the facing surface to which a grounding potential is applied, and a grounding region.
    A first pad provided on the facing surface and connected to the first signal line, and
    A second pad provided on the facing surface and connected to the second signal line, and
    A third pad provided on the facing surface, adjacent to the second pad via the grounding region, and connected to the third signal line,
    A fourth pad provided on the facing surface and connected to the fourth signal line, and
    With
    The ground contact area includes an intervening portion between the second pad and the third pad, and a non-intervening portion deviating from the intervening portion.
    The facing surfaces of the substrate include a first region between the first pad and the second pad, a second region between the second pad and the intervening portion, the first pad and the first pad. Includes a third region between each of the two pads and the non-intervening portion.
    The facing surface of the substrate has a trench in at least one of the first region, the second region, and the third region.
    Wiring structure.
  2.  前記トレンチは少なくとも前記第1領域に位置する、請求項1に記載の配線構造。 The wiring structure according to claim 1, wherein the trench is located at least in the first region.
  3.  前記トレンチは少なくとも前記第2領域に位置する、請求項1または2に記載の配線構造。 The wiring structure according to claim 1 or 2, wherein the trench is located at least in the second region.
  4.  前記トレンチは少なくとも前記第1領域および前記第2領域に位置する、請求項1に記載の配線構造。 The wiring structure according to claim 1, wherein the trench is located at least in the first region and the second region.
  5.  前記トレンチは少なくとも前記第1領域、前記第2領域および前記第3領域に位置する、請求項1に記載の配線構造。 The wiring structure according to claim 1, wherein the trench is located at least in the first region, the second region, and the third region.
  6.  前記対向面は縁を有しており、前記対向面上において、前記第1パッド、前記第2パッド、前記第3パッドおよび前記第4パッドの各々は前記縁に隣接している、請求項1から5のいずれか1項に記載の配線構造。 The facing surface has an edge, and each of the first pad, the second pad, the third pad, and the fourth pad is adjacent to the edge on the facing surface, claim 1. The wiring structure according to any one of 5 to 5.
  7.  前記基体はセラミックスからなる、請求項1から6のいずれか1項に記載の配線構造。 The wiring structure according to any one of claims 1 to 6, wherein the substrate is made of ceramics.
  8.  前記第1パッド、前記第2パッド、前記第3パッド、前記第4パッドおよび前記接地領域の各々の上に、前記ボールグリッドアレイを構成する導電性ボールをさらに備える、請求項1から7のいずれか1項に記載の配線構造。 Any of claims 1 to 7, further comprising conductive balls constituting the ball grid array on each of the first pad, the second pad, the third pad, the fourth pad, and the ground contact area. The wiring structure described in item 1.
  9.  前記導電性ボールははんだボールである、請求項8に記載の配線構造。 The wiring structure according to claim 8, wherein the conductive ball is a solder ball.
  10.  前記導電性ボールの体積と等しい体積を有する球の直径をボール径と定義したとき、前記トレンチは前記ボール径の1/3以上かつ前記ボール径以下の深さを有している、請求項8または9に記載の配線構造。 8. When the diameter of a sphere having a volume equal to the volume of the conductive ball is defined as the ball diameter, the trench has a depth of 1/3 or more of the ball diameter and less than or equal to the ball diameter. Or the wiring structure according to 9.
  11.  前記トレンチは100μm以上かつ300μm以下の深さを有している、請求項1から10のいずれか1項に記載の配線構造。 The wiring structure according to any one of claims 1 to 10, wherein the trench has a depth of 100 μm or more and 300 μm or less.
  12.  前記基体は、少なくとも1つの電子部品が実装されることになる実装面と、前記実装面上の空間を囲む枠部とを有している、請求項1から11のいずれか1項に記載の配線構造。 The substrate according to any one of claims 1 to 11, wherein the substrate has a mounting surface on which at least one electronic component is to be mounted and a frame portion surrounding the space on the mounting surface. Wiring structure.
  13.  前記少なくとも1つの電子部品は光学部品を含み、前記枠部は貫通孔部および透光部の少なくともいずれかを有している、請求項12に記載の配線構造。 The wiring structure according to claim 12, wherein the at least one electronic component includes an optical component, and the frame portion has at least one of a through hole portion and a translucent portion.
PCT/JP2020/036178 2019-12-26 2020-09-25 Wiring structure WO2021131192A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150467A (en) * 2003-11-17 2005-06-09 Kyocera Corp Semiconductor device
JP2014135372A (en) * 2013-01-10 2014-07-24 Mitsubishi Electric Corp Package for housing semiconductor element
JP2016531439A (en) * 2013-08-08 2016-10-06 インヴェンサス・コーポレイション Ultra-high performance interposer
JP2019114689A (en) * 2017-12-25 2019-07-11 京セラ株式会社 High frequency substrate, high frequency package, and high frequency module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005150467A (en) * 2003-11-17 2005-06-09 Kyocera Corp Semiconductor device
JP2014135372A (en) * 2013-01-10 2014-07-24 Mitsubishi Electric Corp Package for housing semiconductor element
JP2016531439A (en) * 2013-08-08 2016-10-06 インヴェンサス・コーポレイション Ultra-high performance interposer
JP2019114689A (en) * 2017-12-25 2019-07-11 京セラ株式会社 High frequency substrate, high frequency package, and high frequency module

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