WO2021129542A1 - 集成芯片及其制造方法、全彩集成芯片和显示面板 - Google Patents

集成芯片及其制造方法、全彩集成芯片和显示面板 Download PDF

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Publication number
WO2021129542A1
WO2021129542A1 PCT/CN2020/137776 CN2020137776W WO2021129542A1 WO 2021129542 A1 WO2021129542 A1 WO 2021129542A1 CN 2020137776 W CN2020137776 W CN 2020137776W WO 2021129542 A1 WO2021129542 A1 WO 2021129542A1
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Prior art keywords
layer
light
integrated chip
electrodes
electrode
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PCT/CN2020/137776
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English (en)
French (fr)
Inventor
赵强
秦快
郭恒
王昌奇
谢宗贤
范凯亮
蒋纯干
Original Assignee
佛山市国星光电股份有限公司
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Priority claimed from CN201911358755.8A external-priority patent/CN113035854A/zh
Priority claimed from CN201922390051.0U external-priority patent/CN211295128U/zh
Application filed by 佛山市国星光电股份有限公司 filed Critical 佛山市国星光电股份有限公司
Priority to US17/788,151 priority Critical patent/US20230029972A1/en
Publication of WO2021129542A1 publication Critical patent/WO2021129542A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/507—Wavelength conversion elements the elements being in intimate contact with parts other than the semiconductor body or integrated with parts other than the semiconductor body

Definitions

  • the present invention relates to the field of display technology, in particular to an integrated chip and a manufacturing method thereof, a full-color integrated chip and a display panel.
  • Micro LED display As an emerging display technology, Micro LED display has obvious advantages in terms of high brightness, fast response time, high resolution, high color gamut, and long life compared to LCD and OLED. Therefore, Micro LED display brings significant advantages to the field of display technology. A revolution in technological innovation.
  • the distance between the positive and negative electrodes of the light-emitting chip becomes smaller, which increases the requirements for the processing accuracy of the circuit substrate and the bonding process.
  • the size of a single light-emitting chip is small, since each light-emitting chip has positive and negative electrodes, each light-emitting chip needs to be independently controlled.
  • the complexity of the circuit substrate design increases , The substrate design becomes more difficult.
  • the main purpose of the present invention is to provide an integrated chip and a manufacturing method thereof, a full-color integrated chip and a display panel, so as to solve the cumbersome manufacturing process of the Micro LED display panel in the prior art, and not only greatly reduce the production and processing of the display panel Efficiency affects the production period of the display screen, and will reduce the yield of the display panel due to the low yield rate of the laid chips, resulting in the problem of low production efficiency of the display screen.
  • the integrated chip adopts a common electrode structure, which reduces the number of electrodes of the integrated chip as a whole and increases the area of a single electrode compared with the traditional light-emitting chip with independent electrodes.
  • the integrated chip has a small number of wires, low transfer difficulty, and display
  • the panel circuit substrate has the characteristics of low difficulty in design and low precision of circuit substrate processing, and has good practicability.
  • a method for manufacturing an integrated chip which is used for forming and processing the electrode structure of the integrated chip, including: step S1, fabricating light-emitting parts, and making the light-emitting parts include a matrix distributed N ⁇ m light-emitting unit groups, where n is the number of rows, m is the number of columns, and n and m are both positive integers greater than or equal to 1, and each light-emitting unit group includes x ⁇ y light-emitting units distributed in a matrix Unit, where x is the number of rows, y is the number of columns, and x and y are both positive integers greater than or equal to 1.
  • the light-emitting unit includes an a-pole electrode and a b-pole electrode;
  • the a-pole electrodes are electrically connected together to form m ⁇ y first electrodes, and the b-pole electrodes of the same row of light-emitting units in the same row of light-emitting unit groups are respectively electrically connected to form n ⁇ x second electrodes; step S2, electrically lead m ⁇ y first electrodes and n ⁇ x second electrodes to the conductive ends to form m ⁇ y first lead electrodes and n ⁇ x second lead electrodes.
  • the pin electrode and the second pin electrode are used for electrical connection with the circuit substrate.
  • a-pole electrodes of the light-emitting units of the same row of the same row of light-emitting unit groups are electrically connected by evaporation or deposition to form m ⁇ y first electrodes
  • the b-electrodes of the light-emitting units of the same row of the same row of light-emitting unit groups are electrically connected by evaporation or deposition to form n ⁇ x second electrodes.
  • step S2 includes: step S21, electrically leading the m ⁇ y first electrodes to the peripheral edges of the integrated chip to form m ⁇ y first lead electrodes; step S22, adding n ⁇ x The second electrodes respectively electrically lead the conductive ends to the peripheral edges of the integrated chip to form n ⁇ x second pin electrodes; and make m ⁇ y first pin electrodes and n ⁇ x second pin electrodes It is distributed in sequence around the edge of the integrated chip.
  • step S22 both m and n are set to 2, x is set to 3, and y is set to 1, and the two first electrodes and six second electrodes are led to the peripheral edges of the integrated chip to form conductive ends. Two first pin electrodes and six second pin electrodes.
  • step S2 an N layer of insulating protection layer is deposited or evaporated on the surface where the first electrode and the second electrode of the light-emitting part are located; and sequentially on the surface of the insulating protection layer away from the first electrode and the second electrode
  • the metal circuit layer is arranged by evaporation or deposition to form an N-layer metal circuit layer; the first electrode, the second electrode and the N-layer metal circuit layer are electrically connected through the metal vias on the insulating protection layer, where N is greater than or A positive integer equal to 2.
  • an insulating layer is provided on the side of the Nth metal circuit layer away from the insulating protection layer, and the insulating layer covers the metal traces and metal vias on the Nth metal circuit layer.
  • the Nth metal circuit layer includes m ⁇ y first pin electrodes and n ⁇ x second pin electrodes.
  • an identification mark for identifying the polarity of the first pin electrode or the polarity of the second pin electrode is provided on the insulating protection layer in contact with the Nth metal circuit layer.
  • the insulating protection layer is a silicon dioxide layer or a silicon nitride layer.
  • the insulating protection layer is formed by printing, deposition or evaporation.
  • an integrated chip is provided, which is manufactured by the above-mentioned integrated chip manufacturing method.
  • an integrated chip including: a light-emitting portion, the light-emitting portion includes a light-emitting layer and an electrode structure, the electrode structure is electrically connected to the light-emitting layer; a pin portion, the pin portion is disposed under the electrode structure , And electrically connected to the electrode structure; the pin portion includes N layers of metal circuit layers and insulating protective layers stacked in sequence, wherein an insulating protective layer is provided between the electrode structure and the adjacent metal circuit layer, and An insulating protective layer is arranged between two adjacent metal circuit layers, and the insulating protective layer is provided with metal vias for conductors to pass through.
  • the N metal circuit layers are electrically connected by the conductors, where N ⁇ 2.
  • the light-emitting layer includes n ⁇ m light-emitting unit groups distributed in a matrix, where n is the number of rows, m is the number of columns, and both n and m are positive integers greater than or equal to 1, and the light-emitting unit groups include a matrix Distributed x ⁇ y light-emitting units, where x is the number of rows, y is the number of columns, and x and y are both positive integers greater than or equal to 1; the electrode structure includes electrodes electrically connected to the multiple light-emitting units in a one-to-one correspondence Each electrode group includes a-pole electrodes and b-pole electrodes.
  • the a-pole electrodes of the light-emitting unit in the same column of the same column of light-emitting unit groups are electrically connected together to form m ⁇ y first electrodes; the same row of light-emitting unit groups are the same
  • the b-pole electrodes of the row light-emitting units are respectively electrically connected to form n ⁇ x second electrodes.
  • the pin part forms a first pin electrode and a second pin electrode at the Nth metal circuit layer, wherein the first pin electrode is m ⁇ y connected to the plurality of first electrodes in a one-to-one correspondence.
  • the second pin electrodes are n ⁇ x corresponding to the plurality of second electrodes one-to-one.
  • an identification mark for identifying the polarity of the first pin electrode or the second pin electrode is provided on the insulating protection layer in contact with the Nth metal circuit layer.
  • an insulating layer is provided on the side of the Nth metal circuit layer away from the insulating protection layer, and the insulating layer covers the metal traces and metal vias on the Nth metal circuit layer.
  • the integrated chip further includes a plurality of light processing parts, the plurality of light processing parts are distributed on the light emitting part in a matrix form along the light emitting surface of the integrated chip, and are located above the light emitting layer, and the multiple light processing parts and The light-emitting units are arranged in one-to-one correspondence, and the light-emitting part also includes a P-GaN layer and a metal contact layer stacked from top to bottom under the light-emitting layer.
  • the electrode structure includes a positive electrode and a negative electrode. The negative electrode is electrically connected to the light-emitting unit, and the positive electrode passes through the metal.
  • the contact layer and the P-GaN layer are electrically connected to the light emitting unit.
  • the light-emitting part further includes an n-GaN layer, a buffer layer and a first passivation layer, and the n-GaN layer, the buffer layer and the first passivation layer are sequentially stacked and arranged between the light-emitting layer and the light processing part from bottom to top;
  • the part also includes a DBR reflective layer and a second passivation layer, wherein the DBR reflective layer covers the buffer layer, the n-GaN layer and the outer peripheral side of the electrode structure and the bottom of the metal contact layer, and the second passivation layer covers the DBR reflective layer
  • the second passivation layer is an insulating protective layer on the outer peripheral side and the bottom of the device.
  • a full-color integrated chip including: the above-mentioned integrated chip; a light processing section, the light processing section is arranged above the integrated chip, and the light processing section includes red quantum dot primitives and green quantum dots.
  • a barrier wall is arranged between any two adjacent primitives among the dot primitives and the light-transmitting complementary color primitives, the red quantum dot primitives, the green quantum dot primitives, and the light-transmitting complementary color primitives.
  • the integrated chip is a blue integrated chip
  • the light-transmitting complementary color element is a transparent scattering quantum dot layer.
  • the integrated chip is an ultraviolet light integrated chip
  • the light-transmitting complementary color element is a blue quantum dot layer.
  • a display panel including: a circuit substrate and a plurality of integrated chips, the integrated chip is the above-mentioned integrated chip, and the plurality of integrated chips are arranged on the circuit substrate in a matrix form; a packaging adhesive layer , The packaging glue layer covers the circuit substrate and encapsulates multiple integrated chips.
  • a display panel including: a circuit substrate and a plurality of full-color integrated chips, the full-color integrated chip is the above-mentioned full-color integrated chip, and the plurality of full-color integrated chips are arranged in a matrix form On the circuit substrate; an encapsulation adhesive layer, which covers the circuit substrate and encapsulates a plurality of full-color integrated chips.
  • an integrated chip with a new structure can be manufactured by providing a specific integrated chip manufacturing method, which can quickly and conveniently manufacture the electrode structure of the integrated chip, which not only ensures the light-emitting characteristics of the integrated chip, but also Ensure the light-emitting performance of the display panel, and make the integrated chip have multiple light-emitting points in an integrated form, so that in the process of manufacturing the display panel, the number of transfers of the integrated chip is greatly reduced, thereby helping to improve the production and processing efficiency of the display panel , To shorten the production period of the display screen, and at the same time avoid reducing the yield of the display panel due to the low yield of the laying chip, and improve the production efficiency of the display screen.
  • the integrated chip adopts a common electrode structure, which reduces the number of electrodes of the integrated chip as a whole compared with the traditional light-emitting chip with independent electrodes; the integrated chip has a small number of wires, low transfer difficulty, and low difficulty in designing display panel circuit substrates.
  • the circuit board has the characteristics of low processing precision requirements, and has good practicability.
  • FIG. 1 shows a schematic diagram of a distribution state of a plurality of first electrodes, a plurality of second electrodes, and a plurality of light-emitting unit groups in a process of manufacturing a light-emitting part of an integrated chip according to an alternative embodiment of the present invention
  • FIG. 2 shows a schematic diagram of a distribution state of a plurality of first electrodes and a plurality of second electrodes after covering a plurality of light-emitting unit groups in FIG. 1;
  • Figure 3 shows the distribution of the multiple first pin electrodes and the multiple second pin electrodes after the multiple first electrodes and multiple second electrodes in Figure 2 electrically lead the conductive ends to the peripheral edges of the integrated chip State diagram;
  • FIG. 4 shows a schematic diagram of the distribution state of a plurality of first pin electrodes and a plurality of second pin electrodes after covering the electrically lead-out conductive ends in FIG. 3;
  • FIG. 5 shows a schematic diagram of a distribution state of a plurality of first pin electrodes and a plurality of second pin electrodes in a process of manufacturing a light-emitting part of an integrated chip according to another alternative embodiment of the present invention
  • FIG. 6 shows a schematic structural diagram of a display panel according to an optional embodiment of the present invention.
  • FIG. 7 shows a schematic structural diagram of the display panel in FIG. 6 when multiple integrated chips are not packaged with a packaging glue layer
  • Fig. 8 shows a schematic structural diagram of an integrated chip according to an alternative embodiment of the present invention.
  • FIG. 9 shows a schematic diagram of the state of the integrated chip in FIG. 8 viewed from a top perspective
  • Fig. 10 shows a schematic structural diagram of an integrated chip according to an alternative embodiment of the present invention.
  • FIG. 11 shows a schematic structural diagram of a display panel according to an optional embodiment of the present invention.
  • FIG. 12 shows a schematic structural diagram of the display panel in FIG. 11 when multiple integrated chips are not packaged with a packaging glue layer.
  • Circuit substrate 2. Integrated chip; 3. Encapsulation layer; 100, light-emitting part; 10, light-emitting layer; 20, electrode structure; 200, light processing part; 201, red quantum dot element; 202, green quantum dot Primitive; 203, light-transmitting complementary color primitive; 300, light-blocking wall layer; 301, groove; 400, pin part; 11, light-emitting unit group; 200, light processing part; 204, light-emitting surface; 30, P- GaN layer; 40, metal contact layer; 21, positive electrode; 22, negative electrode; 50, n-GaN layer; 60, buffer layer; 70, first passivation layer; 80, DBR reflective layer; 90, second passivation layer .
  • the present invention provides an integrated chip and a manufacturing method thereof, a full-color integrated chip and a display panel; it should be noted that the display panel includes a circuit substrate and a display panel disposed thereon. Multiple integrated chips or multiple full-color integrated chips on the above, wherein the integrated chip is the above-mentioned integrated chip and the following integrated chip, and the full-color integrated chip includes the above-mentioned integrated chip and the following integrated chip.
  • the manufacturing method of the integrated chip is used for forming and processing the electrode structure of the integrated chip, including: step S1, fabricating a light-emitting part, and making the light-emitting part include n ⁇ m light-emitting unit groups distributed in a matrix form , Where n is the number of rows, m is the number of columns, and both n and m are positive integers greater than or equal to 1.
  • Each light-emitting unit group includes x ⁇ y light-emitting units distributed in a matrix, where x is the number of rows , Y is the number of columns, and x and y are both positive integers greater than or equal to 1.
  • the light-emitting unit includes an a-pole electrode and a b-pole electrode; Together, to form m ⁇ y first electrodes, and electrically connect the b-pole electrodes of the same row of light-emitting units in the same row of light-emitting unit groups to form n ⁇ x second electrodes; step S2, add m ⁇ y One electrode and n ⁇ x second electrodes electrically lead out the conductive ends respectively to form m ⁇ y first pin electrodes and n ⁇ x second pin electrodes, the first pin electrode and the second pin electrode Used for electrical connection with the circuit board.
  • This application provides a specific integrated chip manufacturing method to manufacture an integrated chip with a new structure, which can quickly and conveniently manufacture the electrode structure of the integrated chip, which can not only ensure the light-emitting characteristics of the integrated chip, but also ensure the luminescence of the display panel. Performance, and enables the integrated chip to have multiple light-emitting points in an integrated form, thereby greatly reducing the number of transfers of the integrated chip in the process of manufacturing the display panel, which is beneficial to improve the production and processing efficiency of the display panel and shorten the display screen
  • the production period is to avoid lowering the yield of the display panel due to the low yield of the laid chips, and improve the production efficiency of the display screen.
  • the integrated chip adopts a common electrode structure, which reduces the number of electrodes of the integrated chip as a whole compared with the traditional light-emitting chip with independent electrodes; the integrated chip has a small number of wires, low transfer difficulty, and low difficulty in designing display panel circuit substrates.
  • the circuit board has the characteristics of low processing precision requirements, and has good practicability.
  • the a-pole electrodes of the light-emitting unit in the same column of the same column of the light-emitting unit group are electrically connected by evaporation or deposition to form m ⁇ y first electrodes, and the same row is formed by evaporation or deposition.
  • the b-pole electrodes of the light-emitting units in the same row of the light-emitting unit group are electrically connected to form n ⁇ x second electrodes.
  • step S2 includes: step S21, electrically lead the m ⁇ y first electrodes to the peripheral edges of the integrated chip to form m ⁇ y first lead electrodes; step S22: The n ⁇ x second electrodes electrically lead the conductive ends to the peripheral edges of the integrated chip to form n ⁇ x second pin electrodes; and make m ⁇ y first pin electrodes and n ⁇ x second pin electrodes.
  • the pin electrodes are sequentially spaced around the edge of the integrated chip. In this way, it is convenient to control the separation distance between two adjacent pin electrodes, avoid electrical interference between the pin electrodes, ensure the circuit stability of the integrated chip, and improve the display reliability of the display panel.
  • step S22 both m and n are set to 2, x is set to 3, and y is set to 1, and the two first electrodes and six second electrodes are connected to the integrated chip. Conductive ends are drawn from the peripheral edges to form two first pin electrodes and six second pin electrodes.
  • the integrated chip of this structure is not only convenient for processing and manufacturing, but also easy to electrically guide the first electrode and the second electrode to form pin electrodes, which is beneficial to ensure the electrical connection and installation of the integrated chip.
  • step S2 an N layer of insulating protection layer is deposited or evaporated on the surface where the first electrode and the second electrode of the light-emitting part are located; A metal circuit layer is provided on the surface of the layer by evaporation or deposition to form an N-layer metal circuit layer; the first electrode, the second electrode and the N-layer metal circuit layer are electrically connected through metal vias on the insulating protection layer, where N It is a positive integer greater than or equal to 2. In this way, it is advantageous to arrange the electrodes of the integrated chip according to the design requirements.
  • an insulating protective layer is provided between the electrode and the metal circuit layer and between two adjacent metal circuit layers.
  • an insulating layer is provided on the side of the Nth metal circuit layer away from the insulating protection layer, and the insulating layer covers the metal traces and metal vias on the Nth metal circuit layer. In this way, it is conducive to the electrical stability of the integrated chip and ensures that it is stably lit.
  • the Nth metal circuit layer includes m ⁇ y first pin electrodes and n ⁇ x second pin electrodes. It should also be noted that the first pin electrode and the second pin electrode are provided with an insulating layer, so that the plurality of pin electrodes can expose the insulating layer to facilitate subsequent connection with other components.
  • the insulating protection layer in contact with the Nth metal circuit layer is provided with an identification mark for identifying the polarity of the first pin electrode or the polarity of the second pin electrode.
  • an identification mark for identifying the polarity of the first pin electrode or the polarity of the second pin electrode.
  • a plurality of first pin electrodes and a plurality of second pin electrodes are sequentially spaced around the edge of the integrated chip; in this figure, the two pin electrodes labeled 3 and 4 are the first pins
  • the first pin electrode is the negative electrode
  • the six pin electrodes labeled 1, 2, and 5 to 8 are the second pin electrodes
  • the second pin electrode is the positive electrode.
  • the first pin electrode is located at the end of the first electrode in the length direction
  • the second pin electrode is located at the middle or end of the second electrode in the length direction;
  • the two lead electrodes marked 2 and 7 are the first lead electrodes
  • the first lead electrode is the negative electrode
  • the six lead electrodes marked 1, 3 to 6 and 8 are the second lead electrodes.
  • the pin electrode, and the second pin electrode is the positive electrode.
  • the insulating protection layer is a silicon dioxide layer or a silicon nitride layer.
  • the insulating protective layer is formed by printing, deposition or evaporation.
  • the integrated chip is manufactured by the above-mentioned integrated chip manufacturing method; and the full-color integrated chip includes the above-mentioned integrated chip and a light processing part, the light processing part is arranged above the integrated chip, and the light processing The part includes a red quantum dot primitive, a green quantum dot primitive and a light-transmitting complementary color primitive.
  • the red quantum dot primitive, a green quantum dot primitive and a light-transmitting complementary color primitive are arranged between any two adjacent primitives. Retaining wall. In this way, it is ensured that the integrated chip has the characteristic of stably emitting white light.
  • the integrated chip is a blue integrated chip
  • the light-transmitting complementary color element is a transparent scattering quantum dot layer.
  • the integrated chip is an ultraviolet light integrated chip
  • the light-transmitting complementary color element is a blue quantum dot layer.
  • the display panel includes a circuit substrate, a plurality of integrated chips and a packaging glue layer, the integrated chip is the above-mentioned integrated chip, and the plurality of integrated chips are arranged on the circuit substrate in the form of a matrix.
  • the packaging glue layer covers the circuit substrate and encapsulates a plurality of integrated chips.
  • the display panel includes a circuit substrate, a plurality of full-color integrated chips and a packaging glue layer, the full-color integrated chip is the above-mentioned full-color integrated chip, and the plurality of full-color integrated chips
  • the chips are arranged on the circuit substrate in the form of a matrix; the packaging glue layer covers the circuit substrate and encapsulates a plurality of full-color integrated chips.
  • the present invention provides an integrated chip.
  • the integrated chip can be manufactured by the above-mentioned integrated chip manufacturing method.
  • the display panel includes a circuit substrate 1 and a plurality of integrated chips 2 arranged in a matrix on the circuit substrate 1.
  • the integrated chips 2 are the above and below The integrated chip 2; FIG.
  • the display panel 6 includes a circuit substrate 1 and a plurality of full-color integrated chips arranged on the circuit substrate 1 in the form of a matrix.
  • the full-color integrated chip is the above-mentioned And the full-color integrated chip described below; of course, in the embodiment not shown, the packaging adhesive layer 3 covers the circuit substrate 1 and encapsulates multiple full-color integrated chips to ensure that multiple full-color integrated chips The sealed installation characteristics.
  • the integrated chip 2 includes a light-emitting part 100 and a pin part 400.
  • the light-emitting part 100 includes a light-emitting layer 10 and an electrode structure 20, and the electrode structure 20 is electrically connected to the light-emitting layer 10.
  • the pin part 400 is disposed under the electrode structure 20 and is electrically connected to the electrode structure 20; the pin part 400 includes N layers of metal circuit layers and insulating protection layers stacked in sequence, wherein the electrode structure 20 and the adjacent one An insulating protective layer is arranged between the metal circuit layers, and an insulating protective layer is arranged between two adjacent metal circuit layers.
  • the insulating protective layer is provided with metal vias for conductors to pass through.
  • the N-layer metal circuit layer It is electrically connected through a conductor, where N ⁇ 2.
  • the present application provides an integrated chip 2 with a new structure, which optimizes the specific structure of the lead part 400 of the integrated chip 2 that electrically interacts with the electrode structure. Under the premise of ensuring that the lead part 400 is easily formed and manufactured, it not only improves The electrical connection stability of the integrated chip 2 after installation is improved, and the single integrated chip 2 with the pin part 400 of the structure of the present application can have more light-emitting points or a larger light-emitting surface, which is beneficial to meet the preset requirements of the integrated chip 2
  • the light-emitting characteristics of the display panel is beneficial to reduce the number of integrated chips 2 mounted on the circuit substrate of the display panel, and in the process of manufacturing the display panel, the number of transfers of the integrated chip 2 is greatly reduced, thereby helping to improve the display panel
  • the production and processing efficiency of the display screen is shortened, and the yield rate of the integrated chip 2 is too low to reduce the yield of the display panel due to
  • the integrated chip 2 adopts a common electrode structure, which reduces the number of electrodes of the integrated chip 2 as a whole compared with the traditional light-emitting chip using independent electrodes; the integrated chip 2 has a small number of wires, low transfer difficulty, and a display panel circuit substrate 1. It has the characteristics of low design difficulty and low processing precision requirements of the circuit substrate 1, and has good practicability.
  • the light-emitting layer 10 includes n ⁇ m light-emitting unit groups 11 distributed in a matrix, where n is the number of rows and m is The number of columns, and both n and m are positive integers greater than or equal to 1.
  • the light-emitting unit group 11 includes x ⁇ y light-emitting units distributed in a matrix, where x is the number of rows, y is the number of columns, and both x and y Is a positive integer greater than or equal to 1;
  • the electrode structure 20 includes electrode groups electrically connected to a plurality of light-emitting units in a one-to-one correspondence, and each electrode group includes a-pole electrodes and b-pole electrodes, and the same row of light-emitting units in the same row of light-emitting unit groups 11
  • the a-pole electrodes of the light-emitting unit group 11 are electrically connected together to form m ⁇ y first electrodes;
  • the b-pole electrodes of the light-emitting unit in the same row of the same row of light-emitting unit group 11 are electrically connected to form n ⁇ x second electrodes.
  • the pin portion 400 forms a first pin electrode and a second pin electrode at the N-th metal circuit layer, where the first pin electrode is a one-to-one connection with a plurality of first electrodes. ⁇ y, and the second pin electrodes are n ⁇ x corresponding to the plurality of second electrodes one-to-one.
  • the pin part 400 includes two stacked metal circuit layers and two insulating protective layers, wherein an insulating protective layer is provided between the electrode structure 20 and the adjacent first metal circuit layer, and the corresponding An insulating protective layer is provided between two adjacent metal circuit layers, and the insulating protective layer is provided with metal vias for conductors to pass through;
  • the light-emitting layer 10 includes 4 light-emitting unit groups 11 and 4 light-emitting unit groups distributed in a matrix 11 is distributed in a 2 ⁇ 2 determinant, each light-emitting unit group 11 includes 3 light-emitting units distributed in a matrix, and the 3 light-emitting units are distributed in a 3 ⁇ 1 determinant.
  • an insulating protective layer in contact with the Nth metal circuit layer is provided with An identification mark that identifies the polarity of the first lead electrode or the second lead electrode.
  • an insulating layer is provided on the side of the Nth metal circuit layer away from the insulating protection layer, and the insulating layer covers the metal traces and metal vias on the Nth metal circuit layer.
  • the integrated chip 2 further includes a plurality of light processing parts 200, and the plurality of light processing parts 200 are distributed on the light emitting part 100 in a matrix along the light emitting surface 204 of the integrated chip, and are located on the light emitting layer 10. And a plurality of light processing parts 200 are arranged in a one-to-one correspondence with a plurality of light-emitting units.
  • the light-emitting part 100 also includes a P-GaN layer 30 and a metal contact layer 40 stacked from top to bottom under the light-emitting layer 10, and an electrode structure 20 includes a positive electrode 21 and a negative electrode 22, wherein the negative electrode 22 is electrically connected to the light emitting unit, and the positive electrode 21 is electrically connected to the light emitting unit through the metal contact layer 40 and the P-GaN layer 30.
  • the integrated chip 2 with this structure has a reasonable structure and stable light emission.
  • the light-emitting part 100 further includes an n-GaN layer 50, a buffer layer 60, and a first passivation layer 70.
  • the n-GaN layer 50, the buffer layer 60 and the first passivation layer 70 are sequentially stacked from bottom to top. Between the light-emitting layer 10 and the light processing part 200.
  • the negative electrode of the electrode structure 20 is electrically connected to the n-GaN layer so as to be electrically connected to the light-emitting unit.
  • the light emitting part 100 further includes a DBR reflective layer 80 and a second passivation layer 90, wherein the DBR reflective layer 80 covers the buffer layer 60, the n-GaN layer 50, the outer peripheral side of the electrode structure 20, and the bottom of the metal contact layer 40.
  • the second passivation layer 90 covers the outer peripheral side and the bottom of the DBR reflective layer 80, and the second passivation layer 90 is an insulating protective layer.
  • the full-color integrated chip provided by the present application is the above-mentioned integrated chip 2.
  • the light processing unit 200 of the integrated chip includes a red quantum dot element 201, a green quantum dot element 202, and a light-transmitting complementary color element.
  • Element 203, a retaining wall is provided between any two adjacent elements of the red quantum dot element 201, the green quantum dot element 202, and the light-transmitting complementary color element 203.
  • the integrated chip is a blue integrated chip
  • the light-transmitting complementary color element 203 is a transparent scattering quantum dot layer.
  • the integrated chip is an ultraviolet light integrated chip
  • the light-transmitting complementary color element 203 is a blue quantum dot layer.
  • the light-emitting part 100 includes a light-blocking wall layer 300 located above the light-emitting layer 10, and the light-blocking wall layer 300 is formed with a plurality of particles distributed in a matrix along the light-emitting surface 204.
  • the red quantum dot element 201, the green quantum dot element 202, and the light-transmitting complementary color element 203 are all formed in the respective corresponding grooves 301 by spraying, and the grooves 301 are filled.
  • the groove 301 is formed on the light barrier layer 300 by a photolithography process and penetrates the light barrier layer 300.
  • the depth of the groove 301 is greater than or equal to 1 um and less than or equal to 1000 um.
  • FIG. 10 in a schematic structural diagram of an integrated chip according to another embodiment of the present invention, those skilled in the art know that the insulating member located under the n-GaN layer 50 is the third passivation layer 51.
  • the applicant actively corrected the form of the filler of the n-GaN layer 50 and the filler of the third passivation layer 51, and added a mark to the insulating member.
  • reference numerals are added to FIG. 11 and FIG. 12, and the form of the filler representing the n-GaN layer 50 and the third passivation layer 51 is actively corrected.
  • spatial relative terms can be used here, such as “above”, “above”, “above the surface”, “above”, etc., to describe as shown in the figure Shows the spatial positional relationship between one device or feature and other devices or features. It should be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the device in the drawing is turned upside down, then a device described as “above other devices or structures” or “above other devices or structures” will then be positioned as “below the other devices or structures” or “on Under other devices or structures”. Thus, the exemplary term “above” may include both orientations “above” and “below”. The device can also be positioned in other different ways (rotated by 90 degrees or in other orientations), and the relative description of the space used here will be explained accordingly.

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Abstract

一种集成芯片（2）及其制造方法、全彩集成芯片和显示面板，其中，集成芯片（2）的制作方法用于成型加工集成芯片（2）的电极结构（20），包括步骤S1，制作发光部（100），并使发光部（100）包括以矩阵形式分布的多个发光单元组（11），步骤S2，将发光部（100）的多个第一电极和多个第二电极分别电性引出导电端，以形成多个第一引脚电极和多个第二引脚电极，第一引脚电极和第二引脚电极用于与电路基板（1）电性连接。主要目的在于提供以解决现有技术中的Micro LED显示面板的制作过程繁琐，不仅大大地降低了显示面板的生产加工效率，影响了显示屏的生产工期，而且会因铺设芯片的良率过低而降低显示面板的成品合格率，导致显示屏的生产效率低下的问题。

Description

集成芯片及其制造方法、全彩集成芯片和显示面板
本申请要求于2019年12月25日提交至中国国家知识产权局，申请号为201911358755.8，发明名称为“集成芯片及其制造方法、全彩集成芯片和显示面板”的专利申请以及于2019年12月25日提交至中国国家知识产权局，申请号为201922390051.0，发明名称为“集成芯片、全彩集成芯片和显示面板”的专利申请的优先权。
技术领域
本发明涉及显示技术领域，具体而言，涉及一种集成芯片及其制造方法、全彩集成芯片和显示面板。
背景技术
Micro LED显示作为一个新兴的显示技术，相比LCD，OLED，在高亮度、快速响应时间、高分辨率、高色域以及长寿命等方面优势明显，因此，Micro LED显示为显示技术领域带来了一次技术革新革命。
Micro LED显示面板在制造过程中，需要以转移芯片的方式将数量繁多的芯片依次铺设到电路基板上，频繁的转移芯片操作导致显示面板的制作过程繁琐，不仅大大地降低了显示面板的生产加工效率，影响了显示屏的生产工期，而且会因铺设芯片的良率过低而降低显示面板的成品合格率，导致显示屏的生产效率低下。
另外，当发光芯片的尺寸较小时，发光芯片的正负电极之间的间距变小，对电路基板的加工精度要求以及固晶工艺的要求增加。同时，单颗发光芯片尺寸较小时，由于每个发光芯片都具有正负两个电极，每个发光芯片均需要独立控制，当基板上的发光芯片设置数量较多时，电路基板设计的复杂度增加，基板设计难度变大。
发明内容
本发明的主要目的在于提供一种集成芯片及其制造方法、全彩集成芯片和显示面板，以解决现有技术中的Micro LED显示面板的制作过程繁琐，不仅大大地降低了显示面板的生产加工效率，影响了显示屏的生产工期，而且会因铺设芯片的良率过低而降低显示面板的成品合格率，导致显示屏的生产效率低下的问题。此外，集成芯片采用公共电极结构，与传统的发光芯片采用独立电极的方式相对比，减少了集成芯片整体的电极数量，增大了单个电极面积；集成芯片具有接线数量少、转移难度低、显示面板电路基板设计难度低、电路基板加工精度要求低等特点，具有良好的实用性。
为了实现上述目的，根据本发明的一个方面，提供了一种集成芯片的制造方法，用于成型加工集成芯片的电极结构，包括：步骤S1，制作发光部，并使发光部包括以矩阵形式分布的n×m个发光单元组，其中，n为行数，m为列数，且n和m均为大于或等于1的正整数， 各发光单元组包括以矩阵形式分布的x×y个发光单元，其中，x为行数，y为列数，且x和y均为大于或等于1的正整数，发光单元包括a极电极和b极电极；将同一列发光单元组的同一列发光单元的a极电极分别电连接在一起，以形成m×y个第一电极，将同一行发光单元组的同一行发光单元的b极电极分别电连接，以形成n×x个第二电极；步骤S2，将m×y个第一电极和n×x个第二电极分别电性引出导电端，以形成m×y个第一引脚电极和n×x个第二引脚电极，第一引脚电极和第二引脚电极用于与电路基板电性连接。
进一步地，使用蒸镀或沉积的方式将同一列发光单元组的同一列发光单元的a极电极分别电连接，以形成m×y个第一电极，
使用蒸镀或沉积的方式将同一行发光单元组的同一行发光单元的b极电极分别电连接，以形成n×x个第二电极。
进一步地，步骤S2包括：步骤S21，将m×y个第一电极分别向集成芯片的四周边缘电性引出导电端，以形成m×y个第一引脚电极；步骤S22，将n×x个第二电极分别向集成芯片的四周边缘电性引出导电端，以形成n×x个第二引脚电极；并使m×y个第一引脚电极和n×x个第二引脚电极绕集成芯片的边缘依次间隔分布。
进一步地，在步骤S22中，将m和n均设置为2，x设置为3，y设置为1，将两个第一电极和六个第二电极向集成芯片的四周边缘引出导电端以形成两个第一引脚电极和六个第二引脚电极。
进一步地，在步骤S2中，在发光部的第一电极和第二电极所在的表面上沉积或蒸镀N层绝缘保护层；以及依次在远离第一电极和第二电极的绝缘保护层表面上利用蒸镀或沉积的方法设置金属线路层，形成N层金属线路层；第一电极、第二电极和N层金属线路层通过绝缘保护层上的金属过孔电连接，其中，N为大于或等于2的正整数。
进一步地，第N层金属线路层上远离绝缘保护层的一侧设有绝缘层，绝缘层覆盖第N层金属线路层上的金属走线和金属过孔。
进一步地，第N层金属线路层包括m×y个第一引脚电极和n×x个第二引脚电极。
进一步地，与第N层金属线路层接触的绝缘保护层上设置有用于识别第一引脚电极的极性或第二引脚电极的极性的识别标记。
进一步地，绝缘保护层为二氧化硅层或氮化硅层。
进一步地，绝缘保护层通过印刷、沉积或蒸镀形成。根据本发明的另一方面，提供了一种集成芯片，由上述的集成芯片的制造方法制造而成。
根据本发明的另一方面，提供了一种集成芯片，包括：发光部，发光部包括发光层和电极结构，电极结构与发光层电连接；引脚部，引脚部设置于电极结构的下方，并与电极结构电连接；引脚部包括N层依次叠置的金属线路层和绝缘保护层，其中，电极结构和与其相邻的一层金属线路层之间设置有一层绝缘保护层，以及相邻的两层金属线路层之间设置有一层 绝缘保护层，绝缘保护层上开设有用于导体经过的金属过孔，N层金属线路层通过导体电连接，其中，N≥2。
进一步地，发光层包括呈矩阵分布的n×m个发光单元组，其中，n为行数，m为列数，且n和m均为大于或等于1的正整数，发光单元组包括呈矩阵分布的x×y个发光单元，其中，x为行数，y为列数，且x和y均为大于或等于1的正整数；电极结构包括与多个发光单元一一对应电连接的电极组，各电极组包括a极电极和b极电极，同一列发光单元组的同一列发光单元的a极电极分别电连接在一起，形成m×y个第一电极；同一行发光单元组的同一行发光单元的b极电极分别电连接，形成n×x个第二电极。
进一步地，引脚部在第N层金属线路层处形成第一引脚电极和第二引脚电极，其中，第一引脚电极为与多个第一电极一一对应连接的m×y个，第二引脚电极为与多个第二电极一一对应的n×x个。
进一步地，N＝2，m＝2，n＝2，x＝3，y＝1。
进一步地，与第N层金属线路层接触的绝缘保护层上设置有用于识别第一引脚电极或第二引脚电极的极性的识别标记。
进一步地，第N层金属线路层上远离绝缘保护层的一侧设有绝缘层，绝缘层覆盖第N层金属线路层上的金属走线和金属过孔。
进一步地，集成芯片还包括多个光处理部，多个光处理部沿集成芯片的发光面以矩阵的形式分布在发光部上，并位于发光层的上方，且多个光处理部与多个发光单元一一对应设置，发光部还包括由上至下层叠设置在发光层下方的P-GaN层和金属接触层，电极结构包括正极和负极，其中，负极与发光单元电连接，正极通过金属接触层和P-GaN层与发光单元电连接。
进一步地，发光部还包括n-GaN层、缓冲层和第一钝化层，n-GaN层、缓冲层和第一钝化层由下至上依次层叠设置在发光层和光处理部之间；发光部还包括DBR反射层和第二钝化层，其中，DBR反射层覆盖在缓冲层、n-GaN层和电极结构的外周侧以及金属接触层的底部，第二钝化层覆盖在DBR反射层的外周侧和底部，第二钝化层为一层绝缘保护层。
根据本发明的另一方面，提供了一种全彩集成芯片，包括：上述的集成芯片；光处理部，光处理部设置在集成芯片的上方，光处理部包括红色量子点基元、绿色量子点基元和透光补色基元，红色量子点基元、绿色量子点基元和透光补色基元中任意两个相邻的基元之间设置有挡墙。
进一步地，集成芯片为蓝光集成芯片，透光补色基元为透明散射量子点层。
进一步地，集成芯片为紫外光集成芯片，透光补色基元为蓝色量子点层。
根据本发明的另一方面，提供了一种显示面板，包括：电路基板和多个集成芯片，集成芯片为上述的集成芯片，多个集成芯片以矩阵的形式设置在电路基板上；封装胶层，封装胶层覆盖在电路基板上并封装多个集成芯片。
根据本发明的另一方面，提供了一种显示面板，包括：电路基板和多个全彩集成芯片，全彩集成芯片为上述的全彩集成芯片，多个全彩集成芯片以矩阵的形式设置在电路基板上；封装胶层，封装胶层覆盖在电路基板上并封装多个全彩集成芯片。
应用本发明的技术方案，通过提供一种特定的集成芯片的制造方法制造出一种新型结构的集成芯片，能够快捷方便地制造出集成芯片的电极结构，不仅能够确保集成芯片的发光特性，以保证显示面板的发光性能，而且使得集成芯片具有一体形式的多个发光点，从而在生产制造显示面板的过程中，大大地减少了转移集成芯片的次数，从而有利于提升显示面板的生产加工效率，缩短显示屏的生产工期，同时避免因铺设芯片的良率过低而降低显示面板的成品合格率，提高显示屏的生产效率。此外，集成芯片采用共极结构，与传统的发光芯片采用独立电极的方式相对比，减少了集成芯片整体的电极数量；集成芯片具有接线数量少、转移难度低、显示面板电路基板设计难度低、电路基板加工精度要求低等特点，具有良好的实用性。
附图说明
构成本申请的一部分的说明书附图用来提供对本发明的进一步理解，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1示出了根据本发明的一种可选实施例的制作集成芯片的发光部的过程中，多个第一电极、多个第二电极和多个发光单元组的分布状态示意图；
图2示出了图1中的覆盖了多个发光单元组后的多个第一电极和多个第二电极的分布状态示意图；
图3示出了图2中的多个第一电极和多个第二电极向集成芯片的四周边缘电性引出导电端后，多个第一引脚电极和多个第二引脚电极的分布状态示意图；
图4示出了图3中的覆盖了电性引出导电端后，多个第一引脚电极和多个第二引脚电极的分布状态示意图；
图5示出了根据本发明的另一种可选实施例的制作集成芯片的发光部的过程中，多个第一引脚电极和多个第二引脚电极的分布状态示意图；
图6示出了根据本实发明的一种可选实施例的显示面板的结构示意图；
图7示出了图6中的显示面板未使用封装胶层封装多个集成芯片时的结构示意图；
图8示出了根据本发明的一种可选实施例的集成芯片的结构示意图；
图9示出了以俯视视角看图8中的集成芯片的状态示意图；
图10示出了根据本发明的一种可选实施例的集成芯片的结构示意图；
图11示出了根据本实发明的一种可选实施例的显示面板的结构示意图；
图12示出了图11中的显示面板未使用封装胶层封装多个集成芯片时的结构示意图。
其中，上述附图包括以下附图标记：
1、电路基板；2、集成芯片；3、封装胶层；100、发光部；10、发光层；20、电极结构；200、光处理部；201、红色量子点基元；202、绿色量子点基元；203、透光补色基元；300、挡光墙层；301、凹槽；400、引脚部；11、发光单元组；200、光处理部；204、发光面；30、P-GaN层；40、金属接触层；21、正极；22、负极；50、n-GaN层；60、缓冲层；70、第一钝化层；80、DBR反射层；90、第二钝化层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了解决现有技术中的Micro LED显示面板的制作过程繁琐，不仅大大地降低了显示面板的生产加工效率，影响了显示屏的生产工期，而且会因铺设芯片的良率过低而降低显示面板的成品合格率，导致显示屏的生产效率低下的问题，本发明提供了一种集成芯片及其制造方法、全彩集成芯片和显示面板；需要说明的是，显示面板包括电路基板和设置在其上的多个集成芯片或多个全彩集成芯片，其中，集成芯片为上述和下述的集成芯片，全彩集成芯片包括上述和下述的集成芯片。
如图1和图2所示，集成芯片的制作方法用于成型加工集成芯片的电极结构，包括：步骤S1，制作发光部，并使发光部包括以矩阵形式分布的n×m个发光单元组，其中，n为行数，m为列数，且n和m均为大于或等于1的正整数，各发光单元组包括以矩阵形式分布的x×y个发光单元，其中，x为行数，y为列数，且x和y均为大于或等于1的正整数，发光单元包括a极电极和b极电极；将同一列发光单元组的同一列发光单元的a极电极分别电连接在一起，以形成m×y个第一电极，将同一行发光单元组的同一行发光单元的b极电极分别电连接，以形成n×x个第二电极；步骤S2，将m×y个第一电极和n×x个第二电极分别电性引出导电端，以形成m×y个第一引脚电极和n×x个第二引脚电极，第一引脚电极和第二引脚电极用于与电路基板电性连接。
本申请通过提供一种特定的集成芯片的制造方法制造出一种新型结构的集成芯片，能够快捷方便地制造出集成芯片的电极结构，不仅能够确保集成芯片的发光特性，以保证显示面板的发光性能，而且使得集成芯片具有一体形式的多个发光点，从而在生产制造显示面板的过程中，大大地减少了转移集成芯片的次数，从而有利于提升显示面板的生产加工效率，缩短显示屏的生产工期，同时避免因铺设芯片的良率过低而降低显示面板的成品合格率，提高显示屏的生产效率。此外，集成芯片采用共极结构，与传统的发光芯片采用独立电极的方式 相对比，减少了集成芯片整体的电极数量；集成芯片具有接线数量少、转移难度低、显示面板电路基板设计难度低、电路基板加工精度要求低等特点，具有良好的实用性。
可选地，使用蒸镀或沉积的方式将同一列发光单元组的同一列发光单元的a极电极分别电连接，以形成m×y个第一电极，使用蒸镀或沉积的方式将同一行发光单元组的同一行发光单元的b极电极分别电连接，以形成n×x个第二电极。这样，有利于控制集成芯片的加工制造成本，而且能够确保第一电极和第二电极的极性以及稳定性。
如图3所示，步骤S2包括：步骤S21，将m×y个第一电极分别向集成芯片的四周边缘电性引出导电端，以形成m×y个第一引脚电极；步骤S22，将n×x个第二电极分别向集成芯片的四周边缘电性引出导电端，以形成n×x个第二引脚电极；并使m×y个第一引脚电极和n×x个第二引脚电极绕集成芯片的边缘依次间隔分布。这样，便于控制相邻的两个引脚电极之间的间隔距离，避免引脚电极之间的电性干扰，确保集成芯片的电路稳定，从而提高显示面板的显像可靠性。
在本申请的图示实施例中，在步骤S22中，将m和n均设置为2，x设置为3，y设置为1，将两个第一电极和六个第二电极向集成芯片的四周边缘引出导电端以形成两个第一引脚电极和六个第二引脚电极。这种结构形式的集成芯片不仅便于加工制造，而且容易对第一电极和第二电极进行电性引导以形成引脚电极，有利于确保集成芯片的电性连接安装。
还需要说明的是，在步骤S2中，在发光部的第一电极和第二电极所在的表面上沉积或蒸镀N层绝缘保护层；以及依次在远离第一电极和第二电极的绝缘保护层表面上利用蒸镀或沉积的方法设置金属线路层，形成N层金属线路层；第一电极、第二电极和N层金属线路层通过绝缘保护层上的金属过孔电连接，其中，N为大于或等于2的正整数。这样，有利于根据设计要求将集成芯片的电极进行布置。
在本申请的一个实施例中，在电极和金属线路层之间以及相邻两个金属线路层之间均设置有绝缘保护层。
还需要说明的是，第N层金属线路层上远离绝缘保护层的一侧设有绝缘层，绝缘层覆盖第N层金属线路层上的金属走线和金属过孔。这样，有利于集成芯片的电性稳定性，确保其稳定被点亮。
可选地，第N层金属线路层包括m×y个第一引脚电极和n×x个第二引脚电极。还需要说明的是，上述第一引脚电极和第二引脚电极穿设出绝缘层，这样，该多个引脚电极能够露出绝缘层，便于后续与其它部件连接。
如图4和图5所示，与第N层金属线路层接触的绝缘保护层上设置有用于识别第一引脚电极的极性或第二引脚电极的极性的识别标记。这样，便于对第一引脚电极的极性以及第二引脚电极的极性进行准确识别，同时还能够准确获知第一引脚电极或者第二引脚电极的位置。
在图4中，多个第一引脚电极和多个第二引脚电极绕集成芯片的边缘依次间隔分布；在该图中，标记为3和4的两个引脚电极为第一引脚电极，且第一引脚电极为负极，标记为1、2和5至8的六个引脚电极为第二引脚电极，且第二引脚电极为正极。
而在图5中，第一引脚电极位于第一电极长度方向的端部，第二引脚电极位于第二电极长度方向的中部或端部；这样，在能够确保相邻的两个引脚电极之间具有安全距离的前提下，大大地降低了加工生成集成芯片的复杂程度。该图中，标记为2和7的两个引脚电极为第一引脚电极，且第一引脚电极为负极，标记为1、3至6和8的六个引脚电极为第二引脚电极，且第二引脚电极为正极。
可选地，绝缘保护层为二氧化硅层或氮化硅层。
考虑到集成芯片的加工制造的经济性，绝缘保护层通过印刷、沉积或蒸镀形成。
在本申请的图示实施例中，集成芯片由上述的集成芯片的制作方法制造而成；而全彩集成芯片包括上述的集成芯片和光处理部，光处理部设置在集成芯片的上方，光处理部包括红色量子点基元、绿色量子点基元和透光补色基元，红色量子点基元、绿色量子点基元和透光补色基元中任意两个相邻的基元之间设置有挡墙。这样，确保集成芯片具有稳定地发出白光的特性。
可选地，集成芯片为蓝光集成芯片，透光补色基元为透明散射量子点层。
当然，同样可选地，集成芯片为紫外光集成芯片，透光补色基元为蓝色量子点层。
在本申请的一个可选的显示面板的实施例中，显示面板包括电路基板、多个集成芯片和封装胶层，集成芯片为上述的集成芯片，多个集成芯片以矩阵的形式设置在电路基板上；封装胶层覆盖在电路基板上并封装多个集成芯片。
在本申请的另一个可选的显示面板的实施例中，显示面板包括电路基板、多个全彩集成芯片和封装胶层，全彩集成芯片为上述的全彩集成芯片，多个全彩集成芯片以矩阵的形式设置在电路基板上；封装胶层覆盖在电路基板上并封装多个全彩集成芯片。
为了解决现有技术中的Micro LED显示面板的制作过程繁琐，不仅大大地降低了显示面板的生产加工效率，影响了显示屏的生产工期，而且会因铺设芯片的良率过低而降低显示面板的成品合格率，导致显示屏的生产效率低下的问题，本发明提供了一种集成芯片。其中，该集成芯片可以采用上述的集成芯片的制造方法制作而成。其中，如图6和图7所示，显示面板包括电路基板1和以矩阵的形式设置在电路基板1上的多个集成芯片2，该图示实施例中，集成芯片2为上述和下述所述的集成芯片2；图6中设置了封装胶层3，封装胶层3覆盖在电路基板1上并封装多个集成芯片2，以确保多个集成芯片2的密封安装特性。而在本申请的一个未图示的可选实施例中，显示面板包括电路基板1和以矩阵的形式设置在电路基板1上的多个全彩集成芯片，同样地，全彩集成芯片为上述和下述所述的全彩集成芯片；当然，在该未图示的实施例中，封装胶层3覆盖在电路基板1上并封装多个全彩集成芯片，以确保多个全彩集成芯片的密封安装特性。
如图6至图8、图10至图12所示，集成芯片2包括发光部100和引脚部400，发光部100包括发光层10和电极结构20，电极结构20与发光层10电连接，引脚部400设置于电极结构20的下方，并与电极结构20电连接；引脚部400包括N层依次叠置的金属线路层和绝缘保护层，其中，电极结构20和与其相邻的一层金属线路层之间设置有一层绝缘保护层，以及相邻的两层金属线路层之间设置有一层绝缘保护层，绝缘保护层上开设有用于导体经过的金属过孔，N层金属线路层通过导体电连接，其中，N≥2。本申请提供了一种新型结构的集成芯片2，优化了集成芯片2的与电极结构电性作用的引脚部400的具体结构，在确保了引脚部400便于成型制造的前提下，不仅提高了集成芯片2安装后的电性连接稳定性，而且具有本申请结构的引脚部400的单一集成芯片2能够具有更多的发光点或更大的发光面，有利于满足集成芯片2预设的发光特性，从而有利于减少显示面板的电路基板上所安装的集成芯片2的数量，进而在生产制造显示面板的过程中，大大地减少了转移集成芯片2的次数，从而有利于提升显示面板的生产加工效率，缩短显示屏的生产工期，同时避免因铺设集成芯片2的良率过低而降低显示面板的成品合格率，提高显示屏的生产效率。此外，集成芯片2采用共极结构，与传统的发光芯片采用独立电极的方式相对比，减少了集成芯片2整体的电极数量；集成芯片2具有接线数量少、转移难度低、显示面板电路基板1设计难度低、电路基板1加工精度要求低等特点，具有良好的实用性。
为了提升单一集成芯片2的发光特性，有利于控制显示面板的显像性能，可选地，发光层10包括呈矩阵分布的n×m个发光单元组11，其中，n为行数，m为列数，且n和m均为大于或等于1的正整数，发光单元组11包括呈矩阵分布的x×y个发光单元，其中，x为行数，y为列数，且x和y均为大于或等于1的正整数；电极结构20包括与多个发光单元一一对应电连接的电极组，各电极组包括a极电极和b极电极，同一列发光单元组11的同一列发光单元的a极电极分别电连接在一起，形成m×y个第一电极；同一行发光单元组11的同一行发光单元的b极电极分别电连接，形成n×x个第二电极。这样，确保了x×y个发光单元集成在一起形成发光单元组11，多个发光单元组11又集成形成集成芯片2，在生产制造显示面板时，只需要逐一将多个集成芯片2转移到电路基板1，便能够顺利实现显示面板的成型制造。
需要说明的是，引脚部400在第N层金属线路层处形成第一引脚电极和第二引脚电极，其中，第一引脚电极为与多个第一电极一一对应连接的m×y个，第二引脚电极为与多个第二电极一一对应的n×x个。
在本申请的优选实施例中，提出了具有最佳的发光部100和引脚部400结构形式的集成芯片2，其中，N＝2，m＝2，n＝2，x＝3，y＝1。也就是说，引脚部400包括两层叠置的金属线路层和两层绝缘保护层，其中，电极结构20和与其相邻的第一层金属线路层之间设置有一层绝缘保护层，以及相邻的两层金属线路层之间设置有一层绝缘保护层，绝缘保护层上开设有用于导体经过的金属过孔；发光层10包括呈矩阵分布的4个发光单元组11，4个发光单元组11以2×2的行列式分布，各发光单元组11包括呈矩阵分布的3个发光单元，3个发光单元以3×1的行列式分布。
为了便于对第一引脚电极或第二引脚电极的极性进行准确识别，以提升集成芯片2的安装效率，可选地，与第N层金属线路层接触的绝缘保护层上设置有用于识别第一引脚电极或第二引脚电极的极性的识别标记。
可选地，第N层金属线路层上远离绝缘保护层的一侧设有绝缘层，绝缘层覆盖第N层金属线路层上的金属走线和金属过孔。
如图8和图10所示，集成芯片2还包括多个光处理部200，多个光处理部200沿集成芯片的发光面204以矩阵的形式分布在发光部100上，并位于发光层10的上方，且多个光处理部200与多个发光单元一一对应设置，发光部100还包括由上至下层叠设置在发光层10下方的P-GaN层30和金属接触层40，电极结构20包括正极21和负极22，其中，负极22与发光单元电连接，正极21通过金属接触层40和P-GaN层30与发光单元电连接。这种结构形式的集成芯片2结构合理，发光稳定。
如图8所示，发光部100还包括n-GaN层50、缓冲层60和第一钝化层70，n-GaN层50、缓冲层60和第一钝化层70由下至上依次层叠设置在发光层10和光处理部200之间。
具体的，电极结构20的负极与n-GaN层电连接从而和发光单元电连接。
发光部100还包括DBR反射层80和第二钝化层90，其中，DBR反射层80覆盖在缓冲层60、n-GaN层50和电极结构20的外周侧以及金属接触层40的底部，第二钝化层90覆盖在DBR反射层80的外周侧和底部，第二钝化层90为一层绝缘保护层。如图9所示，本申请提供的全彩集成芯片，为上述的集成芯片2，其中，集成芯片的光处理部200包括红色量子点基元201、绿色量子点基元202和透光补色基元203，红色量子点基元201、绿色量子点基元202和透光补色基元203中任意两个相邻的基元之间设置有挡墙。
可选地，集成芯片为蓝光集成芯片，透光补色基元203为透明散射量子点层。
可选地，集成芯片为紫外光集成芯片，透光补色基元203为蓝色量子点层。
在本申请的图示实施例中，如图8所示，发光部100包括位于发光层10上方的挡光墙层300，挡光墙层300上形成有沿发光面204以矩阵形式分布的多个凹槽301，各光处理部200的红色量子点基元201、绿色量子点基元202和透光补色基元203均分别设置在一个凹槽301内。
可选地，红色量子点基元201、绿色量子点基元202和透光补色基元203均以喷涂的方式形成在各自对应的凹槽301内，并填充凹槽301。
可选地，凹槽301以光刻工艺形成在挡光墙层300上并贯穿挡光墙层300。
可选地，凹槽301的深度大于等于1um且小于等于1000um。
如图10所示，在本发明的另一实施例的集成芯片的结构示意图中，本领域技术人员都知道位于n-GaN层50下方的起绝缘作用的构件为第三钝化层51。为了便于理解，申请人主动更正了n-GaN层50的填充物和第三钝化层51的填充物的形式，并对起绝缘作用的构件增加 了标记。基于同样的理由，在附图11和附图12中增加了附图标记，并主动更正了代表n-GaN层50和第三钝化层51的填充物的形式。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本申请的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
为了便于描述，在这里可以使用空间相对术语，如“在……之上”、“在……上方”、“在……上表面”、“上面的”等，用来描述如在图中所示的一个器件或特征与其他器件或特征的空间位置关系。应当理解的是，空间相对术语旨在包含除了器件在图中所描述的方位之外的在使用或操作中的不同方位。例如，如果附图中的器件被倒置，则描述为“在其他器件或构造上方”或“在其他器件或构造之上”的器件之后将被定位为“在其他器件或构造下方”或“在其他器件或构造之下”。因而，示例性术语“在……上方”可以包括“在……上方”和“在……下方”两种方位。该器件也可以其他不同方式定位(旋转90度或处于其他方位)，并且对这里所使用的空间相对描述作出相应解释。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本申请的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、工作、器件、组件和/或它们的组合。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施方式能够以除了在这里图示或描述的那些以外的顺序实施。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (24)

  1. 一种集成芯片的制造方法，用于成型加工集成芯片的电极结构，其特征在于，包括：
    步骤S1，制作发光部，并使所述发光部包括以矩阵形式分布的n×m个发光单元组，其中，n为行数，m为列数，且n和m均为大于或等于1的正整数，各所述发光单元组包括以矩阵形式分布的x×y个发光单元，其中，x为行数，y为列数，且x和y均为大于或等于1的正整数，所述发光单元包括a极电极和b极电极；将同一列发光单元组的同一列发光单元的a极电极分别电连接在一起，以形成m×y个第一电极，将同一行发光单元组的同一行发光单元的b极电极分别电连接，以形成n×x个第二电极；
    步骤S2，将m×y个所述第一电极和n×x个所述第二电极分别电性引出导电端，以形成m×y个第一引脚电极和n×x个第二引脚电极，所述第一引脚电极和所述第二引脚电极用于与电路基板电性连接。
  2. 根据权利要求1所述的集成芯片的制造方法，其特征在于，
    使用蒸镀或沉积的方式将同一列所述发光单元组的同一列所述发光单元的a极电极分别电连接，以形成m×y个第一电极，
    使用蒸镀或沉积的方式将同一行所述发光单元组的同一行所述发光单元的b极电极分别电连接，以形成n×x个第二电极。
  3. 根据权利要求1所述的集成芯片的制造方法，其特征在于，所述步骤S2包括：
    步骤S21，将m×y个所述第一电极分别向所述集成芯片的四周边缘电性引出导电端，以形成m×y个所述第一引脚电极；
    步骤S22，将n×x个所述第二电极分别向所述集成芯片的四周边缘电性引出导电端，以形成n×x个第二引脚电极；
    并使m×y个所述第一引脚电极和n×x个所述第二引脚电极绕所述集成芯片的边缘依次间隔分布。
  4. 根据权利要求3所述的集成芯片的制造方法，其特征在于，在所述步骤S22中，将m和n均设置为2，x设置为3，y设置为1，将两个所述第一电极和六个所述第二电极向所述集成芯片的四周边缘引出导电端以形成所述两个所述第一引脚电极和六个所述第二引脚电极。
  5. 根据权利要求1所述的集成芯片的制造方法，其特征在于，在所述步骤S2中，在所述发光部的所述第一电极和所述第二电极所在的表面上沉积或蒸镀N层绝缘保护层；以及依次在远离所述第一电极和所述第二电极的所述绝缘保护层表面上利用蒸镀或沉积的方法设置金属线路层，形成N层金属线路层；所述第一电极、所述第二电极和N层所述金属线路层通过所述绝缘保护层上的金属过孔电连接，其中，N为大于或等于2的正整数。
  6. 根据权利要求5所述的集成芯片的制造方法，其特征在于，第N层所述金属线路层上远离所述绝缘保护层的一侧设有绝缘层，所述绝缘层覆盖第N层所述金属线路层上的金属走线和金属过孔。
  7. 根据权利要求5所述的集成芯片的制造方法，其特征在于，第N层所述金属线路层包括m×y个所述第一引脚电极和n×x个所述第二引脚电极。
  8. 根据权利要求5所述的集成芯片的制造方法，其特征在于，与第N层所述金属线路层接触的所述绝缘保护层上设置有用于识别所述第一引脚电极的极性或所述第二引脚电极的极性的识别标记。
  9. 根据权利要求5所述的集成芯片的制造方法，其特征在于，所述绝缘保护层为二氧化硅层或氮化硅层。
  10. 根据权利要求5所述的集成芯片的制造方法，其特征在于，所述绝缘保护层通过印刷、沉积或蒸镀形成。
  11. 一种集成芯片，其特征在于，由权利要求1至10中任一项所述的集成芯片的制造方法制造而成。
  12. 根据权利要求11所述的集成芯片，其特征在于，包括：
    发光部(100)，所述发光部(100)包括发光层(10)和电极结构(20)，所述电极结构(20)与所述发光层(10)电连接；
    引脚部(400)，所述引脚部(400)设置于所述电极结构(20)的下方，并与所述电极结构(20)电连接；所述引脚部(400)包括N层依次叠置的金属线路层和绝缘保护层，其中，所述电极结构(20)和与其相邻的一层所述金属线路层之间设置有一层所述绝缘保护层，以及相邻的两层所述金属线路层之间设置有一层所述绝缘保护层，所述绝缘保护层上开设有用于导体经过的金属过孔，N层所述金属线路层通过所述导体电连接，其中，N≥2。
  13. 根据权利要求12所述的集成芯片，其特征在于，
    所述发光层(10)包括呈矩阵分布的n×m个发光单元组(11)，其中，n为行数，m为列数，且n和m均为大于或等于1的正整数，所述发光单元组(11)包括呈矩阵分布的x×y个发光单元，其中，x为行数，y为列数，且x和y均为大于或等于1的正整数；所述电极结构(20)包括与多个所述发光单元一一对应电连接的电极组，各所述电极组包括a极电极和b极电极，同一列所述发光单元组(11)的同一列所述发光单元的a极电极分别电连接在一起，形成m×y个第一电极；同一行所述发光单元组(11)的同一行所述发光单元的b极电极分别电连接，形成n×x个第二电极。
  14. 根据权利要求13所述的集成芯片，其特征在于，所述引脚部(400)在第N层所述金属线路层处形成第一引脚电极和第二引脚电极，其中，所述第一引脚电极为与多个所述第 一电极一一对应连接的m×y个，所述第二引脚电极为与多个所述第二电极一一对应的n×x个。
  15. 根据权利要求13或14所述的集成芯片，其特征在于，N＝2，m＝2，n＝2，x＝3，y＝1。
  16. 根据权利要求14所述的集成芯片，其特征在于，与第N层所述金属线路层接触的所述绝缘保护层上设置有用于识别所述第一引脚电极或所述第二引脚电极的极性的识别标记。
  17. 根据权利要求12所述的集成芯片，其特征在于，第N层所述金属线路层上远离所述绝缘保护层的一侧设有绝缘层，所述绝缘层覆盖第N层所述金属线路层上的金属走线和金属过孔。
  18. 根据权利要求12所述的集成芯片，其特征在于，所述集成芯片还包括多个光处理部(200)，多个所述光处理部(200)沿所述集成芯片的发光面(204)以矩阵的形式分布在所述发光部(100)上，并位于所述发光层(10)的上方，且多个所述光处理部(200)与多个所述发光单元一一对应设置，所述发光部(100)还包括由上至下层叠设置在所述发光层(10)下方的P-GaN层(30)和金属接触层(40)，所述电极结构(20)包括正极(21)和负极(22)，其中，所述负极(22)与所述发光单元电连接，所述正极(21)通过所述金属接触层(40)和所述P-GaN层(30)与所述发光单元电连接。
  19. 根据权利要求18所述的集成芯片，其特征在于，
    所述发光部(100)还包括n-GaN层(50)、缓冲层(60)和第一钝化层(70)，所述n-GaN层(50)、所述缓冲层(60)和所述第一钝化层(70)由下至上依次层叠设置在所述发光层(10)和所述光处理部(200)之间；
    所述发光部(100)还包括DBR反射层(80)和第二钝化层(90)，其中，所述DBR反射层(80)覆盖在所述缓冲层(60)、所述n-GaN层(50)和所述电极结构(20)的外周侧以及所述金属接触层(40)的底部，所述第二钝化层(90)覆盖在所述DBR反射层(80)的外周侧和底部，所述第二钝化层(90)为一层所述绝缘保护层。
  20. 一种全彩集成芯片，其特征在于，包括：
    权利要求11所述的集成芯片；
    光处理部(200)，所述光处理部(200)设置在所述集成芯片的上方，所述光处理部(200)包括红色量子点基元(201)、绿色量子点基元(202)和透光补色基元(203)，所述红色量子点基元(201)、所述绿色量子点基元(202)和所述透光补色基元(203)中任意两个相邻的基元之间设置有挡墙。
  21. 根据权利要求20所述的全彩集成芯片，其特征在于，所述集成芯片为蓝光集成芯片，所述透光补色基元(203)为透明散射量子点层。
  22. 根据权利要求20所述的全彩集成芯片，其特征在于，所述集成芯片为紫外光集成芯片，所述透光补色基元(203)为蓝色量子点层。
  23. 一种显示面板，其特征在于，包括：
    电路基板和多个集成芯片，所述集成芯片为权利要求11所述的集成芯片，多个所述集成芯片以矩阵的形式设置在所述电路基板上；
    封装胶层，所述封装胶层覆盖在所述电路基板上并封装多个所述集成芯片。
  24. 一种显示面板，其特征在于，包括：
    电路基板和多个全彩集成芯片，所述全彩集成芯片为权利要求20至22中任一项所述的全彩集成芯片，多个所述全彩集成芯片以矩阵的形式设置在所述电路基板上；
    封装胶层，所述封装胶层覆盖在所述电路基板上并封装多个所述全彩集成芯片。
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