WO2021129454A1

WO2021129454A1 - Mvb chip

Info

Publication number: WO2021129454A1
Application number: PCT/CN2020/136407
Authority: WO
Inventors: 陈玉飞; 潘峰; 石勇; 周达; 石小磊
Original assignee: 中车大连电力牵引研发中心有限公司
Priority date: 2019-12-26
Filing date: 2020-12-15
Publication date: 2021-07-01
Also published as: CN113050461A

Abstract

An MVP chip, the chip comprising: a master control unit (13) and a codec unit (11) electrically connected to one another; the codec unit (11) is used for receiving MVB communication data from an MVB bus, decoding the MVB communication data and sending master frame decoded data to the master control unit (13), and simultaneously encoding data to be sent and sending same to the MVB bus; the master control unit (13) is used for determining action information corresponding to the master frame decoded data on the basis of the master frame decoded data and acquiring and sending data to be sent on the basis of the action information, and can also implement master frame scheduling, master frame determining, slave frame processing, and host computer access, can implement an MVB network link control protocol and comply with IEC61375 protocol regulations, and has the functions of MVB1-4 type devices, increasing the reliability and stability of train operation.

Description

MVB chip

Technical field

The present invention relates to the technical field of vehicle buses, in particular to an MVB chip.

Background technique

With the rapid development of road traffic, the multifunctional vehicle bus (MVB) protocol, as an important part of the train communication network (TCN), has become a key technology of the high-speed electric train control system, which can be used for train status detection, fault diagnosis and on-board vehicles. Operations such as equipment development and debugging.

At present, each sub-control unit in the train network control system in the rail field uses MVB chips for bus communication. MVB will be located in the same vehicle or fixedly connected to equipment in different vehicles and connected to the vehicle bus on the train communication network. MVB The media access to the bus adopts a master-slave mode of centralized control and periodic distribution.

However, the bus communication methods in the prior art are all centrally controlled and managed by the only bus manager CPU on the bus. Generally, this communication method causes problems of low real-time performance and poor stability.

Summary of the invention

The present invention provides an MVB chip to realize the MVB network link control protocol, and conforms to the IEC61375 protocol, and also has the functions of MVB1 to 4 types of equipment, and improves the reliability and stability of train operation.

In the first aspect, an MVB chip provided by an embodiment of the present invention includes:

Coding and decoding unit, CPU interface, main control unit, internal bus management unit and storage unit,

The main control unit is electrically connected to the CPU interface and the internal bus management unit respectively; the CPU interface is used to connect to the host computer interface and establish communication; the storage unit is respectively connected to the encoding and decoding unit and the The main control unit and the internal bus management unit are electrically connected; the encoding and decoding unit is electrically connected with the main control unit and the internal bus management unit respectively;

The encoding and decoding unit is configured to receive MVB communication data from the MVB bus, decode the MVB communication data to obtain the main frame decoded data, and send the main frame decoded data to the main control unit, and The data to be sent is encoded and sent to the MVB bus;

The main control unit is configured to determine the action information corresponding to the main frame decoded data according to the main frame decoded data; and obtain and send the data to be sent according to the action information.

In an optional embodiment, if the action information is received data, the data to be sent is decoded data from a frame, and the main control unit is specifically configured to control the encoding and decoding unit to receive data from the CPU. The interface receives the communication data sent by the CPU, decodes the communication data, obtains the decoded data from the frame, and sends the decoded data from the frame to the storage unit;

If the action information is sending data, and the data to be sent is encoded slave frame data, the master control unit is specifically configured to send the slave frame data to the storage unit through the internal bus management unit. The encoding and decoding unit receives and encodes the slave frame data to obtain the encoded slave frame data, and sends the encoded slave frame data to the MVB bus.

In an optional embodiment, the internal bus further includes an uplink internal line and a downlink internal line; the internal bus management unit is configured to switch between the uplink internal line and the downlink internal line according to the judgment of the main control unit. The line is switched.

In an optional embodiment, the encoding and decoding unit is further configured to receive MVB communication data from the MVB bus, decode the MVB communication data to obtain the main frame decoded data, and decode the main frame The data is stored in the storage unit.

In an optional embodiment, it further includes: a line switching unit;

The line switching unit is electrically connected to the internal bus management unit, and is electrically connected to the encoding and decoding unit;

The line switching unit is used to control the selection of two data channels in the line switching unit through the main control unit according to the operating state of the encoding and decoding unit.

In an optional embodiment, it further includes:

An interface unit, which is electrically connected to the encoding and decoding unit, and is used to receive MVB communication data from the MVB bus.

In an optional embodiment, the chip has the function of MVB1 to 4 types of equipment.

In an optional embodiment, the production process of the chip is 0.18um CMOS, and the package is QFP144.

In an optional embodiment, the chip is configured through an application interface function API and connected to the upper computer, wherein the interface protocol adopts UART.

In an optional embodiment, the external crystal oscillator of the chip is 24 MHz, including EMD and ESD dual-medium communication.

In the second aspect, a method for chip development provided by the present invention is applied to the chip described in any one of the first aspects, including: front-end design, front-end verification, back-end design, back-end verification, chip processing, and chip testing the process of.

The present invention provides an MVB chip, which includes: an encoding and decoding unit, a CPU interface, a main control unit, an internal bus management unit, and a storage unit. The main control unit is electrically connected to the CPU interface internal bus management unit; the CPU The interface is used to connect to the host computer interface and establish communication; the storage unit is electrically connected to the encoding and decoding unit, the main control unit, and the internal bus management unit; the encoding and decoding unit and the main control unit , The internal bus management unit is electrically connected; the encoding and decoding unit is used to receive MVB communication data from the MVB bus and decode the MVB communication data (because decoding needs to decode the main frame, the same slave frame data must be analyzed ), and send the main frame decoded data to the main control unit; at the same time, encode and send the data to be sent to the MVB bus; the main control unit is used to determine the main frame decoded data corresponding to the main frame decoded data according to the main frame decoded data According to the action information, obtain and send the data to be sent. It can also realize the main frame scheduling (for example, the upper computer is configured as the main device), the main frame judgment, the slave frame processing, and the upper computer access, and the MVB network link can be realized The control protocol is in compliance with the IEC61375 protocol, and it also has the function of MVB1~4 equipment, which improves the reliability and stability of train operation.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor.

Figure 1 is a schematic diagram of a typical application scenario of the present invention;

2 is a schematic diagram of the structure of an MVB chip provided by Embodiment 1 of the present invention;

FIG. 3 is a schematic diagram of a data sequence of an MVB chip provided by Embodiment 1 of the present invention;

4 is a schematic diagram of the structure of the MVB chip provided by the second embodiment of the present invention;

FIG. 5(a) is the first schematic diagram of the timing diagram of the MVB chip provided by the third embodiment of the present invention;

FIG. 5(b) is the second schematic diagram of the timing diagram of the MVB chip provided by the third embodiment of the present invention;

FIG. 5(c) is the third schematic diagram of the timing diagram of the MVB chip provided by the third embodiment of the present invention;

FIG. 6 is a schematic diagram of the design flow of the MVB chip provided by the fourth embodiment of the present invention.

11. Codec unit, 12, CPU interface, 13, main control unit, 14, internal bus management unit, 15, line switching unit, 16, storage unit.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used Describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described herein can, for example, be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those clearly listed. Those steps or units may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or equipment.

The technical solutions of the present invention and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

Figure 1 is a schematic diagram of a typical application scenario of the present invention. MVB chips are widely used in rail transit industries such as locomotives, high-speed rails, EMUs, and subways. As shown in Figure 1, MVB chip 10 is used in locomotive 01, and the MVB chip is used for network Communication can realize the MVB network link control protocol and comply with the IEC61375 protocol. It also has the functions of MVB1~4 equipment, which improves the reliability and stability of train operation.

FIG. 2 is a schematic structural diagram of an MVB chip provided by Embodiment 1 of the present invention. As shown in FIG. 2, the MVB chip in this embodiment may include: an encoding and decoding unit 11, a CPU interface 12, a main control unit 13, and an internal bus management unit 14. Storage unit 16.

Specifically, the encoding and decoding unit 11, the CPU interface 12, the main control unit 13, the internal bus management unit 14, and the storage unit 16. The main control unit 13 is electrically connected to the CPU interface 12 and the internal bus management unit 14; the CPU interface 12 is used for Connect with the host computer interface and establish communication; the storage unit 16 is electrically connected to the codec unit 11, the main control unit 13, and the internal bus management unit 14; the codec unit 11 is electrically connected to the main control unit 13, and the internal bus management unit 14 respectively. Connection; encoding and decoding unit 11, used to receive MVB communication data from the MVB bus, and decode the MVB communication data to obtain the main frame decoded data, and send the main frame decoded data to the main control unit, and encode the data to be sent Then send it to the MVB bus; the main control unit 13 is used to determine the action information corresponding to the main frame decoded data according to the main frame decoded data; and according to the action information, obtain and send the data to be sent.

In this embodiment, the MVB network link control protocol is implemented. The data frame of the MVB protocol can include a master frame and a slave frame. For example, the length of the master frame is fixed at 33 bits, and the length of the slave frame can be 33 bits, 49 bits, and 81 bits. , 153, 297 and so on. The signals transmitted on the MVB bus are digital information. These digital signals are transmitted in frames as the basic unit. The main frame includes the command information of the MVB bus. The falling edge of the MVB bus line level included in the secondary frame can be set as the beginning of each frame. In an optional embodiment, except for the frame header and the frame tail, they are all standard Manchester codes, and the frame headers of the main frame and the slave frame have different codes.

In an optional embodiment, the MVB encoding mechanism, for example, uses the start-of-frame delimiter SSD, and the data frame type determiner "F_code". And the data type can be divided into process data frame (F=0~4), its slave frame data has 16bit, 32bit, 64bit, 128bit or 256bit; message data frame (F=12), occasional data, its slave frame data has 256bit; supervision data frame (F=8,9,13,14,15), its slave frame data has 16bit. It may also include Addr address bits, CheckSum check sequence, ED delimiter end, etc. For details, please refer to Figure 3 below. Figure 3 is a schematic diagram of the data sequence of the MVB chip provided by the first embodiment of the present invention, as shown in Figure 3. The line signal is terminated after the 8-bit check sequence, and the termination delimiter does not occupy a place, as shown by the bold arrow in Figure 3. A complete master/slave frame data should include the start delimiter, frame data, and check sequence And the termination delimiter is considered a valid frame.

In an optional embodiment, if the action information is received data, the data to be sent is decoded data from the frame, and the main control unit is specifically used to control the encoding and decoding unit to receive the communication data sent by the CPU from the CPU interface, and The communication data is decoded to obtain the decoded data from the frame, and the decoded data from the frame is sent to the storage unit; if the action information is sending data, the data to be sent is the encoded slave frame data, and the main control unit, specifically used for the storage unit, will The slave frame data is sent to the encoding and decoding unit through the internal bus management unit, and the encoding and decoding unit receives the encoded slave frame data after encoding the slave frame data, and sends the encoded slave frame data to the MVB bus.

Specifically, if the action information is an instruction to receive data, the communication data sent by the CPU is received through the CPU interface 12 and the communication data is decoded to obtain the slave frame data, and the decoded data from the frame is sent to the storage unit 16. If the action information is sending data, and the data to be sent is the encoded slave frame data, the master control unit 13, specifically used for the storage unit 16 to send the slave frame data to the encoding and decoding unit 11 through the internal bus management unit 14, and the encoding and decoding unit 11 The unit 11 receives the encoded slave frame data after encoding the slave frame data, and sends the encoded slave frame data to the MVB bus.

In an optional embodiment, the internal bus further includes an uplink internal line and a downlink internal line; the internal bus management unit is configured to switch between the uplink internal line and the downlink internal line according to the judgment of the main control unit.

In this embodiment, the internal bus also includes an uplink internal line and a downlink internal line, which are respectively used for the management and switching of uplink data and downlink data. When the main control unit detects that the uplink internal line has data transmission, it manages the uplink data; When the main control unit detects that the downlink internal line has data transmission, it manages the downlink data, realizes the distribution and scheduling of the bus, and reduces the power consumption of the chip.

In an optional embodiment, the encoding and decoding unit is also used to receive MVB communication data from the MVB bus, decode the MVB communication data to obtain the main frame decoded data, and store the main frame decoded data in the storage unit.

Specifically, the encoding and decoding unit 11 receives MVB communication data from the MVB bus, decodes the MVB communication data to obtain the main frame decoded data, and stores the main frame decoded data in the storage unit 16.

FIG. 4 is a schematic structural diagram of an MVB chip provided in the second embodiment of the present invention. As shown in FIG. 4, the MVB chip in this embodiment further includes a line switching unit 15 on the basis of FIG. 2.

Specifically, the line switching unit 15 is electrically connected to the internal bus management unit 14 and is electrically connected to the encoding and decoding unit 11; the line switching unit 15 is used for controlling two lines of the line switching unit through the main control unit according to the operating state of the encoding and decoding unit. The choice of data channel.

In this embodiment, the encoding and decoding unit has two data channels A and B, which can respectively receive or send transmission data. When it is detected that one of the data channels is not working normally, the main control unit 13 switches the line switch unit 15 The other data channel keeps continuously and normally open, which can ensure the reliability of the redundancy of the two data channels and realize the redundancy function.

In an optional embodiment, it further includes: an interface unit, which is electrically connected to the encoding and decoding unit, and is configured to receive MVB communication data from the MVB bus.

Specifically, the encoding and decoding unit 11 may receive MVB communication data from the MVB bus through the interface unit, and then process the MVB communication data through the encoding and decoding unit, so that the train can run reliably and safely.

In this embodiment, the chip front-end design requirements specified in the IEC61375 protocol are fully complied with. The encoding and decoding unit realizes Manchester encoding and decoding and encoding and decoding of the special MVB network message format, and completes the encoding and decoding of the signal after level conversion; the CPU interface mainly communicates with the upper computer and realizes the UART communication protocol. Complete the configuration and data interaction of the upper computer; the main control unit is the core unit of the MVB link protocol control, which realizes the functions of bus management, data communication and processing; the internal bus management unit is responsible for the distribution and scheduling of the bus; the line switching is mainly for the MVB Two-way bus for monitoring and management functions. It realizes the MVB network link control protocol and complies with the IEC61375 protocol. It also has the functions of MVB1~4 equipment to improve the reliability and stability of train operation. In an optional embodiment, the MVB chip can support the functions of MVB devices without CPU. Only hard-wired settings can be used for process data communication and monitoring data communication of a specific port, which greatly meets the needs of network communication. .

In an alternative embodiment, the production process of the chip is 0.18um CMOS, and the package is QFP144.

In this embodiment, the MVB chip does not have high requirements on the production process. For example, the production process is 0.18um CMOS (Complementary Metal Oxide Semiconductor), and the package is versatile. For example, the package is QFP144, and FPQ (Plastic Quad Flat Pockage, square flat package technology) facilitates subsequent practical applications. It has the advantages of low cost, simple integration, and good compatibility.

In an alternative embodiment, the chip is configured through an application interface API, and the interface protocol adopts URAT.

In this embodiment, the user can configure the chip through the application interface function API (Application Programming Interface) and connect it to the host computer. The interface protocol adopts UART (Universal Asynchronous Receiver/Transmitter), and the user The operation is simple and easy to master.

In an alternative embodiment, the external crystal oscillator of the MVB chip only needs 24 MHz, including EMD and ESD dual-medium communication.

In an alternative embodiment, after the MVB chip uses an external chip crystal oscillator, its clock frequency is the frequency of the crystal oscillator, for example, only 24 MHz is required. The MVB physical layer provides three different media. They can run at the same rate and are compatible with EMD and ESD dual media communication. ESD is a short-distance transmission with a transmission distance of 20 meters. For example, a standard RS-485 transceiver can support 32 This device is suitable for enclosed small rooms. EMD electrical appliances mid-distance transmission, the transmission distance can reach 200 meters, supports 32 devices, shielded twisted pair, transformer coupling. OGF long-distance optical glass fiber medium, the transmission distance can reach 2000 meters. With the continuous development of MVB technology, MVB physical layer media is mainly based on EMD. Each bus segment of the MVB must be connected to each other via a repeater connecting different media, a star coupler that connects the optical fiber to the bus, and one of two types of couplers.

In an optional embodiment, the MVB chip implements the protocol requirements specified in the IEC61375 standard, and implements the MVB link protocol control function. It also has all the functions of MVB1～4 types of equipment, mainly including: process data (supports 4096 ports), message data (256 bytes for each send and receive queue), monitoring data (full network scan, 4096 device address ports), bus Management (8192 main frames can be written at one time), user-defined configuration.

In an alternative embodiment, the MVB devices connected on the MVB bus can be classified into categories 0 to 5 devices according to their performance. Among them, category 0 devices do not have data communication capabilities, and mainly include repeaters and bus couplers, etc. . Class 1 equipment has process data transmission performance and equipment status response performance; Class 2~5 equipment not only has the performance of Class 1 equipment, but also has the performance of transmitting message data; In addition, Class 4 and Class 5 equipment also have MVB bus management Features. Therefore, the embodiment of the present invention has all the functions of MVB1 to 4 types of equipment, realizes the protocol requirements specified in the IEC61375 standard, and realizes the MVB link protocol control function.

The dedicated train network MVB chip of the embodiment of the present invention has low power consumption, simple integration, and low cost; it can also be easily configured with the upper computer through the CPU interface, and the user can configure it flexibly according to actual needs, and the operation is simple and easy to master; In addition, the independent research and development of the MVB chip has perfect functions and good compatibility, which can replace similar foreign chips, increase the localization rate of train network control systems, and increase train costs.

In an alternative embodiment, the interface between the host computer and the MVB chip is implemented through a simple UART protocol. The interfaces mainly include address bus, data bus, and read and write signals. The specific timing requirements are shown in Figure 5(a), It has been clearly marked in Figure 5(b) and Figure 5(c). Fig. 5(a) is the first schematic diagram of the timing diagram of the MVB chip provided by the third embodiment of the present invention; Fig. 5(b) is the second schematic diagram of the timing diagram of the MVB chip provided by the third embodiment of the present invention; Fig. 5(c) is The third schematic diagram of the timing diagram of the MVB chip provided by the third embodiment of the present invention. As shown in Figure 5(a) address and read and write signal timing, where Adderss lines: address bus, IOR: read signal signal, IOW: write signal, refer to Table 1 below for details.

Table 1

时序Timing	符号symbol	minmin	maxmax
地址线相对于IOR/IOW延迟Address line relative to IOR/IOW delay	t _asu t _asu	--	20ns20ns
地址保持时间Address hold time	t _ahd t _ahd	0ns0ns	--
访问周期Visit cycle	t _cyc t _cyc	200ns200ns	To
访问空闲时间Visit free time	t _idle t _idle	80ns80ns	--

Figure 5(b) read cycle timing diagram, where IOR: read signal, SD: data bus. Refer to Table 2 below for details.

Table 2

时序Timing	符号symbol	minmin	maxmax
数据出现在总线上Data appears on the bus	t _doe t _doe	0ns0ns	--
数据有效(此时刻后可访问)Data is valid (accessible after this time)	t _acc t _acc	--	130ns130ns
数据保持时间Data retention time	t _dhld t _dhld	0ns0ns	--
高阻态最大恢复时间Maximum recovery time in high resistance state	t _dts t _dts	--	30ns30ns

Figure 5(c) is a timing diagram of the write cycle, where IOW: write signal, SD: data bus. Details are shown in Table 3.

table 3

时序Timing	符号symbol	minmin	maxmax
数据建立时间Data establishment time	t _dsu t _dsu	--	80ns80ns
数据保持时间Data retention time	t _dhd t _dhd	0ns0ns	--

It can be seen from these timing diagrams that the timing requirements are relatively simple and easy to implement. The host computer interface mainly completes the configuration and data interaction of the CPU to the MVB chip, and then realizes the sending and receiving and deployment of MVB network data.

In this embodiment, the bus management function is a necessary function of the MVB chip 4 types of equipment and is responsible for bus communication scheduling; the line redundancy switching function is a function of the MVB bus redundancy and reliability, which can ensure the reliability of the two-wire redundancy. Greatly meet the needs of train network communication.

Referring to FIG. 6, FIG. 6 is a schematic diagram of the design flow of the MVB chip provided by the fourth embodiment of the present invention. As shown in Figure 6, the MVB chip design process includes front-end design, front-end verification, back-end design, back-end verification, chip processing, and chip testing. The front-end design mainly uses hardware description language (VHDL) to implement the protocol function code or called RTL realization; the front-end verification is the functional verification of the front-end design code to see if it meets the functional requirements; the back-end design is mainly for the front-end Code synthesis, layout and physical layout design; back-end verification is mainly to check whether the time model meets the time requirements, whether the functions required by the time are realized, and whether the circuit completes normal functions under the conditions specified by the design requirements; chip processing It is the physical realization of the previously realized functions according to the requirements of the production process; the chip test is mainly to carry out packaging test, function verification test, consistency test, and type test test on the produced chip.

In addition, the embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium stores computer-executable instructions. When at least one processor of the user equipment executes the computer-executable instructions, the user equipment executes the aforementioned various possibilities. Methods.

Among them, the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another. The storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and the storage medium may be located in the ASIC. In addition, the ASIC may be located in the user equipment. Of course, the processor and the storage medium may also exist as discrete components in the communication device.

A person of ordinary skill in the art can understand that all or part of the steps in the foregoing method embodiments can be implemented by a program instructing relevant hardware. The aforementioned program can be stored in a computer readable storage medium. When the program is executed, it executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk, or optical disk and other media that can store program code.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the technical solutions of the embodiments of the present invention. range.

Claims

An MVB chip, characterized in that it comprises:

Coding and decoding unit, CPU interface, main control unit, internal bus management unit and storage unit,

The main control unit is electrically connected to the CPU interface and the internal bus management unit respectively; the CPU interface is used to connect to the host computer interface and establish communication; the storage unit is respectively connected to the encoding and decoding unit and the The main control unit and the internal bus management unit are electrically connected; the encoding and decoding unit is electrically connected with the main control unit and the internal bus management unit respectively;

The encoding and decoding unit is configured to receive MVB communication data from the MVB bus, decode the MVB communication data, send the main frame decoded data to the main control unit, and encode the data to be sent Then send it to the MVB bus;

The main control unit is configured to determine the action information corresponding to the main frame decoded data according to the main frame decoded data; and obtain and send the data to be sent according to the action information.
The chip according to claim 1, wherein if the action information is received data, the data to be sent is decoded data from a frame, and the master control unit is specifically configured to control the encoding and decoding unit from The CPU interface receives the communication data sent by the CPU, decodes the communication data, obtains the decoded data from the frame, and sends the decoded data from the frame to the storage unit;

If the action information is sending data, and the data to be sent is encoded slave frame data, the master control unit is specifically configured to send the slave frame data to the storage unit through the internal bus management unit. The encoding and decoding unit receives and encodes the slave frame data to obtain the encoded slave frame data, and sends the encoded slave frame data to the MVB bus.
The chip according to claim 1, wherein the internal bus further comprises an uplink internal circuit and a downlink internal circuit; the internal bus management unit is used to convert the uplink internal circuit and the internal circuit according to the judgment of the main control unit. The downlink internal line is switched.
The chip according to claim 1, wherein the encoding and decoding unit is further configured to receive MVB communication data from the MVB bus, and decode the MVB communication data to obtain the main frame decoded data, and combine the The main frame decoded data is stored in the storage unit.
The chip according to claim 1, further comprising: a line switching unit;

The line switching unit is electrically connected to the internal bus management unit, and is electrically connected to the encoding and decoding unit;

The line switching unit is used to control the selection of two data channels in the line switching unit through the main control unit according to the operating state of the encoding and decoding unit.
The chip according to any one of claims 1 to 4, further comprising:

An interface unit, which is electrically connected to the encoding and decoding unit, and is used to receive MVB communication data from the MVB bus.
The chip according to any one of claims 1 to 4, wherein the chip has the function of MVB1 to 4 types of equipment.
The chip according to any one of claims 1 to 4, wherein the production process of the chip is 0.18um CMOS, and the package is QFP144.
The chip according to any one of claims 1 to 4, wherein the chip is configured through an application interface function API and connected to a host computer, wherein the interface protocol adopts UART.
The chip according to any one of claims 1 to 4, wherein the external crystal oscillator of the chip is 24 MHz, including EMD and ESD dual-medium communication.