WO2021128284A1 - 二次变换的约束方法及其装置 - Google Patents

二次变换的约束方法及其装置 Download PDF

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WO2021128284A1
WO2021128284A1 PCT/CN2019/129210 CN2019129210W WO2021128284A1 WO 2021128284 A1 WO2021128284 A1 WO 2021128284A1 CN 2019129210 W CN2019129210 W CN 2019129210W WO 2021128284 A1 WO2021128284 A1 WO 2021128284A1
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unit
transformation
secondary transformation
coding unit
transform
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PCT/CN2019/129210
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English (en)
French (fr)
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姚杰
朱建清
数井君彦
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富士通株式会社
姚杰
朱建清
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Priority to PCT/CN2019/129210 priority Critical patent/WO2021128284A1/zh
Publication of WO2021128284A1 publication Critical patent/WO2021128284A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]

Definitions

  • the embodiments of the present application relate to the technical field of video coding and decoding.
  • LFNST low-frequency non-separable transform
  • RST Reduced Secondary Transform
  • the embodiments of the present application provide a method and device for restricting secondary transformation.
  • a method for constraining a secondary transformation wherein the method includes:
  • the secondary transformation is enabled.
  • a constraining device for secondary transformation wherein the device includes:
  • a judging unit which judges whether the scan position of the last significant coefficient of one or more transformation units in a coding unit is not less than 1 when the intra-frame sub-partition (ISP) mode is selected;
  • a processing unit which enables the secondary conversion when the judgment unit judges yes.
  • an encoder includes a forward primary transform unit, a secondary transform unit, and a quantization unit, wherein, when the intra sub-partition (ISP) mode is selected, If the scanning position of the last effective coefficient of one or more transformation units in a coding unit is not less than 1, the secondary transformation unit is enabled, and the secondary transformation unit uses a low-frequency secondary transformation method.
  • ISP intra sub-partition
  • a decoder includes a dequantization unit, an inverse secondary transform unit, and an inverse primary transform unit, wherein when the intra sub-partition (ISP) mode is selected If the scan position of the last effective coefficient of one or more transform units in the coding unit is not less than 1, the inverse secondary transform unit is enabled, and the inverse secondary transform unit uses low-frequency secondary Change method.
  • ISP intra sub-partition
  • a computer-readable program wherein when the program is executed in an information processing device, the program causes the information processing device to execute the first aspect of the embodiments of the present application.
  • a storage medium storing a computer-readable program, wherein the computer-readable program enables an information processing device to perform the secondary transformation described in the first aspect of the embodiments of the present application. Constraint method.
  • the beneficial effect of the embodiments of the present application is that the embodiments of the present application simplifies the constraint conditions of the secondary transformation, and when the intra-sub-partition (ISP) mode is selected, the scanning position of the last effective coefficient is still considered. Reduce the complexity and running time of the codec and improve the processing speed of the codec.
  • ISP intra-sub-partition
  • Figure 1 is a schematic diagram of the encoder
  • Figure 2 is a schematic diagram of the position of the secondary transform (secondary transform) in the encoder
  • FIG. 3 is a schematic diagram of the constraint method of the secondary transformation according to an embodiment of the present application.
  • FIG. 4 is another schematic diagram of the constraint method of the secondary transformation according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a restraining device for secondary transformation according to an embodiment of the present application.
  • Fig. 6 is a schematic diagram of an image processing device according to an embodiment of the present application.
  • Fig. 7 is another schematic diagram of the image processing device of the embodiment of the present application.
  • the terms “first”, “second”, etc. are used to distinguish different elements from the terms, but they do not indicate the spatial arrangement or chronological order of these elements. These elements should not be used by these terms. Limited.
  • the term “and/or” includes any and all combinations of one or more of the associated listed terms.
  • the terms “comprising”, “including”, “having” and the like refer to the existence of the stated features, elements, elements or components, but do not exclude the presence or addition of one or more other features, elements, elements or components.
  • the first aspect of the embodiments of the present application provides a method for restricting secondary transformation, which is applied to a codec system, such as the aforementioned VVC.
  • the secondary transformation here can be applied to both the encoder in the codec system and the codec. Decoder in the decoding system.
  • Figure 1 is a schematic diagram of the encoder. As shown in Figure 1, the encoder includes a transform/quantization unit 11, an entropy encoding unit 12, a dequantization/inverse transform unit 13, an intra prediction unit 14, and a motion estimation/compensation unit 15. , And the loop filter 16.
  • the residual information obtained from the input video is transformed and quantized, and the quantized transform coefficients obtained are provided to the entropy encoding unit 12 for entropy encoding; at the decoding end, the output of the transform/quantization unit 11 is dequantized and inversed Transform, the output obtained and the predictor obtained by intra-prediction of the input video (optionally, the output obtained by motion estimation and compensation on the input video and the decoded image) are provided to the loop filter 16 Perform loop filtering to obtain decoded pictures.
  • Figure 2 is a schematic diagram of the position of the secondary transform (also called secondary transform) in the above-mentioned encoder.
  • the secondary transform is located between the forward main transform 21 and the quantization 22, which is called It is the forward secondary transform 25; at the decoding end, the secondary transform is located between the dequantization 23 and the inverse primary transform 24, which is called the inverse secondary transform 26.
  • FIG. 3 is a schematic diagram of the constraint method of the secondary transformation in the embodiment of the present application. As shown in FIG. 3, the constraint method of the secondary transformation in the embodiment of the present application includes:
  • only the scan position of the last significant coefficient of one or more transformation units in the coding unit is used to determine whether the secondary transformation is applicable, and whether the ISP mode is selected is no longer considered, which simplifies the constraints of the secondary transformation. Conditions, reduce the complexity and running time of the codec and improve the processing speed of the codec.
  • the secondary transformation may be a low frequency secondary transformation (LFNST).
  • LFNST low frequency secondary transformation
  • This application does not limit the processing process of the low frequency secondary transformation, and can refer to related technologies.
  • this application is not limited to this, and the secondary transformation may also be other transformation technologies developed with the development of coding and decoding technologies.
  • this application takes the secondary transformation to the low-frequency secondary transformation as an example for description.
  • the secondary transformation is enabled, that is, the processing process of the secondary transformation is adopted, and the secondary transformation is applicable.
  • the forward main transformation 21 and the quantization 22 The processing of the forward secondary transformation 25 is added in between; in addition, on the decoding side, the processing of the inverse secondary transformation 26 is also added between the dequantization 23 and the inverse primary transformation 24.
  • This application does not limit the processing methods of the forward primary transform 21, the forward secondary transform 25, the quantization 22, the dequantization 23, the inverse secondary transform 26, and the inverse primary transform 24, and related technologies can be referred to.
  • Table 1 shows the grammar specifications of coding units after adopting the method of the embodiment of the present application.
  • Table 2 shows the syntax specification of the transform tree in the syntax specification of the coding unit.
  • the above-mentioned secondary transformation is disabled, that is, the secondary transformation is not applicable.
  • the decoding end only the forward main transform 21 and the above quantization 22 processing are performed on the residual information, and there is no forward secondary transformation 25 processing; at the decoding end, only the received code
  • the stream undergoes the above-mentioned dequantization 23 and inverse primary transformation 24 processing without the inverse secondary transformation 26 processing.
  • This application does not limit the processing methods of forward main transform 21, quantization 22, dequantization 23, and inverse main transform 24, and can refer to related technologies.
  • the scan position of the last significant coefficient (lastScanPos) of one or more transformation units in the coding unit (coding unit) of the secondary transformation is ignored.
  • the constraint conditions apply.
  • the above constraint conditions are also taken into consideration, that is, the secondary condition is determined by one or more transformation units in the coding unit. It is applicable when the scan position of the last effective coefficient is not less than 1 (enable secondary transformation), thus simplifying the constraint conditions of secondary transformation, reducing the complexity and running time of encoding and decoding, and improving the processing of encoding and decoding. speed.
  • FIG. 4 is another schematic diagram of the constraint method of the secondary transformation according to an embodiment of the present application. As shown in FIG. 4, the method includes:
  • LFNST index is not sent and is inferred to be 0.
  • whether to enable LFNST is determined only based on whether LfnstDcOnly is 0, regardless of whether the ISP mode is selected, which simplifies the constraint conditions of LFNST, reduces the complexity and running time of encoding and decoding, and improves the processing speed of encoding and decoding.
  • FIGS. 3 and 4 only schematically illustrate the embodiments of the present application, but the present application is not limited thereto. For example, some other operations can be added. Those skilled in the art can make appropriate modifications based on the foregoing content, and are not limited to the description of the foregoing FIGS. 3 and 4.
  • the embodiment of the present application only determines whether the secondary transformation is applicable based on one constraint condition, and no longer considers whether the IPS mode is selected, which simplifies the constraint condition of the secondary transformation, reduces the complexity and running time of encoding and decoding, and improves the encoding and decoding. Decoding processing speed.
  • the second aspect of the embodiments of the present application provides a secondary transformation restraining device, which corresponds to the method of the first aspect of the embodiments, and the same content will not be repeated.
  • FIG. 5 is a schematic diagram of a secondary transformation restraining device of an embodiment of the present application.
  • the secondary transformation restraining device 500 of an embodiment of the present application includes a judging unit 501 and a processing unit 502.
  • the judging unit 501 is used for When the intra-sub-partition (ISP) mode is selected, it is judged whether the scanning position of the last effective coefficient of one or more transform units in the coding unit is not less than 1; the processing unit 502 is used to judge whether the judgment unit 501 is yes When, enable (enable) secondary conversion.
  • ISP intra-sub-partition
  • the above-mentioned secondary transformation is a low frequency secondary transformation (LFNST).
  • LFNST low frequency secondary transformation
  • the processing unit 502 disables the above-mentioned secondary transform.
  • the processing unit 502 only enables the above-mentioned secondary transformation when the scan position of the last significant coefficient of one or more transformation units in the coding unit is not less than 1.
  • the restriction device for the secondary transformation can be located at any position of the codec system and can be implemented in any manner, which is not limited in this application.
  • the secondary transformation restraint device 500 may also include other components or modules, and for the specific content of these components or modules, reference may be made to related technologies.
  • the embodiment of the present application only determines whether the secondary transformation is applicable based on one constraint condition, and no longer considers whether the IPS mode is selected, which simplifies the constraint condition of the secondary transformation, reduces the complexity and running time of encoding and decoding, and improves the encoding and decoding. Decoding processing speed.
  • the third aspect of the embodiments of the present application provides an image processing device.
  • FIG. 6 is a schematic diagram of an image processing device according to an embodiment of the present application.
  • the image processing device 600 includes an encoding device 601 and a decoding device 602.
  • the encoding device 601 includes: a forward main transform unit 6011, a secondary transformation unit 6012, and a quantization unit 6013.
  • the decoding device 602 includes a dequantization unit 6021, an inverse secondary transformation unit 6022, and an inverse primary transformation unit 6023.
  • the secondary transform unit 6012 and the inverse secondary transformation unit 6022 are enabled, and the secondary transformation unit 6012 and the inverse secondary transformation unit 6022 use a low-frequency secondary transformation method.
  • the image processing device is an encoder.
  • the encoder also includes other components, such as the entropy encoding unit 12 and the intra prediction unit shown in FIG. 14. Loop filter 16, motion estimation/compensation unit 15, etc.
  • the specific content of each constituent unit reference may be made to related technologies, which will not be repeated here.
  • the image processing device is a decoder.
  • the decoder also includes other components, such as a loop filter, a motion estimation/compensation unit, and the like. Regarding the specific content of each constituent unit, reference may be made to related technologies, which will not be repeated here.
  • the processing methods of the forward main transform unit 6011, the secondary transform unit 6012, and the quantization unit 6013 are the same as those of the forward main transform 21, the forward secondary transform 25, and the quantization 22 in FIG. technology.
  • the secondary transformation unit 6012 is enabled when the scan position of the last significant coefficient of one or more transformation units in the coding unit is not less than 1, that is, when the In intra-sub-partition (ISP) mode, if the scan position of the last significant coefficient of one or more transformation units in the coding unit is not less than 1, the secondary transformation unit 6012 is enabled to perform its secondary transformation function
  • ISP In intra-sub-partition
  • the secondary transformation unit 6012 may use a low frequency secondary transformation (LFNST) method, and the application is not limited to this.
  • LFNST low frequency secondary transformation
  • the processing methods of the dequantization unit 6021, the inverse secondary transformation unit 6022, and the inverse primary transformation unit 6023 are the same as those of the dequantization 23, the inverse secondary transformation 26, and the inverse primary transformation 24 in FIG. .
  • the inverse secondary transform unit 6022 is enabled when the scan position of the last significant coefficient of one or more transform units in a coding unit is not less than 1, that is, when the In the intra-sub-partition (ISP) mode, if the scan position of the last significant coefficient of one or more transformation units in the coding unit is not less than 1, the inverse secondary transformation unit 6022 is enabled to perform its secondary transformation For the specific functions performed by it, you can refer to related technologies, which will not be repeated here.
  • ISP intra-sub-partition
  • the inverse secondary transform unit 6022 may use a low frequency secondary transform (LFNST) method, and the present application is not limited to this.
  • LFNST low frequency secondary transform
  • the image processing device 600 may also include other components or modules. For the specific content of these components or modules, reference may be made to related technologies.
  • Fig. 7 is another schematic diagram of the image processing device of the embodiment of the present application.
  • the image processing device 700 may include: a central processing unit (CPU) 701 and a memory 702; the memory 702 is coupled to the central processing unit 701.
  • the memory 702 can store various data; in addition, it also stores information processing programs, which are executed under the control of the central processing unit 701.
  • the constraining device for the secondary transformation of the second aspect of the embodiment may be integrated into the central processing unit 701.
  • the central processing unit 701 may be configured to implement the method described in the first aspect of the embodiment.
  • the secondary transformation restraining device of the second aspect of the embodiment may be configured separately from the central processing unit 701.
  • the secondary transformation restraining device of the second aspect of the embodiment may be configured to be connected to the central processing unit 701.
  • the chip connected to 701 realizes the function of the secondary conversion restraint device in the second aspect of the embodiment under the control of the central processing unit 701.
  • the image processing device may further include: an input/output (I/O) device 703 and a display 704, etc.; wherein the functions of the above-mentioned components are similar to those of the prior art, and will not be repeated here.
  • I/O input/output
  • the image processing equipment does not necessarily include all the components shown in FIG. 7; in addition, the image processing equipment may also include components not shown in FIG. 7, such as the aforementioned encoding device 601 and decoding device 602. .
  • the aforementioned encoding device 601 and decoding device 602 can be integrated into the central processing unit 701, or the aforementioned encoding device 601 and decoding device 602 can be configured separately from the central processing unit 701, for example, it can be configured to be integrated with the central processing unit 701.
  • the connected chip realizes its function through the control of the central processing unit 701. For details, please refer to related technologies.
  • the embodiment of the present application only determines whether the secondary transformation is applicable based on one constraint condition, and no longer considers whether the IPS mode is selected, which simplifies the constraint condition of the secondary transformation, reduces the complexity and running time of encoding and decoding, and improves the encoding and decoding. Decoding processing speed.
  • the fourth aspect of the embodiments of the present application provides an encoding and decoding system, including an encoder and a decoder, and the encoder and the decoder may be implemented by the image processing device described in the third aspect of the embodiment. Since in the foregoing embodiments, the encoder and the decoder have been described, the content of the encoder and the decoder are combined with this, and will not be repeated here.
  • An embodiment of the present application provides a computer-readable program, wherein when the program is executed in an image processing device, the program causes the image processing device to execute the method described in the first aspect of the embodiment.
  • An embodiment of the present application provides a storage medium storing a computer readable program, wherein the computer readable program causes an image processing device to execute the method described in the first aspect of the embodiment.
  • the above devices and methods of this application can be implemented by hardware, or can be implemented by hardware combined with software.
  • This application relates to such a computer-readable program, when the program is executed by a logic component, the logic component can realize the above-mentioned device or constituent component, or the logic component can realize the above-mentioned various methods Or steps.
  • This application also relates to storage media used to store the above programs, such as hard disks, magnetic disks, optical disks, DVDs, flash memory, etc.
  • the method/device described in conjunction with the embodiments of the present application may be directly embodied as hardware, a software module executed by a processor, or a combination of the two.
  • one or more of the functional block diagrams and/or one or more combinations of the functional block diagrams shown in the figure may correspond to each software module of the computer program flow or each hardware module.
  • These software modules can respectively correspond to the steps shown in the figure.
  • These hardware modules can be implemented by solidifying these software modules by using a field programmable gate array (FPGA), for example.
  • FPGA field programmable gate array
  • the software module can be located in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM or any other form of storage medium known in the art.
  • a storage medium may be coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium; or the storage medium may be a component of the processor.
  • the processor and the storage medium may be located in the ASIC.
  • the software module can be stored in the memory of the mobile terminal, or can be stored in a memory card that can be inserted into the mobile terminal.
  • the software module can be stored in the MEGA-SIM card or a large-capacity flash memory device.
  • One or more of the functional blocks and/or one or more combinations of the functional blocks described in the drawings can be implemented as general-purpose processors, digital signal processors (DSPs) for performing the functions described in this application. ), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or any appropriate combination thereof.
  • DSPs digital signal processors
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • One or more of the functional blocks described in the drawings and/or one or more combinations of the functional blocks can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, or multiple micro-processing Processor, one or more microprocessors in communication with the DSP, or any other such configuration.
  • An encoder comprising a memory and a processor, the memory storing a computer program, and the processor is configured to execute the computer program to implement the following method:
  • the secondary transformation is enabled.
  • a decoder comprising a memory and a processor, the memory storing a computer program, and the processor is configured to execute the computer program to implement the following method:
  • the secondary transformation is enabled.
  • a coding and decoding system comprising an encoder and a decoder, the encoder and the decoder are respectively configured to: when the intra sub-partition (ISP) mode is selected, if the coding unit (coding unit) If the scan position of the last significant coefficient of one or more transform units is not less than 1, the secondary transform is enabled.
  • ISP intra sub-partition

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Abstract

本申请实施例提供一种二次变换的约束方法及其装置。该方法包括：当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则使能(enable)二次变换。本申请实施例简化了二次变换的约束条件，降低了编解码的复杂度和运行时间并提高了编解码的处理速度。

Description

二次变换的约束方法及其装置 技术领域
本申请实施例涉及视频编解码技术领域。
背景技术
在多功能视频编码(Versatile Video Coding，VVC)中，低频不可分变换(Low-frequency non-separable transform，LFNST，也称为简化的二次变换(Reduced Secondary Transform，RST))在前向主变换和量化(在编码端)之间以及在去量化和逆主变换(在解码端)之间应用。为了在编码效率和复杂性之间取得更好的平衡，仅当最后有效系数的扫描位置遵守一定约束时，LFNST才被限制为适用。
应该注意，上面对技术背景的介绍只是为了方便对本申请的技术方案进行清楚、完整的说明，并方便本领域技术人员的理解而阐述的。不能仅仅因为这些方案在本申请的背景技术部分进行了阐述而认为上述技术方案为本领域技术人员所公知。
发明内容
发明人发现，当前LFNST的约束条件考虑的因素比较多，导致编解码的复杂度比较高。
为了解决上述问题或其他类似问题，本申请实施例提供一种二次变换的约束方法及其装置。
根据本申请实施例的第一方面，提供了一种二次变换的约束方法，其中，所述方法包括：
当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则使能(enable)二次变换。
根据本申请实施例的第二方面，提供了一种二次变换的约束装置，其中，所述装置包括：
判断单元，其在选择了帧内子分区(ISP)模式时，判断编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置是否不小于1；
处理单元，其在所述判断单元判断为是时，使能(enable)二次变换。
根据本申请实施例的第三方面，提供了一种编码器，所述编码器包括前向主变换单元、次级变换单元以及量化单元，其中，当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则所述次级变换单元被使能，所述次级变换单元使用低频二次变换方法。
根据本申请实施例的第四方面，提供了一种解码器，所述解码器包括去量化单元、逆次级变换单元以及逆主变换单元，其中，当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则所述逆次级变换单元被使能，所述逆次级变换单元使用低频二次变换方法。
根据本申请实施例的其它方面，提供了一种计算机可读程序，其中当在信息处理设备中执行所述程序时，所述程序使得所述信息处理设备执行本申请实施例的第一方面所述的二次变换的约束方法。
根据本申请实施例的其它方面，提供了一种存储有计算机可读程序的存储介质，其中所述计算机可读程序使得信息处理设备执行本申请实施例的第一方面所述的二次变换的约束方法。
本申请实施例的有益效果在于：本申请实施例简化了二次变换的约束条件，在选择了帧内子分区(Intra Sub-Partitions，ISP)模式的情况下，仍然考虑最后有效系数的扫描位置，降低了编解码的复杂度和运行时间并提高了编解码的处理速度。
参照后文的说明和附图，详细公开了本申请的特定实施方式，指明了本申请的原理可以被采用的方式。应该理解，本申请的实施方式在范围上并不因而受到限制。在所附权利要求的条款的范围内，本申请的实施方式包括许多改变、修改和等同。
针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用，与其它实施方式中的特征相组合，或替代其它实施方式中的特征。
应该强调，术语“包括/包含”在本文使用时指特征、整件、步骤或组件的存在，但并不排除一个或更多个其它特征、整件、步骤或组件的存在或附加。
附图说明
在本申请实施例的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。此外，在附图中，类似的标 号表示几个附图中对应的部件，并可用于指示多于一种实施方式中使用的对应部件。
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是编码器的一个示意图；
图2是二次变换(次级变换)在编码器中的位置的示意图；
图3是本申请实施例的二次变换的约束方法的一个示意图；
图4是本申请实施例的二次变换的约束方法的另一个示意图；
图5是本申请实施例的二次变换的约束装置的一个示意图；
图6是本申请实施例的图像处理设备的一个示意图；
图7是本申请实施例的图像处理设备的另一个示意图。
具体实施方式
参照附图，通过下面的说明书，本申请的前述以及其它特征将变得明显。在说明书和附图中，具体公开了本申请的特定实施方式，其表明了其中可以采用本申请的原则的部分实施方式，应了解的是，本申请不限于所描述的实施方式，相反，本申请包括落入所附权利要求的范围内的全部修改、变型以及等同物。
在本申请实施例中，术语“第一”、“第二”等用于对不同元素从称谓上进行区分，但并不表示这些元素的空间排列或时间顺序等，这些元素不应被这些术语所限制。术语“和/或”包括相关联列出的术语的一种或多个中的任何一个和所有组合。术语“包含”、“包括”、“具有”等是指所陈述的特征、元素、元件或组件的存在，但并不排除存在或添加一个或多个其他特征、元素、元件或组件。
在本申请实施例中，单数形式“一”、“该”等包括复数形式，应广义地理解为“一种”或“一类”而并不是限定为“一个”的含义；此外术语“所述”应理解为既包括单数形式也包括复数形式，除非上下文另外明确指出。此外术语“根据”应理解为“至少部分根据……”，术语“基于”应理解为“至少部分基于……”，除非上下文另外明确指出。
下面结合附图对本申请的各种实施方式进行说明。这些实施方式只是示例性的， 不是对本申请的限制。
实施例的第一方面
本申请实施例的第一方面提供一种二次变换的约束方法，应用于编解码系统，例如前述VVC中，这里的二次变换既可以应用于编解码系统中的编码器也可以应用于编解码系统中的解码器。
图1是编码器的一个示意图，如图1所示，该编码器包括变换/量化单元11、熵编码单元12、去量化/逆变换单元13、帧内预测单元14、运动估计/补偿单元15、以及环路滤波器16。在编码端，从输入的视频获得的残差信息经过变换和量化，得到量化的变换系数提供给熵编码单元12进行熵编码；在解码端，对变换/量化单元11的输出进行去量化和逆变换，得到的输出与对输入视频进行帧内预测得到的预测因子(可选的，还包括通过对输入的视频和解码获得的图像进行运动估计和补偿得到的输出)提供给环路滤波器16进行环路滤波，得到解码的图片。
图2是二次变换(也称为次级变换)在上述编码器中的位置的示意图，如图2所示，在编码端，二次变换位于前向主变换21和量化22之间，称为前向次级变换25；在解码端，二次变换位于去量化23和逆主变换24之间，称为逆次级变换26。
图3是本申请实施例的二次变换的约束方法的一个示意图，如图3所示，本申请实施例的二次变换的约束方法包括：
301：当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数(lastScanPos)的扫描位置不小于1，则使能(enable)二次变换。
根据本申请实施例，仅根据编码单元内的一个或多个变换单元的最后有效系数的扫描位置来决定二次变换是否适用，而不再考虑ISP模式是否被选择，简化了二次变换的约束条件，降低了编解码的复杂度和运行时间并提高了编解码的处理速度。
在本申请实施例中，二次变换可以是低频二次变换(LFNST)，本申请对低频二次变换的处理过程不做限制，可以参考相关技术。但本申请不限于此，二次变换也可能是随着编解码技术发展的其它变换技术，为了方便说明，本申请以二次变换为低频二次变换为例进行说明。
在本申请实施例中，使能二次变换，也即二次变换的处理过程被采用，二次变换 是适用的，如图2所示，在编码端，在前向主变换21和量化22之间增加了前向次级变换25的处理；此外，在解码端，在去量化23和逆主变换24之间也增加了逆次级变换26的处理。本申请对前向主变换21、前向次级变换25、量化22、去量化23、逆次级变换26以及逆主变换24的处理方式不做限制，可以参考相关技术。
在本申请实施例中，编码单元内的一个或多个变换单元的最后有效系数的扫描位置不小于1是指编码单元中的参数LfnstDcOnly＝＝0。也即，在LfnstDcOnly＝＝0的情况下，二次变换适用。
以下的表1示出了采用本申请实施例的方法后编码单元(coding unit)的语法规范。
Figure PCTCN2019129210-appb-000001
Figure PCTCN2019129210-appb-000002
以下的表2示出了上述编码单元的语法规范中的变换树(transform tree)的语法规范。
Figure PCTCN2019129210-appb-000003
Figure PCTCN2019129210-appb-000004
在表1和表2中，在LfnstDcOnly＝＝0的情况下，使能低频二次变换(LFNST)，通过LFNST获得的信息被编入码流(比特流)。
在本申请实施例中，如果编码单元内的所有变换单元的最后有效系数(lastScanPos)的扫描位置均小于1，则禁能(disable)上述二次变换，也即，二次变换不适用。在编码端，如图2所示，仅对残差信息进行上述前向主变换21和上述量化22的处理，而没有前向次级变换25的处理；在解码端，仅对接收到的码流进行上述去量化23和逆主变换24的处理，而没有逆次级变换26的处理。本申请对前向主变换21、量化22、去量化23以及逆主变换24的处理方式不做限制，可以参考相关技术。
在本申请实施例中，编码单元内的所有变换单元的最后有效系数的扫描位置均小于1是指编码单元中的参数LfnstDcOnly＝＝1。如前所述，在LfnstDcOnly＝＝1的情况下，二次变换不适用。
在现有的二次变换的约束条件中，当选择了ISP模式时，则忽略“二次变换在编码单元(coding unit)内的一个或多个变换单元的最后有效系数(lastScanPos)的扫描位置不小于1时适用”的约束条件。在本申请实施例中，与现有的二次变换的约束条件不同，本申请在选择了ISP模式时，也考虑上述约束条件，即二次条件在编码单 元内的一个或多个变换单元的最后有效系数的扫描位置不小于1的情况下适用(使能二次变换)，由此，简化了二次变换的约束条件，降低了编解码的复杂度和运行时间并提高了编解码的处理速度。
图4是本申请实施例的二次变换的约束方法的另一个示意图，如图4所示，该方法包括：
401：判断是否LfnstDcOnly＝＝0，如果判断为是，则执行402，否则执行403；
402：LFNST适用；
403：LFNST索引不发送并推断为0。
由此，仅根据LfnstDcOnly是否为0来决定是否使能LFNST，不考虑ISP模式是否被选择，简化了LFNST的约束条件，降低了编解码的复杂度和运行时间并提高了编解码的处理速度。
值得注意的是，附图3和4仅示意性地对本申请实施例进行了说明，但本申请不限于此。例如还可以增加其他的一些操作。本领域的技术人员可以根据上述内容进行适当地变型，而不仅限于上述附图3和4的记载。
值得注意的是，以上仅对与本申请相关的各操作或过程进行了说明，但本申请不限于此。该方法还可以包括其他操作或者过程，关于这些操作或者过程的具体内容，可以参考现有技术。
本申请实施例仅根据一个约束条件来决定二次变换是否适用，而不再考虑IPS模式是否被选择，简化了二次变换的约束条件，降低了编解码的复杂度和运行时间并提高了编解码的处理速度。
实施例的第二方面
本申请实施例的第二方面提供一种二次变换的约束装置，该装置与实施例的第一方面的方法对应，相同的内容不再重复说明。
图5是本申请实施例的二次变换的约束装置的示意图，如图5所示，本申请实施例的二次变换的约束装置500包括判断单元501和处理单元502，判断单元501用于在选择了帧内子分区(ISP)模式时，判断编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置是否不小于1；处理单元502用于在判断单元501判断为是时，使能(enable)二次变换。
在一些实施例中，上述二次变换为低频二次变换(LFNST)。
在一些实施例中，编码单元内的一个或多个变换单元的最后有效系数的扫描位置不小于1是指编码单元中的参数LfnstDcOnly＝＝0。
在一些实施例中，如果判断单元501判断为编码单元内的所有变换单元的最后有效系数的扫描位置均小于1，则处理单元502禁能(disable)上述二次变换。
在一些实施例中，编码单元内的所有变换单元的最后有效系数的扫描位置均小于1是指编码单元中的参数LfnstDcOnly＝＝1。
在一些实施例中，处理单元502仅在编码单元内的一个或多个变换单元的最后有效系数的扫描位置不小于1的情况下使能上述二次变换。
关于二次变换在编解码系统中的位置已经在实施例的第一方面做了详细说明，此处不再赘述。
在本申请实施例中，该二次变换的约束装置可以位于编解码系统的任意位置，可以通过任意的方式实现，本申请对此不做限制。
值得注意的是，以上仅对与本申请相关的各部件或模块进行了说明，但本申请不限于此。二次变换的约束装置500还可以包括其他部件或者模块，关于这些部件或者模块的具体内容，可以参考相关技术。
本申请实施例仅根据一个约束条件来决定二次变换是否适用，而不再考虑IPS模式是否被选择，简化了二次变换的约束条件，降低了编解码的复杂度和运行时间并提高了编解码的处理速度。
实施例的第三方面
本申请实施例的第三方面提供一种图像处理设备。
图6是本申请实施例的图像处理设备的一个示意图，如图6所示，本申请实施例的图像处理设备600包括编码装置601和解码装置602，该编码装置601包括：前向主变换单元6011、次级变换单元6012以及量化单元6013，该解码装置602包括去量化单元6021、逆次级变换单元6022以及逆主变换单元6023。在本申请实施例中，当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则次级变换单元6012和逆次级变换单元6022被使能，次级变换单元6012和逆次级变换单元6022使用低频二次变换方法。
在一些实施例中，该图像处理设备是编码器，该编码器除了包括上述编码装置601和上述解码装置602以外，还包括其他组成，例如图1所示的熵编码单元12、帧内预测单元14、环路滤波器16、运动估计/补偿单元15等。关于各组成单元的具体内容，可以参考相关技术，此处不再赘述。
在一些实施例中，该图像处理设备是解码器，该解码器除了包括上述编码装置601和上述解码装置602以外，还包括其他组成，例如环路滤波器、运动估计/补偿单元等。关于各组成单元的具体内容，可以参考相关技术，此处不再赘述。
在本申请实施例中，前向主变换单元6011、次级变换单元6012以及量化单元6013的处理方式与图2的前向主变换21、前向次级变换25以及量化22相同，可以参考相关技术。
在本申请实施例中，次级变换单元6012在编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1的情况下被使能，也即，当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则次级变换单元6012被使能执行其次级变换的功能，关于具体其所执行的功能，可以参考相关技术，此处不再赘述。
在本申请实施例中，次级变换单元6012可以使用低频二次变换(LFNST)方法，本申请不限于此。
在本申请实施例中，去量化单元6021、逆次级变换单元6022以及逆主变换单元6023的处理方式与图2的去量化23、逆次级变换26以及逆主变换24，可以参考相关技术。
在本申请实施例中，逆次级变换单元6022在编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1的情况下被使能，也即，当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则逆次级变换单元6022被使能执行其次级变换的功能，关于具体其所执行的功能，可以参考相关技术，此处不再赘述。
在本申请实施例中，逆次级变换单元6022可以使用低频二次变换(LFNST)方法，本申请不限于此。
值得注意的是，以上仅对与本申请相关的各部件或模块进行了说明，但本申请不限于此。图像处理设备600还可以包括其他部件或者模块，关于这些部件或者模块的 具体内容，可以参考相关技术。
图7是本申请实施例的图像处理设备的另一个示意图。如图7所示，图像处理设备700可以包括：中央处理器(CPU)701和存储器702；存储器702耦合到中央处理器701。其中该存储器702可存储各种数据；此外还存储信息处理的程序，并且在中央处理器701的控制下执行该程序。
在一些实施例中，实施例的第二方面的二次变换的约束装置可以被集成到中央处理器701中。其中，中央处理器701可以被配置为实现如实施例的第一方面所述的方法。
在一些实施例中，实施例的第二方面的二次变换的约束装置可以与中央处理器701分开配置，例如可以将实施例的第二方面的二次变换的约束装置配置为与中央处理器701连接的芯片，通过中央处理器701的控制来实现实施例的第二方面的二次变换的约束装置的功能。
此外，如图7所示，图像处理设备还可以包括：输入输出(I/O)设备703和显示器704等；其中，上述部件的功能与现有技术类似，此处不再赘述。值得注意的是，图像处理设备也并不是必须要包括图7中所示的所有部件；此外，图像处理设备还可以包括图7中没有示出的部件，例如前述的编码装置601和解码装置602。其中，前述编码装置601和解码装置602可以被集成到中央处理器701中，或者，前述的编码装置601和解码装置602可以与中央处理器701分开配置，例如将其配置为与中央处理器701连接的芯片，通过中央处理器701的控制来实现其功能，具体可以参考相关技术。
本申请实施例仅根据一个约束条件来决定二次变换是否适用，而不再考虑IPS模式是否被选择，简化了二次变换的约束条件，降低了编解码的复杂度和运行时间并提高了编解码的处理速度。
实施例的第四方面
本申请实施例的第四方面提供一种编解码系统，包括编码器和解码器，该编码器和解码器可以通过如实施例的第三方面所述的图像处理设备来实现。由于在前述实施例中，已经对该编码器和该解码器做了说明，其内容被合并与此，此处不再赘述。
本申请实施例提供一种计算机可读程序，其中当在图像处理设备中执行所述程序时，所述程序使得所述图像处理设备执行如实施例的第一方面所述的方法。
本申请实施例提供一种存储有计算机可读程序的存储介质，其中所述计算机可读程序使得图像处理设备执行如实施例的第一方面所述的方法。
本申请以上的装置和方法可以由硬件实现，也可以由硬件结合软件实现。本申请涉及这样的计算机可读程序，当该程序被逻辑部件所执行时，能够使该逻辑部件实现上文所述的装置或构成部件，或使该逻辑部件实现上文所述的各种方法或步骤。本申请还涉及用于存储以上程序的存储介质，如硬盘、磁盘、光盘、DVD、flash存储器等。
结合本申请实施例描述的方法/装置可直接体现为硬件、由处理器执行的软件模块或二者组合。例如，图中所示的功能框图中的一个或多个和/或功能框图的一个或多个组合，既可以对应于计算机程序流程的各个软件模块，亦可以对应于各个硬件模块。这些软件模块，可以分别对应于图中所示的各个步骤。这些硬件模块例如可利用现场可编程门阵列(FPGA)将这些软件模块固化而实现。
软件模块可以位于RAM存储器、闪存、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、移动磁盘、CD-ROM或者本领域已知的任何其它形式的存储介质。可以将一种存储介质耦接至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息；或者该存储介质可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。该软件模块可以存储在移动终端的存储器中，也可以存储在可插入移动终端的存储卡中。例如，若设备(如移动终端)采用的是较大容量的MEGA-SIM卡或者大容量的闪存装置，则该软件模块可存储在该MEGA-SIM卡或者大容量的闪存装置中。
针对附图中描述的功能方框中的一个或多个和/或功能方框的一个或多个组合，可以实现为用于执行本申请所描述功能的通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或者其它可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件或者其任意适当组合。针对附图描述的功能方框中的一个或多个和/或功能方框的一个或多个组合，还可以实现为计算设备的组合，例如，DSP和微处理器的组合、多个微处理器、与DSP通信结合的一个或多个微处理器或者任何其它这种配置。
以上结合具体的实施方式对本申请进行了描述，但本领域技术人员应该清楚，这 些描述都是示例性的，并不是对本申请保护范围的限制。本领域技术人员可以根据本申请的精神和原理对本申请做出各种变型和修改，这些变型和修改也在本申请的范围内。
关于包括以上实施例的实施方式，还公开下述的附记：
1、一种编码器，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器被配置为执行所述计算机程序而实现以下方法：
当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则使能(enable)二次变换。
2、一种解码器，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器被配置为执行所述计算机程序而实现以下方法：
当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则使能(enable)二次变换。
3、一种编解码系统，包括编码器和解码器，所述编码器和所述解码器分别被配置为：当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则使能(enable)二次变换。

Claims (14)

  1. 一种二次变换的约束方法，其特征在于，所述方法包括：
    当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则使能(enable)二次变换。
  2. 根据权利要求1所述的方法，其中，所述二次变换为低频二次变换LFNST)。
  3. 根据权利要求1所述的方法，其中，编码单元内的一个或多个变换单元的最后有效系数的扫描位置不小于1是指所述编码单元中的参数LfnstDcOnly＝＝0。
  4. 根据权利要求1所述的方法，其中，如果编码单元内的所有变换单元的最后有效系数的扫描位置均小于1，则禁能(disable)所述二次变换。
  5. 根据权利要求4所述的方法，其中，编码单元内的所有变换单元的最后有效系数的扫描位置均小于1是指所述编码单元中的参数LfnstDcOnly＝＝1。
  6. 根据权利要求1所述的方法，其中，使能所述二次变换仅在所述编码单元内的一个或多个变换单元的最后有效系数的扫描位置不小于1的情况下执行。
  7. 一种二次变换的约束装置，其特征在于，所述装置包括：
    判断单元，其在选择了帧内子分区(ISP)模式时，判断编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置是否不小于1；
    处理单元，其在所述判断单元判断为是时，使能(enable)二次变换。
  8. 根据权利要求7所述的装置，其中，所述二次变换为低频二次变换(LFNST)。
  9. 根据权利要求7所述的装置，其中，编码单元内的一个或多个变换单元的最后有效系数的扫描位置不小于1是指所述编码单元中的参数LfnstDcOnly＝＝0。
  10. 根据权利要求7所述的装置，其中，如果所述判断单元判断为编码单元内的所有变换单元的最后有效系数的扫描位置均小于1，则所述处理单元禁能(disable)所述二次变换。
  11. 根据权利要求10所述的装置，其中，编码单元内的所有变换单元的最后有效系数的扫描位置均小于1是指所述编码单元中的参数LfnstDcOnly＝＝1。
  12. 根据权利要求7所述的装置，其中，所述处理单元仅在所述编码单元内的一个或多个变换单元的最后有效系数的扫描位置不小于1的情况下使能所述二次变换。
  13. 一种图像处理设备，所述图像处理设备包括编码装置和解码装置，所述编码 装置包括：前向主变换单元、次级变换单元以及量化单元，所述解码装置包括：去量化单元、逆次级变换单元以及逆主变换单元，其特征在于，当选择了帧内子分区(ISP)模式时，如果编码单元(coding unit)内的一个或多个变换单元的最后有效系数的扫描位置不小于1，则所述次级变换单元和所述逆次级变换单元被使能，所述次级变换单元和所述逆次级变换单元使用低频二次变换方法。
  14. 根据权利要求13所述的图像处理设备，其中，所述图像处理设备为编码器或者解码器。
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