WO2021124453A1 - Inverter circuit - Google Patents

Inverter circuit Download PDF

Info

Publication number
WO2021124453A1
WO2021124453A1 PCT/JP2019/049446 JP2019049446W WO2021124453A1 WO 2021124453 A1 WO2021124453 A1 WO 2021124453A1 JP 2019049446 W JP2019049446 W JP 2019049446W WO 2021124453 A1 WO2021124453 A1 WO 2021124453A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
potential
switching element
state
wiring
Prior art date
Application number
PCT/JP2019/049446
Other languages
French (fr)
Japanese (ja)
Inventor
歩生 小石
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to JP2021565211A priority Critical patent/JPWO2021124453A1/ja
Priority to PCT/JP2019/049446 priority patent/WO2021124453A1/en
Publication of WO2021124453A1 publication Critical patent/WO2021124453A1/en

Links

Images

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the technology disclosed herein relates to an inverter circuit.
  • Japanese Patent Publication No. 2013-243877 discloses an inverter circuit including two MOSFETs connected in series.
  • a gate drive circuit is connected to the gate of each MOSFET.
  • Each gate drive circuit applies a negative potential to the gate of the MOSFET when controlling the MOSFET to the off state.
  • the MOSFET may turn on unintentionally (hereinafter referred to as erroneous turning on). For example, when the MOSFET of the upper arm turns on, the drain potential of the MOSFET of the lower arm rises. Then, the gate potential of the MOSFET of the lower arm rises momentarily due to the capacitive coupling between the drain and the gate of the MOSFET of the lower arm. Due to this increase in the gate potential, the MOSFET of the lower arm may be erroneously turned on. In addition, false on may occur in the MOSFET of the upper arm.
  • the MOSFET of the lower arm when the MOSFET of the lower arm is turned on, the source potential of the MOSFET of the upper arm is lowered, and the gate potential of the MOSFET of the upper arm is lowered accordingly. Therefore, the drain potential of the MOSFET of the upper arm rises relative to the gate potential. Then, the gate potential of the upper arm rises momentarily due to the capacitive coupling between the drain and the gate of the MOSFET of the upper arm. Due to this increase in the gate potential, the MOSFET of the upper arm may be erroneously turned on.
  • the MOSFET of the own arm (that is, the MOSFET that is kept in the off state) may be erroneously turned on by the turn-on of the MOSFET of the opposite arm (that is, the MOSFET that is not the MOSFET of the own arm).
  • This specification proposes a technique for suppressing erroneous ON of a switching element in an inverter circuit and suppressing a decrease in a gate threshold value.
  • the inverter circuit includes high-potential wiring, low-potential wiring, intermediate wiring connected to the traveling motor, between the high-potential wiring and the intermediate wiring, and between the intermediate wiring and the low-potential wiring.
  • the first switching element connected to one side, the second switching element connected to the other between the high-potential wiring and the intermediate wiring, and the other between the intermediate wiring and the low-potential wiring, and the second switching. It has a gate drive circuit connected to the gate of the element.
  • the gate drive circuit sets the potential applied to the gate to a gate-on potential and a negative potential higher than the gate threshold of the second switching element.
  • a potential higher than the negative potential and lower than the gate threshold is applied to the gate.
  • the value of the potential applied to the gate of the second switching element in the second state may be higher than the negative potential and lower than the gate threshold value, and may be negative or positive. , May be zero.
  • the gate drive circuit changes the potential applied to the gate between the gate-on potential and the negative potential in the first state, and in the second state, the potential is higher than the negative potential and lower than the gate threshold. Is applied to the gate. That is, in the first state in which the inverter circuit is operating, the above-mentioned erroneous on can occur, so that the gate drive circuit applies a negative potential to the gate in order to maintain the second switching element in the off state. On the other hand, in the second state in which the inverter circuit is not operating, both the first switching element and the second switching element do not switch (that is, they are maintained in the off state), so that the above-mentioned increase in the gate potential does not occur.
  • the gate drive circuit applies a potential higher than the negative potential to the gate of the second switching element.
  • a potential higher than the negative potential to the gate of the second switching element.
  • the inverter circuit by changing the potential applied to the gate according to the operating condition of the inverter circuit, it is possible to suppress the occurrence of erroneous ON and suppress the decrease of the gate threshold value.
  • the circuit diagram of the inverter circuit 10. The circuit diagram which shows the series circuit of the switching element 22a, 22d. The graph which shows the change of each value when the switching element 22a is switched in the 1st state. The graph which shows each value in the 2nd state. The graph which shows the change of each value when the switching element 22d is switched in the 1st state. The flowchart of the state determination process of the inverter circuit 10.
  • a control device connected to the gate drive circuit may be further provided.
  • the inverter circuit may be mounted on a vehicle.
  • the control device may determine that it is in the first state when the vehicle is traveling, and may determine that it is in the second state when the vehicle is stopped.
  • the first switching element and the second switching element may be FETs (Field Effect Transistors) provided on a SiC substrate.
  • the switching element provided with the SiC substrate has a low gate threshold value, the above-mentioned erroneous on is likely to occur. For this reason, the techniques disclosed herein are particularly useful for inverter circuits that include FETs on SiC substrates.
  • the inverter circuit 10 is mounted on an electric vehicle (including a hybrid vehicle and a fuel cell vehicle).
  • the inverter circuit 10 shown in FIG. 1 converts the DC power supplied from the DC power supply 20 into three-phase AC power, and supplies the three-phase AC power to the traveling motor (hereinafter, simply referred to as a motor) 18.
  • the inverter circuit 10 has a high-potential wiring 12, a low-potential wiring 14, and three intermediate wirings 16a to 16c.
  • the positive electrode of the DC power supply 20 is connected to the high potential wiring 12.
  • the negative electrode of the DC power supply 20 is connected to the low potential wiring 14. Therefore, a higher potential is applied to the high-potential wiring 12 than to the low-potential wiring 14.
  • the intermediate wirings 16a to 16c are connected to the motor 18.
  • the inverter circuit 10 has six switching elements 22a to 22f and six gate drive circuits 30a to 30f.
  • the switching elements 22a to 22f are insulated gate type switching elements, respectively, and are MOSFETs in this embodiment.
  • the switching elements 22a to 22f include a SiC substrate. Current switching is performed inside the SiC substrate. Since the switching elements 22a to 22f provided with the SiC substrate have a low gate threshold value, erroneous ON is likely to occur.
  • another semiconductor substrate such as a Si substrate or a GaN substrate may be used.
  • the drain of the switching element 22a is connected to the high potential wiring 12.
  • the source of the switching element 22a is connected to the intermediate wiring 16a.
  • the gate of the switching element 22a is connected to the gate drive circuit 30a.
  • the gate drive circuit 30a controls the potential of the gate of the switching element 22a.
  • the drain of the switching element 22b is connected to the high potential wiring 12.
  • the source of the switching element 22b is connected to the intermediate wiring 16b.
  • the gate of the switching element 22b is connected to the gate drive circuit 30b.
  • the gate drive circuit 30b controls the potential of the gate of the switching element 22b.
  • each of the switching elements 22a to 22c may be referred to as an upper arm switching element.
  • the drain of the switching element 22d is connected to the intermediate wiring 16a.
  • the source of the switching element 22d is connected to the low potential wiring 14.
  • the gate of the switching element 22d is connected to the gate drive circuit 30d.
  • the gate drive circuit 30d controls the potential of the gate of the switching element 22d.
  • the drain of the switching element 22e is connected to the intermediate wiring 16b.
  • the source of the switching element 22e is connected to the low potential wiring 14.
  • the gate of the switching element 22e is connected to the gate drive circuit 30e.
  • the gate drive circuit 30e controls the potential of the gate of the switching element 22e. When the switching element 22e is turned on, a current flows from the intermediate wiring 16b to the low potential wiring 14.
  • the drain of the switching element 22f is connected to the intermediate wiring 16c.
  • the source of the switching element 22f is connected to the low potential wiring 14.
  • the gate of the switching element 22f is connected to the gate drive circuit 30f.
  • the gate drive circuit 30f controls the potential of the gate of the switching element 22f. When the switching element 22f is turned on, a current flows from the intermediate wiring 16c to the low potential wiring 14.
  • each of the switching elements 22d to 22f may be referred to as a lower arm switching element.
  • Diodes 24a to 24f are connected in parallel to each of the switching elements 22a to 22f.
  • Each of the anodes of the diodes 24a-24f is connected to the source of the corresponding switching elements 22a-22f.
  • Each of the cathodes of the diodes 24a to 24f is connected to the drain of the corresponding switching elements 22a to 22f.
  • the gate drive circuits 30a to 30f are connected to the control device 40.
  • the control device 40 outputs a gate drive signal for controlling the potential of the gate of each of the switching elements 22a to 22f to each of the gate drive circuits 30a to 30f.
  • FIG. 2 shows a series circuit of the switching element 22a and the switching element 22d.
  • signals are input from the control device 40 to the gate drive circuits 30a and 30d.
  • the control device 40 determines whether or not the vehicle is traveling. That is, the control device 40 determines whether or not power is being supplied from the inverter circuit 10 to the motor 18.
  • the control device 40 inputs signals to the gate drive circuits 30a and 30d according to the determination result.
  • the gate drive signal Sa1 is input from the control device 40 to the gate drive circuit 30a.
  • the gate drive circuit 30a switches the switching element 22a based on the gate drive signal Sa1.
  • the gate drive signal Sd1 is input from the control device 40 to the gate drive circuit 30d.
  • the gate drive circuit 30d switches the switching element 22d based on the gate drive signal Sd1.
  • the gate drive circuits 30a and 30d switch the switching elements 22a and 22d based on the gate drive signals Sa1 and Sd1, so that the motor 18 is supplied with electric power.
  • the gate drive circuits 30a and 30d control the potential of each gate so that the switching element 22a and the switching element 22d do not turn on at the same time.
  • the gate drive signal Sa2 is input from the control device 40 to the gate drive circuit 30a.
  • the gate drive circuit 30a controls the potential of the gate of the switching element 22a so as to keep the switching element 22a in the off state based on the gate drive signal Sa2.
  • the gate drive signal Sd2 is input from the control device 40 to the gate drive circuit 30d.
  • the gate drive circuit 30d controls the potential of the gate of the switching element 22d so as to keep the switching element 22d in the off state based on the gate drive signal Sd2.
  • FIG. 3 shows the operation in the first state. That is, the gate drive signal Sa1 is input from the control device 40 to the gate drive circuit 30a, and the gate drive signal Sd1 is input from the control device 40 to the gate drive circuit 30d. Further, FIG. 3 shows changes in each value when switching the switching element 22a of the upper arm while keeping the switching element 22d of the lower arm in the off state in the first state.
  • reference numeral Vga indicates the gate potential of the switching element 22a of the upper arm
  • reference numeral Vdsa indicates the drain-source voltage of the switching element 22a of the upper arm.
  • Vgd indicates the gate potential of the switching element 22d of the lower arm
  • reference numeral Vdsd indicates the drain-source voltage of the switching element 22d of the lower arm.
  • the gate potential VGA is shown as the potential of the switching element 22a with respect to the source
  • the gate potential Vgd is shown as the potential of the switching element 22d with respect to the source.
  • the gate drive circuit 30a controls the gate potential VGA of the switching element 22a to the gate-off potential Voffa1.
  • the gate-off potential Voffa1 is lower than the gate threshold value Vtha of the switching element 22a.
  • the gate-off potential Voffa1 is a negative potential (that is, a potential lower than the source of the switching element 22a). Since the gate-off potential Voffa1 is lower than the gate threshold value Vtha, the switching element 22a is turned off.
  • the gate drive circuit 30d controls the gate potential Vgd of the switching element 22d to the gate-off potential Voffd1.
  • the gate-off potential Voffd1 is lower than the gate threshold value Vthd of the switching element 22d.
  • the gate-off potential Voffd1 is a negative potential (that is, a potential lower than the source of the switching element 22d). Since the gate-off potential Voffd1 is lower than the gate threshold value Vthd, the switching element 22d is off. In this state, since the motor 18 is driven, the potential of the intermediate wiring 16a is lower than the potential of the low potential wiring 14. Therefore, as shown by the arrow 100 in FIG. 2, a current flows from the low potential wiring 14 to the intermediate wiring 16a via the diode 24d. Since the diode 24d is on, the drain-source voltage Vdsd of the switching element 22d is approximately 0V. Further, since the potential difference between the high potential wiring 12 and the intermediate wiring 16a is applied to the switching element 22a, the drain-source voltage Vdsa of the switching element 22a becomes a high voltage.
  • the gate drive circuit 30a raises the gate potential VGA of the switching element 22a from the gate-off potential Voffa1 to the gate-on potential Vona.
  • the gate-on potential Vona is higher than the gate threshold Vza. Therefore, immediately after the timing t1, the switching element 22a turns on.
  • the current indicated by the arrow 100 in FIG. 2 is stopped, and as shown by the arrow 102, the current flows from the high potential wiring 12 to the intermediate wiring 16a via the switching element 22a. Since the switching element 22a turns on, the drain-source voltage Vdsa of the switching element 22a drops to approximately 0V immediately after the timing t1. Therefore, the potential of the drain of the switching element 22d rises to a high potential.
  • the drain-source voltage Vdsd of the switching element 22d rises to a high voltage.
  • the gate drive circuit 30d continues to apply the gate-off potential Voffd1 (that is, the negative potential) to the gate of the switching element 22d.
  • Voffd1 that is, the negative potential
  • the gate of the switching element 22d is momentarily coupled by the capacitance via the parasitic capacitance (Cd in FIG. 2) between the drain and the gate of the switching element 22d.
  • a surge voltage 90 is applied to the. Therefore, immediately after the timing t1, the gate potential Vgd rises momentarily.
  • the gate drive circuit 30d applies a gate-off potential Voffd1 (that is, a negative potential) to the gate of the switching element 22d. Therefore, even if the surge voltage 90 is applied, the gate potential Vgd does not reach the gate threshold value Vthd. As a result, erroneous ON of the switching element 22d is suppressed.
  • Voffd1 that is, a negative potential
  • FIG. 4 shows the operation of the second state. That is, the gate drive signal Sa2 is input from the control device 40 to the gate drive circuit 30a, and the gate drive signal Sd2 is input from the control device 40 to the gate drive circuit 30d.
  • the inverter circuit 10 does not supply electric power to the motor 18, both the switching element 22a and the switching element 22d are maintained in the off state. That is, the switching element 22a and the switching element 22d do not switch.
  • the gate drive circuit 30a controls the gate potential VGA of the switching element 22a to the gate-off potential Voffa2.
  • the gate-off potential Voffa2 is lower than the gate threshold value Vtha of the switching element 22a. Therefore, the switching element 22a is turned off.
  • the gate-off potential Voffa2 is higher than the gate-off potential Voffa1 in the first state shown in FIG. In this embodiment, the gate-off potential Voffa2 is higher than 0V and lower than the gate threshold Vthd.
  • the gate drive circuit 30d controls the gate potential Vgd of the switching element 22d to the gate-off potential Voffd2.
  • the gate-off potential Voffd2 is lower than the gate threshold value Vthd of the switching element 22d.
  • the switching element 22d is turned off. Further, the gate-off potential Voffd2 is higher than the gate-off potential Voffd1 in the first state shown in FIG. In this embodiment, the gate-off potential Voffd2 is higher than 0V. In this state, since no current flows through the inverter circuit 10, the potential of the intermediate wiring 16a is floating, and the potential difference between the high potential wiring 12 and the low potential wiring 14 is applied to the series circuit of the switching element 22a and the switching element 22d. To. Therefore, the drain-source voltage Vdsd of the switching element 22a and the drain-source voltage Vdsd of the switching element 22d are substantially equal. In the second state, the gate drive circuit 30a continues to apply the gate-off potential Voffa2 to the gate of the switching element 22a. Further, the gate drive circuit 30d continues to apply the gate-off potential Voffd2 to the gate of the switching element 22d.
  • the surge voltage 90 described in the first state is not applied to the gate of the switching element 22d. Therefore, in the second state, even if the potential applied to the gate (that is, the gate-off potential Voltage2) for maintaining the switching element 22d in the off state is set to a value higher than the gate-off potential Voltage1 in the first state, The switching element 22d is not erroneously turned on due to the surge voltage 90.
  • the gate-off potential Voffd2 that is, a potential higher than the gate-off potential Voffd1
  • FIG. 5 shows the operation in the first state. That is, the gate drive signal Sa1 is input from the control device 40 to the gate drive circuit 30a, and the gate drive signal Sd1 is input from the control device 40 to the gate drive circuit 30d.
  • FIG. 5 shows changes in each value when switching the switching element 22d of the lower arm while maintaining the switching element 22a of the upper arm in the off state in the first state, unlike FIG.
  • the initial states of the gate potentials VGA and Vda of the switching elements 22a and 22d shown in FIG. 5 are the same as the initial states of FIG. That is, both the switching element 22a and the switching element 22d are off.
  • the potential of the intermediate wiring 16a is higher than the potential of the high potential wiring 12. Therefore, as shown by the arrow 104 in FIG. 2, a current flows from the intermediate wiring 16a to the high potential wiring 12 via the diode 24a. Since the diode 24a is on, the drain-source voltage Vdsa of the switching element 22a is approximately 0V. Further, since the potential difference between the intermediate wiring 16a and the low potential wiring 14 is applied to the switching element 22d, the drain-source voltage Vdsd of the switching element 22d becomes a high voltage.
  • the gate drive circuit 30d raises the gate potential Vgd of the switching element 22d from the gate-off potential Voffd1 to the gate-on potential Vondo.
  • the gate-on potential Bond is higher than the gate threshold Vthd. Therefore, immediately after the timing t2, the switching element 22d turns on. Then, the current indicated by the arrow 104 in FIG. 2 is stopped, and as shown by the arrow 106, the current flows from the intermediate wiring 16a to the low potential wiring 14 via the switching element 22d. Since the switching element 22d turns on, the drain-source voltage Vdsd of the switching element 22d drops to approximately 0V immediately after the timing t2. Therefore, the potential of the source of the switching element 22a drops to a low potential.
  • the potential of the drain of the switching element 22a is relatively high with respect to the potential of the source. Therefore, the drain-source voltage Vdsa of the switching element 22a rises to a high voltage.
  • the gate drive circuit 30a continues to apply the gate-off potential Voffa1 (that is, the negative potential) to the gate of the switching element 22a.
  • Voffa1 that is, the negative potential
  • the gate of the switching element 22a is momentarily connected by the capacitance coupling via the parasitic capacitance (Ca in FIG. 2) between the drain and the gate of the switching element 22a.
  • a surge voltage 92 is applied to the. Therefore, immediately after the timing t2, the gate potential Vga rises momentarily.
  • the gate drive circuit 30a applies a gate-off potential Voffa1 (that is, a negative potential) to the gate of the switching element 22a. Therefore, even if the surge voltage 92 is applied, the gate potential VGA does not reach the gate threshold value Vtha. As a result, erroneous ON of the switching element 22a is suppressed.
  • Voffa1 that is, a negative potential
  • the potentials applied to the gates of the switching elements 22a and 22d are set according to the operating condition of the inverter circuit 10.
  • the potential (off state) it is possible to suppress the occurrence of erroneous on and suppress the decrease of the gate threshold with time.
  • the control device 40 determines whether the inverter circuit 10 is in the first state or the second state.
  • the state determination process is repeatedly executed while the main switch of the vehicle is on.
  • the control device 40 determines whether or not the vehicle is traveling.
  • the control device 40 proceeds to S12. It can be determined that the vehicle is running, for example, by detecting that the D (drive) range is selected in the shift lever of the vehicle and the vehicle speed is not zero.
  • the control device 40 determines that the vehicle is traveling and is in the first state (that is, the state in which the inverter circuit 10 is supplying electric power to the motor 18). Then, the control device 40 outputs the gate drive signals Sa1 and Sd1 for commanding the target output to the gate drive circuits 30a and 30d, respectively.
  • the gate drive circuit 30a applies a potential that changes between the gate-on potential Vona and the gate-off potential Voffa1 (that is, a negative potential) described above to the gate of the switching element 22a.
  • the gate drive circuit 30d applies a potential that changes between the gate-on potential Bond and the gate-off potential Voffd1 (that is, a negative potential) described above to the gate of the switching element 22d. As a result, the switching elements 22a and 22d are switched, and electric power is supplied to the motor 18.
  • control device 40 determines in S10 that the vehicle is stopped (NO in S10), the control device 40 proceeds to S14.
  • the fact that the vehicle is stopped means that, for example, the P (parking) range or the N (neutral) range is selected in the shift lever of the vehicle, the vehicle speed is zero and the brake pedal is depressed, and the vehicle speed. It can be determined by detecting that the state in which is zero continues for a predetermined period of time.
  • the control device 40 determines that the vehicle is in the second state (that is, the state in which the power is not supplied from the inverter circuit 10 to the motor 18) because the vehicle is stopped. Then, the control device 40 outputs the gate drive signals Sa2 and Sd2 to the gate drive circuits 30a and 30d, respectively. As a result, the gate drive circuit 30a applies the above-mentioned gate-off potential Voffa2 (that is, a potential higher than 0V and lower than the gate threshold value Vtha) to the gate of the switching element 22a.
  • Voffa2 that is, a potential higher than 0V and lower than the gate threshold value Vtha
  • the gate drive circuit 30d applies the above-mentioned gate-off potential Voffad (that is, a potential higher than 0V and lower than the gate threshold value Vthd) to the gate of the switching element 22d. That is, the switching elements 22a and 22d are maintained in the off state.
  • Voffad that is, a potential higher than 0V and lower than the gate threshold value Vthd
  • the gate-off potentials Voffa2 and Voffd2 had values higher than 0V.
  • the gate-off potential Voffa2 may be higher than the gate-off potential Vofa1 and lower than the gate threshold value Vtha.
  • the gate-off potential Voffd2 may be higher than the gate-off potential Voffd1 and lower than the gate threshold value Vthd. That is, the values of the gate-off potentials Voffa2 and Voffd2 may be negative, positive, or zero.
  • the switching element 22a or the switching element 22d of the embodiment is an example of the "first switching element” of the claim, and the switching element 22d or the switching element 22a of the embodiment is an example of the "second switching element” of the claim. is there.
  • the gate-off potentials Voffa1 and Voffd1 of the embodiment are examples of the "negative potential” of the claim.
  • the gate-off potentials Voffa2 and Voffd2 of the embodiment are an example of the claim "potential higher than negative potential and lower than gate threshold value".

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

Disclosed is an inverter circuit that supplies power to a traveling motor. This inverter circuit is provided with: a high-potential wire; a low-potential wire; an intermediate wire connected to the traveling motor; a first switching element connected to one of a part between the high-potential wire and the intermediate wire and a part between the intermediate wire and the low-potential wire; a second switching element connected to the other of the part between the high-potential wire and the intermediate wire and the part between the intermediate wire and the low-potential wire; and a gate driving circuit connected to a gate of the second switching element. In a first state where the inverter circuit supplies power to the traveling motor, the gate driving circuit changes a potential to be applied to the gate between a negative potential and a gate-on potential higher than a gate threshold value of the second switching element. In a second state where the inverter circuit does not supply power to the traveling motor, the gate driving circuit applies, to the gate, a potential higher than the negative potential but lower than the gate threshold value.

Description

インバータ回路Inverter circuit
 本明細書に開示の技術は、インバータ回路に関する。 The technology disclosed herein relates to an inverter circuit.
 日本公開特許公報第2013-243877号には、直列に接続された2つのMOSFETを備えるインバータ回路が開示されている。各MOSFETのゲートには、ゲート駆動回路が接続されている。各ゲート駆動回路は、MOSFETをオフ状態に制御するときに、MOSFETのゲートに負電位を印加する。 Japanese Patent Publication No. 2013-243877 discloses an inverter circuit including two MOSFETs connected in series. A gate drive circuit is connected to the gate of each MOSFET. Each gate drive circuit applies a negative potential to the gate of the MOSFET when controlling the MOSFET to the off state.
 MOSFETが意図せずオンする現象(以下、誤オンという。)が生じる場合がある。例えば、上アームのMOSFETがターンオンすると、下アームのMOSFETのドレイン電位が上昇する。すると、下アームのMOSFETのドレイン-ゲート間の容量結合によって、下アームのMOSFETのゲート電位が瞬間的に上昇する。このゲート電位の上昇によって、下アームのMOSFETが誤オンする場合がある。また、誤オンは、上アームのMOSFETで生じる場合もある。すなわち、下アームのMOSFETがターンオンすると、上アームのMOSFETのソース電位が低下し、それに伴って上アームのMOSFETのゲート電位が低下する。このため、上アームのMOSFETのドレイン電位がゲート電位に対して相対的に上昇する。すると、上アームのMOSFETのドレイン-ゲート間の容量結合によって、上アームのゲート電位が瞬間的に上昇する。このゲート電位の上昇によって、上アームのMOSFETが誤オンする場合がある。このように、自アームのMOSFET(すなわち、オフ状態に維持されているMOSFET)が、対向アームのMOSFET(すなわち、自アームのMOSFETではない方のMOSFET)のターンオンによって誤オンする場合がある。 The MOSFET may turn on unintentionally (hereinafter referred to as erroneous turning on). For example, when the MOSFET of the upper arm turns on, the drain potential of the MOSFET of the lower arm rises. Then, the gate potential of the MOSFET of the lower arm rises momentarily due to the capacitive coupling between the drain and the gate of the MOSFET of the lower arm. Due to this increase in the gate potential, the MOSFET of the lower arm may be erroneously turned on. In addition, false on may occur in the MOSFET of the upper arm. That is, when the MOSFET of the lower arm is turned on, the source potential of the MOSFET of the upper arm is lowered, and the gate potential of the MOSFET of the upper arm is lowered accordingly. Therefore, the drain potential of the MOSFET of the upper arm rises relative to the gate potential. Then, the gate potential of the upper arm rises momentarily due to the capacitive coupling between the drain and the gate of the MOSFET of the upper arm. Due to this increase in the gate potential, the MOSFET of the upper arm may be erroneously turned on. In this way, the MOSFET of the own arm (that is, the MOSFET that is kept in the off state) may be erroneously turned on by the turn-on of the MOSFET of the opposite arm (that is, the MOSFET that is not the MOSFET of the own arm).
 上述したように、日本公開特許公報第2013-243877号のインバータ回路では、各MOSFETをオフ状態に制御するときに、ゲートに負電位を印加する。すなわち、ゲート電位が瞬間的に上昇しても、ゲート電位がゲート閾値を超えないように各MOSFETのゲート電位が制御される。これにより、MOSFETの誤オンを抑制する。 As described above, in the inverter circuit of Japanese Patent Application Laid-Open No. 2013-243877, a negative potential is applied to the gate when each MOSFET is controlled to the off state. That is, even if the gate potential rises momentarily, the gate potential of each MOSFET is controlled so that the gate potential does not exceed the gate threshold value. This suppresses erroneous ON of the MOSFET.
 MOSFETがオフ状態である間に、MOSFETのゲートに負電位が印加されると、MOSFETのゲート閾値が経時的に低下するという問題が生じる。本明細書では、インバータ回路におけるスイッチング素子の誤オンを抑制するとともに、ゲート閾値の低下を抑制する技術を提案する。 If a negative potential is applied to the gate of the MOSFET while the MOSFET is in the off state, there arises a problem that the gate threshold of the MOSFET decreases with time. This specification proposes a technique for suppressing erroneous ON of a switching element in an inverter circuit and suppressing a decrease in a gate threshold value.
 本明細書は、走行用モータに電力を供給するインバータ回路を開示する。前記インバータ回路は、高電位配線と、低電位配線と、前記走行用モータに接続されている中間配線と、前記高電位配線と前記中間配線の間及び前記中間配線と前記低電位配線の間の一方に接続されている第1スイッチング素子と、前記高電位配線と前記中間配線の間及び前記中間配線と前記低電位配線の間の他方に接続されている第2スイッチング素子と、前記第2スイッチング素子のゲートに接続されているゲート駆動回路を備えている。前記ゲート駆動回路は、前記インバータ回路が前記走行用モータに電力を供給している第1状態では、前記ゲートに印加する電位を、前記第2スイッチング素子のゲート閾値よりも高いゲートオン電位と負電位との間で変化させ、前記インバータ回路が前記走行用モータに電力を供給していない第2状態では、前記負電位よりも高いとともに前記ゲート閾値よりも低い電位を前記ゲートに印加する。 This specification discloses an inverter circuit that supplies electric power to a traveling motor. The inverter circuit includes high-potential wiring, low-potential wiring, intermediate wiring connected to the traveling motor, between the high-potential wiring and the intermediate wiring, and between the intermediate wiring and the low-potential wiring. The first switching element connected to one side, the second switching element connected to the other between the high-potential wiring and the intermediate wiring, and the other between the intermediate wiring and the low-potential wiring, and the second switching. It has a gate drive circuit connected to the gate of the element. In the first state in which the inverter circuit supplies electric power to the traveling motor, the gate drive circuit sets the potential applied to the gate to a gate-on potential and a negative potential higher than the gate threshold of the second switching element. In the second state in which the inverter circuit does not supply electric power to the traveling motor, a potential higher than the negative potential and lower than the gate threshold is applied to the gate.
 なお、第2状態において第2スイッチング素子のゲートに印加する電位の値は、上記負電位よりも高いとともにゲート閾値よりも低ければよく、負であってもよいし、正であってもよいし、ゼロであってもよい。 The value of the potential applied to the gate of the second switching element in the second state may be higher than the negative potential and lower than the gate threshold value, and may be negative or positive. , May be zero.
 上記のインバータ回路では、ゲート駆動回路が、第1状態では、ゲートに印加する電位をゲートオン電位と負電位の間で変化させ、第2状態では、上記負電位よりも高くゲート閾値よりも低い電位をゲートに印加する。すなわち、インバータ回路が動作している第1状態では、上述した誤オンが生じ得るために、ゲート駆動回路が、第2スイッチング素子のオフ状態に維持するために負電位をゲートに印加する。一方で、インバータ回路が動作していない第2状態では、第1スイッチング素子と第2スイッチング素子が共にスイッチングしない(すなわち、オフ状態に維持される)ため、上述したゲート電位の上昇が生じない。このような場合には、ゲート駆動回路が、第2スイッチング素子のゲートに、上記負電位よりも高い電位をゲートに印加する。これにより、スイッチング素子がオフ状態のときに常にゲートに負電位を印加する構成と比較して、スイッチング素子のゲート閾値が低下することを抑制することができる。このように、上記のインバータ回路では、インバータ回路の動作状況に応じて、ゲートに印加する電位を変化させることにより、誤オンの発生を抑制するとともに、ゲート閾値の低下を抑制することができる。 In the above inverter circuit, the gate drive circuit changes the potential applied to the gate between the gate-on potential and the negative potential in the first state, and in the second state, the potential is higher than the negative potential and lower than the gate threshold. Is applied to the gate. That is, in the first state in which the inverter circuit is operating, the above-mentioned erroneous on can occur, so that the gate drive circuit applies a negative potential to the gate in order to maintain the second switching element in the off state. On the other hand, in the second state in which the inverter circuit is not operating, both the first switching element and the second switching element do not switch (that is, they are maintained in the off state), so that the above-mentioned increase in the gate potential does not occur. In such a case, the gate drive circuit applies a potential higher than the negative potential to the gate of the second switching element. As a result, it is possible to suppress a decrease in the gate threshold value of the switching element as compared with a configuration in which a negative potential is always applied to the gate when the switching element is in the off state. As described above, in the above-mentioned inverter circuit, by changing the potential applied to the gate according to the operating condition of the inverter circuit, it is possible to suppress the occurrence of erroneous ON and suppress the decrease of the gate threshold value.
インバータ回路10の回路図。The circuit diagram of the inverter circuit 10. スイッチング素子22a、22dの直列回路を示す回路図。The circuit diagram which shows the series circuit of the switching element 22a, 22d. 第1状態においてスイッチング素子22aがスイッチングするときの各値の変化を示すグラフ。The graph which shows the change of each value when the switching element 22a is switched in the 1st state. 第2状態における各値を示すグラフ。The graph which shows each value in the 2nd state. 第1状態においてスイッチング素子22dがスイッチングするときの各値の変化を示すグラフ。The graph which shows the change of each value when the switching element 22d is switched in the 1st state. インバータ回路10の状態判断処理のフローチャート。The flowchart of the state determination process of the inverter circuit 10.
 本明細書が開示する技術要素について、以下に列記する。なお、以下の各技術要素は、それぞれ独立して有用なものである。 The technical elements disclosed in this specification are listed below. The following technical elements are useful independently.
 本明細書が開示する一例の構成では、前記ゲート駆動回路に接続されている制御装置をさらに備えていてもよい。前記インバータ回路は、車両に搭載されてよい。前記制御装置は、前記車両が走行している場合に前記第1状態であると判断し、前記車両が停止している場合に前記第2状態であると判断してもよい。 In the configuration of one example disclosed in the present specification, a control device connected to the gate drive circuit may be further provided. The inverter circuit may be mounted on a vehicle. The control device may determine that it is in the first state when the vehicle is traveling, and may determine that it is in the second state when the vehicle is stopped.
 本明細書が開示する一例の構成では、前記第1スイッチング素子及び前記第2スイッチング素子は、SiC基板に設けられたFET(Field Effect Transistor)であってよい。 In the configuration of an example disclosed in the present specification, the first switching element and the second switching element may be FETs (Field Effect Transistors) provided on a SiC substrate.
 SiC基板を備えるスイッチング素子は、低いゲート閾値を有しているため、上述した誤オンが生じ易い。このため、本明細書に開示の技術は、SiC基板に設けられたFETを備えるインバータ回路に特に有用である。 Since the switching element provided with the SiC substrate has a low gate threshold value, the above-mentioned erroneous on is likely to occur. For this reason, the techniques disclosed herein are particularly useful for inverter circuits that include FETs on SiC substrates.
(実施例)
 以下、図面を参照して、本実施例のインバータ回路10について説明する。インバータ回路10は、電気自動車(ハイブリッド車や燃料電池車を含む)に搭載される。図1に示すインバータ回路10は、直流電源20から供給される直流電力を三相交流電力に変換し、三相交流電力を走行用モータ(以下、単にモータという。)18に供給する。インバータ回路10は、高電位配線12と、低電位配線14と、3つの中間配線16a~16cを有している。直流電源20の正極は、高電位配線12に接続されている。直流電源20の負極は、低電位配線14に接続されている。したがって、高電位配線12には、低電位配線14よりも高い電位が印加される。各中間配線16a~16cは、モータ18に接続されている。
(Example)
Hereinafter, the inverter circuit 10 of this embodiment will be described with reference to the drawings. The inverter circuit 10 is mounted on an electric vehicle (including a hybrid vehicle and a fuel cell vehicle). The inverter circuit 10 shown in FIG. 1 converts the DC power supplied from the DC power supply 20 into three-phase AC power, and supplies the three-phase AC power to the traveling motor (hereinafter, simply referred to as a motor) 18. The inverter circuit 10 has a high-potential wiring 12, a low-potential wiring 14, and three intermediate wirings 16a to 16c. The positive electrode of the DC power supply 20 is connected to the high potential wiring 12. The negative electrode of the DC power supply 20 is connected to the low potential wiring 14. Therefore, a higher potential is applied to the high-potential wiring 12 than to the low-potential wiring 14. The intermediate wirings 16a to 16c are connected to the motor 18.
 インバータ回路10は、6個のスイッチング素子22a~22fと、6個のゲート駆動回路30a~30fを有している。スイッチング素子22a~22fは、それぞれ、絶縁ゲート型のスイッチング素子であり、本実施例ではMOSFETである。スイッチング素子22a~22fは、SiC基板を備えている。SiC基板の内部で電流のスイッチングが行われる。SiC基板を備えるスイッチング素子22a~22fは、ゲート閾値が低いため、誤オンが生じ易い。なお、SiC基板に代えて、Si基板やGaN基板等の他の半導体基板を用いてもよい。 The inverter circuit 10 has six switching elements 22a to 22f and six gate drive circuits 30a to 30f. The switching elements 22a to 22f are insulated gate type switching elements, respectively, and are MOSFETs in this embodiment. The switching elements 22a to 22f include a SiC substrate. Current switching is performed inside the SiC substrate. Since the switching elements 22a to 22f provided with the SiC substrate have a low gate threshold value, erroneous ON is likely to occur. Instead of the SiC substrate, another semiconductor substrate such as a Si substrate or a GaN substrate may be used.
 スイッチング素子22aのドレインは、高電位配線12に接続されている。スイッチング素子22aのソースは、中間配線16aに接続されている。スイッチング素子22aのゲートは、ゲート駆動回路30aに接続されている。ゲート駆動回路30aは、スイッチング素子22aのゲートの電位を制御する。スイッチング素子22aがオンすると、高電位配線12から中間配線16aへ電流が流れる。スイッチング素子22bのドレインは、高電位配線12に接続されている。スイッチング素子22bのソースは、中間配線16bに接続されている。スイッチング素子22bのゲートは、ゲート駆動回路30bに接続されている。ゲート駆動回路30bは、スイッチング素子22bのゲートの電位を制御する。スイッチング素子22bがオンすると、高電位配線12から中間配線16bへ電流が流れる。スイッチング素子22cのドレインは、高電位配線12に接続されている。スイッチング素子22cのソースは、中間配線16cに接続されている。スイッチング素子22cのゲートは、ゲート駆動回路30cに接続されている。ゲート駆動回路30cは、スイッチング素子22cのゲートの電位を制御する。スイッチング素子22cがオンすると、高電位配線12から中間配線16cへ電流が流れる。以下では、スイッチング素子22a~22cのそれぞれを上アームのスイッチング素子ということがある。 The drain of the switching element 22a is connected to the high potential wiring 12. The source of the switching element 22a is connected to the intermediate wiring 16a. The gate of the switching element 22a is connected to the gate drive circuit 30a. The gate drive circuit 30a controls the potential of the gate of the switching element 22a. When the switching element 22a is turned on, a current flows from the high potential wiring 12 to the intermediate wiring 16a. The drain of the switching element 22b is connected to the high potential wiring 12. The source of the switching element 22b is connected to the intermediate wiring 16b. The gate of the switching element 22b is connected to the gate drive circuit 30b. The gate drive circuit 30b controls the potential of the gate of the switching element 22b. When the switching element 22b is turned on, a current flows from the high potential wiring 12 to the intermediate wiring 16b. The drain of the switching element 22c is connected to the high potential wiring 12. The source of the switching element 22c is connected to the intermediate wiring 16c. The gate of the switching element 22c is connected to the gate drive circuit 30c. The gate drive circuit 30c controls the potential of the gate of the switching element 22c. When the switching element 22c is turned on, a current flows from the high potential wiring 12 to the intermediate wiring 16c. In the following, each of the switching elements 22a to 22c may be referred to as an upper arm switching element.
 スイッチング素子22dのドレインは、中間配線16aに接続されている。スイッチング素子22dのソースは、低電位配線14に接続されている。スイッチング素子22dのゲートは、ゲート駆動回路30dに接続されている。ゲート駆動回路30dは、スイッチング素子22dのゲートの電位を制御する。スイッチング素子22dがオンすると、中間配線16aから低電位配線14へ電流が流れる。スイッチング素子22eのドレインは、中間配線16bに接続されている。スイッチング素子22eのソースは、低電位配線14に接続されている。スイッチング素子22eのゲートは、ゲート駆動回路30eに接続されている。ゲート駆動回路30eは、スイッチング素子22eのゲートの電位を制御する。スイッチング素子22eがオンすると、中間配線16bから低電位配線14へ電流が流れる。スイッチング素子22fのドレインは、中間配線16cに接続されている。スイッチング素子22fのソースは、低電位配線14に接続されている。スイッチング素子22fのゲートは、ゲート駆動回路30fに接続されている。ゲート駆動回路30fは、スイッチング素子22fのゲートの電位を制御する。スイッチング素子22fがオンすると、中間配線16cから低電位配線14へ電流が流れる。以下では、スイッチング素子22d~22fのそれぞれを下アームのスイッチング素子ということがある。 The drain of the switching element 22d is connected to the intermediate wiring 16a. The source of the switching element 22d is connected to the low potential wiring 14. The gate of the switching element 22d is connected to the gate drive circuit 30d. The gate drive circuit 30d controls the potential of the gate of the switching element 22d. When the switching element 22d is turned on, a current flows from the intermediate wiring 16a to the low potential wiring 14. The drain of the switching element 22e is connected to the intermediate wiring 16b. The source of the switching element 22e is connected to the low potential wiring 14. The gate of the switching element 22e is connected to the gate drive circuit 30e. The gate drive circuit 30e controls the potential of the gate of the switching element 22e. When the switching element 22e is turned on, a current flows from the intermediate wiring 16b to the low potential wiring 14. The drain of the switching element 22f is connected to the intermediate wiring 16c. The source of the switching element 22f is connected to the low potential wiring 14. The gate of the switching element 22f is connected to the gate drive circuit 30f. The gate drive circuit 30f controls the potential of the gate of the switching element 22f. When the switching element 22f is turned on, a current flows from the intermediate wiring 16c to the low potential wiring 14. In the following, each of the switching elements 22d to 22f may be referred to as a lower arm switching element.
 スイッチング素子22a~22fのそれぞれに対して、ダイオード24a~24fが並列に接続されている。ダイオード24a~24fのアノードのそれぞれは、対応するスイッチング素子22a~22fのソースに接続されている。ダイオード24a~24fのカソードのそれぞれは、対応するスイッチング素子22a~22fのドレインに接続されている。各スイッチング素子22a~22fがスイッチングすることで、直流電力が三相交流電力に変換される。 Diodes 24a to 24f are connected in parallel to each of the switching elements 22a to 22f. Each of the anodes of the diodes 24a-24f is connected to the source of the corresponding switching elements 22a-22f. Each of the cathodes of the diodes 24a to 24f is connected to the drain of the corresponding switching elements 22a to 22f. By switching each of the switching elements 22a to 22f, DC power is converted into three-phase AC power.
 ゲート駆動回路30a~30fは、制御装置40に接続されている。制御装置40は、ゲート駆動回路30a~30fのそれぞれに対して、各スイッチング素子22a~22fのゲートの電位を制御するためのゲート駆動信号を出力する。 The gate drive circuits 30a to 30f are connected to the control device 40. The control device 40 outputs a gate drive signal for controlling the potential of the gate of each of the switching elements 22a to 22f to each of the gate drive circuits 30a to 30f.
 以下では、スイッチング素子22aとスイッチング素子22dの直列回路の動作を例として説明するが、スイッチング素子22bとスイッチング素子22eの直列回路、及び、スイッチング素子22cとスイッチング素子22fの直列回路についても同様に動作する。 Hereinafter, the operation of the series circuit of the switching element 22a and the switching element 22d will be described as an example, but the same operation will be performed on the series circuit of the switching element 22b and the switching element 22e and the series circuit of the switching element 22c and the switching element 22f. To do.
 図2は、スイッチング素子22aとスイッチング素子22dの直列回路を示している。図2に示すように、ゲート駆動回路30a、30dには、制御装置40から信号が入力される。後に詳述するが、制御装置40は、車両が走行しているか否かを判断する。すなわち、制御装置40は、インバータ回路10からモータ18に電力を供給しているか否かを判断する。制御装置40は、判定結果に応じて、ゲート駆動回路30a、30dに信号を入力する。 FIG. 2 shows a series circuit of the switching element 22a and the switching element 22d. As shown in FIG. 2, signals are input from the control device 40 to the gate drive circuits 30a and 30d. As will be described in detail later, the control device 40 determines whether or not the vehicle is traveling. That is, the control device 40 determines whether or not power is being supplied from the inverter circuit 10 to the motor 18. The control device 40 inputs signals to the gate drive circuits 30a and 30d according to the determination result.
 インバータ回路10からモータ18に電力を供給している状態(以下、第1状態という。)では、ゲート駆動回路30aには、制御装置40からゲート駆動信号Sa1が入力される。第1状態では、ゲート駆動回路30aは、ゲート駆動信号Sa1に基づいて、スイッチング素子22aをスイッチングさせる。また、第1状態では、ゲート駆動回路30dには、制御装置40からゲート駆動信号Sd1が入力される。ゲート駆動回路30dは、ゲート駆動信号Sd1に基づいて、スイッチング素子22dをスイッチングさせる。このように、第1状態では、ゲート駆動回路30a、30dが、ゲート駆動信号Sa1、Sd1に基づいてスイッチング素子22a、22dをスイッチングさせることにより、モータ18に電力が供給される。第1状態では、ゲート駆動回路30a、30dは、スイッチング素子22aとスイッチング素子22dが同時にオンすることがないように、各ゲートの電位を制御する。 In a state where power is being supplied from the inverter circuit 10 to the motor 18 (hereinafter referred to as the first state), the gate drive signal Sa1 is input from the control device 40 to the gate drive circuit 30a. In the first state, the gate drive circuit 30a switches the switching element 22a based on the gate drive signal Sa1. Further, in the first state, the gate drive signal Sd1 is input from the control device 40 to the gate drive circuit 30d. The gate drive circuit 30d switches the switching element 22d based on the gate drive signal Sd1. As described above, in the first state, the gate drive circuits 30a and 30d switch the switching elements 22a and 22d based on the gate drive signals Sa1 and Sd1, so that the motor 18 is supplied with electric power. In the first state, the gate drive circuits 30a and 30d control the potential of each gate so that the switching element 22a and the switching element 22d do not turn on at the same time.
 また、インバータ回路10からモータ18に電力を供給していない状態(以下、第2状態という。)では、ゲート駆動回路30aには、制御装置40からゲート駆動信号Sa2が入力される。第2状態では、ゲート駆動回路30aは、ゲート駆動信号Sa2に基づいて、スイッチング素子22aをオフ状態に維持するように、スイッチング素子22aのゲートの電位を制御する。また、第2状態では、ゲート駆動回路30dには、制御装置40からゲート駆動信号Sd2が入力される。ゲート駆動回路30dは、ゲート駆動信号Sd2に基づいて、スイッチング素子22dをオフ状態に維持するように、スイッチング素子22dのゲートの電位を制御する。 Further, in a state where power is not supplied from the inverter circuit 10 to the motor 18 (hereinafter referred to as a second state), the gate drive signal Sa2 is input from the control device 40 to the gate drive circuit 30a. In the second state, the gate drive circuit 30a controls the potential of the gate of the switching element 22a so as to keep the switching element 22a in the off state based on the gate drive signal Sa2. Further, in the second state, the gate drive signal Sd2 is input from the control device 40 to the gate drive circuit 30d. The gate drive circuit 30d controls the potential of the gate of the switching element 22d so as to keep the switching element 22d in the off state based on the gate drive signal Sd2.
 図3は、第1状態の動作を示している。すなわち、ゲート駆動回路30aには制御装置40からゲート駆動信号Sa1が入力され、ゲート駆動回路30dには制御装置40からゲート駆動信号Sd1が入力されている。また、図3は、第1状態において、下アームのスイッチング素子22dをオフ状態に維持しながら上アームのスイッチング素子22aをスイッチングさせるときの各値の変化を示している。図3及び後述する図4~図5において、参照符号Vgaは上アームのスイッチング素子22aのゲート電位を示しており、参照符号Vdsaは上アームのスイッチング素子22aのドレイン-ソース間電圧を示しており、参照符号Vgdは下アームのスイッチング素子22dのゲート電位を示しており、参照符号Vdsdは下アームのスイッチング素子22dのドレイン-ソース間電圧を示している。なお、ゲート電位Vgaはスイッチング素子22aのソースに対する電位として示されており、ゲート電位Vgdはスイッチング素子22dのソースに対する電位として示されている。 FIG. 3 shows the operation in the first state. That is, the gate drive signal Sa1 is input from the control device 40 to the gate drive circuit 30a, and the gate drive signal Sd1 is input from the control device 40 to the gate drive circuit 30d. Further, FIG. 3 shows changes in each value when switching the switching element 22a of the upper arm while keeping the switching element 22d of the lower arm in the off state in the first state. In FIGS. 3 and 4 to 5, which will be described later, reference numeral Vga indicates the gate potential of the switching element 22a of the upper arm, and reference numeral Vdsa indicates the drain-source voltage of the switching element 22a of the upper arm. , Reference symbol Vgd indicates the gate potential of the switching element 22d of the lower arm, and reference numeral Vdsd indicates the drain-source voltage of the switching element 22d of the lower arm. The gate potential VGA is shown as the potential of the switching element 22a with respect to the source, and the gate potential Vgd is shown as the potential of the switching element 22d with respect to the source.
 図3に示す初期状態では、ゲート駆動回路30aは、スイッチング素子22aのゲート電位Vgaをゲートオフ電位Voffa1に制御する。ゲートオフ電位Voffa1は、スイッチング素子22aのゲート閾値Vthaよりも低い。ゲートオフ電位Voffa1は、負電位(すなわち、スイッチング素子22aのソースよりも低い電位)である。ゲートオフ電位Voffa1がゲート閾値Vthaよりも低いため、スイッチング素子22aはオフしている。また、初期状態では、ゲート駆動回路30dは、スイッチング素子22dのゲート電位Vgdをゲートオフ電位Voffd1に制御する。ゲートオフ電位Voffd1は、スイッチング素子22dのゲート閾値Vthdよりも低い。ゲートオフ電位Voffd1は、負電位(すなわち、スイッチング素子22dのソースよりも低い電位)である。ゲートオフ電位Voffd1がゲート閾値Vthdよりも低いため、スイッチング素子22dはオフしている。この状態では、モータ18が駆動しているため、中間配線16aの電位が低電位配線14の電位よりも低くなる。このため、図2の矢印100に示すように、低電位配線14からダイオード24dを介して中間配線16aに電流が流れる。ダイオード24dがオンしているので、スイッチング素子22dのドレイン-ソース間電圧Vdsdは略0Vとなる。また、スイッチング素子22aには、高電位配線12と中間配線16aの間の電位差が印加されるので、スイッチング素子22aのドレイン-ソース間電圧Vdsaは高電圧となる。 In the initial state shown in FIG. 3, the gate drive circuit 30a controls the gate potential VGA of the switching element 22a to the gate-off potential Voffa1. The gate-off potential Voffa1 is lower than the gate threshold value Vtha of the switching element 22a. The gate-off potential Voffa1 is a negative potential (that is, a potential lower than the source of the switching element 22a). Since the gate-off potential Voffa1 is lower than the gate threshold value Vtha, the switching element 22a is turned off. Further, in the initial state, the gate drive circuit 30d controls the gate potential Vgd of the switching element 22d to the gate-off potential Voffd1. The gate-off potential Voffd1 is lower than the gate threshold value Vthd of the switching element 22d. The gate-off potential Voffd1 is a negative potential (that is, a potential lower than the source of the switching element 22d). Since the gate-off potential Voffd1 is lower than the gate threshold value Vthd, the switching element 22d is off. In this state, since the motor 18 is driven, the potential of the intermediate wiring 16a is lower than the potential of the low potential wiring 14. Therefore, as shown by the arrow 100 in FIG. 2, a current flows from the low potential wiring 14 to the intermediate wiring 16a via the diode 24d. Since the diode 24d is on, the drain-source voltage Vdsd of the switching element 22d is approximately 0V. Further, since the potential difference between the high potential wiring 12 and the intermediate wiring 16a is applied to the switching element 22a, the drain-source voltage Vdsa of the switching element 22a becomes a high voltage.
 その後、タイミングt1において、ゲート駆動回路30aが、スイッチング素子22aのゲート電位Vgaをゲートオフ電位Voffa1からゲートオン電位Vonaまで引き上げる。ゲートオン電位Vonaは、ゲート閾値Vthaよりも高い。したがって、タイミングt1の直後に、スイッチング素子22aがターンオンする。すると、図2に矢印100で示す電流が停止し、矢印102に示すように、高電位配線12からスイッチング素子22aを介して中間配線16aへ電流が流れる。スイッチング素子22aがターンオンするので、タイミングt1の直後に、スイッチング素子22aのドレイン-ソース間電圧Vdsaが略0Vまで低下する。このため、スイッチング素子22dのドレインの電位が高電位まで上昇する。すなわち、スイッチング素子22dのドレイン-ソース間電圧Vdsdが高電圧まで上昇する。ここで、ゲート駆動回路30dは、スイッチング素子22dのゲートにゲートオフ電位Voffd1(すなわち、負電位)を印加し続ける。タイミングt1の直後にスイッチング素子22dのドレインの電位が急激に上昇すると、スイッチング素子22dのドレイン-ゲート間の寄生容量(図2のCd)を介した容量結合によって、スイッチング素子22dのゲートに瞬間的にサージ電圧90が印加される。このため、タイミングt1の直後に、ゲート電位Vgdが瞬間的に上昇する。しかしながら、第1状態では、ゲート駆動回路30dが、スイッチング素子22dのゲートにゲートオフ電位Voffd1(すなわち、負電位)を印加している。このため、サージ電圧90が印加されても、ゲート電位Vgdがゲート閾値Vthdに達しない。これによって、スイッチング素子22dの誤オンが抑制される。 After that, at the timing t1, the gate drive circuit 30a raises the gate potential VGA of the switching element 22a from the gate-off potential Voffa1 to the gate-on potential Vona. The gate-on potential Vona is higher than the gate threshold Vza. Therefore, immediately after the timing t1, the switching element 22a turns on. Then, the current indicated by the arrow 100 in FIG. 2 is stopped, and as shown by the arrow 102, the current flows from the high potential wiring 12 to the intermediate wiring 16a via the switching element 22a. Since the switching element 22a turns on, the drain-source voltage Vdsa of the switching element 22a drops to approximately 0V immediately after the timing t1. Therefore, the potential of the drain of the switching element 22d rises to a high potential. That is, the drain-source voltage Vdsd of the switching element 22d rises to a high voltage. Here, the gate drive circuit 30d continues to apply the gate-off potential Voffd1 (that is, the negative potential) to the gate of the switching element 22d. When the potential of the drain of the switching element 22d rises sharply immediately after the timing t1, the gate of the switching element 22d is momentarily coupled by the capacitance via the parasitic capacitance (Cd in FIG. 2) between the drain and the gate of the switching element 22d. A surge voltage 90 is applied to the. Therefore, immediately after the timing t1, the gate potential Vgd rises momentarily. However, in the first state, the gate drive circuit 30d applies a gate-off potential Voffd1 (that is, a negative potential) to the gate of the switching element 22d. Therefore, even if the surge voltage 90 is applied, the gate potential Vgd does not reach the gate threshold value Vthd. As a result, erroneous ON of the switching element 22d is suppressed.
 図4は、第2状態の動作を示している。すなわち、ゲート駆動回路30aには制御装置40からゲート駆動信号Sa2が入力され、ゲート駆動回路30dには制御装置40からゲート駆動信号Sd2が入力されている。第2状態では、インバータ回路10がモータ18に電力を供給しないので、スイッチング素子22aとスイッチング素子22dは、共にオフ状態に維持される。すなわち、スイッチング素子22a及びスイッチング素子22dはスイッチングしない。 FIG. 4 shows the operation of the second state. That is, the gate drive signal Sa2 is input from the control device 40 to the gate drive circuit 30a, and the gate drive signal Sd2 is input from the control device 40 to the gate drive circuit 30d. In the second state, since the inverter circuit 10 does not supply electric power to the motor 18, both the switching element 22a and the switching element 22d are maintained in the off state. That is, the switching element 22a and the switching element 22d do not switch.
 図4に示す第2状態では、ゲート駆動回路30aは、スイッチング素子22aのゲート電位Vgaをゲートオフ電位Voffa2に制御する。ゲートオフ電位Voffa2は、スイッチング素子22aのゲート閾値Vthaよりも低い。このため、スイッチング素子22aはオフしている。また、ゲートオフ電位Voffa2は、図3に示す第1状態のゲートオフ電位Voffa1よりも高い。本実施例では、ゲートオフ電位Voffa2は0Vよりも高くゲート閾値Vthdよりも低い。また、ゲート駆動回路30dは、スイッチング素子22dのゲート電位Vgdをゲートオフ電位Voffd2に制御する。ゲートオフ電位Voffd2は、スイッチング素子22dのゲート閾値Vthdよりも低い。このため、スイッチング素子22dはオフしている。また、ゲートオフ電位Voffd2は、図3に示す第1状態のゲートオフ電位Voffd1よりも高い。本実施例では、ゲートオフ電位Voffd2は0Vよりも高い。この状態では、インバータ回路10に電流が流れないので、中間配線16aの電位がフローティングとなり、高電位配線12と低電位配線14の間の電位差がスイッチング素子22aとスイッチング素子22dの直列回路に印加される。このため、スイッチング素子22aのドレイン-ソース間電圧Vdsaとスイッチング素子22dのドレイン-ソース間電圧Vdsdは略等しい電圧となる。第2状態では、ゲート駆動回路30aは、スイッチング素子22aのゲートにゲートオフ電位Voffa2を印加し続ける。また、ゲート駆動回路30dは、スイッチング素子22dのゲートにゲートオフ電位Voffd2を印加し続ける。 In the second state shown in FIG. 4, the gate drive circuit 30a controls the gate potential VGA of the switching element 22a to the gate-off potential Voffa2. The gate-off potential Voffa2 is lower than the gate threshold value Vtha of the switching element 22a. Therefore, the switching element 22a is turned off. Further, the gate-off potential Voffa2 is higher than the gate-off potential Voffa1 in the first state shown in FIG. In this embodiment, the gate-off potential Voffa2 is higher than 0V and lower than the gate threshold Vthd. Further, the gate drive circuit 30d controls the gate potential Vgd of the switching element 22d to the gate-off potential Voffd2. The gate-off potential Voffd2 is lower than the gate threshold value Vthd of the switching element 22d. Therefore, the switching element 22d is turned off. Further, the gate-off potential Voffd2 is higher than the gate-off potential Voffd1 in the first state shown in FIG. In this embodiment, the gate-off potential Voffd2 is higher than 0V. In this state, since no current flows through the inverter circuit 10, the potential of the intermediate wiring 16a is floating, and the potential difference between the high potential wiring 12 and the low potential wiring 14 is applied to the series circuit of the switching element 22a and the switching element 22d. To. Therefore, the drain-source voltage Vdsd of the switching element 22a and the drain-source voltage Vdsd of the switching element 22d are substantially equal. In the second state, the gate drive circuit 30a continues to apply the gate-off potential Voffa2 to the gate of the switching element 22a. Further, the gate drive circuit 30d continues to apply the gate-off potential Voffd2 to the gate of the switching element 22d.
 上記の通り、第2状態では、スイッチング素子22a及びスイッチング素子22dが共にスイッチングしない。このため、スイッチング素子22dのゲートには、第1状態で説明したサージ電圧90が印加されない。このため、第2状態では、スイッチング素子22dをオフ状態に維持するためにゲートに印加する電位(すなわち、ゲートオフ電位Voffd2)を、第1状態におけるゲートオフ電位Voffd1よりも高い値に設定しても、サージ電圧90によるスイッチング素子22dの誤オンが生じない。また、第2状態では、スイッチング素子22dのゲートにゲートオフ電位Voffd2(すなわち、ゲートオフ電位Voffd1よりも高い電位)を印加することによって、スイッチング素子22dのゲート閾値が低下することを抑制することができる。 As described above, in the second state, neither the switching element 22a nor the switching element 22d is switched. Therefore, the surge voltage 90 described in the first state is not applied to the gate of the switching element 22d. Therefore, in the second state, even if the potential applied to the gate (that is, the gate-off potential Voltage2) for maintaining the switching element 22d in the off state is set to a value higher than the gate-off potential Voltage1 in the first state, The switching element 22d is not erroneously turned on due to the surge voltage 90. Further, in the second state, by applying the gate-off potential Voffd2 (that is, a potential higher than the gate-off potential Voffd1) to the gate of the switching element 22d, it is possible to suppress a decrease in the gate threshold value of the switching element 22d.
 図5は、第1状態の動作を示している。すなわち、ゲート駆動回路30aには制御装置40からゲート駆動信号Sa1が入力され、ゲート駆動回路30dには制御装置40からゲート駆動信号Sd1が入力されている。図5では、図3とは異なり、第1状態において、上アームのスイッチング素子22aをオフ状態に維持しながら下アームのスイッチング素子22dをスイッチングさせるときの各値の変化を示している。 FIG. 5 shows the operation in the first state. That is, the gate drive signal Sa1 is input from the control device 40 to the gate drive circuit 30a, and the gate drive signal Sd1 is input from the control device 40 to the gate drive circuit 30d. FIG. 5 shows changes in each value when switching the switching element 22d of the lower arm while maintaining the switching element 22a of the upper arm in the off state in the first state, unlike FIG.
 図5に示すスイッチング素子22a、22dの各ゲート電位Vga、Vdaの初期状態は、図3の初期状態と同様である。すなわち、スイッチング素子22aとスイッチング素子22dが共にオフしている。この状態では、モータ18が駆動しているため、中間配線16aの電位が高電位配線12の電位よりも高くなる。このため、図2の矢印104に示すように、中間配線16aからダイオード24aを介して高電位配線12に電流が流れる。ダイオード24aがオンしているので、スイッチング素子22aのドレイン-ソース間電圧Vdsaは略0Vとなる。また、スイッチング素子22dには、中間配線16aと低電位配線14の間の電位差が印加されるので、スイッチング素子22dのドレイン-ソース間電圧Vdsdは高電圧となる。 The initial states of the gate potentials VGA and Vda of the switching elements 22a and 22d shown in FIG. 5 are the same as the initial states of FIG. That is, both the switching element 22a and the switching element 22d are off. In this state, since the motor 18 is driven, the potential of the intermediate wiring 16a is higher than the potential of the high potential wiring 12. Therefore, as shown by the arrow 104 in FIG. 2, a current flows from the intermediate wiring 16a to the high potential wiring 12 via the diode 24a. Since the diode 24a is on, the drain-source voltage Vdsa of the switching element 22a is approximately 0V. Further, since the potential difference between the intermediate wiring 16a and the low potential wiring 14 is applied to the switching element 22d, the drain-source voltage Vdsd of the switching element 22d becomes a high voltage.
 その後、タイミングt2において、ゲート駆動回路30dが、スイッチング素子22dのゲート電位Vgdをゲートオフ電位Voffd1からゲートオン電位Vondまで引き上げる。ゲートオン電位Vondは、ゲート閾値Vthdよりも高い。したがって、タイミングt2の直後に、スイッチング素子22dがターンオンする。すると、図2に矢印104で示す電流が停止し、矢印106に示すように、中間配線16aからスイッチング素子22dを介して低電位配線14へ電流が流れる。スイッチング素子22dがターンオンするので、タイミングt2の直後に、スイッチング素子22dのドレイン-ソース間電圧Vdsdが略0Vまで低下する。このため、スイッチング素子22aのソースの電位が低電位まで低下する。すなわち、スイッチング素子22aのドレインの電位が、ソースの電位に対して相対的に高くなる。このため、スイッチング素子22aのドレイン-ソース間電圧Vdsaが高電圧まで上昇する。ここで、ゲート駆動回路30aは、スイッチング素子22aのゲートにゲートオフ電位Voffa1(すなわち、負電位)を印加し続ける。タイミングt2の直後にスイッチング素子22aのドレインの電位が急激に上昇すると、スイッチング素子22aのドレイン-ゲート間の寄生容量(図2のCa)を介した容量結合によって、スイッチング素子22aのゲートに瞬間的にサージ電圧92が印加される。このため、タイミングt2の直後に、ゲート電位Vgaが瞬間的に上昇する。しかしながら、第1状態では、ゲート駆動回路30aがスイッチング素子22aのゲートにゲートオフ電位Voffa1(すなわち、負電位)を印加している。このため、サージ電圧92が印加されても、ゲート電位Vgaがゲート閾値Vthaに達しない。これによって、スイッチング素子22aの誤オンが抑制される。 After that, at the timing t2, the gate drive circuit 30d raises the gate potential Vgd of the switching element 22d from the gate-off potential Voffd1 to the gate-on potential Vondo. The gate-on potential Bond is higher than the gate threshold Vthd. Therefore, immediately after the timing t2, the switching element 22d turns on. Then, the current indicated by the arrow 104 in FIG. 2 is stopped, and as shown by the arrow 106, the current flows from the intermediate wiring 16a to the low potential wiring 14 via the switching element 22d. Since the switching element 22d turns on, the drain-source voltage Vdsd of the switching element 22d drops to approximately 0V immediately after the timing t2. Therefore, the potential of the source of the switching element 22a drops to a low potential. That is, the potential of the drain of the switching element 22a is relatively high with respect to the potential of the source. Therefore, the drain-source voltage Vdsa of the switching element 22a rises to a high voltage. Here, the gate drive circuit 30a continues to apply the gate-off potential Voffa1 (that is, the negative potential) to the gate of the switching element 22a. When the potential of the drain of the switching element 22a rises sharply immediately after the timing t2, the gate of the switching element 22a is momentarily connected by the capacitance coupling via the parasitic capacitance (Ca in FIG. 2) between the drain and the gate of the switching element 22a. A surge voltage 92 is applied to the. Therefore, immediately after the timing t2, the gate potential Vga rises momentarily. However, in the first state, the gate drive circuit 30a applies a gate-off potential Voffa1 (that is, a negative potential) to the gate of the switching element 22a. Therefore, even if the surge voltage 92 is applied, the gate potential VGA does not reach the gate threshold value Vtha. As a result, erroneous ON of the switching element 22a is suppressed.
 以上に説明したように、本実施例のインバータ回路10によれば、インバータ回路10の動作状況に応じて、スイッチング素子22a、22dのゲートに印加する電位(詳細には、スイッチング素子22a、22dをオフ状態とする電位)を変化させることにより、誤オンの発生を抑制するとともに、ゲート閾値の経時的な低下を抑制することができる。 As described above, according to the inverter circuit 10 of the present embodiment, the potentials applied to the gates of the switching elements 22a and 22d (specifically, the switching elements 22a and 22d are set according to the operating condition of the inverter circuit 10). By changing the potential (off state), it is possible to suppress the occurrence of erroneous on and suppress the decrease of the gate threshold with time.
 次に、図6を参照して、インバータ回路10の状態を判断する処理について説明する。この状態判断処理では、制御装置40は、インバータ回路10が第1状態であるのか第2状態であるのかを判断する。状態判断処理は、車両のメインスイッチがオンしている間、繰り返し実行される。図6のS10において、制御装置40は、車両が走行しているのか否かを判断する。制御装置40は、車両が走行していると判断する場合(S10でYES)、S12へ進む。車両が走行していることは、例えば、車両のシフトレバーにおいてD(ドライブ)レンジが選択されている、且つ、車速がゼロでないこと等を検知することによって判断することができる。 Next, the process of determining the state of the inverter circuit 10 will be described with reference to FIG. In this state determination process, the control device 40 determines whether the inverter circuit 10 is in the first state or the second state. The state determination process is repeatedly executed while the main switch of the vehicle is on. In S10 of FIG. 6, the control device 40 determines whether or not the vehicle is traveling. When the control device 40 determines that the vehicle is traveling (YES in S10), the control device 40 proceeds to S12. It can be determined that the vehicle is running, for example, by detecting that the D (drive) range is selected in the shift lever of the vehicle and the vehicle speed is not zero.
 S12において、制御装置40は、車両が走行しているために第1状態(すなわち、インバータ回路10からモータ18に電力を供給している状態)であると判断する。そして、制御装置40は、目標出力を指令するゲート駆動信号Sa1、Sd1を各ゲート駆動回路30a、30dに出力する。これにより、ゲート駆動回路30aが、スイッチング素子22aのゲートに、上述したゲートオン電位Vonaとゲートオフ電位Voffa1(すなわち、負電位)との間で変化する電位を印加する。また、ゲート駆動回路30dが、スイッチング素子22dのゲートに、上述したゲートオン電位Vondとゲートオフ電位Voffd1(すなわち、負電位)との間で変化する電位を印加する。これにより、スイッチング素子22a、22dがスイッチングし、モータ18に電力が供給される。 In S12, the control device 40 determines that the vehicle is traveling and is in the first state (that is, the state in which the inverter circuit 10 is supplying electric power to the motor 18). Then, the control device 40 outputs the gate drive signals Sa1 and Sd1 for commanding the target output to the gate drive circuits 30a and 30d, respectively. As a result, the gate drive circuit 30a applies a potential that changes between the gate-on potential Vona and the gate-off potential Voffa1 (that is, a negative potential) described above to the gate of the switching element 22a. Further, the gate drive circuit 30d applies a potential that changes between the gate-on potential Bond and the gate-off potential Voffd1 (that is, a negative potential) described above to the gate of the switching element 22d. As a result, the switching elements 22a and 22d are switched, and electric power is supplied to the motor 18.
 一方、制御装置40は、S10において、車両が停止していると判断する場合(S10でNO)、S14へ進む。車両が停止していることは、例えば、車両のシフトレバーにおいてP(パーキング)レンジ又はN(ニュートラル)レンジが選択されていること、車速がゼロである且つブレーキペダルが踏まれていること、車速がゼロである状態が所定期間継続していること等を検知することによって判断することができる。 On the other hand, when the control device 40 determines in S10 that the vehicle is stopped (NO in S10), the control device 40 proceeds to S14. The fact that the vehicle is stopped means that, for example, the P (parking) range or the N (neutral) range is selected in the shift lever of the vehicle, the vehicle speed is zero and the brake pedal is depressed, and the vehicle speed. It can be determined by detecting that the state in which is zero continues for a predetermined period of time.
 S14において、制御装置40は、車両が停止しているために第2状態(すなわち、インバータ回路10からモータ18に電力を供給していない状態)であると判断する。そして、制御装置40は、ゲート駆動信号Sa2、Sd2を各ゲート駆動回路30a、30dに出力する。これにより、ゲート駆動回路30aが、スイッチング素子22aのゲートに、上述したゲートオフ電位Voffa2(すなわち、0Vよりも高くゲート閾値Vthaよりも低い電位)を印加する。また、ゲート駆動回路30dが、スイッチング素子22dのゲートに、上述したゲートオフ電位Voffad(すなわち、0Vよりも高くゲート閾値Vthdよりも低い電位)を印加する。すなわち、スイッチング素子22a、22dがオフ状態に維持される。 In S14, the control device 40 determines that the vehicle is in the second state (that is, the state in which the power is not supplied from the inverter circuit 10 to the motor 18) because the vehicle is stopped. Then, the control device 40 outputs the gate drive signals Sa2 and Sd2 to the gate drive circuits 30a and 30d, respectively. As a result, the gate drive circuit 30a applies the above-mentioned gate-off potential Voffa2 (that is, a potential higher than 0V and lower than the gate threshold value Vtha) to the gate of the switching element 22a. Further, the gate drive circuit 30d applies the above-mentioned gate-off potential Voffad (that is, a potential higher than 0V and lower than the gate threshold value Vthd) to the gate of the switching element 22d. That is, the switching elements 22a and 22d are maintained in the off state.
 上述した実施形態では、ゲートオフ電位Voffa2、Voffd2が0Vよりも高い値を有していた。しかしながら、ゲートオフ電位Voffa2は、ゲートオフ電位Voffa1よりも高くゲート閾値Vthaよりも低ければよい。また、ゲートオフ電位Voffd2は、ゲートオフ電位Voffd1よりも高くゲート閾値Vthdよりも低ければよい。すなわち、ゲートオフ電位Voffa2、Voffd2の値は、負であってもよいし、正であってもよいし、ゼロであってもよい。 In the above-described embodiment, the gate-off potentials Voffa2 and Voffd2 had values higher than 0V. However, the gate-off potential Voffa2 may be higher than the gate-off potential Vofa1 and lower than the gate threshold value Vtha. Further, the gate-off potential Voffd2 may be higher than the gate-off potential Voffd1 and lower than the gate threshold value Vthd. That is, the values of the gate-off potentials Voffa2 and Voffd2 may be negative, positive, or zero.
(対応関係)
 実施例のスイッチング素子22a又はスイッチング素子22dが、請求項の「第1スイッチング素子」の一例であり、実施例のスイッチング素子22d又はスイッチング素子22aが、請求項の「第2スイッチング素子」の一例である。実施例のゲートオフ電位Voffa1、Voffd1が、請求項の「負電位」の一例である。実施例のゲートオフ電位Voffa2、Voffd2が、請求項の「負電位よりも高いとともにゲート閾値よりも低い電位」の一例である。
(Correspondence)
The switching element 22a or the switching element 22d of the embodiment is an example of the "first switching element" of the claim, and the switching element 22d or the switching element 22a of the embodiment is an example of the "second switching element" of the claim. is there. The gate-off potentials Voffa1 and Voffd1 of the embodiment are examples of the "negative potential" of the claim. The gate-off potentials Voffa2 and Voffd2 of the embodiment are an example of the claim "potential higher than negative potential and lower than gate threshold value".
 以上、実施形態について詳細に説明したが、これらは例示にすぎず、請求の範囲を限定するものではない。請求の範囲に記載の技術には、以上に例示した具体例をさまざまに変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独あるいは各種の組み合わせによって技術有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの1つの目的を達成すること自体で技術有用性を持つものである。 Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in this specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

Claims (3)

  1.  走行用モータに電力を供給するインバータ回路であって、
     高電位配線と、
     低電位配線と、
     前記走行用モータに接続されている中間配線と、
     前記高電位配線と前記中間配線の間、及び、前記中間配線と前記低電位配線の間の一方に接続されている第1スイッチング素子と、
     前記高電位配線と前記中間配線の間、及び、前記中間配線と前記低電位配線の間の他方に接続されている第2スイッチング素子と、
     前記第2スイッチング素子のゲートに接続されているゲート駆動回路、
     を備えており、
     前記ゲート駆動回路は、
     前記インバータ回路が前記走行用モータに電力を供給している第1状態では、前記ゲートに印加する電位を、前記第2スイッチング素子のゲート閾値よりも高いゲートオン電位と、負電位との間で変化させ、
     前記インバータ回路が前記走行用モータに電力を供給していない第2状態では、前記負電位よりも高いとともに前記ゲート閾値よりも低い電位を前記ゲートに印加する、
     インバータ回路。
    An inverter circuit that supplies electric power to a traction motor.
    With high potential wiring
    With low potential wiring
    The intermediate wiring connected to the traveling motor and
    A first switching element connected between the high-potential wiring and the intermediate wiring and between the intermediate wiring and the low-potential wiring.
    A second switching element connected to the other between the high-potential wiring and the intermediate wiring and between the intermediate wiring and the low-potential wiring.
    A gate drive circuit connected to the gate of the second switching element,
    Is equipped with
    The gate drive circuit
    In the first state in which the inverter circuit supplies electric power to the traveling motor, the potential applied to the gate changes between a gate-on potential higher than the gate threshold of the second switching element and a negative potential. Let me
    In the second state in which the inverter circuit does not supply electric power to the traveling motor, a potential higher than the negative potential and lower than the gate threshold value is applied to the gate.
    Inverter circuit.
  2.  前記ゲート駆動回路に接続されている制御装置をさらに備えており、
     前記インバータ回路は、車両に搭載されており、
     前記制御装置は、
     前記車両が走行している場合に、前記第1状態であると判断し、
     前記車両が停止している場合に、前記第2状態であると判断する、請求項1に記載のインバータ回路。
    It further includes a control device connected to the gate drive circuit.
    The inverter circuit is mounted on the vehicle and
    The control device is
    When the vehicle is traveling, it is determined that the vehicle is in the first state, and the vehicle is determined to be in the first state.
    The inverter circuit according to claim 1, wherein when the vehicle is stopped, it is determined that the vehicle is in the second state.
  3.  前記第1スイッチング素子及び前記第2スイッチング素子は、SiC基板に設けられたFET(Field Effect Transistor)である、請求項1又は2に記載のインバータ回路。 The inverter circuit according to claim 1 or 2, wherein the first switching element and the second switching element are FETs (Field Effect Transistors) provided on a SiC substrate.
PCT/JP2019/049446 2019-12-17 2019-12-17 Inverter circuit WO2021124453A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2021565211A JPWO2021124453A1 (en) 2019-12-17 2019-12-17
PCT/JP2019/049446 WO2021124453A1 (en) 2019-12-17 2019-12-17 Inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/049446 WO2021124453A1 (en) 2019-12-17 2019-12-17 Inverter circuit

Publications (1)

Publication Number Publication Date
WO2021124453A1 true WO2021124453A1 (en) 2021-06-24

Family

ID=76477308

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/049446 WO2021124453A1 (en) 2019-12-17 2019-12-17 Inverter circuit

Country Status (2)

Country Link
JP (1) JPWO2021124453A1 (en)
WO (1) WO2021124453A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011229011A (en) * 2010-04-21 2011-11-10 Sumitomo Heavy Ind Ltd Control circuit of switching transistor and power converting device using the same
WO2016116998A1 (en) * 2015-01-19 2016-07-28 株式会社日立製作所 Semiconductor device, method for manufacturing same, power conversion device, three-phase motor system, automobile, and railway carriage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011229011A (en) * 2010-04-21 2011-11-10 Sumitomo Heavy Ind Ltd Control circuit of switching transistor and power converting device using the same
WO2016116998A1 (en) * 2015-01-19 2016-07-28 株式会社日立製作所 Semiconductor device, method for manufacturing same, power conversion device, three-phase motor system, automobile, and railway carriage

Also Published As

Publication number Publication date
JPWO2021124453A1 (en) 2021-06-24

Similar Documents

Publication Publication Date Title
US8395422B2 (en) Drive circuit for switching device
US9813009B1 (en) Active gate clamping for inverter switching devices using grounded gate terminals
US11171638B2 (en) Electronic apparatus
WO2008088075A1 (en) Driving circuit for power semiconductor element
JP4509092B2 (en) Electronic equipment and power supply circuit
US9419508B2 (en) Driving apparatus for driving switching elements of power conversion circuit
KR101297460B1 (en) Apparatus for driving gate
JP2009194514A (en) Gate drive circuit of power semiconductor
US11799472B2 (en) Drive circuit
WO2021124453A1 (en) Inverter circuit
WO2014128942A1 (en) Device for driving semiconductor element
JP5407349B2 (en) Switch circuit
JP2020195213A (en) Driving circuit of switching transistor
JP6131874B2 (en) Inverter circuit failure detection method, drive device, and motor drive system
CN116436453A (en) Multi-level power device grid driver with miller clamping function
JP2020096444A (en) Switching circuit
JP5313796B2 (en) Power semiconductor drive circuit and drive method
US10651842B2 (en) Drive circuit for object switch
US20200287499A1 (en) Control circuit for a multi-phase motor
KR101836247B1 (en) Inverter driving apparatus
US8638129B2 (en) Power circuit
JP2014124055A (en) Gate driving circuit
US20240113614A1 (en) Driving circuit of bridge circuit
US11855612B2 (en) High-side driver
US20240007094A1 (en) Gate driver

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19956929

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021565211

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19956929

Country of ref document: EP

Kind code of ref document: A1