WO2021114550A1 - 一种发光装置 - Google Patents

一种发光装置 Download PDF

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Publication number
WO2021114550A1
WO2021114550A1 PCT/CN2020/087213 CN2020087213W WO2021114550A1 WO 2021114550 A1 WO2021114550 A1 WO 2021114550A1 CN 2020087213 W CN2020087213 W CN 2020087213W WO 2021114550 A1 WO2021114550 A1 WO 2021114550A1
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Prior art keywords
layer
light
chip
sub
bonding
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PCT/CN2020/087213
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English (en)
French (fr)
Inventor
刘士伟
郑高林
何安和
王庆
林素慧
彭康伟
洪灵愿
曾江斌
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厦门三安光电有限公司
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Application filed by 厦门三安光电有限公司 filed Critical 厦门三安光电有限公司
Priority to KR1020217033919A priority Critical patent/KR102622149B1/ko
Priority to CN202080005596.8A priority patent/CN112840468A/zh
Publication of WO2021114550A1 publication Critical patent/WO2021114550A1/zh
Priority to US17/664,950 priority patent/US20220285596A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the invention relates to a flip-chip light-emitting diode and a light-emitting element mounted with the flip-chip light-emitting diode through flip chip technology.
  • Light-emitting diodes apply current to semiconductor materials to release energy in the form of light through the combination of electrons and holes. Compared with traditional light sources, light-emitting diodes have the advantages of low power consumption, environmental protection, long service life, and fast response, making current light-emitting diodes widely used in the field of lighting and display.
  • bonding techniques commonly used include wire bonding and flip chip.
  • flip-chip technology has the advantages of reducing chip packaging volume and shortening signal transmission paths, and has been widely used in the packaging of high-power light-emitting diode chips.
  • One of the flip-chip bonding techniques is to brush solder paste between the eutectic bonding electrode of the light-emitting diode and the eutectic bonding electrode on the package substrate or application circuit board, and then, through a reflow furnace for example, the light-emitting diode chip and package The substrate or application circuit board is heated to realize eutectic welding.
  • the present invention provides a light-emitting element comprising: a flip-chip light-emitting diode and a carrier substrate.
  • the flip-chip light-emitting diode includes a semiconductor light-emitting sequence.
  • the bonding electrode wherein the first bonding electrode and the second bonding electrode start from the side of the semiconductor light-emitting sequence, and sequentially include a transition metal layer and a bonding layer;
  • the first bonding electrode and the second bonding electrode of the flip-chip light-emitting diode are fixed on the carrier substrate through a solder paste, wherein the bonding layer has a first part and a second part, and only the first part forms a eutectic layer with the tin in the solder paste.
  • the two parts are between the eutectic layer and the transition metal layer.
  • the thickness of the first part of the bonding layer on the top surface of the transition metal layer is between 50 nm and 300 nm.
  • the second part of the bonding layer serves as an intermediate layer between the eutectic layer and the transition metal layer to maintain the original interface bonding force between the bonding layer and the transition metal layer, thereby improving the die bonding ability of the light-emitting diode after it is mounted on the carrier substrate.
  • Increase the thrust value ; at the same time, prevent tin from passing through the bonding layer to the transition metal layer or further to the epitaxial surface, causing chip failure.
  • FIG. 1 is a schematic structural diagram of a light-emitting diode of the first embodiment fixed on a packaging substrate through a reflow soldering process;
  • FIG. 2 is a schematic diagram of a top view of the light emitting diode in the first embodiment from the side of the first bonding electrode and the second bonding electrode;
  • FIG. 3 is a schematic cross-sectional structure view along the thickness direction of the position of the dotted line A of the light emitting diode of FIG. 2;
  • FIG. 4 is a schematic diagram of the metal layer of the second bonding electrode of the light-emitting diode according to the first embodiment
  • Figure 5 is a graph of the relative value of the thrust value of the sample mentioned in Example 1, where the thrust value of the Ni300nm sample is taken as the reference value of 1, and the values of the other samples are measured relative to the thrust value of the Ni300nm sample. Relative value of thrust value;
  • FIG. 7 is a schematic diagram of the metal layer of the second bonding electrode of the light-emitting diode of the second embodiment
  • FIG. 8 is a schematic diagram of the metal layer of the second bonding electrode of the light emitting diode of the third embodiment
  • FIG. 9 shows a schematic top view of the flip-chip high-voltage light-emitting diode of the fourth embodiment
  • FIG. 10 shows a schematic cross-sectional structure view along line A in FIG. 9, wherein the cross-sectional structure from left to right in FIG. 10 is a cross-sectional structure along the arrow direction of line A in FIG. 9;
  • FIG. 11 shows a schematic cross-sectional structure view along line B in FIG. 10, wherein the cross-sectional structure from left to right in FIG. 11 is a cross-sectional structure along the arrow direction of line B in FIG. 9;
  • FIG. 12 shows a comparison diagram of the thrust value of the flip-chip high-voltage light-emitting diode in the prior art and the present invention, wherein the thrust value of the No. 1 chip is the reference value 1, and the thrust value of the No. 2 chip is the thrust value of the No. 1 chip 1.6 times of
  • FIG. 13 shows a schematic diagram of a top view structure of an existing flip-chip high-voltage light-emitting diode
  • FIG. 14 shows a schematic cross-sectional structure view along line A'in FIG. 13, wherein the cross-sectional structure from left to right in FIG. 14 is a cross-sectional structure along the arrow direction of line A'in FIG.
  • 10 daughter chip; 100, 400: substrate; 200: semiconductor light emitting sequence; 202, 401: first conductivity type semiconductor layer; 203, 402: light emitting layer; 204, 403: second conductivity type semiconductor layer; 205, 404 : Transparent electrode layer; 206: insulating dielectric layer; 207, 406: first metal electrode; 208, 407: second metal electrode; 209, 410: first bonding electrode; 210, 411: second bonding electrode; 210a: stress Buffer layer; 210b: stress transition layer; 210c: bonding layer; 210c1: first part; 210c2: second part; 210e: precipitation blocking layer; 210f: adhesion layer; 300: packaging substrate; 302, 303: first packaging electrode And the second package electrode; 304, 305: solder paste; 405: transparent insulating layer; 408: interconnection electrode; 409: reflective layer; 412: other metal pads.
  • the present invention provides a light-emitting element as follows, comprising: a flip-chip light-emitting diode and a carrier substrate, the flip-chip light-emitting diode is fixed on the carrier substrate by a solder paste, and the flip-chip light-emitting diode includes a semiconductor light-emitting sequence, wherein the semiconductor light-emitting sequence It is a multi-layer and stacked layer by layer.
  • the first and second bonding electrodes are located on the same side of the semiconductor light-emitting sequence and have opposite electrical properties.
  • the first and second bonding electrodes start from the side of the semiconductor light-emitting sequence, in sequence Including a transition metal layer and a bonding layer, the bonding layer includes a first part and a second part;
  • the eutectic layer, between the flip chip light emitting diode and the carrier substrate, is the eutectic layer formed by the eutectic of the first part of the bonding layer of the first bonding electrode and the second bonding electrode and the tin in the solder paste.
  • a bonding layer with a second thickness remains between the layer and the transition metal layer, wherein from the stacking direction of the semiconductor light emitting sequence, the thickness of the second part of the bonding layer is between 50 nm and 300 nm.
  • the carrier substrate is a package substrate or a circuit board.
  • the reflow soldering process is at least once, for example, once or twice.
  • the light-emitting element is a package body, which includes a package substrate 300 and a flip-chip light-emitting diode mounted on the package substrate 300.
  • the flip-chip light emitting diode includes at least a first bonding electrode 209 and a second bonding electrode 210 with opposite electrical properties.
  • the first bonding electrodes 209 and 210 of the light emitting diode are respectively connected to the first package electrode 302 and the second package electrode 303 of the package substrate 300 through solder pastes 304 and 305 and a single reflow process.
  • the packaging substrate 300 may be selected according to application requirements, such as a flexible substrate, such as a flexible filament lamp or a flexible substrate FPC of a light ribbon, or a COB aluminum-based substrate or an FR4 flexible substrate, for example.
  • the packaging substrate includes a first packaging electrode 302 and a second packaging electrode 303.
  • the solder pastes 302 and 303 may be selected from at least one of tin-Ag, tin-Bi, tin-Zn, tin-Ag-Cu, tin-Cu, and tin-Au alloys (all of which contain tin).
  • the solder pastes 302 and 303 connect the first bonding electrode 209 and the second bonding electrode 210 to the first package electrode 302 and the second package electrode 303 provided on the package substrate 300, respectively.
  • the solder pastes 302 and 303 are in contact with the top surfaces of the first and second bonding electrodes 209 and 210 and are spread under pressure to cover the side surfaces of the first and second bonding electrodes 209 and 210, respectively.
  • the tin in the solder paste diffuses from the top and side surfaces of the first bonding electrode 209 and the second bonding electrode 210 to the inside of the first bonding electrode and the second bonding electrode to form a eutectic layer with a certain thickness .
  • the temperature of reflow soldering can be conventionally selected according to different solder pastes with different melting points, usually the lowest is 150° and the highest is 270°.
  • the light-emitting element may also be an applied light-emitting element, such as a display, including a circuit board and a flip-chip light-emitting diode.
  • the flip-chip light-emitting diode is directly mounted on the circuit board through a solder paste and a reflow soldering process.
  • the circuit board may be a flexible circuit board, such as a PCB board, made of polyimide or polyester film as the main material.
  • the light-emitting diode may have a conventional size or smaller than the conventional size.
  • the side length of the semiconductor light-emitting sequence of a small-sized light-emitting diode is preferably less than or equal to 300 microns, preferably between 100-300 microns, or 100-200 Micrometer, or a size smaller than 100 micrometers, preferably at least 40 micrometers.
  • light-emitting diodes below 100 microns may optionally have no transparent substrate on the main light-emitting surface.
  • the thickness of the semiconductor light-emitting sequence is between 1 and 8 microns.
  • the small-sized light-emitting diode has the above-mentioned horizontal area and thickness, and can be easily applied to various electronic devices that require small and thin light-emitting devices.
  • the flip-chip light-emitting diode specifically includes: a semiconductor light-emitting sequence 200, a first bonding electrode 209 and a second bonding electrode 210 that are located on the same side of the semiconductor light-emitting sequence 200 and have opposite electrical properties.
  • the first bonding electrode 209 and the second bonding electrode 210 generally have the same composition of multiple metal layers, and the specific self-semiconductor light emitting sequence includes a transition metal layer and a bonding layer.
  • the multiple metal layers of the first bonding electrode 209 and the second bonding electrode 210 may be formed through a sputtering plating process.
  • the transition metal layer is between the bonding layer and the passivation layer 208, and the transition metal layer is one or more layers, for example, a transition metal layer It is at least one functional layer of the stress buffer layer 210a, the stress transition layer 210b, and the reflective layer.
  • the transition metal layer is a combination of a stress buffer layer 210a and a stress transition layer 210b, wherein the stress buffer layer 210a is used to relieve the stress of the subsequently formed bonding layer 210c, and prevent excessive stress in the bonding layer from causing cracks.
  • the stress buffer layer 210a is used to relieve the stress of the subsequently formed bonding layer 210c, and prevent excessive stress in the bonding layer from causing cracks.
  • the stress buffer layer 210a can also be used as a reflective layer to provide a high reflection effect on the radiation waveband of the light-emitting layer, for example, a reflectance above 80%.
  • an additional reflective layer is also formed, and the reflective layer produces a high reflection effect on the radiation band of the light-emitting layer, for example, a reflectivity of more than 80%.
  • the preferred stress buffer layer 210a is one or more of Ti, Al, Cu, and Au.
  • the stress transition layer 210b adheres to the interface between the stress buffer layer 210a and the bonding layer 210c.
  • the stress transition layer 210b can act as a stress transition between the bonding layer and the stress buffer layer, increasing the bonding force between the two layers.
  • the stress transition layer 210b is preferably Ti or Cr.
  • the bonding layer 210c is used to form a eutectic layer with the tin in the solder paste when the first bonding electrode 209 and the second bonding electrode 210 are bonded to the packaging substrate or the application substrate through a reflow process.
  • the transition metal layer and the bonding layer are deposited sequentially through an evaporation process.
  • the bonding layer can better cover the top surface and sidewalls of the transition metal layer, and is dense , The surface flatness and the interface bonding force between the metal layers are higher.
  • multiple photomask patterns can be used to define the coverage area of the bonding layer to assist multiple coating processes to increase the thickness of the sidewall of the bonding layer covering the transition metal layer.
  • the thickness of the bonding layer covering the sidewall of the transition metal layer can be thick enough through multiple coating processes, so that after the solder paste is installed on the packaging substrate or circuit board, the sidewall of the transition metal layer and the formed eutectic layer There is a second part of the bonding layer in between, thereby improving the eutectic ability of the sidewall position, and preventing tin from passing through the bonding layer into the transition metal layer, and even reaching the surface of the epitaxial layer, causing chip failure.
  • the bonding layer 210c includes a first part 210c1 and a second part 210c2.
  • the first part 210c1 is used to form a eutectic layer with tin in the solder paste.
  • the second part 210c2 is between the first part and the transition metal layer.
  • the second part of the bonding layer 210c Compared with the first part, 210c2 is closer to the semiconductor light emitting sequence.
  • the second part 210c2 of the bonding layer 210c is used as an intermediate layer between the eutectic layer and the transition metal layer, maintaining the original interface bonding force between the bonding layer and the transition metal layer, and preventing direct contact between the eutectic layer and the transition metal layer , To prevent the original bonding layer and the transition metal layer from being damaged, thereby improving the die bonding ability of the light-emitting diode after mounting on the carrier substrate, and increasing the thrust value; at the same time, tin passes through the bonding layer to the transition metal layer or further reaches the epitaxial surface , Causing chip failure.
  • the defined thickness of the second portion 210c2 of the bonding layer 210c between the eutectic layer and the transition metal layer is T1. Due to the uneven diffusion of tin in the eutectic layer, T1 of the present invention is The second portion 210c2 of the bonding layer 210c between the eutectic layer and the transition metal layer has a minimum thickness, and T1 is greater than 0 nm, preferably, T1 is at least 50 nm.
  • the thicker second part 210c2 bonding layer can maintain the interface force between the original bonding layer and the transition metal layer, increase the thrust value of the pad; and prevent tin from spreading in the bonding layer at a local position to reach the original bonding layer of the bonding layer too quickly
  • the interface between the transition metal layer and the transition metal layer further diffuses into other metal layers or diffuses to the surface of the epitaxial layer to prevent chip failure.
  • the bonding layer can also form a thicker coating on the sidewall of the transition metal layer to improve Eutectic and barrier at the sidewall position. From the perspective of the stacking direction of the semiconductor light-emitting sequence, the second part of the bonding layer is between the eutectic layer and the transition metal layer.
  • the thickness T1 is at most 300nm.
  • the thickness of the second part 210c2 that is too thick does not improve the bonding ability and the thrust value. On the contrary, it will cause excessive stress on the bonding electrode, which is prone to cracks.
  • the first part 210c1 and the second part 210c2 of the bonding layer 210c are all Ni layers or alloy layers or co-plating layers containing Ni with a mass percentage of Ni greater than 50%. At least one of the alloy layers or co-plating layers may be allowed Other metal layers, such as Ti layer or Au layer, are inserted into the Ni layer to form a composite layer of interlayer, or allow other metal layers such as Ti layer or Au layer and Ni layer to be stacked at once or repeatedly to form a composite layer, and the content of Ni in the composite layer
  • the total thickness is greater than the thickness of other metal layers, the thickness of at least one other metal layer between adjacent Ni layers allows Sn to pass through, and the layer closest to the transition metal layer in the composite layer is Ni.
  • the thrust value curve shown in Fig. 5 reflects that the light-emitting diodes with the first bonding electrode and the second bonding electrode with different thicknesses of the bonding layer are used as test samples, and they are fixed on the carrier substrate through solder paste and two reflow soldering processes. After loading, the test result of the thrust value of the light-emitting diode falling off the carrier substrate.
  • the bonding layer is a Ni layer
  • the stress buffer layer is Al
  • the stress transition layer is Ti.
  • the composition of the solder paste is tin, silver and copper, and the reflow temperature is 270°C.
  • the carrier substrate is a flexible circuit board FPC board. It can be seen that as the thickness of the bonding layer increases, the thrust value increases.
  • the thickness of the bonding layer is 300 nm
  • the thickness of the bonding layer and the thickness of the eutectic layer formed by tin are insufficient, resulting in low bonding ability and low thrust value.
  • the thickness of the bonding layer is 500nm
  • the thickness of the bonding layer and the thickness of the eutectic layer formed by tin increase, which leads to an increase in the bonding ability and the thrust value.
  • the maximum thickness of the eutectic layer formed by the diffusion of tin in the bonding layer is close to 500nm.
  • Theoretically The bonding layer of 500nm can form a sufficiently thick eutectic layer with tin.
  • the local diffusion is still too fast, and the tin will reach the transition metal layer.
  • the original bonding force formed during the coating process of the bonding layer and the transition metal layer is partially destroyed, the thrust value is not enough, and the tin will reach the transition metal layer or the epitaxial surface, leading to the risk of chip failure.
  • the thrust value is further increased when the bonding layer is thickened to 750nm.
  • the FIB-SEM image of the second bonding electrode obtained after the sample with the bonding layer thickness of 750nm is fixed on the carrier substrate by brushing solder paste and two reflow soldering processes, and combined with EDX analysis, the tin is in the bonding layer
  • the average thickness of the eutectic layer formed by the medium diffusion is about 500nm.
  • the bonding layer of the remaining thickness is also included between the eutectic layer and the transition metal layer.
  • the bonding layer of the remaining thickness completely prevents tin from reaching the interface of the transition metal layer, including It prevents the locally diffused tin in the bonding layer from reaching the interface of the transition metal layer, while maintaining the original bonding force formed during the coating process of the bonding layer and the transition metal layer, which has a further improvement compared to the sample with a bonding layer of 500nm value.
  • the flip-chip light emitting diode of the present invention provides a main light output surface on the side of the first conductive semiconductor layer 202 of the semiconductor light emitting sequence, or when the substrate 100 supports the light emitting semiconductor sequence, the substrate 100
  • the second surface that is transparent and has a distance away from the semiconductor light emitting sequence is the main light output surface of the light emitting diode.
  • the substrate 100 includes a first surface, a second surface, and sidewalls. The first surface and the second surface are opposite to each other.
  • the substrate 100 includes a plurality of protrusions formed at least on at least a portion of the first surface.
  • the substrate 100 may be a patterned sapphire substrate.
  • the first surface of the substrate 100 supports the semiconductor light emitting sequence.
  • the substrate 100 is a growth substrate, such as a sapphire substrate, on which a semiconductor light-emitting sequence is obtained on the surface of the sapphire substrate through a MOCVD process, and the growth substrate supports the semiconductor light-emitting sequence for making electrodes and passivation layers Process and cutting process of semiconductor light-emitting sequence and substrate to obtain a single light-emitting diode; or the substrate is a bonded substrate, and after the growth of the semiconductor light-emitting sequence is completed on the growth substrate, it is transferred to the bonded substrate through the bonding process Complete the electrode, passivation layer manufacturing process, semiconductor light-emitting sequence, and the cutting process of the substrate to obtain a single light-emitting diode.
  • the semiconductor light emitting sequence 200 includes a semiconductor layer 202 of a first conductivity type, an active layer 203 and a semiconductor layer 204 of a second conductivity type.
  • the first conductivity may be n-type or p-type.
  • the second conductivity is opposite to the first conductivity, and may be n-type or p-type.
  • the specific semiconductor light emitting sequence may include III-V type nitride-based semiconductors, for example, may include nitride-based semiconductors such as (Al, Ga, In)N to provide light radiation in the ultraviolet, blue, or green wavelength bands; or ( Al, Ga, In) P phosphide semiconductors or (Al, Ga, In) As arsenide semiconductors provide red light or infrared light radiation.
  • the outer surface of the second conductivity type semiconductor layer 204 is located at the farthest position from the main light output surface or the substrate 100.
  • the semiconductor light emitting sequence is etched along the thickness direction from a part of the surface of the second conductive type semiconductor layer 204, so that the second conductive type semiconductor layer 204 and the active layer 203 and only a part of the thickness of the first conductive type semiconductor layer 202 are removed to form Groove or step area.
  • the groove portion or the step area partially exposes the first conductive type semiconductor layer 202.
  • a first metal electrode metal layer 206 having a predetermined thickness and width is formed in the groove or step area where the first conductive type semiconductor layer 202 is exposed, and on one of the outer surfaces of the second conductive type semiconductor layer 204 A transparent electrode layer 205 and a second metal electrode metal layer 207 having a predetermined thickness and a predetermined area are formed on the region.
  • the surface of the second conductive type semiconductor layer 204 may be covered with a metal reflective layer on the entire surface, such as silver.
  • the insulating layer 208 covers the top surface and sidewalls of the semiconductor light-emitting sequence.
  • the first bonding electrode 209 and the second bonding electrode 210 cover the surface of the passivation layer 208, and pass through the first and second openings of the passivation layer 208, respectively.
  • the first metal electrode metal layer 206 and the second metal electrode metal layer 207 are in contact. There is a certain horizontal distance between the first bonding electrode 209 and the second bonding electrode 210 to ensure that there is no short circuit due to contact with each other.
  • the passivation layer 208 may be transparent, or it may have a reflective function, for example, a DBR reflective layer including an insulating layer.
  • the present embodiment can prevent tin from reaching the interface of other metal pads by retaining the bonding layer of the second thickness between the transition metal layer and the eutectic layer, destroying the interface force between the bonding layer and the transition metal layer, thereby increasing
  • the die bonding capability improves the thrust value of the light-emitting diode after it is mounted on the package substrate.
  • the solution of the present invention is applicable to packaged light-emitting elements obtained by mounting flip-chip light-emitting diodes on a package substrate through solder paste and one-time reflow soldering process, or applied light-emitting components obtained directly through solder paste and one-time reflow soldering on a circuit substrate.
  • Package Bulk light-emitting elements can be further mounted on a circuit board through a single solder paste and reflow soldering to obtain application products, which are preferably suitable for packages or applications with flexible mounting substrates that require pastes for die-bonding capability, as well as for application products. Small size flip-chip light-emitting diodes to improve eutectic capability and thrust value.
  • the stress buffer layer 210a of the bonding electrode is designed as multiple layers, preferably two layers or three layers, and other metal layers can be added between two adjacent layers of the stress buffer layer 210a.
  • the stress buffer layer is Al
  • the other metal layer is the precipitation barrier layer 210e
  • the precipitation barrier layer and the stress buffer layer are repeatedly stacked to prevent Al precipitation.
  • TiAl repeatedly stacks layers.
  • the thickness ratio of the precipitation blocking layer to the stress buffer layer is less than or equal to 1:3.
  • a thicker precipitation blocking layer reduces the stress buffer effect of the stress buffer layer 210a and increases the resistance of the bonding electrode.
  • the first bonding electrode 209 and the second bonding electrode 210 further include a bottom layer.
  • the bottom layer is an adhesion layer 210f, such as Ti or Cr.
  • the layer 210f is located between the transition metal layer and the semiconductor light emitting sequence, covers the surface of the passivation layer 208 and directly contacts the passivation layer 208.
  • the thickness of the adhesion layer 210f is preferably less than or equal to 5 nm to minimize the effect of light absorption.
  • High-voltage flip-chip light-emitting diodes are a kind of flip-chip light-emitting diodes. With good heat dissipation performance, they can be used in high-power fields such as lighting, backlighting, RGB display screens, and flexible filaments. High-voltage flip-chips are also paying more and more attention to the combination of electrodes on the substrate. Die-bonding ability, especially the die-bonding ability on flexible substrates.
  • the flip-chip light-emitting diodes of the first to third embodiments may also be a flip-chip high-voltage light-emitting diode, as shown in FIGS.
  • the substrate 400 is a transparent substrate, the front side is used to carry the semiconductor light emitting sequence, and the back side is used to provide the main light output surface.
  • Each sub-chip 10 includes a semiconductor light emitting sequence, and the semiconductor light emitting sequence includes a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer.
  • the passivation layer is a reflective layer 409 made of insulating material, covering each sub-chip and in the trench.
  • the reflective layer 409 has a first bonding electrode through hole and a second bonding electrode through hole.
  • the electrode through holes and the second bonding electrode through holes are respectively located above the first sub-chip and the n-th sub-chip; the first bonding electrode 410 and the second bonding electrode 411, which are electrically opposite to each other, are respectively located in the first and n-th sub-chips.
  • the surface of the reflective layer 409 covered on the chip is filled with the first bonding electrode through hole and the second bonding electrode through hole, and the first bonding electrode 409 passes through the part filled in the first bonding electrode through hole and the second bonding electrode through hole. It is electrically connected to the second conductivity type semiconductor layer of the first sub-chip and the first conductivity type semiconductor layer of the nth sub-chip.
  • the first bonding electrode 400 and the second bonding electrode 400 include a transition metal layer and a bonding layer.
  • the first bonding electrode and the second bonding electrode have the same design as the first to third embodiments, which can improve the die bonding ability of the high-voltage flip-chip light emitting diode.
  • this embodiment also proposes the following improvements to the flip-chip high-voltage light-emitting diode:
  • n sub-chips on the substrate 400 and isolated from each other n is greater than or equal to 3, and are respectively the first sub-chip, the n-th sub-chip and at least one other sub-chip, and the n sub-chips are located on the substrate and are mutually connected.
  • the reflective layer 409 also has at least one first other opening and/or at least one second other opening, and the first other opening and/or at least one second other opening is above the at least one other sub-chip;
  • the first bonding electrode 410 extends to the surface of the reflective layer 409 covered on at least one other sub-chip, and fills the first other openings of the reflective layer, or the second bonding electrode extends to the reflective layer covered on at least one other sub-chip On the surface, the second other openings of the reflective layer are filled at the same time.
  • the geometric area of the bonding electrode on other sub-chips can be increased, and the bonding electrode can be improved in other sub-chips.
  • the die bonding capability on the chip improves the die bonding capability of the bonding electrode as a whole.
  • the flip-chip light-emitting diode includes the following chip manufacturing process:
  • a semiconductor light-emitting sequence is obtained on the front surface of the substrate 400.
  • the semiconductor light-emitting sequence is multilayered.
  • This embodiment can be called an epitaxial structure, including a first conductive semiconductor layer 401 and an active semiconductor layer sequentially stacked on the front surface of the substrate 400.
  • each sub-chip has an epitaxial structure, and each epitaxial structure provides a light-emitting area.
  • the three epitaxial structures in FIG. 10 are defined as the first sub-chip, the second sub-chip, and the third sub-chip in order from left to right.
  • a transparent electrode layer 404 is formed on the second conductivity type semiconductor layer 403 of each of the above-mentioned sub-chips.
  • the transparent electrode layer 404 has an ohmic contact function and a lateral current spreading function.
  • a transparent insulating layer (CBL) 405 is covered on the transparent electrode layer 404, on the side surface of the epitaxial structure and the bottom of the trench.
  • the transparent insulating layer 405 can connect the epitaxial structure of the three sub-chips and the trench between the three sub-chips.
  • the non-electrode setting area of the structure is insulated and protected.
  • the material of the transparent insulating layer 405 may be silicon dioxide SiO 2 , Si 3 N 4, etc., which may be formed by methods such as plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition). From the perspective of the stacking direction of the semiconductor light emitting sequence, the preferred thickness of the transparent insulating layer 405 is between 100 nm and 1000 nm.
  • the part of the transparent insulating layer 405 covering the first and third sub-chips is partially etched to etch the first metal electrode through hole and the second metal electrode through hole, the first metal electrode through hole and the second metal electrode
  • the through holes correspond to the positions of the first metal electrodes and the second metal electrodes of the first and third sub-chips.
  • the bottom of the first metal electrode through holes is on the surface of the transparent electrode layer 404 of the first sub-chip, and the second metal
  • the bottom of the electrode via is the surface of the first conductivity type semiconductor layer 401 of the third sub-chip.
  • the transparent insulating layer 405 covering the first, second, and third chiplets is etched to form a plurality of interconnection electrode vias.
  • a plurality of interconnection electrode vias of the transparent insulating layer 405 are distributed on the first conductive type semiconductor layers of the first and second sub-chips and on the transparent electrode layers of the second and third sub-chips.
  • the first metal electrode through hole of the transparent insulating layer 405 covering the first sub-chip is filled with conductive metal to form the first metal electrode 406, and the second metal electrode through hole of the insulating layer covering the third sub-chip is filled with conductive metal
  • the conductive metal is filled to form the second metal electrode 407.
  • the first metal electrode 406 is in contact with the transparent conductive layer, and the second metal electrode 407 is in contact with the first conductive type semiconductor layer.
  • an interconnection electrode 408 that electrically connects two adjacent sub-chips can be formed.
  • the interconnection electrode 408 is formed on the insulating layer in the trench and has two ends, which extend to the two adjacent sub-chips. On the chip, by filling the interconnection electrode through holes of two adjacent sub-chips, one end is in contact with the first conductive type semiconductor layer of one sub-chip and the other end is in contact with the surface of the transparent electrode layer of the other sub-chip.
  • one of the interconnection electrodes is connected to the first conductivity type semiconductor layer 401 of the first sub-chip and the transparent electrode layer of the second sub-chip, and the other interconnect electrode is connected to the first conductivity type semiconductor of the second sub-chip Layer 401 and the transparent electrode layer of the third chiplet.
  • the first metal electrode 406, the second metal electrode 407 and the interconnection electrode 408 extend from the through hole to the area adjacent to the upper surface of the local insulating layer around the through hole of the transparent insulating layer.
  • the materials of the first metal electrode 406, the second metal electrode 407, and the interconnect electrode 408 are the same.
  • the reflective layer 409 is formed after the preparation of the first metal electrode 406, the second metal electrode 407 and the interconnection electrode 408 is completed.
  • the reflective layer 409 covers the transparent insulating layer, the first metal electrode and the second metal electrode, including covering the upper part of each sub-chip, around the sidewalls and the trench.
  • the reflective layer reflects the light radiated by the semiconductor light-emitting sequence of each sub-chip, and reflects the light to the back of the substrate, thereby enhancing the backlight of the substrate to emit light.
  • the thickness of the Bragg reflection layer is 2-6 microns.
  • a first bonding electrode through hole and a second bonding electrode through hole are respectively formed through an etching process, and A bonding electrode through hole and a second bonding electrode through hole are filled with conductive metal to form the first bonding electrode 410 and the second bonding electrode 411.
  • the first bonding electrode 410 is conductively connected to the first metal electrode 406 of the first sub-chip, that is, the bottom of the first bonding electrode through hole contacts the first metal electrode 406; and the second bonding electrode 411 is connected to the first metal electrode 406.
  • the second metal electrode 407 of the n-chip is conductively connected, that is, the bottom of the second bonding electrode through hole contacts the second metal electrode 407. Since the first bonding electrode through hole and the second bonding electrode through hole will cause the reflection area loss of the reflective layer, the area of the first bonding electrode through hole or the second bonding electrode through hole usually occupies the first sub-chip or the n-th sub-chip The area will not exceed 20%.
  • the first bonding electrode 410 and the second bonding electrode 411 are simultaneously fabricated to extend above the other sub-chip regions except the first and n-th sub-chips.
  • the portion of the reflective layer 409 covering the other chiplets can also form at least one first other opening and/or through the etching process step. Or at least one second other opening.
  • the first coupling electrode 410 and the second coupling electrode 411 are respectively filled in the corresponding first other opening and the second other opening. The first other opening and the second other opening are used to fill the first bonding electrode and the second bonding electrode, which can increase the geometric area of the two bonding electrodes.
  • the first other opening and the second other opening are through holes penetrating the reflective layer, wherein the bottoms of the first other opening and the second other opening are both located on the transparent insulating layer 405 covering the other sub-chips.
  • the transparent insulating layer 405 insulates and isolates the first bonding electrode filled in the first other openings and the semiconductor light emitting stack, and at the same time insulates and isolates the second bonding electrode filled in the second other openings and the semiconductor light emitting stack.
  • the transparent insulating layer can prevent current from flowing into the semiconductor light-emitting stack from the pads filled in the first other opening and the second other opening, so that the sub-chips are only connected by interconnecting electrodes to avoid short circuit problems.
  • the reflective layer covering the second chiplet is simultaneously provided with a first other opening and a second other opening.
  • the flip-chip high-voltage light-emitting diode provided by the present invention, at least one first other opening and at least one second other opening are formed on the reflective layer 409 of other sub-chips other than the head and tail, and the first bonding electrode 410 and the second bonding electrode 411 are respectively filled with corresponding
  • the first other opening and the second other opening can increase the area of the bonding electrode of the sub-chip in the middle position, thereby increasing the die bonding ability of the middle sub-chip, so as to increase the thrust value of the overall chip; in addition, it can avoid the local bonding of other sub-chips.
  • the crystal does not work, and local peeling occurs to prevent the overall reliability of the high-voltage light-emitting diode from being reduced; and it can make the force of each sub-chip closer and the light-emitting area closer and uniform after the die.
  • the number of the first other openings or the second other openings on each chiplet other than the head and tail is multiple, and the number of the first other openings or the second other openings on each other chiplet The distribution of uniform spacing between the other openings.
  • the combined electrode filled in the openings can also diffract or reflect light to a certain extent, which can reduce light loss, and the diffraction or reflection effect is relative to one of the same horizontal area.
  • the bonding electrode filled in the opening has a better effect, and can evenly distribute the force on the surface of the other chiplets after the bonding electrode is die-bonded.
  • the number and total area of the first other openings and the second other openings on one of the other sub-chips are the same as the number and total area of the first bonding electrode through holes.
  • the number of the other sub-chips is an even number
  • the reflective layer has only the first other openings above half of the other sub-chips, and the number of the first other sub-chip openings above each sub-chip of the half of the other sub-chips is equal
  • the reflective layer has only the second other openings above the other half of the other sub-chips, and the number of the second other sub-chip openings above each sub-chip of the other half of the other sub-chips is equal.
  • the number of the other sub-chips is an odd number
  • one of the other sub-chips of the reflective layer has a first other opening and a second other opening at the same time
  • the number of the remaining other sub-chips is an even number
  • the reflective layer is on the remaining other sub-chips.
  • the reflective layer is only the second above the other half of the other sub-chips Other openings, and the number of openings of the second other sub-chips above each sub-chip is equal.
  • the ratio of the area of the first other opening or the second other opening of each sub-chip to the horizontal projection area of the semiconductor light-emitting sequence of the other sub-chip does not exceed 20%, so as to significantly reduce the light loss. It has both a better overall thrust value and a smaller light loss.
  • the ratio of the area of the first other opening or the second other opening of each sub-chip to the horizontal projection area of the semiconductor light-emitting sequence of the other sub-chip is 5-15%.
  • the flip-chip high voltage The light-emitting diode has a relatively excellent overall thrust value and a smaller light loss.
  • each of the first other openings and each of the second other openings is a columnar or conical truncated hole
  • the horizontal cross-section is circular or polygonal
  • the horizontal aperture is preferably 2-40 microns, more preferably 10 ⁇ 30 microns.
  • the number of the first other openings and the second other openings on each sub-chip other than the head and tail is preferably 2-40.
  • the flip-chip high-voltage light-emitting diode may further include other metal pads 412, which are located between the transparent insulating layer and the reflective layer covered on the other sub-chips, and the other metal pads are connected to the first other opening and the first other opening and the second sub-chip.
  • the first bonding electrode extends above at least one other sub-chip, filling the first other openings of the transparent insulating layer and contacting other metal pads at the bottom of the opening, and/or the second bonding electrode extends to Above at least one other sub-chip, the second other opening of the transparent insulating layer is filled and the bottom of the opening is in contact with other metal pads.
  • the other metal pads may be formed through the same step as the first metal electrode, the second metal electrode, and the interconnection electrode.
  • Figure 12 reflects the relative thrust data of the existing chip and the chip of this embodiment.
  • the structure of the existing chip is shown in Figures 13-14.
  • the existing chip and the chip of this embodiment are named respectively Chip No. 1 and Chip No. 2, in which chip No. 1 is a flip-chip high-voltage light-emitting diode made using the existing technical solution, and chip No. 2 is a flip-chip high-voltage light-emitting diode made using the solution of this embodiment, and each includes 3 sub-chips.
  • the three sub-chips are the first sub-chip, the second sub-chip, and the third sub-chip, wherein the first sub-chip and the second sub-chip are covered with the first bonding electrode, and the second sub-chip and the third sub-chip are covered There is a second bonding electrode.
  • the insulating layer covering the second sub-chip of chip No. 2 has two first other openings and two second other openings.
  • the above two flip-chip high-voltage light-emitting diodes are soldered on the substrate using the same reflow soldering process, and the thrust value of each flip-chip high-voltage light-emitting diode is tested. Refer to Figure 12 for the measured relative thrust value data, which can be seen from Figure 12.
  • the thrust value of the No. 2 chip is about 1.16 times the thrust value of the No. 1 chip. It can be seen that the first other opening and the second other opening are added to the middle sub-chip, and the first bonding electrode 410 and the second bonding electrode 411 fill the corresponding first other opening and the second other opening, which can significantly increase the overall chip The thrust value.
  • the other metal pads can also have a reflective function and be a metal reflective layer, which can improve light efficiency, or as another alternative, the bottom layer of the first bonding electrode and the second bonding electrode has Light reflectivity, the bottom layer forms a metal reflective layer that has the ability to reflect the light emitted by the flip-chip high-voltage light-emitting diode, such as a mirror surface aluminum layer, a lens silver layer, and the like.
  • first other openings and the second openings of the reflective layer may also be non-through holes, and the bottom of the opening is located in the reflective layer, which can also increase the geometric area of the bonding electrode on other sub-chips. , Improve the ability of die bonding.
  • a plurality of other openings are provided on the reflective layer on the other sub-chips other than the head and the end to fill the bonding electrode, increase the geometric area of the bonding electrode on the other sub-chips, and increase the overall The thrust value of the chip; it can also avoid the poor bonding ability of the bonding electrode on other sub-chips, prevent local peeling of the bonding electrode without labor, and avoid the reliability of the chip under working conditions.
  • the reflective layer is provided with through-pad holes on the first and last chips.
  • the reflection area of the first and last chips has been reduced. Multiple other openings are provided on the sub-chips at the same time, without adding other openings on the first and last sub-chips, the difference in the reflection area of the reflective layer of each sub-chip can be reduced, and the uniform light emission of each sub-chip can be achieved as much as possible.
  • the high-voltage flip chip of the present invention can be installed in packaging products or applications in the fields of lighting, backlighting, RGB display screens, flexible filaments, etc., especially the flexible substrate as the packaging or application of the mounting substrate.

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Abstract

一种发光元件，包括：倒装发光二极管和承载基板，倒装发光二极管通过锡膏固定于承载基板上；所述的倒装发光二极管包括半导体发光序列、位于半导体发光序列的同一侧且电性相反的第一结合电极和第二结合电极；其中第一结合电极和第二结合电极自半导体发光序列一侧开始，依次包括过渡金属层、结合层；从半导体发光序列的堆叠方向上看，结合层包括第一部分和第二部分；共晶层，介于倒装发光二极管与承载基板之间，为所述第一结合电极和第二结合电极的结合层的第一部分与锡膏中的锡共晶形成，结合层第二部分介于共晶层与过渡金属层之间。

Description

一种发光装置 技术领域
本发明涉及一种倒装发光二极管以及通过覆晶技术安装有倒装发光二极管的发光元件。
背景技术
发光二极管是对半导体材料施加电流，以通过电子与空穴的结合将能量以光的形式释出。相较于传统光源，发光二极管具有低功率消耗、环保、使用寿命长及反应快等优势，使得当前发光二极管在照明领域及显示领域中广泛运用。
为将发光二极管芯片安装在封装基板或运用基板上以获得封装体或应用品，常见采用的接合技术有打线及覆晶。其中，覆晶技术具有缩小芯片封装体积及缩短信号传输路径等优点，目前已经广泛应用于大功率发光二极管芯片的封装。其中一种覆晶接合技术具体是，在发光二极管的共晶结合电极与封装基板或应用电路板上的共晶结合电极之间刷锡膏，接着，通过例如回焊炉对发光二极管芯片与封装基板或应用电路板加热，实现共晶焊接。
近年来，随着显示、柔性灯丝、柔性灯带等应用领域的发展，其中相当一部分产品使用柔性基板作为芯片的安装基板，然而由于柔性基板热膨胀系数较大，对倒装共晶结合电极结构的固晶能力提出了更高的要求，将传统倒装共晶结合电极结构应用到以上产品时易出现以下异常：固晶后推力值较低，回流焊后容易出现掉电极。
另外一方面，因显示屏对像素要求的不断提升，像素间距(pitch)要求越来越小，芯片要求越做越小。而随着芯片尺寸的不断缩小，芯片上两电极的共晶结合电极提供的共晶面积减小。不管是柔性安装基板还是刚性基板，受限于共晶结合电极共晶面积，小尺寸的芯片的共晶能力也降低，因此需要考虑如何提升小尺寸芯片的共晶能力，并且保证共晶结合电极焊接的可靠性。
发明概述
技术问题
问题的解决方案
技术解决方案
本发明提供如下一种发光元件，包括：倒装发光二极管和承载基板，所述的倒装发光二极管包括半导体发光序列，位于半导体发光序列的同一侧且电性相反的第一结合电极和第二结合电极，其中第一结合电极和第二结合电极自半导体发光序列一侧开始，依次包括过渡金属层、结合层；
所述倒装发光二极管第一结合电极和第二结合电极通过锡膏固定于承载基板上，其中结合层具有第一部分和第二部分，仅第一部分与锡膏中的锡形成共晶层，第二部分介于共晶层与过渡金属层之间。
优选地，所述结合层第一部分在过渡金属层的顶面上的厚度介于50nm～300nm之间。
发明的有益效果
有益效果
结合层的第二部分作为中间层介于共晶层与过渡金属层之间，维持原来结合层与过渡金属层之间的界面结合力，从而提升发光二极管安装在承载基板后的固晶能力，提升推力值；同时防止锡穿过结合层到达过渡金属层或者进一步到达外延表面，引起芯片失效。
对附图的简要说明
附图说明
图1为实施例一的发光二极管经过一次回流焊工艺固定在封装基板上的结构示意图；
图2为实施例一的发光二极管从第一结合电极和第二结合电极一侧俯视发光发光二极管的俯视结构示意图；
图3为沿着图2的发光二极管的虚线A位置的厚度方向的剖视结构示意图；
图4为实施例一的发光二极管的第二结合电极的金属层示意图；
图5为实施例一所提及的样品的推力值相对值的曲线图，其中Ni300nm的样品的推力值作为基准值为1，其它样品的值为相应样品测试的推力值相对于Ni300n m样品的推力值的相对值；
图6为实施例一所提及的结合层为Ni750nm的样品的第二结合电极的局部FIB-SEM图；
图7为实施例二的发光二极管的第二结合电极的金属层示意图；
图8为实施例三的发光二极管的第二结合电极的金属层示意图；
图9示出了实施四的倒装高压发光二极管的俯视结构示意图；
图10示出了图9中沿线A的剖视结构示意图，其中图10中从左至右方向的剖视结构为图9中沿着线A箭头方向的剖视结构；
图11示出了图10中沿线B的剖视结构示意图，其中图11中从左至右方向的剖视结构为图9中沿着线B箭头方向的剖视结构；
图12示出了现有技术中的以及本发明的倒装高压发光二极管的推力值对比图，其中1号芯片的推力值为基准值1，2号芯片的推力值是1号芯片的推力值的1.6倍左右；
图13示出了现有的倒装高压发光二极管的俯视结构示意图；
图14示出了图13中沿线A’的剖视结构示意图，其中图14中从左至右方向的剖视结构为图13中沿着线A’箭头方向的剖视结构。
附图标记
10：子芯片；100、400：衬底；200：半导体发光序列；202、401：第一导电型半导体层；203、402：发光层；204、403：第二导电型半导体层；205、404：透明电极层；206：绝缘介质层；207、406：第一金属电极；208、407：第二金属电极；209、410：第一结合电极；210、411：第二结合电极；210a：应力缓冲层；210b：应力过渡层；210c：结合层；210c1：第一部分；210c2：第二部分；210e：阻挡析出层；210f：粘附层；300：封装基板；302、303：第一封装电极和第二封装电极；304、305：锡膏；405：透明绝缘层；408：互连电极；409：反射层；412：其它金属垫。
发明实施例
本发明的实施方式
实施例一
现在将参照附图详细描述本发明的实施例。提供这些实施例使得本公开彻底和完整，并且向本领域技术人员充分传达本发明的范围。因此，本发明可以以许多不同的形式实施，并且不应该被解释为限于这里给出的示例性实施例。在附图中，为了清楚起见，可以夸大元件的尺寸(诸如宽度、长度和厚度)。在整个说明书中，相同的附图标记表示相同的元件。
本发明提供如下所述一种发光元件，包括：倒装发光二极管和承载基板，倒装发光二极管通过锡膏固定于承载基板上，所述的倒装发光二极管包括半导体发光序列，其中半导体发光序列为多层，并且逐层堆叠，位于半导体发光序列的同一侧且电性相反的第一结合电极和第二结合电极，其中第一结合电极和第二结合电极自半导体发光序列一侧开始，依次包括过渡金属层、结合层，结合层包括第一部分和第二部分；
共晶层，介于倒装发光二极管与承载基板之间，为所述第一结合电极和第二结合电极的结合层的第一部分与锡膏中的锡共晶形成的共晶层，共晶层与过渡金属层之间还保留第二厚度的结合层，其中从半导体发光序列的堆叠方向上看，所述结合层的第二部分的厚度介于50nm～300nm之间。
所述的承载基板为封装基板或者电路板。
所述的回流焊工艺为至少一次，例如一次或者两次。
如图1所示，所述发光元件为一封装体，包括封装基板300和被安装在封装基板300上的倒装发光二极管。倒装发光二极管，至少包括电性相反的第一结合电极209和第二结合电极210。发光二极管的第一结合电极209和210分别通过锡膏304、305以及一次回流焊工艺连接到封装基板300的第一封装电极302和第二封装电极303。
封装基板300可以根据应用需求选择，例如柔性基板，例如柔性灯丝灯或灯带的柔性基板FPC，或者例如COB铝基基板或者FR4柔性基板。封装基板上包括第一封装电极302和第二封装电极303。
也可以进一步将封装体的封装基板通过焊膏以及回流焊工艺安装于线路基板上以获得应用品的发光元件，其中发光二极管的第一结合电极和第二结合电极需要经过两次的回流焊工艺处理。
焊膏302和303可选自锡-Ag、锡-Bi、锡-Zn、锡-Ag-Cu、锡-Cu和锡-Au合金(其都含有锡)的至少一种。
焊膏302和303将第一结合电极209和第二结合电极210分别连接到被设置在封装基板300的第一封装电极302和第二封装电极303。这里，焊膏302和303与第一结合电极209和第二结合电极210的顶面接触并且在压力下展开以分别覆盖第一结合电极209和第二结合电极210的侧表面。在回流焊工艺条件下，锡膏中的锡从第一结合电极209和第二结合电极210的顶面和侧表面扩散至第一结合电极和第二结合电极的内部形成一定厚度的共晶层。回流焊的温度可以根据具有不同熔点的不同锡膏进行常规选择，通常最低在150°，最高是270°。
所述发光元件也可以是应用品的发光元件，例如显示，包括电路板和倒装发光二极管，倒装发光二极管通过锡膏和一次回流焊工艺直接被安装在电路板上。所述的电路板可以是柔性电路板，例如PCB板，例如聚酰亚胺或聚酯薄膜为主要材料制成。
发光二极管可以具有常规尺寸或者是比常规尺寸小，例如小尺寸的发光二极管的半导体发光序列边长宽度优选地小于等于300微米，较佳地，介于100～300微米之间，或者100～200微米，或为100微米以下更小的尺寸，优选的至少40微米。其中100微米以下的发光二极管，可选择的，在光主要出光面上不具备透明性衬底。半导体发光序列的厚度介于1～8微米之间。小尺寸发光二极管具有上述水平面积及厚度，可容易地应用到要求小型和或薄型发光装置的各种电子装置。
如图2～3所示，所述倒装发光二极管具体包括：半导体发光序列200，位于半导体发光序列200的同一侧且电性相反的第一结合电极209和第二结合电极210。
第一结合电极209和第二结合电极210通常具有相同的多层金属层组成，具体的自半导体发光序列的一侧开始包括：过渡金属层、结合层。可通过溅射镀工艺形成第一结合电极209和第二结合电极210的多层金属层。
如图4所示，以第二结合电极210为例，具体的，所述的过渡金属层介于结合层与钝化层208之间，过渡金属层为一层或多层，例如过渡金属层为应力缓冲层210a、应力过渡层210b和反射层的至少一种功能层。
作为一个实施方式，过渡金属层为应力缓冲层210a和应力过渡层210b的组合， 其中应力缓冲层210a用于消除后续形成的结合层210c层的应力，防止结合层的应力过大，导致产生裂缝而容易漏电的情形，而使发光二极管芯片的质量降低。
应力缓冲层210a也可以作为反射层，以提供对发光层的辐射波段产生高的反射效果，例如80％以上的反射率。或者形成应力缓冲层210a之前，还包括形成一层额外的反射层，反射层对发光层的辐射波段产生高的反射效果，例如80％以上的反射率。
较佳的应力缓冲层210a为Ti、Al、Cu、Au中的一种或多种。
粘附于应力缓冲层210a和结合层210c的界面之间的应力过渡层210b，此应力过渡层210b能够作为结合层与应力缓冲层之间应力过渡作用，增加两层之间的结合力。应力过渡层210b，优选地为Ti或Cr。
结合层210c用于在第一结合电极209以及第二结合电极210通过回流焊工艺接合于封装基板或者应用基板上时，与锡膏中的锡形成共晶层。
较佳的，通过蒸镀工艺依次沉积过渡金属层以及结合层，相较于其它工艺，例如电镀，可使结合层更佳的包覆所述过渡金属层的顶面和侧壁，并且致密性、表面平整性以及金属层之间的界面结合力更高。更佳的，可采用多次光罩图形定义结合层的覆盖区域辅助多次镀膜工艺使结合层覆盖在过渡金属层的侧壁的厚度增加。进一步的，可通过多次镀膜工艺，使结合层覆盖在过渡金属层的侧壁的厚度够厚，使通过锡膏安装于封装基板或电路板之后，过渡金属层侧壁与形成的共晶层之间具有第二部分的结合层，由此提升侧壁位置的共晶能力，并且阻挡锡穿过结合层到过渡金属层内、甚至到达外延层的表面，导致芯片失效。
结合层210c包括第一部分210c1和第二部分210c2，第一部分210c1用于与锡膏中的锡形成共晶层，第二部分210c2介于第一部分和过渡金属层之间，结合层210c第二部分210c2相较于第一部分更靠近半导体发光序列，当结合电极通过回流焊工艺接合于承载基板上时，结合层第一部分与锡膏中的锡形成共晶层。结合层210c的第二部分210c2作为中间层介于共晶层与过渡金属层之间，维持原来结合层与过渡金属层之间的界面结合力，防止共晶层与过渡金属层之间直接接触，防止原来结合层与过渡金属层之间的结合力被破坏，从而提升发光二极管安装在 承载基板后的固晶能力，提升推力值；同时锡穿过结合层到达过渡金属层或者进一步到达外延表面，引起芯片失效。
从半导体发光序列的堆叠方向上看，共晶层与过渡金属层之间结合层210c第二部分210c2的定义厚度为T1，由于锡在共晶层中的扩散不均匀性，本发明的T1为共晶层与过渡金属层之间的结合层210c第二部分210c2最小厚度，并且T1大于0nm，较佳的，T1至少为50nm。较厚的第二部分210c2结合层，可维持原来结合层与过渡金属层之间界面作用力，增加焊盘的推力值；并且防止锡在结合层中局部位置扩散过快到达结合层原来结合层与过渡金属层之间界面进一步扩散至其它的金属层中或扩散至外延层表面，防止出现芯片失效的问题；另外结合层也可对过渡金属层的侧壁形成更厚厚度的包覆，改善侧壁位置的共晶和阻挡。从半导体发光序列的堆叠方向上看，结合层的第二部分介于共晶层与过渡金属层之间厚度T1至多300nm，过厚的第二部分210c2厚度对固晶能力以及推力值并没有改善作用，反而会导致结合电极的应力过大，容易产生裂缝。
其中结合层210c的第一部分210c1和第二部分210c2，可选的都为Ni层或者含Ni且Ni质量百分含量大于50％的合金层或共镀层，合金层或共镀层中或允许至少一其它金属层例如Ti层或Au层，插入Ni层中形成夹层的复合层，或者允许其它的金属层例如Ti层或Au层与Ni层一次堆叠或重复堆叠形成复合层，并且复合层中Ni的总厚度大于其它金属层的厚度，相邻Ni层之间的至少一其它金属层的厚度允许Sn穿过，并且复合层中与过渡金属层最临近的层是Ni。
如图5所示的推力值曲线图，反映的是将第一结合电极和第二结合电极具有不同厚度的结合层的发光二极管作为测试样品，通过锡膏以及两次回流焊工艺固定于承载基板上后，发光二极管从承载基板上发生脱落的推力值测试结果。其中结合层为Ni层，应力缓冲层为Al，应力过渡层为Ti。锡膏的成分为锡银铜，回流焊的温度为270℃。其中承载基板为柔性电路板FPC板。可以看出随着结合层的厚度增加，推力值有所提升。从半导体发光序列的堆叠方向上看，当结合层厚度为300nm，由于结合层的厚度与锡形成的共晶层厚度不够，导致固晶能力低，推力值低。当结合层厚度为500nm，结合层的厚度与锡形成的共晶层厚度增加，导致固晶能力提升，推力值提升，锡在结合层中扩散形成的共晶层的最大厚 度接近500nm，理论上，500nm的结合层能够与锡形成足够厚的共晶层，然而由于结合层内部的致密性或厚度等局部不均匀的现象，导致局部扩散仍然有过快的现象，锡会到达过渡金属层的界面，原来结合层与过渡金属层镀膜工艺过程中形成的界面结合力部分被破坏，推力值不够，并且锡会到达过渡金属层中或外延表面，导致芯片失效的风险产生。而结合层加厚至750nm时推力值进一步提升。结合图6提供的是结合层厚度为750nm的样品通过刷锡膏以及两次回流焊工艺固定于承载基板上后获得的第二结合电极的FIB-SEM图，并且结合EDX分析，锡在结合层中扩散形成的共晶层的平均厚度为500nm左右，介于共晶层与过渡金属层之间还包括其余厚度的结合层，其余厚度的结合层完全阻挡了锡到达过渡金属层的界面，包括阻挡结合层中局部扩散过快的锡到达过渡金属层的界面，同时维持了原来结合层与过渡金属层镀膜工艺过程中形成的界面结合力，因而相对于结合层为500nm的样品有进一步提升推力值。
如图3所示，本发明的倒装发光二极管，在半导体发光序列的第一导电性半导体层202一侧提供光主要输出面，或者在衬底100支撑发光半导体序列的情况下，衬底100透明且具有远离半导体发光序列的第二表面为发光二极管的光主要输出面。衬底100包括第一表面、第二表面以及侧壁，其中第一表面和第二表面相对，衬底100包括至少形成在第一表面的至少一部分区域的多个突起。例如，衬底100可以为经图案化的蓝宝石基板。衬底100的第一表面支撑半导体发光序列。
衬底100为生长基板，例如为蓝宝石衬底，蓝宝石衬底上通过MOCVD工艺在其表面上获得半导体发光序列，并且所述的生长基板支撑所述的半导体发光序列进行电极、钝化层的制作工艺以及半导体发光序列、衬底的切割工艺以获得单一的发光二极管；或者所述的衬底为键合基板，半导体发光序列的生长在生长基板上完成后，通过键合工艺转移至键合基板完成电极、钝化层的制作工艺以及半导体发光序列、衬底的切割工艺以获得单一的发光二极管。所述的半导体发光序列200在衬底100上可以是一个或者多个，多个半导体发光序列200之间以串联或者并联的方式进行电性连接。
半导体发光序列200包括第一导电类型半导体层202、有源层203和第二导电类 型半导体层204。这里，第一导电性可以是n型或p型。第二导电性与第一导电性相反，并且可以是n型或p型。具体的半导体发光序列可包括III-V型氮化物类半导体，例如可包括如(Al、Ga、In)N的氮化物类半导体，以提供紫外、蓝光或绿光波段的光辐射；或者包括(Al、Ga、In)P的磷化物半导体或者(Al、Ga、In)As的砷化物类半导体以提供红光或红外光的光辐射。
在半导体发光序列中，第二导电类型半导体层204的外表面位于距离光主要输出面或者衬底100最远的位置。从第二导电类型半导体层204的部分表面沿着厚度方向蚀刻半导体发光序列，使得第二导电类型半导体层204和有源层203以及仅第一导电类型半导体层202的部分厚度被移除以形成槽部或台阶区域。槽部或台阶区域使第一导电类型半导体层202部分被暴露。在发光二极管中，在第一导电类型半导体层202被暴露的槽部或台阶区域形成具有预定厚度和宽度的第一金属电极金属层206，并且在第二导电类型半导体层204的外表面的一个区域上形成具有预定厚度和预定面积透明电极层205和第二金属电极金属层207。第二导电类型半导体层204的表面可以覆盖一层整面的金属反射层，例如银。
绝缘层208覆盖半导体发光序列的顶面和侧壁，第一结合电极209和第二结合电极210覆盖在钝化层208的表面，并且通过钝化层208的第一开口以及第二开口分别与第一金属电极金属层206和第二金属电极金属层207接触。第一结合电极209和第二结合电极210之间具有一定的水平间距，以保证彼此之间不会发生接触而短路。所述的钝化层208可以是透明的，也可以是具有反射功能，例如包括绝缘层的DBR反射层。
综上所述，本实施例通过在过渡金属层与共晶层之间保留第二厚度的结合层可防止锡到达其它金属垫的界面，破坏结合层与过渡金属层的界面作用力，从而可增加固晶能力，提升发光二极管安装在封装基板后的推力值。本发明的方案适用于倒装发光二极管通过锡膏和一次回流焊工艺安装到封装基板获得的封装体发光元件或直接通过锡膏一次回流焊安装到线路基板上获得的应用品的发光元件，封装体发光元件可以进一步通过一次锡膏和回流焊安装在电路基板上获得应用品的发光元件，较佳的适用于对固晶能力要求膏的具有柔性安装基板的封装体或应用品，以及适用于小尺寸的倒装发光二极管，以改善共晶能力和推 力值。
实施例二
如图7所示，本实施例将结合电极的所述应力缓冲层210a设计为多层，较佳的为两层或三层，应力缓冲层210a的相邻两层之间可以增加其它金属层，例如应力缓冲层为Al的情况下，其它金属层为阻挡析出层210e，该阻挡析出层与应力缓冲层重复堆叠，可防止Al析出。例如TiAl重复堆叠层。较佳的，阻挡析出层与应力缓冲层的厚度比例是小于等于1∶3。较厚的阻挡析出层会降低应力缓冲层210a的应力缓冲效果，以及增加结合电极的电阻。
实施例三
作为实施例一的改进，如图8所示，所述的第一结合电极209和第二结合电极210还进一步包括底层，该底层为一层粘附层210f，如Ti或Cr，该粘附层210f位于过渡金属层与半导体发光序列之间，覆盖在钝化层208的表面并且直接接触钝化层208。该粘附层210f层的厚度较佳的是小于等于5nm，以尽量降低吸光的影响。
实施例四
高压倒装发光二极管是倒装发光二极管的一种，凭借良好的散热性能可应用于照明、背光、RGB显屏、柔性灯丝等大功率领域，高压倒装芯片也越发关注结合电极的在基板上的固晶能力，特别的是柔性基板上的固晶能力。
因此作为一个改进，实施例一～三的倒装发光二极管也可以是一种倒装的高压发光二极管，如图9～11所示，其包括一衬底400以及位于一衬底400上且彼此之间隔离的至少两颗子芯片10，即第1子芯片和第n子芯片，其中n≥2。
所述的衬底400为透明衬底，正面用于承载半导体发光序列，背面用于提供光主要输出面。每一子芯片10包括一半导体发光序列，半导体发光序列包括第一导电类型半导体层、发光层和第二导电类型半导体层。钝化层，为由绝缘材料制成的反射层409，覆盖在所述每一子芯片上以及沟槽内，反射层409具有第一结合电极通孔和第二结合电极通孔，第一结合电极通孔和第二结合电极通孔分别位于第1子芯片和第n子芯片上方；彼此电性相反的第一结合电极410和第二结合电极411，分别位于第1子芯片和第n子芯片上覆盖的反射层409表面上，并填 充第一结合电极通孔和第二结合电极通孔，第一结合电极409通过填充在第一结合电极通孔和第二结合电极通孔内的部分电连接至第1子芯片的第二导电类型半导体层以及第n子芯片的第一导电类型半导体层。
其中第一结合电极400和第二结合电极400包括过渡金属层、结合层。第一结合电极和第二结合电极与实施例一～三相同设计，可提升高压倒装发光二极管的固晶能力。
另外，本实施例对倒装高压发光二极管还提出如下改进：
其中，衬底400上且彼此之间隔离的n颗子芯片，n大于等于3，分别为第1子芯片、第n子芯片和至少一其它子芯片，n颗子芯片位于衬底上且彼此之间通过沟槽而隔离；反射层409还具有至少一第一其它开口和/或至少一第二其它开口，第一其它开口和/或至少一第二其它开口在至少一其它子芯片上方；该第一结合电极410延伸至至少一其它子芯片上覆盖的反射层409表面上，且填充反射层的第一其它开口，和或第二结合电极延伸至至少一其它子芯片上覆盖的反射层表面上，同时填充反射层的第二其它开口。通过在非第1和第n子芯片的其它子芯片上的反射层上设置多个其它开口，用于填充结合电极，可增加结合电极在其它子芯片上的几何面积，提升结合电极在其它子芯片上固晶能力，从而提升结合电极整体的固晶能力。
本实施例对倒装高压发光二极管的结构结合制程、附图进行详细说明，倒装发光二极管包括如下芯片制程：
首先在衬底400正面上获得半导体发光发光序列，半导体发光序列为多层，本实施例可称作外延结构，包括在衬底400的正面上依次层叠的第一导电型半导体层401、有源层402以及第二导电型半导体层403。
然后，对外延结构蚀刻以在外延结构上形成孔洞或者台阶，孔洞的底部或者台阶上露出部分N型层。然后采用蚀刻工艺制作出沟槽，沟槽的深度至衬底的表面，以露出衬底，沟槽使外延结构彼此隔离，从而形成多颗子芯片。由此每一颗子芯片具有一个外延结构，每一个外延结构提供一个发光区域。如本实施例中，为了便于描述，将图10中的三个外延结构从左至右依序定义为第1子芯片、第2子芯片和第3子芯片。
接着，在上述每一子芯片的第二导电型半导体层403上形成一透明电极层404。透明电极层404具有欧姆接触作用和横向电流扩展作用。
然后，在透明电极层404上、外延结构的侧面上以及沟槽底部覆盖一透明绝缘层(CBL)405，该透明绝缘层405可将三颗子芯片的外延结构以及三个子芯片之间沟槽结构的非电极设置区域进行绝缘保护。透明绝缘层405的材料可以为二氧化硅SiO 2、Si 3N 4等，其可以采用诸如等离子体增强化学的气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)等方法形成。从半导体发光序列的堆叠方向上看，透明绝缘层405较佳的厚度为100～1000nm之间。
接着，对透明绝缘层405覆盖在第1和第3子芯片上的部分进行局部蚀刻，蚀刻出第一金属电极通孔和第二金属电极通孔，第一金属电极通孔和第二金属电极通孔与后续在第1和第3子芯片的第一金属电极、第二金属电极的位置对应，其中第一金属电极通孔的底部为于第1子芯片透明电极层404表面，第二金属电极通孔的底部为第3子芯片第一导电型半导体层401的表面。同时对第1、第2和3子芯片上覆盖的透明绝缘层405蚀刻以形成多个互连电极通孔。透明绝缘层405的多个互连电极通孔分布在第1和第2子芯片的第一导电类型半导体层上、第2和第3子芯片的透明电极层上。
对在第1子芯片上覆盖的透明绝缘层405第一金属电极通孔内填充导电金属而制成第一金属电极406，在第3子芯片上覆盖的绝缘层的第二金属电极通孔内填充导电金属而制成第二金属电极407。第一金属电极406与透明导电层接触，第二金属电极407与第一导电类型半导体层接触。形成第一金属电极的同时可形成电性连接相邻两个子芯片的互连电极408，互连电极408形成在沟槽内的绝缘层上，并且具有两端，两端延伸至相邻两子芯片上，通过填充相邻两个子芯片的互连电极通孔，一端与其中一个子芯片的第一导电类型半导体层以及另外一端与另外一个子芯片的透明电极层的表面接触。
如图10所示，其中一个互连电极连接第1子芯片的第一导电型半导体层401以及第2子芯片的透明电极层，另外一个互连电极连接第2子芯片的第一导电型半导体层401以及第3子芯片的透明电极层。并且较佳的，第一金属电极406、第二金属电极407和互连电极408从通孔内延伸至透明绝缘层通孔周围的局部绝缘层上 表面临近区域。
第一金属电极406、第二金属电极407和互连电极408的材料相同。
在第一金属电极406、第二金属电极407和互连电极408制备完成后形成反射层409。反射层409覆盖在透明绝缘层、第一金属电极和第二金属电极上，包括覆盖在每一子芯片的上方、侧壁周围以及沟槽上。在衬底为透明衬底的情况下，反射层对每一子芯片的半导体发光序列辐射的光进行反射，反射光至衬底的背面，提升衬底的背光出光。较佳的，布拉格反射层的厚度为2～6微米。
在反射层409上对应第1子芯片的第一金属电极位置和第n子芯片的第二金属电极的位置通过蚀刻工艺分别形成第一结合电极通孔和第二结合电极通孔，并在第一结合电极通孔和第二结合电极通孔填充导电金属而制成第一结合电极410和第二结合电极411。在本实施例中，第一结合电极410与第1子芯片的第一金属电极406导电连接，即第一结合电极通孔的底部接触第一金属电极406；而第二结合电极411则与第n子芯片的第二金属电极407导电连接，即第二结合电极通孔的底部接触第二金属电极407。由于第一结合电极通孔和第二结合电极通孔会导致反射层的反射面积损失，因此第一结合电极通孔或第二结合电极通孔的面积通常占据第1子芯片或第n子芯片的面积不会超过20％。
第一结合电极410和第二结合电极411同时制作成延伸至除第1、第n子芯片的其它子芯片区域的上方。
在通过蚀刻工艺分别形成第一结合电极通孔和第二结合电极通孔的同时，通过该蚀刻工艺步骤可使反射层409覆盖在其它子芯片上方的部分也形成至少一第一其它开口和/或至少一第二其它开口。且第一结合电极410和第二结合电极411分别填充在对应的第一其它开口和第二其它开口内。第一其它开口与第二其它开口用于填充第一结合电极和第二结合电极，可增加两个结合电极的几何面积。
优选地，第一其它开口和第二其它开口为贯穿反射层的通孔，其中第一其它开口和第二其它开口的底部均位于覆盖在其它子芯片上的透明绝缘层405上。透明绝缘层405绝缘隔离第一其它开口内填充的第一结合电极与半导体发光叠层，同时绝缘隔离第二其它开口内填充的第二结合电极与半导体发光叠层。透明绝缘层可防止电流从第一其它开口和第二其它开口内填充的焊盘部分流入半导体发 光叠层，由此子芯片之间仅通过互连电极连接，避免出现短路问题。
如图9～10所示，第2子芯片上覆盖的反射层同时开设有第一其它开口和第二其它开口。
本发明提供的倒装高压发光二极管在非首尾的其它子芯片的反射层409形成至少一第一其它开口和至少一第二其它开口，第一结合电极410和第二结合电极411分别填充对应的第一其它开口和第二其它开口，可增加中间位置的子芯片的结合电极的面积，从而增加中间子芯片的固晶能力，以增加整体芯片的推力值；另外避免其它子芯片局部焊盘固晶不劳，发生局部剥离现象，防止装高压发光二极管整体可靠性降低；并且可使得每个子芯片在固晶后受力更接近和发光面积更接近和均匀。
在本实施例中，非首尾的每一子芯片上的第一其它开口或者第二其它开口的数量均为多个，并且每一其它子芯片上的这些第一其它开口之间和或者这些第二其它开口之间均匀间距的分布，开口为多个，开口内填充的结合电极也可一定程度的对光进行衍射或反射，可降低光损失，并且衍射或反射效果相对于相同水平面积的一个开口内填充的结合电极效果更佳，并且可使得结合电极在固晶后该其它子芯片表面受力均衡分布。较佳的，其中一其它子芯片上的第一其它开口和第二其它开口数量和或总面积与第一结合电极通孔的数量和或总面积相同。
优选地，所述其它子芯片的数量为偶数，反射层在一半的其它子芯片上方仅有第一其它开口，并且该一半的其它子芯片的每个子芯片上方的第一其它子芯片开口数量相等，反射层在其余一半的其它子芯片上上方仅有第二其它开口，并且该其余另一半的其它子芯片的每个子芯片上方的第二其它子芯片开口数量相等。
优选地，所述其它子芯片的数量为奇数，反射层其中一个其它子芯片上方同时具有第一其它开口和第二其它开口，其余的其它子芯片的数量为偶数，反射层在其余其它子芯片的一半数量的其它子芯片上方仅有第一其它开口，并且每个子芯片上方的第一其它子芯片开口数量相等；反射层在其余其它子芯片的另外一半数量的其它子芯片上方仅有第二其它开口，并且每个子芯片上方的第二其 它子芯片开口数量相等。
另外，由于用结合电极填充第一其它开口或者第二其它开口会造成反射层的面积降低，芯片整体反射率的降低，存在一定的光损失。因此，较佳的，每一个子芯片的第一其它开口或者第二其它开口的面积占该其它子芯片的半导体发光序列的水平投影面积的比例不超过20％，以使光损失明显降低，以使其兼具较佳整体推力值，以及较小的光损失。
较佳的，每一个子芯片的第一其它开口或者第二其它开口的面积占该其它子芯片的半导体发光序列的水平投影面积的比例为5～15％，在此比例上，该倒装高压发光二极管具有相对优异的整体推力值，以及更小的光损失。
每一第一其它开口和每一第二其它开口的形状均为柱状或锥形台状的孔，水平截面为圆形或多边形，且其水平孔径优选为2～40微米，更优的为10～30微米。
非首尾的每一子芯片上的第一其它开口和第二其它开口的数量优选为2～40个。
另外，作为一个实施方式，倒装高压发光二极管还可包括其它金属垫412，该其它金属垫位于其它子芯片上覆盖的透明绝缘层和反射层之间，其它金属垫与第一其它开口和第二其它开口位置对应，第一结合电极延伸至至少一其它子芯片的上方，填充透明绝缘层的第一其它开口并且在开口内底部与其它金属垫接触，和/或该第二结合电极延伸至至少一其它子芯片的上方，填充透明绝缘层的第二其它开口并且在开口内底部与其它金属垫接触。其它金属垫可以与第一金属电极、第二金属电极和互连电极通过同一步骤形成。
图12反映的是现有的芯片和本实施例的芯片的推力相对值数据，其中现有的芯片的结构如图13～14所示，现有的芯片和本实施例的芯片分别被命名为1号芯片和2号芯片，其中1号芯片为采用现有技术方案制成的倒装高压发光二极管，2号芯片为采用本实施例的方案制成的倒装高压发光二极管，分别包括3个子芯片，3个子芯片分别为第1子芯片、第2子芯片、第3子芯片，其中第1子芯片和第2子芯片上覆盖有第一结合电极，第2子芯片和第3子芯片覆盖有第二结合电极。与1号芯片的唯一差别在于，2号芯片的第2子芯片上覆盖的绝缘层上具有2个第一其它开口以及有2个第二其它开口。上述两个倒装高压发光二极管以相同的回流焊 工艺焊接在基板上，测试各倒装高压发光二极管的推力值，所测得的推力相对值数据参考图12，从图12中可以看出，以1号芯片的推力值作为基准，2号芯片的推力值是1号芯片的推力值的约1.16倍。可见，在中间的子芯片上增加第一其它开口和第二其它开口，并且第一结合电极410和第二结合电极411填充对应的第一其它开口和第二其它开口后，可以明显增加整体芯片的推力值。
作为一个替代性的实施方式，所述的其它金属垫也可以具有反射功能，为金属反射层，可提升光效，或者作为另外一种替代方式，第一结合电极和第二结合电极的底层具有光反射性，底层形成对该倒装高压发光二极管出射的光线具有反射能力的金属反射层，金属反射层例如镜面铝层、镜片银层等。
作为一个替代性的实施方式，所述反射层的第一其它开口和第二其开口也可以是非通孔，开口的底部位于反射层内，也能够实现增加结合电极在其它子芯片上的几何面积，提升固晶能力。
本实施例通过对倒装高压发光二极管改进，在非首尾的其它子芯片上的反射层上设置多个其它开口，用于填充结合电极，增加结合电极在其它子芯片上的几何面积，增加整体芯片的推力值；也可避免结合电极在其它的子芯片上的固晶能力差，防止局部固晶不劳发生结合电极在局部发生剥离，避免芯片在工作条件下可靠性降低；另外当每个子芯片的半导体发光叠层提供的发光面积接近或相等时，反射层在首尾两芯片上的部分设置焊盘通孔，首尾芯片的反射面积已经有所减小，为提升固晶面积，在其它的子芯片上的部分同时设置多个其它开口，而不在首尾子芯片上增加其它开口，可每一个子芯片的反射层的反射面积的差异减小，并且尽量实现每个子芯片均匀出光。
本发明的高压倒装芯片可以安装于照明、背光、RGB显屏、柔性灯丝等领域的封装品或应用品，特别是柔性基板作为安装基板的封装体或者应用体。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的改动与润饰，故本发明的保护范围当视所附权利要求界定范围为准。

Claims (35)

  1. 一种发光元件，包括：倒装发光二极管和承载基板，倒装发光二极管通过锡膏固定于承载基板上；所述的倒装发光二极管包括半导体发光序列、位于半导体发光序列的同一侧且电性相反的第一结合电极和第二结合电极；其中第一结合电极和第二结合电极自半导体发光序列一侧开始，依次包括过渡金属层、结合层，从半导体发光序列的堆叠方向上看，结合层包括第一部分和第二部分；共晶层，介于倒装发光二极管与承载基板之间，为所述第一结合电极和第二结合电极的结合层的第一部分与锡膏中的锡共晶形成，结合层第二部分介于共晶层与过渡金属层之间。
  2. 根据权利要求1所述的一种发光元件，其特征在于：其中从半导体发光序列的堆叠方向上看，所述结合层第二部分介于共晶层与过渡金属层之间的厚度至少50nm，至多300nm。
  3. 根据权利要求1所述的一种发光元件，其特征在于：所述的过渡金属层包括应力缓冲层、反射层或应力过渡层的至少一种。
  4. 根据权利要求3所述的一种发光元件，其特征在于：所述的过渡金属层包括应力缓冲层，所述的应力缓冲层为Ti、Al、Cu、Au中的一种或多种。
  5. 根据权利要求1所述的一种发光元件，其特征在于：所述的结合层的第二部分为Ni层或Ni层中插入其它的金属层或主要含Ni的合金层或共镀层。
  6. 根据权利要求5所述的一种发光元件，其特征在于：其中共晶层和结合层的第二部分覆盖在过渡金属层的顶面和侧壁。
  7. 根据权利要求1所述的一种发光元件，其特征在于：所述的过渡金属层包括应力缓冲层，应力缓冲层与结合层之间还包括应力过渡层。
  8. 根据权利要求7所述的一种发光元件，其特征在于：所述的应力过渡层为Ti或Cr。
  9. 根据权利要求1所述的一种发光元件，其特征在于：所述的过渡金属层包括应力缓冲层，且应力缓冲层为多层，相邻应力缓冲层之间包括一层阻挡析出层，从半导体发光序列的堆叠方向上看，阻挡析出层和应力缓冲层以小于或者等于1∶3的厚度重复堆叠。
  10. 根据权利要求9所述的一种发光元件，其特征在于：所述的阻挡析出层为Ti或Cr。
  11. 根据权利要求1所述的一种发光元件，其特征在于：所述的承载基板为封装基板或者电路板，所述的倒装发光二极管通过一次回流焊工艺安装在承载基板上。
  12. 根据权利要求1所述的一种发光元件，其特征在于：所述的承载基板为电路板，倒装发光二极管通过两次回流焊工艺直接或间接安装在电路板上。
  13. 根据权利要求11或12所述的一种发光元件，其特征在于：所述的承载基板为柔性基板。
  14. 根据权利要求1所述的一种发光元件，其特征在于：倒装发光二极管为倒装高压二极管，包括n颗子芯片和一个衬底，n颗子芯片位于衬底上且彼此之间通过沟槽而相互独立，n大于等于3，分别为第1子芯片、第n子芯片和至少一其它子芯片，每一子芯片包括一半导体发光序列，半导体发光序列包括第一导电类型半导体层、发光层和第二导电类型半导体层。
  15. 根据权利要求14所述的一种发光元件，其特征在于：还包括绝缘性反射层；所述反射层覆盖在所述每一子芯片的半导体发光序列上以及沟槽内，反射层具有第一结合电极通孔和第二结合电极通孔，第一结合电极通孔和第二结合电极通孔分别位于第1子芯片和第n子芯片上；第一结合电极通过第一结合电极通孔电连接至第1子芯片的第二导电类型半导体层，第二结合电极通过第二结合电极通孔电连接至第n子芯片的第一导电类型半导体层。
  16. 根据权利要求15所述的一种发光元件，其特征在于：反射层上具 有位于至少一其它子芯片上的至少一第一其它开口和/或至少一第二其它开口；该第一结合电极位于所述第1子芯片的上方并延伸至至少一其它子芯片上方，且填充反射层的第一其它开口，和/或第二结合电极位于所述第2子芯片的上方延伸至至少一其它子芯片上方，同时填充反射层的第二其它开口。
  17. 根据权利要求16所述的元件，其特征在于：所述第一其它开口和/或所述第二其它开口均为贯穿反射层的通孔。
  18. 根据权利要求16所述的发光元件，其特征在于：还包括透明绝缘层，所述透明绝缘层覆盖在所述每一子芯片的半导体发光序列上以及沟槽内，并且具有开口；彼此电性相反的第一电极和第二电极，填充透明绝缘层的开口并分别连接至第1和第n子芯片的第二导电类型半导体层和第一导电类型半导体层；所述反射层覆盖在透明绝缘层、第一电极和第二电极上；彼此电性相反的第一结合电极和第二结合电极，位于第1子芯片和第n子芯片上覆盖的反射层表面上，填充在第一结合电极通孔和第二结合电极通孔内以电连接至第一电极和第二电极。
  19. 根据权利要求16所述的发光元件，其特征在于：该第一结合电极延伸至至少一其它子芯片上覆盖的反射层表面上，且填充至反射层的第一其它开口的底部，和/或第二结合电极延伸至至少一其它子芯片上覆盖的反射层表面上，同时填充至第二其它开口的底部，所述透明绝缘层介于第一其它开口的底部和第二其它开口的底部与其它子芯片的半导体发光序列之间。
  20. 根据权利要求16所述的发光元件，其特征在于：所述其它子芯片的每一个都具有第一其它开口和/或第二其它开口，第一结合电极同时延伸至至少一其它子芯片的上方，填充反射层的第一其它开口，和/或该第二结合电极同时延伸至至少一其它子芯片的上方，且填充反射层的第二其它开口。
  21. 根据权利要求16所述的发光元件，其特征在于：所述其它子芯片 的每一个都具有多个第一其它开口和/或第二其它开口，多个第一其它开口之间和/或第二其它开口之间具有均匀间距。
  22. 根据权利要求16所述的发光元件，其特征在于：其它子芯片的数量为偶数，一半的其它子芯片上的反射层仅有第一其它开口，其余一半的其它子芯片上的反射层仅有第二其它开口。
  23. 根据权利要求16所述的发光元件，其特征在于：其它子芯片的数量为奇数，其中一其它子芯片上同时具有第一其它开口和第二其它开口。
  24. 根据权利要求16所述的发光元件，其特征在于：所述第一其它开口和/或第二其它开口均为柱状或锥形台状的孔，且其孔径为2～40微米。
  25. 根据权利要求16所述的发光元件，其特征在于：所述第一其它开口和/或第二其它开口的孔径为10～30微米。
  26. 根据权利要求16所述的发光元件，其特征在于：每一其它子芯片的第一其它开口和第二其它开口的数量总和为2～40个。
  27. 根据权利要求16所述的发光元件，其特征在于：每一子芯片的半导体发光序列堆叠层包括顶面和侧壁，顶面与透明绝缘层之间还具有透明导电层。
  28. 根据权利要求16所述的发光元件，其特征在于：所述反射层为布拉格反射层。
  29. 根据权利要求16所述的发光元件，其特征在于：从半导体发光序列的堆叠方向上看，所述反射层的厚度为2～6微米。
  30. 根据权利要求19所述的发光元件，其特征在于：还包括互连电极，位于沟槽上的透明绝缘层上，并跨过沟槽延伸至相邻两子芯片上，填充透明绝缘层的开口电性连接相邻两子芯片，互连电极同时位于透明绝缘层与反射层之间。
  31. 根据权利要求19所述的发光元件，其特征在于：还包括其它金属垫，其位于其它子芯片上覆盖的透明绝缘层和反射层之间，其它 金属垫与第一其它开口和第二其它开口位置对应，第一结合电极延伸至至少一其它子芯片的上方，所述的其它金属垫的位置与第一开口和第二开口位置对应，与互连电极间隔一定距离。
  32. 根据权利要求31所述的发光元件，其特征在于：所述的其它金属垫具有反射功能。
  33. 根据权利要求19所述的发光元件，其特征在于：所述第一结合电极和第二结合电极具有底层，底层为光反射层。
  34. 根据权利要求19所述的发光元件，其特征在于：每一个其它子芯片的第一其它开口和第二其它开口的总面积占该子芯片总面积的比例不超过20％。
  35. 根据权利要求19所述的发光元件，其特征在于：所述子芯片上的第一其它开口和第二其它开口的总面积占该子芯片总面积的比例为5～15％。
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