WO2021114505A1 - 一种阵列基板及其制备方法、显示面板 - Google Patents

一种阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021114505A1
WO2021114505A1 PCT/CN2020/079617 CN2020079617W WO2021114505A1 WO 2021114505 A1 WO2021114505 A1 WO 2021114505A1 CN 2020079617 W CN2020079617 W CN 2020079617W WO 2021114505 A1 WO2021114505 A1 WO 2021114505A1
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Prior art keywords
insulating layer
groove
substrate
interlayer insulating
layer
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English (en)
French (fr)
Inventor
黄茜
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/966,128 priority Critical patent/US12107093B2/en
Publication of WO2021114505A1 publication Critical patent/WO2021114505A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display panel.
  • Organic light-emitting display device (full English name: Organic Light-Emitting Diode, OLED for short) is also known as organic electro-laser display device and organic light-emitting semiconductor.
  • the working principle of OLED is: when the power is supplied to the appropriate voltage, the positive electrode holes and the negative electrode charges will be combined in the light-emitting layer, and under the action of the Coulomb force, they will recombine with a certain probability to form excitons in the excited state (electron-hole Yes), and this excited state is unstable in a normal environment.
  • the excitons of the excited state recombine and transfer energy to the luminescent material, making it transition from the ground state energy level to the excited state, and the excited state energy is through the radiative relaxation process It produces photons, releases light energy, and produces light. According to its different formulas, it produces three primary colors of red, green and blue RGB, which constitute the basic colors.
  • OLED has the advantages of low voltage demand, high power saving efficiency, fast response, light weight, thin thickness, simple structure, low cost, wide viewing angle, almost infinitely high contrast, low power consumption, and extremely high response speed. It has become today's One of the most important display technologies.
  • the sidewall of the source-drain layer is prone to a risk of climbing and cracking when the degree exceeds 80 degrees. Therefore, it is necessary to find a new type of array substrate to solve the above-mentioned problems.
  • An object of the present invention is to provide an array substrate, a preparation method thereof, and a display panel, which can avoid the climbing and breaking phenomenon of the sidewalls of the source and drain layers existing in the current array substrate.
  • an embodiment of the present invention provides an array substrate, which includes: a substrate, an active layer, a gate insulating layer, an interlayer insulating layer, and a source and drain layer.
  • the active layer is disposed on the substrate; the gate insulating layer is disposed on the active layer; the interlayer insulating layer is disposed on the gate insulating layer; the source and drain layer It is arranged on the interlayer insulating layer, and the source and drain layers are connected downwardly to the active layer through via holes.
  • the via hole includes a first groove and a second groove that communicate with each other; the first groove is formed by partially recessing the surface of the interlayer insulating layer away from the substrate; the second groove The first groove is partially recessed down near the bottom surface of the substrate until the active layer is formed away from the surface of the substrate; wherein the junction of the first groove and the second groove is formed There is a step.
  • the gate insulating layer includes: a first gate insulating layer and a second gate insulating layer, wherein the first gate insulating layer is disposed on the active layer; the second gate The insulating layer is disposed on the first gate insulating layer.
  • the interlayer insulating layer includes: a first interlayer insulating layer and a second interlayer insulating layer, wherein the first interlayer insulating layer is disposed on the second gate insulating layer; the second interlayer insulating layer The insulating layer is disposed on the first interlayer insulating layer.
  • the first groove is formed by a partial depression of the surface of the second interlayer insulating layer away from the substrate.
  • the bottom surface of the first groove is disposed between the second interlayer insulating layer and the first gate insulating layer.
  • the bottom surface of the first groove is flush with the surface of the second gate insulating layer away from the substrate.
  • Another embodiment of the present invention also provides a method for preparing the array substrate of the present invention, which includes: step S1, providing a substrate, and preparing the active layer on the substrate; step S2, Preparing the gate insulating layer on the active layer; step S3, preparing the interlayer insulating layer on the gate insulating layer; step S4, preparing the source and drain electrodes on the interlayer insulating layer
  • step S1 providing a substrate, and preparing the active layer on the substrate
  • step S2 Preparing the gate insulating layer on the active layer
  • step S4 preparing the source and drain electrodes on the interlayer insulating layer
  • the source and drain layers are connected downwardly to the active layer through via holes.
  • the via in step S4 includes a first groove and a second groove that are connected; the first groove is formed by partially recessing the surface of the interlayer insulating layer away from the substrate, and The second groove is formed by partially recessing the first groove near the bottom surface of the substrate until the active layer is away from the surface of the substrate; wherein the first groove and the second groove A step is formed at the junction.
  • the step S2 includes: preparing the first gate insulating layer on the active layer, and preparing the second gate insulating layer on the first gate insulating layer; and the step S3 includes: preparing the first interlayer insulating layer on the second gate insulating layer, and preparing the second interlayer insulating layer on the first interlayer insulating layer; the process in step S4
  • the hole includes a first groove and a second groove that communicate with each other.
  • the first groove is formed by a partial depression of the surface of the second interlayer insulating layer away from the substrate, and the second groove is formed by the The first groove is partially recessed near the bottom surface of the substrate until the active layer is formed away from the surface of the substrate; wherein a step is formed at the junction of the first groove and the second groove .
  • the via hole in step S4 includes a first groove and a second groove that are connected; the first groove is away from the surface of the substrate from the second interlayer insulating layer through the first set of holes Etching is performed downward; the second groove is formed by etching the first groove close to the bottom surface of the substrate through a second set of holes until the active layer is away from the surface of the substrate; wherein The outer size of the second set of holes is smaller than the outer size of the first set of holes.
  • the via hole in the step S4 includes a first groove and a second groove that are connected; the first groove is away from the surface of the substrate from the second interlayer insulating layer through the second set of holes Etch downwards, and then etch the second interlayer insulation around the second set of holes through the first set of holes; the second groove forms the second set of holes through the first set of holes.
  • the inside of the hole is formed by etching until the surface of the active layer away from the substrate; wherein the outer size of the second set of holes is smaller than the outer size of the first set of holes.
  • the via hole in step S4 includes a first groove and a second groove that are connected; wherein the first groove is a part of the surface of the second interlayer insulating layer away from the substrate. Etch down, and then use oxygen to process the holes of the photoresist to form; the second groove is formed by treating the first groove close to the bottom surface of the substrate until the active layer is far away from the surface of the substrate Partially etched to form a second groove.
  • Another embodiment of the present invention also provides a display panel, which includes the array substrate related to the present invention.
  • the present invention relates to an array substrate, a preparation method thereof, and a display panel.
  • the surface of the interlayer insulating layer of the related array substrate away from the substrate is partially recessed downward to form a first groove.
  • a groove close to the bottom surface of the substrate is partially recessed downward until the surface of the active layer away from the substrate forms a second groove, and the first groove and the second groove communicate with each other to form a via;
  • a climbing height of the source-drain layer connected to the active layer through the via hole in the later stage is changed, so as to avoid the risk of climbing and fracture of the source-drain layer.
  • FIG. 1 is a schematic diagram of the structure of the array substrate of the present invention.
  • FIG. 2 is a second structural diagram of the array substrate of the present invention.
  • Fig. 3 is a schematic diagram of the preparation structure of Example 3 of the present invention.
  • Figure 4 is a schematic diagram of the preparation structure of Example 4 of the present invention.
  • the first gate layer 8. The second gate layer
  • the component can be directly placed on the other component; there may also be an intermediate component on which the component is placed , And the intermediate component is placed on another component.
  • a component is described as “installed to” or “connected to” another component, both can be understood as directly “installed” or “connected”, or a component is “installed to” or “connected to” through an intermediate component Another component.
  • an array substrate 100 includes: a substrate 1, an active layer 2, a gate insulating layer 3, an interlayer insulating layer 4, and a source and drain layer 5.
  • the active layer 2 is disposed on the substrate 1.
  • the gate insulating layer 3 is disposed on the active layer 2.
  • the gate insulating layer 3 includes a first gate insulating layer 31 and a second gate insulating layer 32, wherein the first gate insulating layer 31 is disposed on the active layer 2;
  • the second gate insulating layer 32 is disposed on the first gate insulating layer 31.
  • the interlayer insulating layer 4 is disposed on the gate insulating layer 3.
  • the interlayer insulating layer 4 includes a first interlayer insulating layer 41 and a second interlayer insulating layer 42, wherein the first interlayer insulating layer 41 is disposed on the second gate insulating layer 32 ;
  • the second interlayer insulating layer 42 is disposed on the first interlayer insulating layer 41.
  • the array substrate 100 further includes a source and drain layer 5 disposed on the second interlayer insulating layer 42.
  • the source and drain layers 5 are connected to the active layer 2 through vias 6.
  • the via hole 6 includes a first groove 61 and a second groove 62 that are communicated with each other.
  • the first groove 61 is partially recessed downward from the surface of the second interlayer insulating layer 42 away from the substrate 1; the second groove 62 is formed by the first groove 61 close to the substrate The bottom surface of 1 is partially recessed downward until the active layer 2 is formed away from the surface of the substrate 1.
  • a step 63 is formed at the junction of the first groove 61 and the second groove 62.
  • the bottom surface of the first groove 61 is disposed between the second interlayer insulating layer 42 and the first gate insulating layer 31.
  • the bottom surface of the first groove 61 is preferably flush with the surface of the second gate insulating layer 32 away from the substrate 1.
  • the via hole 6 described in this embodiment includes a first groove 61 and a second groove 62. In actual operation, it may also include a third groove, a fourth groove, and the like.
  • the via hole 6 is mainly configured as the first groove 61 and the second groove 62, thereby changing the time of connecting to the source and drain layer 5 on the active layer 2 through the pass 6 in the later stage. The climbing height can avoid the risk of climbing and breaking of the source drain layer 5.
  • the array substrate 100 further includes a first gate layer 7 and a second gate layer 8, wherein the first gate layer 7 is disposed on the first gate insulating layer 31 and the Between the second gate insulating layer 32; the second gate layer 8 is disposed between the second gate insulating layer 32 and the first interlayer insulating layer 41.
  • the first gate insulating layer 31 mainly prevents contact between the first gate layer 7 and the active layer 2 and avoids short circuits.
  • the second gate insulating layer 32 mainly prevents contact between the first gate layer 7 and the second gate layer 8 and avoids short-circuiting.
  • the present invention also provides a method for preparing the array substrate 100 involved in the present invention, which includes: step S1, a substrate 1 is provided, and the active layer 2 is prepared on the substrate 1.
  • step S2 prepare the gate insulating layer 3 on the active layer 2;
  • step S3 prepare the interlayer insulating layer 4 on the gate insulating layer 3;
  • step S4 prepare the interlayer
  • the source-drain layer 5 is prepared on the insulating layer 4, and the source-drain layer 5 is downwardly connected to the active layer 2 through the via 6.
  • the via 6 in the step S4 includes a first groove 61 and a second groove 62 that are connected; the first groove 61 is partially directed from the surface of the interlayer insulating layer 4 away from the substrate 1
  • the second groove 62 is partially recessed downward by the first groove 61 close to the bottom surface of the substrate 1 until the active layer 2 is formed away from the surface of the substrate 1;
  • a step 63 is formed at the junction of a groove 61 and the second groove 62.
  • the step S2 includes: preparing the first gate insulating layer 31 on the active layer 2, and preparing the second gate insulating layer 32 on the first gate insulating layer 31
  • the step S3 includes: preparing the first interlayer insulating layer 41 on the second gate insulating layer 32, and preparing the second interlayer insulating layer 42 on the first interlayer insulating layer 41
  • the via 6 in the step S4 includes a first groove 61 and a second groove 62 that are connected.
  • the first groove 61 is partially recessed downward from the surface of the second interlayer insulating layer 42 away from the substrate 1, and the second groove 62 is formed by the first groove 61 close to the substrate 1
  • the bottom surface of is partially recessed downward until the active layer 2 is formed away from the surface of the substrate 1; wherein a step 63 is formed at the junction of the first groove 61 and the second groove 62.
  • the via hole 6 in the step S4 includes a first groove 61 and a second groove 62 that are connected.
  • the first groove 61 is formed by etching down the surface of the second interlayer insulating layer 42 away from the substrate 1 through the first set of holes; as shown in FIG. 1, the first groove 61 is formed through the first set of holes.
  • the two sets of holes etch the first groove 61 close to the bottom surface of the substrate 1 until the surface of the active layer 2 away from the substrate 1 to form the second groove 62.
  • the outer size of the second set of holes is smaller than the outer size of the first set of holes.
  • the via hole 6 is mainly set as the first groove 61 and the second groove 62, thereby changing the first step of the source drain layer 5 connected to the active layer 2 through the via 6 in the later stage.
  • the height of the slope thereby avoiding the risk of climbing and breaking of the source drain layer 5.
  • the via hole 6 in the step S4 includes a first groove 61 and a second groove 62 that are connected.
  • the second interlayer insulating layer 42 is etched downward from the surface of the substrate 1 away from the substrate 1 through the second set of holes; as shown in FIG. 1, the second set of holes is used to etch the second
  • the second interlayer insulation 42 on the periphery of the sleeve hole is etched to form the first groove 61; at the same time, the second sleeve hole is inserted into the second sleeve hole through the first sleeve hole until the active layer 2 is far away from the substrate 1
  • the surface of the substrate is etched to form the second groove 62.
  • the outer size of the second set of holes is smaller than the outer size of the first set of holes. Therefore, the via hole 6 is mainly set as the first groove 61 and the second groove 62, thereby changing the first step of the source drain layer 5 connected to the active layer 2 through the via 6 in the later stage. The height of the slope, thereby avoiding the risk of climbing and breaking of the source drain layer 5.
  • the surface of the second interlayer insulating layer 42 away from the substrate 1 is partially etched downward, and then the holes of the photoresist are treated with oxygen to form the first groove 61;
  • the first groove 61 partially etches the surface of the first groove 61 close to the bottom surface of the substrate 1 until the active layer 2 is far away from the substrate 1 to form the second groove 62.
  • a climbing height of the source-drain layer 5 connected to the active layer 2 through the via 6 is changed in the later stage, so as to avoid the risk of the source-drain layer 5 climbing and breaking.
  • the preparation step diagram of the first groove 61 in this embodiment is similar to FIG. 4; the preparation step diagram of the second groove 62 in this embodiment is similar to FIG. 1, which will not be repeated here.
  • the present invention also provides a display panel, which includes the array substrate 100 involved in the present invention.

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

本发明涉及一种阵列基板及其制备方法、显示面板，本发明将所涉及的阵列基板的所述层间绝缘层远离所述基板的表面局部向下凹陷形成第一凹槽，将所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成第二凹槽，所述第一凹槽和所述第二凹槽相连通形成过孔。

Description

一种阵列基板及其制备方法、显示面板
本申请要求于2019年12月10日提交中国专利局、申请号为201911258423.2、发明名称为“一种阵列基板及其制备方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板及其制备方法、显示面板。
 背景技术
有机发光显示装置(英文全称：Organic Light-Emitting Diode, 简称OLED)又称为有机电激光显示装置、有机发光半导体。OLED的工作原理是：当电力供应至适当电压时，正极空穴与阴极电荷就会在发光层中结合，在库伦力的作用下以一定几率复合形成处于激发态的激子（电子-空穴对），而此激发态在通常的环境中是不稳定的，激发态的激子复合并将能量传递给发光材料，使其从基态能级跃迁为激发态，激发态能量通过辐射驰豫过程产生光子，释放出光能，产生光亮，依其配方不同产生红、绿和蓝RGB三基色，构成基本色彩。
OLED具有电压需求低、省电效率高、反应快、重量轻、厚度薄，构造简单，成本低、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点，已经成为当今最重要的显示技术之一。
 技术问题
目前，在源漏极层与有源层连接过孔位置，通常超过80度便容易出现源漏极层侧壁爬坡断裂风险。因此需要寻求一种新型的阵列基板已解决上述问题。
 技术解决方案
本发明的一个目的是提供一种阵列基板及其制备方法、显示面板，其能够避免目前的阵列基板中存在的源漏极层侧壁爬坡断裂现象。
为了解决上述问题，本发明的一个实施方式提供了一种阵列基板，其中包括：基板、有源层、栅极绝缘层、层间绝缘层、以及源漏极层。其中所述有源层设置于所述基板上；所述栅极绝缘层设置于所述有源层上；所述层间绝缘层设置于所述栅极绝缘层上；所述源漏极层设置于所述层间绝缘层上，所述源漏极层通过过孔向下连接至所述有源层上。其中所述过孔包括相连通的第一凹槽和第二凹槽；所述第一凹槽由所述层间绝缘层远离所述基板的表面局部向下凹陷形成；所述第二凹槽由所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成；其中所述第一凹槽和所述第二凹槽的相接处形成有一台阶。
进一步地，其中所述栅极绝缘层包括：第一栅极绝缘层和第二栅极绝缘层，其中所述第一栅极绝缘层设置于所述有源层上；所述第二栅极绝缘层设置于所述第一栅极绝缘层上。其中所述层间绝缘层包括：第一层间绝缘层和第二层间绝缘层，其中所述第一层间绝缘层设置于所述第二栅极绝缘层上；所述第二层间绝缘层设置于所述第一层间绝缘层上。其中所述第一凹槽由所述第二层间绝缘层远离所述基板的表面局部向下凹陷形成。
进一步地，其中所述第一凹槽的底面设置于所述第二层间绝缘层与所述第一栅极绝缘层之间。
进一步地，其中所述第一凹槽的底面与所述第二栅极绝缘层远离所述基板的表面平齐。
本发明的另一个实施方式还提供了一种制备本发明所涉及的阵列基板的制备方法，其中包括：步骤S1，提供一基板，在所述基板上制备所述有源层；步骤S2，在所述有源层上制备所述栅极绝缘层；步骤S3，在所述栅极绝缘层上制备所述层间绝缘层；步骤S4，在所述层间绝缘层上制备所述源漏极层，所述源漏极层通过过孔向下连接于所述有源层上。其中所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；所述第一凹槽由所述层间绝缘层远离所述基板的表面局部向下凹陷形成，所述第二凹槽由所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成；其中所述第一凹槽和所述第二凹槽的相接处形成有一台阶。
进一步地，其中所述步骤S2包括：在所述有源层上制备所述第一栅极绝缘层，在所述第一栅极绝缘层上制备所述第二栅极绝缘层；所述步骤S3包括：在所述第二栅极绝缘层上制备所述第一层间绝缘层，在所述第一层间绝缘层上制备所述第二层间绝缘层；所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽，所述第一凹槽由所述第二层间绝缘层远离所述基板的表面局部向下凹陷形成，所述第二凹槽由所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成；其中所述第一凹槽和所述第二凹槽的相接处形成有一台阶。
进一步地，其中所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；所述第一凹槽通过第一套孔由第二层间绝缘层远离所述基板的表面向下进行刻蚀形成；所述第二凹槽通过第二套孔对所述第一凹槽靠近所述基板的底面直至所述有源层远离所述基板的表面进行刻蚀形成；其中所述第二套孔的外围尺寸小于所述第一套孔的外围尺寸。
进一步地，其中所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；所述第一凹槽通过第二套孔由第二层间绝缘层远离所述基板的表面向下进行刻蚀，然后通过第一套孔对所述第二套孔外围的所述第二层间绝缘进行刻蚀形成；所述第二凹槽通过第一套孔对所述第二套孔内直至所述有源层远离所述基板的表面进行刻蚀形成；其中所述第二套孔的外围尺寸小于所述第一套孔的外围尺寸。
进一步地，其中所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；其中所述第一凹槽是对所述第二层间绝缘层远离所述基板的表面局部向下进行刻蚀，然后用氧气对光阻的孔洞处理形成；所述第二凹槽是对所述第一凹槽靠近所述基板的底面直至所述有源层远离所述基板的表面进行局部刻蚀形成第二凹槽。
本发明的另一个实施方式还提供了一种显示面板，其中包括本发明所涉及的阵列基板。
 有益效果
本发明涉及一种阵列基板及其制备方法、显示面板，本发明将所涉及的阵列基板的所述层间绝缘层远离所述基板的表面局部向下凹陷形成第一凹槽，将所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成第二凹槽，所述第一凹槽和所述第二凹槽相连通形成过孔；由此改变后期通过所述过孔连接于所述有源层上的源漏极层的一次爬坡高度，从而避免源漏极层爬坡断裂的风险。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明阵列基板的结构示意图。
图2是本发明阵列基板的结构示意图二。
图3是本发明实施例3的制备结构示意图。
图4是本发明实施例4的制备结构示意图。
图中部件标识如下：
100、阵列基板
1、基板                        2、有源层
3、栅极绝缘层                  4、层间绝缘层
31、第一栅极绝缘层             32、第二栅极绝缘层
41、第一层间绝缘层             42、第二层间绝缘层
5、源漏极层                    6、过孔
7、第一栅极层                  8、第二栅极层
61、第一凹槽                   62、第二凹槽
63、台阶。
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的 ，本发明并没有限定每个组件的尺寸和厚度。
当某些组件，被描述为“在”另一组件“上”时，所述组件可以直接置于所述另一组件上；也可以存在一中间组件，所述组件置于所述中间组件上，且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时，二者可以理解为直接“安装”或“连接”，或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。
实施例1
如图1所示，一种阵列基板100，其中包括：基板1、有源层2、栅极绝缘层3、层间绝缘层4、以及源漏极层5。
如图1所示，其中所述有源层2设置于所述基板1上。
如图1所示，其中所述栅极绝缘层3设置于所述有源层2上。具体地，其中所述栅极绝缘层3包括第一栅极绝缘层31和第二栅极绝缘层32，其中所述第一栅极绝缘层31设置于所述有源层2上；所述第二栅极绝缘层32设置于所述第一栅极绝缘层31上。
如图1所示，其中所述层间绝缘层4设置于所述栅极绝缘层3上。具体地，其中所述层间绝缘层4包括第一层间绝缘层41和第二层间绝缘层42，其中所述第一层间绝缘层41设置于所述第二栅极绝缘层32上；所述第二层间绝缘层42设置于所述第一层间绝缘层41上。
如图1所示，所述阵列基板100还包括设置于所述第二层间绝缘层42上的源漏极层5。其中所述源漏极层5通过过孔6连接至所述有源层2上。
如图1所示，其中所述过孔6包括相连通的第一凹槽61和第二凹槽62。其中所述第一凹槽61由所述第二层间绝缘层42远离所述基板1的表面局部向下凹陷形成；所述第二凹槽62由所述第一凹槽61靠近所述基板1的底面局部向下凹陷直至所述有源层2远离所述基板1的表面形成。其中所述第一凹槽61和所述第二凹槽62的相接处形成有一台阶63。
如图1所示，其中所述第一凹槽61的底面设置于所述第二层间绝缘层42与所述第一栅极绝缘层31之间。本实施例优选的将所述第一凹槽61的底面与所述第二栅极绝缘层32远离所述基板1的表面平齐。另外，本实施例中所述的过孔6包括第一凹槽61和第二凹槽62，实际操作中，还可以包括第三凹槽、第四凹槽等。本实施例主要是将过孔6设置成第一凹槽61和第二凹槽62，由此改变后期通过所述过,6连接于所述有源层2上的源漏极层5的一次爬坡高度，从而避免源漏极层5爬坡断裂的风险。
如图1所示，所述阵列基板100还包括第一栅极层7以及第二栅极层8，其中所述第一栅极层7设置于所述第一栅极绝缘层31与所述第二栅极绝缘层32之间；所述第二栅极层8设置于所述第二栅极绝缘32与所述第一层间绝缘层41之间。其中所述第一栅极绝缘层31主要是防止第一栅极层7与所述有源层2之间接触，避免其发生短路现象。其中所述第二栅极绝缘层32主要是防止第一栅极层7和第二栅极层8之间接触，避免其发生短路现象。
实施例2
如图2所示，本发明还提供了一种制备本发明所涉及的阵列基板100的制备方法，其中包括：步骤S1，提供一基板1，在所述基板1上制备所述有源层2；步骤S2，在所述有源层2上制备所述栅极绝缘层3；步骤S3，在所述栅极绝缘层3上制备所述层间绝缘层4；步骤S4，在所述层间绝缘层4上制备所述源漏极层5，所述源漏极层5通过过孔6向下连接于所述有源层2上。其中所述步骤S4中的过孔6包括相连通的第一凹槽61和第二凹槽62；所述第一凹槽61由所述层间绝缘层4远离所述基板1的表面局部向下凹陷形成，所述第二凹槽62由所述第一凹槽61靠近所述基板1的底面局部向下凹陷直至所述有源层2远离所述基板1的表面形成；其中所述第一凹槽61和所述第二凹槽62的相接处形成有一台阶63。
具体地，其中所述步骤S2包括：在所述有源层2上制备所述第一栅极绝缘层31，在所述第一栅极绝缘层31上制备所述第二栅极绝缘层32；所述步骤S3包括：在所述第二栅极绝缘层32上制备所述第一层间绝缘层41，在所述第一层间绝缘层41上制备所述第二层间绝缘层42；所述步骤S4中的过孔6包括相连通的第一凹槽61和第二凹槽62。所述第一凹槽61由所述第二层间绝缘层42远离所述基板1的表面局部向下凹陷形成，所述第二凹槽62由所述第一凹槽61靠近所述基板1的底面局部向下凹陷直至所述有源层2远离所述基板1的表面形成；其中所述第一凹槽61和所述第二凹槽62的相接处形成有一台阶63。
实施例3
其中所述步骤S4中的过孔6包括相连通的第一凹槽61和第二凹槽62。如图3所示，通过第一套孔由所述第二层间绝缘层42远离所述基板1的表面向下进行刻蚀形成所述第一凹槽61；如图1所示，通过第二套孔对所述第一凹槽61靠近所述基板1的底面直至所述有源层2远离所述基板1的表面进行刻蚀形成所述第二凹槽62。其中所述第二套孔的外围尺寸小于所述第一套孔的外围尺寸。由此主要是将过孔6设置成第一凹槽61和第二凹槽62，由此改变后期通过所述过,6连接于所述有源层2上的源漏极层5的一次爬坡高度，从而避免源漏极层5爬坡断裂的风险。
实施例4
其中所述步骤S4中的过孔6包括相连通的第一凹槽61和第二凹槽62。如图4所示，通过第二套孔由所述第二层间绝缘层42远离所述基板1的表面向下进行刻蚀；如图1所示，通过第一套孔对所述第二套孔外围的所述第二层间绝缘42进行刻蚀形成所述第一凹槽61；同时通过第一套孔对所述第二套孔内直至所述有源层2远离所述基板1的表面进行刻蚀形成所述第二凹槽62。其中所述第二套孔的外围尺寸小于所述第一套孔的外围尺寸。由此主要是将过孔6设置成第一凹槽61和第二凹槽62，由此改变后期通过所述过,6连接于所述有源层2上的源漏极层5的一次爬坡高度，从而避免源漏极层5爬坡断裂的风险。
实施例5
其中所述步骤S4中，通过对所述第二层间绝缘层42远离所述基板1的表面局部向下进行刻蚀，然后用氧气对光阻的孔洞处理形成所述第一凹槽61；所述第一凹槽61对所述第一凹槽61靠近所述基板1的底面直至所述有源层2远离所述基板1的表面进行局部刻蚀形成所述第二凹槽62。由此改变后期通过所述过孔6连接于所述有源层2上的源漏极层5的一次爬坡高度，从而避免源漏极层5爬坡断裂的风险。本实施例中的第一凹槽61的制备步骤图类似于图4；本实施例中的第二凹槽62的制备步骤图类似于图1，此不赘述。
本发明还提供了一种显示面板，其中包括本发明所涉及的阵列基板100。
以上对本发明所提供的阵列基板及其制备方法、显示面板进行了详细介绍。应理解，本文所述的示例性实施方式应仅被认为是描述性的，用于帮助理解本发明的方法及其核心思想，而并不用于限制本发明。在每个示例性实施方式中对特征或方面的描述通常应被视作适用于其他示例性实施例中的类似特征或方面。尽管参考示例性实施例描述了本发明，但可建议所属领域的技术人员进行各种变化和更改。本发明意图涵盖所附权利要求书的范围内的这些变化和更改，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种阵列基板，其中包括：
    基板；
    有源层，所述有源层设置于所述基板上；
    栅极绝缘层，所述栅极绝缘层设置于所述有源层上；
    层间绝缘层，所述层间绝缘层设置于所述栅极绝缘层上；
    源漏极层，所述源漏极层设置于所述层间绝缘层上，所述源漏极层通过过孔向下连接至所述有源层上；
    其中所述过孔包括相连通的第一凹槽和第二凹槽；
    所述第一凹槽由所述层间绝缘层远离所述基板的表面局部向下凹陷形成；
    所述第二凹槽由所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成；
    其中所述第一凹槽和所述第二凹槽的相接处形成有一台阶。
  2. 根据权利要求1所述的阵列基板，其中所述栅极绝缘层包括：
    第一栅极绝缘层，所述第一栅极绝缘层设置于所述有源层上；
    第二栅极绝缘层，所述第二栅极绝缘层设置于所述第一栅极绝缘层上；
    所述层间绝缘层包括：
    第一层间绝缘层，所述第一层间绝缘层设置于所述第二栅极绝缘层上；
    第二层间绝缘层，所述第二层间绝缘层设置于所述第一层间绝缘层上；
    其中所述第一凹槽由所述第二层间绝缘层远离所述基板的表面局部向下凹陷形成。
  3. 根据权利要求2所述的阵列基板，其中所述第一凹槽的底面设置于所述第二层间绝缘层与所述第一栅极绝缘层之间。
  4. 根据权利要求3所述的阵列基板，其中所述第一凹槽的底面与所述第二栅极绝缘层远离所述基板的表面平齐。
  5. 一种制备权利要求1所述的阵列基板的制备方法，其中包括：
    步骤S1，提供一基板，在所述基板上制备所述有源层；
    步骤S2，在所述有源层上制备所述栅极绝缘层；
    步骤S3，在所述栅极绝缘层上制备所述层间绝缘层；
    步骤S4，在所述层间绝缘层上制备所述源漏极层，所述源漏极层通过过孔向下连接于所述有源层上；
    其中所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；所述第一凹槽由所述层间绝缘层远离所述基板的表面局部向下凹陷形成，所述第二凹槽由所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成；其中所述第一凹槽和所述第二凹槽的相接处形成有一台阶。
  6. 根据权利要求5所述的阵列基板的制备方法，其中所述步骤S2包括：在所述有源层上制备所述第一栅极绝缘层，在所述第一栅极绝缘层上制备所述第二栅极绝缘层；
    所述步骤S3包括：在所述第二栅极绝缘层上制备所述第一层间绝缘层，在所述第一层间绝缘层上制备所述第二层间绝缘层；
    所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；所述第一凹槽由所述第二层间绝缘层远离所述基板的表面局部向下凹陷形成，所述第二凹槽由所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成；其中所述第一凹槽和所述第二凹槽的相接处形成有一台阶。
  7. 根据权利要求6所述的阵列基板的制备方法，其中所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；所述第一凹槽通过第一套孔由第二层间绝缘层远离所述基板的表面向下进行刻蚀形成；所述第二凹槽通过第二套孔对所述第一凹槽靠近所述基板的底面直至所述有源层远离所述基板的表面进行刻蚀形成；其中所述第二套孔的外围尺寸小于所述第一套孔的外围尺寸。
  8. 根据权利要求6所述的阵列基板的制备方法，其中所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；所述第一凹槽通过第二套孔由第二层间绝缘层远离所述基板的表面向下进行刻蚀，然后通过第一套孔对所述第二套孔外围的所述第二层间绝缘进行刻蚀形成；所述第二凹槽通过第一套孔对所述第二套孔内直至所述有源层远离所述基板的表面进行刻蚀形成；其中所述第二套孔的外围尺寸小于所述第一套孔的外围尺寸。
  9. 根据权利要求6所述的阵列基板的制备方法，其中所述步骤S4中的过孔包括相连通的第一凹槽和第二凹槽；其中所述第一凹槽是对所述第二层间绝缘层远离所述基板的表面局部向下进行刻蚀，然后用氧气对光阻的孔洞处理形成；所述第二凹槽是对所述第一凹槽靠近所述基板的底面直至所述有源层远离所述基板的表面进行局部刻蚀形成。
  10. 一种显示面板，其中包括权利要求1所述的阵列基板，所述阵列基板包括：
    基板；
    有源层，所述有源层设置于所述基板上；
    栅极绝缘层，所述栅极绝缘层设置于所述有源层上；
    层间绝缘层，所述层间绝缘层设置于所述栅极绝缘层上；
    源漏极层，所述源漏极层设置于所述层间绝缘层上，所述源漏极层通过过孔向下连接至所述有源层上；
    其中所述过孔包括相连通的第一凹槽和第二凹槽；
    所述第一凹槽由所述层间绝缘层远离所述基板的表面局部向下凹陷形成；
    所述第二凹槽由所述第一凹槽靠近所述基板的底面局部向下凹陷直至所述有源层远离所述基板的表面形成；
    其中所述第一凹槽和所述第二凹槽的相接处形成有一台阶。。
  11. 根据权利要求10所述的显示面板，其中所述栅极绝缘层包括：
    第一栅极绝缘层，所述第一栅极绝缘层设置于所述有源层上；
    第二栅极绝缘层，所述第二栅极绝缘层设置于所述第一栅极绝缘层上；
    所述层间绝缘层包括：
    第一层间绝缘层，所述第一层间绝缘层设置于所述第二栅极绝缘层上；
    第二层间绝缘层，所述第二层间绝缘层设置于所述第一层间绝缘层上；
    其中所述第一凹槽由所述第二层间绝缘层远离所述基板的表面局部向下凹陷形成。
  12. 根据权利要求11所述的显示面板，其中所述第一凹槽的底面设置于所述第二层间绝缘层与所述第一栅极绝缘层之间。
  13. 根据权利要求12所述的显示面板，其中所述第一凹槽的底面与所述第二栅极绝缘层远离所述基板的表面平齐。
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