WO2021109969A1 - 源极驱动器、显示面板及其控制方法、显示装置 - Google Patents

源极驱动器、显示面板及其控制方法、显示装置 Download PDF

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Publication number
WO2021109969A1
WO2021109969A1 PCT/CN2020/132761 CN2020132761W WO2021109969A1 WO 2021109969 A1 WO2021109969 A1 WO 2021109969A1 CN 2020132761 W CN2020132761 W CN 2020132761W WO 2021109969 A1 WO2021109969 A1 WO 2021109969A1
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WIPO (PCT)
Prior art keywords
shift register
circuit
signal
group
register group
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PCT/CN2020/132761
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English (en)
French (fr)
Inventor
王糖祥
杨飞
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京东方科技集团股份有限公司
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Priority to US17/607,831 priority Critical patent/US11804184B2/en
Publication of WO2021109969A1 publication Critical patent/WO2021109969A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a source driver, a display panel and a control method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • PMOLED Passive matrix Organic Light-emitting Diode, passive matrix organic light-emitting diode
  • AMOLED Active-Matrix Organic Light-emitting Diode, active matrix organic light-emitting diode
  • AMOLED display devices Two categories. Among them, AMOLED display devices have the characteristics of ultra-thin, wide viewing angle, low power consumption, fast response, and vivid colors, and are widely used in display products such as mobile phones, TVs, and tablets. In addition, AMOLED has high luminous efficiency and is suitable for high-definition large-size display products.
  • a source driver which includes a plurality of shift register groups, an enable control circuit, and at least one switch circuit that are sequentially cascaded.
  • Each shift register group includes multiple stages of shift registers cascaded in sequence.
  • the shift register group is configured to sample the digitized image data under the control of the first start signal; the first start signal of the nth shift register group is determined by the n-1th shift register group Output, n ⁇ 2 and n is a positive integer.
  • the enable control circuit is configured to output the first on signal or the first off signal under the control of the enable control signal from the timing controller.
  • At least one switch circuit is electrically connected with the enable control circuit.
  • the last-stage shift register in the previous shift register group and the first-stage shift register in the next shift register group are electrically connected through one switch circuit;
  • the switch circuit is configured to connect the previous shift register group with the latter shift register group under the control of the first turn-on signal from the enable control circuit; and, Under the control of the first shutdown signal from the enable control circuit, the previous shift register group and the latter shift register group are disconnected.
  • the source driver further includes a plurality of digital-to-analog conversion circuit groups and gating circuits.
  • One group of digital-to-analog conversion circuits corresponds to one group of shift registers.
  • the digital-to-analog conversion circuit group is configured to convert the digitized image data from the corresponding shift register group into an analog gray-scale signal according to the gamma signal from the gray-scale controller, and output the analog gray-scale signal signal.
  • the gate circuit is at least electrically connected to each of the digital-to-analog conversion circuit groups and the first reference signal terminal.
  • the gating circuit is configured to output the analog gray scale signal from the digital-to-analog conversion circuit group at different time periods, or output the first reference signal transmitted by the first reference signal terminal.
  • the gate circuit is also electrically connected to the second reference signal terminal.
  • the gating circuit is configured to output the analog grayscale signal from the digital-to-analog conversion circuit in different time periods, or output the first reference signal transmitted by the first reference signal terminal, or output the second reference signal.
  • the voltage of the first reference signal is greater than the minimum voltage of the analog gray-scale signal and less than the maximum voltage of the analog gray-scale signal.
  • the source driver further includes a plurality of output buffer circuit groups, each of the output buffer circuit groups is electrically connected to the gate circuit, one output buffer circuit group and one shift register group Corresponding. Except for the output buffer circuit group corresponding to the first shift register group, the other output buffer circuits are electrically connected to the enable control circuit.
  • the switch circuit that receives the first turn-on signal output by the enable control circuit is the target switch circuit.
  • the shift register group that is electrically connected to the target switch circuit and receives the first start signal through the target switch circuit is the target shift register group.
  • the enable control circuit is further configured to shift to the target under the control of the enable control signal from the timing controller when the first on signal is output to the target switch circuit.
  • the output buffer circuit group corresponding to the register group outputs the second turn-on signal or the second turn-off signal.
  • the output buffer circuit group corresponding to the target shift register group is configured to, under the control of the second turn-on signal, output the analog grayscale signal transmitted by the gate circuit in different periods, or output The first reference signal; and, stop working under the control of the second shutdown signal.
  • the output buffer circuit group corresponding to the first shift register group is configured to output the analog gray scale signal transmitted by the gate circuit or output the first reference signal in different time periods.
  • the output buffer circuit group corresponding to the target shift register group is configured to: Under the control of the turn-on signal, output the analog grayscale signal transmitted by the gate circuit in different time periods, or output the first reference signal, or output the second reference signal; and, in the second Stop working under the control of the shutdown signal.
  • the output buffer circuit group corresponding to the first shift register group is configured to output the analog grayscale signal transmitted by the gate circuit, or output the first reference signal, or output the The second reference signal.
  • the source driver further includes a plurality of data latch circuit groups, and one data latch circuit group corresponds to one shift register group and one digital-to-analog conversion circuit group.
  • the data latch circuit group is configured to store the digitized image data output from the corresponding shift register group, and output the stored digitized image data to the corresponding digital-to-analog conversion circuit group under the control of the drive control signal .
  • each of the data latch circuit groups includes a plurality of data latch circuits, and the number of data latch circuits included in each data latch circuit group corresponds to the data latch circuit group The number of shift registers included in the shift register group is positively correlated.
  • the source driver further includes a level conversion circuit electrically connected between the plurality of data latch circuit groups and the plurality of digital-to-analog conversion circuit groups.
  • the level conversion circuit is configured to convert the low-level digitized image data from the data latch circuit group into high-level digitized image data, and output it to the corresponding data latch circuit group The said digital-to-analog conversion circuit group.
  • the source driver further includes a data processor, which is electrically connected to the plurality of shift register groups.
  • the data processor is configured to preprocess the digitized image data, and output the preprocessed digitized image data to the plurality of shift register groups.
  • the source driver further includes a plurality of interface circuits, which are electrically connected to the data processor.
  • the interface circuit is configured to convert the image data from the timing controller into digitized image data, and output the converted digitized image data to the data processor.
  • the switch circuit includes an inverter, a first transmission gate, and a second transmission gate.
  • the first transmission gate includes a first P-type transistor and a first N-type transistor, and the gate of the first N-type transistor is electrically connected to the input terminal of the inverter and the enable control circuit.
  • the gate of the first P-type transistor is electrically connected to the output terminal of the inverter.
  • the last-stage shift register in the n-1th shift register group is electrically connected to the first pole of the first P-type transistor and the first pole of the first N-type transistor, and the nth shift register group
  • the first stage shift register is electrically connected with the second pole of the first P-type transistor and the second pole of the first N-type transistor, n ⁇ 2.
  • the second transmission gate includes a second P-type transistor and a second N-type transistor.
  • the gate of the second P-type transistor is electrically connected to the input terminal of the inverter and the enable control circuit.
  • the gate of the second N-type transistor is electrically connected to the output terminal of the inverter.
  • the shift register of the last stage in the n-1th shift register group is electrically connected to the first pole of the second P-type transistor and the first pole of the second N-type transistor.
  • a display panel which has a display area and a peripheral area.
  • the display panel includes at least one source driver arranged in the peripheral area, the source driver being the source driver described in any one of the above embodiments, and a timing controller arranged in the peripheral area.
  • the timing controller is electrically connected to the source driver.
  • the timing controller is configured to transmit a first start signal to the first shift register group of one of the source drivers; and transmit an enable control signal to the enable control circuit of each of the source drivers.
  • the plurality of source drivers are cascaded in sequence
  • the switch circuit is configured to disconnect between the previous shift register group and the latter shift register group under the control of the first off signal from the enable control circuit, and The previous shift register group is connected with the first shift register group of the next source driver.
  • the display panel further includes a plurality of sub-pixels and a plurality of data lines located in the display area.
  • Each sub-pixel includes a pixel driving circuit, and the source driver is electrically connected to a plurality of the pixel driving circuits through at least one data line.
  • a display device including the display panel described in any of the above embodiments.
  • a method for controlling a display panel wherein the display panel includes a plurality of sub-pixels, at least one source driver, and a timing controller, and each of the sub-pixels includes a pixel driving circuit.
  • the source driver is the source driver according to any one of the above embodiments, and the source driver further includes a gate circuit and a plurality of digital-to-analog conversion circuit groups, and the gate circuit is at least connected to the plurality of digital-to-analog conversion circuits.
  • the conversion circuit group is electrically connected to the first reference signal terminal.
  • the scanning time of a row of sub-pixels includes a data writing phase and a blanking phase
  • the control method of the display panel includes:
  • the enable control circuit of the source driver outputs a first turn-on signal or a first turn-off signal to the switch circuit under the control of the enable control signal from the timing controller;
  • the shift register group of the source driver samples the digitized image data under the control of the first start signal from the timing controller or the previous shift register group, and outputs the sampled digitized image data;
  • the digital-to-analog conversion circuit group of the source driver converts the digitized image data from the corresponding shift register group into an analog gray-scale signal according to the gamma signal from the gray-scale controller, and outputs the analog gray-scale signal signal;
  • the gate circuit In the data writing stage, the gate circuit outputs an analog grayscale signal from the digital-to-analog conversion circuit group; the pixel drive circuit receives an analog grayscale signal from the source driver;
  • the gating circuit In the blanking phase, the gating circuit outputs the first reference signal transmitted by the first reference signal terminal.
  • the gate circuit is also electrically connected to the second reference signal terminal, and the scanning time of a row of sub-pixels further includes a threshold voltage compensation stage.
  • the control method of the display panel further includes:
  • the gating circuit In the compensation phase, the gating circuit outputs the second reference signal transmitted by the second reference signal terminal; the pixel driving circuit receives the second reference signal to drive the pixel driving circuit The transistor performs threshold voltage compensation.
  • FIG. 1 is a structural diagram of a display panel according to some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure
  • FIG. 3 is a structural diagram of a source driver according to some embodiments of the present disclosure.
  • Figure 4 is a partial enlarged view at P in Figure 3;
  • FIG. 5 is a structural diagram of another source driver according to some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of still another source driver according to some embodiments of the present disclosure.
  • FIG. 7 is a structural diagram of yet another source driver according to some embodiments of the present disclosure.
  • FIG. 8 is a structural diagram of yet another source driver according to some embodiments of the present disclosure.
  • FIG. 9 is a structural diagram of a switch circuit according to some embodiments of the present disclosure.
  • FIG. 10 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expression “electrical connection” and its extensions may be used.
  • the term “electrically connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the display device 200 includes a display panel 100.
  • the display device 200 further includes a frame, a circuit board, a display driver IC (Integrated Circuit, IC for short), and other electronic accessories.
  • the above-mentioned display panel 100 is arranged in the frame.
  • the display device 200 may be any device that displays images, whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators, cameras
  • the above-mentioned display panel 100 may be an AMOLED display panel.
  • the display panel 100 has a display area AA (also called Active Area, which is called an active display area in Chinese) and a peripheral area S.
  • the peripheral area S may be arranged in a circle around the display area AA.
  • the display panel 100 includes a plurality of sub-pixels P and a plurality of data lines DL located in the display area AA. It should be noted that, in FIG. 1, the above-mentioned multiple sub-pixels P are arranged in an array form as an example for illustration, but the embodiments of the present disclosure are not limited to this, and the above-mentioned multiple sub-pixels may also be arranged in other ways.
  • each sub-pixel P includes a pixel driving circuit T.
  • a light emitting device L is further provided in the sub-pixel P, and the pixel driving circuit T is electrically connected to the light emitting device L to drive the light emitting device L to emit light.
  • the light-emitting device L is an OLED.
  • the pixel driving circuit T is generally composed of electronic devices such as a thin film transistor (TFT for short) and a capacitor (C for short).
  • TFT thin film transistor
  • C capacitor
  • the pixel driving circuit T may be a pixel driving circuit with a 3T1C structure composed of three TFTs and a capacitor.
  • the peripheral area S of the display panel 100 is provided with at least one source driver 10 and a timing controller 20, and the timing controller 20 is electrically connected to each source driver 10. connection.
  • the source driver 10 is electrically connected to a plurality of pixel driving circuits T through at least one data line DL, and the source driver 10 is configured to receive digitized image data and process the digitized image data. Among them, the process of processing the digitized image data by the source driver 10 will be described later.
  • each source driver 10 may be electrically connected to a plurality of pixel driving circuits T through a plurality of data lines DL, and one end of each data line DL is connected to a data output channel of the source driver 10 (that is, output to the data line DL).
  • the data interface is electrically connected, and the other end is electrically connected to a plurality of pixel driving circuits T.
  • each source driver 10 is electrically connected to each pixel driving circuit T in a plurality of columns of sub-pixels P through a plurality of data lines DL, wherein one data line DL is connected to each of the sub-pixels P in one column.
  • the pixel driving circuit T is electrically connected.
  • the operation of the source driver 10 is controlled by the timing controller 20. If the display panel 100 includes a source driver 10, the timing controller 20 is configured to transmit a first start signal to the source driver 10 to control the source driver 10 to process the received digitized image data. If the display panel 100 includes a plurality of source drivers 10, and the plurality of source drivers 10 are cascaded in sequence, the timing controller 20 is configured to transfer to the first source of the cascaded source drivers 10 The driver 10 transmits a first start signal to control the source driver 10 to process the received digitized image data.
  • the peripheral area S of the display panel 100 is further provided with a gray scale controller 30, and the gray scale controller 30 is electrically connected to each of the source driver 10 and the timing controller 20.
  • the gray scale controller 30 is configured to output a gamma signal to the source driver 10 according to the gray scale data of the sub-pixels in the display image from the timing controller 20.
  • the source driver 10 includes: a plurality of shift register groups 110 and at least one switch circuit 120 that are sequentially cascaded , And enable control circuit 130.
  • each shift register group 110 includes multiple stages of shift registers 110A cascaded sequentially.
  • the shift register group 110 is configured to sample the digitized image data under the control of the first start signal DIO1 from the timing controller 20.
  • the number of shift registers 110A in each shift register group 110 is the same.
  • the number of shift registers 110A in each shift register group 110 is not completely the same.
  • the number of shift registers 110A in at least one shift register group 110 is different from the number of shift registers 110A in other shift register groups 110.
  • the timing controller 20 is configured to transmit the first start signal DIO1 to the first shift register group of a source driver 10 to control the shift register group 110 in the source driver 10 to pair the digitized image Data is sampled; and, an enable control signal is transmitted to the enable control circuit 130 of each source driver 10. If the display panel 100 includes a source driver 10, the timing controller 20 transmits the first start signal DIO1 to the first shift register group of the source driver 10. If the display panel 100 includes a plurality of source drivers 10, the timing controller 20 transmits the first start signal DIO1 to the first shift register group of one of the plurality of source drivers 10. For example, when the multiple source drivers 10 are cascaded sequentially, the timing controller 20 transmits the first start signal to the first source driver 10.
  • the first start signal DIO1 of the first shift register group in the first source driver comes from the timing controller 20. Except for the first source driver, the first start signal DIO1 of the first shift register group of each source driver comes from the second start signal DIO2 output by the previous source driver.
  • the last stage of shift register in each shift register group 110 outputs a second start signal DIO2 after sampling ends, and this second start signal DIO2 serves as the first start signal DIO1 of the next shift register group, That is, the first start signal DIO1 of the nth shift register group is output by the n-1th shift register group, where n ⁇ 2 and n is a positive integer.
  • the enable control circuit 130 is configured to output the first on signal or the first off signal under the control of the enable control signal from the timing controller 20.
  • the first turn-on signal and the first turn-off signal are output to the switch circuit 120 for controlling the working state of the switch circuit 120. Among them, the working state of the switch circuit will be introduced later.
  • the first turn-on signal may be a high-level signal, and the first turn-off signal may be a low-level signal; or, the first turn-on signal may be a low-level signal, and the first turn-off signal may be a high-level signal. Whether the first turn-on signal and the first turn-off signal are high-level signals or low-level signals depends on whether the level signals required by the operating state of the switch circuit 120 are high-level signals or low-level signals.
  • the enable control signal from the timing controller 20 received by the enable control circuit 130 may be a high-level signal or a low-level signal, depending on the enable control circuit 130 to output the first enable signal. Or whether the level signal required by the first off signal is a high-level signal or a low-level signal.
  • the first turn-on signal and the first turn-off signal are used to control the working state of the switch circuit 120, and the working state of the switch circuit 120 is related to the number of shift register groups 110 for sampling (described later); and, The greater the number of shift register groups 110 for sampling and the greater the number of data output channels with the source driver 10, the greater the resolution of the display panel 100. Therefore, whether the enable control signal is a high-level signal or a low-level signal is related to factors such as the resolution of the display panel 100 and the number of data output channels of the source driver 10.
  • Each switch circuit 120 is electrically connected with the enable control circuit 130. As shown in Figure 4, in two adjacent shift register groups 110, a switch circuit is passed between the last shift register in the previous shift register group and the first shift register in the next shift register group. 120 electrical connections.
  • the switch circuit 120 is configured to, under the control of the first turn-on signal from the enable control circuit 130, connect the previous shift register group with the next shift register group to connect the output from the previous shift register group
  • the second start signal DIO2 is transmitted to the next shift register group as the first start signal DIO1 of the next shift register group (this is a working state of the switch circuit 120); and, when it comes from the enable control circuit 130 Under the control of the first closing signal of, the previous shift register group and the next shift register group are disconnected (this is another working state of the switch circuit 120).
  • the switch circuit 120 can be located between any pair of adjacent two shift register groups (as shown in FIG. 4), that is, the n-th
  • the shift register of the last stage in a shift register group and the shift register of the first stage in the nth shift register group are cascaded through a switch circuit 120.
  • the first to n-1th shift register groups are sequentially cascaded
  • the nth to last shift register groups are sequentially cascaded.
  • multiple switch circuits 120 it may be between the last-stage shift register in the odd-numbered shift register group and the first-stage shift register in the even-numbered shift register group adjacent to it, It is electrically connected through a switch circuit 120.
  • the leftmost shift register group in the plurality of shift register groups 110 is the first shift register group
  • the rightmost shift register group is the last shift register group
  • the last shift register group in the first shift register group 110 is
  • the first-stage shift register in the second shift register group is electrically connected to the first-stage shift register in the second shift register group through a switch circuit 120
  • the last-stage shift register in the second shift register group is electrically connected to the third shift register group.
  • the first stage shift register is directly connected.
  • the last stage of shift register in the even-numbered shift register group and the first stage of shift register in the adjacent odd-numbered shift register group are electrically connected through a switch circuit 120.
  • the leftmost shift register group among the multiple shift register groups 110 is the first shift register group
  • the rightmost shift register group is the last shift register group
  • the last shift register group in the second shift register group 110 is
  • the first-stage shift register in the third shift register group is electrically connected to the first-stage shift register in the third shift register group through a switch circuit 120
  • the last-stage shift register in the first shift register group is electrically connected to the second shift register group.
  • the first stage shift register is directly connected.
  • the other shift register groups can be cascaded with the previous shift register group through the switch circuit 120.
  • the n-1th shift register group samples the digitized image data under the control of the first start signal DIO1
  • the last stage shift register of the nth shift register group samples the digitized image data Output and output the second start signal DIO2.
  • the switch circuit 120 If the signal from the enable control circuit 130 received by the switch circuit 120 between the n-1th shift register group and the nth shift register group is the first turn-on signal, the switch circuit 120 performs the first turn-on signal Under the control of, the switch circuit 120 transmits the second start signal DIO2 output by the n-1th shift register group to the nth shift register group as the first start signal DIO1 of the nth shift register group, Control the nth shift register group to sample the digitized image data.
  • the switch circuit 120 In the source driver 10, if the signal from the enable control circuit 130 received by the switch circuit 120 between the n-1th shift register group and the nth shift register group is the first off signal, the switch Under the control of the first closing signal, the switch circuit 120 outputs the second start signal DIO2 output by the n-1th shift register group to the next-stage source driver cascaded with the source driver 10.
  • the first shift register group is used as the first start signal DIO1 of the first shift register group in the next-level source driver.
  • each source driver starts the second output from the previous source driver.
  • the start signal DIO2 is used as the first start signal DIO1 of the first shift register group in the source driver.
  • the switch circuit 120 between the first shift register group and the second shift register group in the source driver 10 is controlled by the first off signal, and the output of the first shift register group starts from the second one.
  • the start signal DIO2 will not be transmitted to the second shift register group, but to the first shift register group in the next-stage source driver 10 cascaded with the source driver 10, as the next-stage source
  • the source driver 10 does not work from the second to the last shift register group, and the first shift register group in the next-stage source driver 10 starts sampling.
  • the switch circuits 120 in the source driver 10 are all in the on state, and the last shift register group outputs the second at the end of sampling.
  • the start signal DIO2 is used as the first start signal DIO1 of the first shift register group in the next-level source driver, so that the shift register group in the next-level source driver performs sampling step by step.
  • the source driver includes a plurality of shift registers, and sampling is performed by the plurality of shift registers, and the number of data output channels is fixed.
  • the source driver includes a plurality of shift register groups 110, and each shift register group 110 includes a plurality of shift registers (it can be understood that the source driver in the related art only includes one shift register).
  • Register group the number of shift register groups 110 to be sampled can be selected through the switch circuit 120, so as to adjust the number of data output channels of the source driver 10: when the resolution of the display panel 100 is larger, the switch is turned on.
  • More shift register groups 110 increase the data output channels of the source driver 10; when the resolution of the display panel 100 is small, fewer shift register groups 110 are turned on to reduce the data output channels of the source driver 10, so that the source
  • the pole driver 10 can be adapted to display panels 100 of multiple resolutions.
  • the first shift register group is controlled by the first start signal DIO1 from the timing controller 20 from the first shift register group.
  • the shift register from stage to the 24th stage performs sampling in sequence, and serially outputs 24 samples of digitized image data, and after the 24th stage shift register outputs the sampled digitized image data, it outputs the second start signal DIO2 as the second The first start signal DIO1 of the shift register group.
  • a switch circuit 120 located between the 24th stage shift register in the first shift register group and the first stage shift register in the second shift register group is turned on under the control of the first turn-on signal , Use the second start signal DIO2 output by the first shift register group as the first start signal DIO1 of the second shift register group, and transmit it to the first stage shift register in the second shift register group, so that
  • the shift registers of the first to 24th stages in the second shift register group sequentially sample, serially output 24 sampled digitized image data, and output the sampled digitized image data after the 24th stage shift register outputs the sampled digitized image data.
  • the second start signal DIO2 is used as the first start signal DIO1 of the third shift register group.
  • a switch circuit 120 located between the 24th stage shift register in the second shift register group and the first stage shift register in the third shift register group receives the first closing signal
  • the third shift register group will not receive the second start signal DIO2 output by the second shift register group as the first start signal DIO1 of the third shift register group, that is, the third shift register group
  • the bit register group does not work, and the third to the last shift register group will not work.
  • the source driver 10 only has the first shift register group and the second shift register group working, and outputs 48 samples. Digitized image data.
  • the number of shift register groups for sampling can be selected through the switch circuit 120, and n shift register groups are selected for sampling, and each shift register group includes m shift registers (m is a positive value greater than 1).
  • the source driver 10 can output m ⁇ n samples of digitized image data.
  • first shift register group and the last shift register group are relative, and the first shift register and the last shift register in the shift register group 110 are also relative. It depends on the forward sampling and reverse sampling of the shift register group.
  • the source driver 10 in FIG. 8 changes from the first shift register group to the last one.
  • the shift register group sequentially performs forward sampling, that is, the shift register group 110 in FIG. 8 performs sampling from left to right.
  • the first shift register in the first shift register group receives from The first start signal DIO1 of the timing controller 20, the shift register of the last stage in the first shift register group outputs the second start signal DIO2 as the first start signal DIO1 of the second shift register group.
  • the source driver 10 in FIG. 9 sequentially performs reverse sampling from the last shift register group to the first shift register group, that is, the shift in FIG. 9
  • the bit register group 110 is sampled from right to left.
  • the last shift register in the last shift register group can be regarded as the first shift register in the first shift register group.
  • the first start signal DIO1 of the timing controller 20 the first shift register in the last shift register group can be regarded as the last shift register in the first shift register group, and the second start signal DIO2 is output.
  • the source register 10 includes a plurality of shift register groups 110, at least one switch circuit 120, and an enable control circuit 130 that are sequentially cascaded, and each shift register group 110 includes successively Cascaded multi-stage shift registers, in two adjacent shift register groups 110, between the last shift register in the previous shift register group and the first shift register in the next shift register group
  • each switch circuit 120 can be turned on or off by the first turn-on signal or the first turn-off signal output by the enable control circuit 130 to control the previous shift register group and the next shift register The group is connected or disconnected.
  • the number of shift register groups 110 for sampling can be selected by controlling the working state of the switch circuit 120, and the number of data output channels of the source driver 10 can be adjusted.
  • the resolution of the display panel 100 is relatively large, turn on Multiple shift register groups 110 increase the data output channels of the source driver 10.
  • the resolution of the display panel 100 is small, fewer shift register groups 110 are turned on, and the data output channels of the source driver 10 are reduced, so that the source
  • the pole driver 10 can be adapted to display panels 100 of various resolutions, and the compatibility of the source driver 10 can be improved.
  • the source driver 10 further includes a gate circuit 140 and a plurality of digital-to-analog conversion circuit groups 150.
  • one digital-to-analog conversion circuit group 150 corresponds to one shift register group 110.
  • the digital-to-analog conversion circuit group 150 is configured to convert the digitized image data from the corresponding shift register group 110 into an analog gray-scale signal according to the gamma signal GMA from the gray-scale controller 30 and output it.
  • the gate circuit 140 is electrically connected to at least the digital-to-analog conversion circuit group 150 and the first reference signal terminal Vref1.
  • the gating circuit 140 is configured to output the analog gray scale signal from the digital-to-analog conversion circuit group 150 or the first reference signal transmitted by the first reference signal terminal Vref1 in different periods.
  • the display panel 100 further includes a power supply circuit, which is used to provide multiple components in the display panel 100 (for example, the source driver 10, the timing controller 20, the grayscale controller 30, etc.) Electrical energy. Based on this, the above-mentioned first reference signal may be provided by the power supply circuit.
  • a power supply circuit which is used to provide multiple components in the display panel 100 (for example, the source driver 10, the timing controller 20, the grayscale controller 30, etc.) Electrical energy. Based on this, the above-mentioned first reference signal may be provided by the power supply circuit.
  • the digital-to-analog conversion circuit group 150 includes a plurality of digital-to-analog conversion circuits, and the number of digital-to-analog conversion circuits included in each digital-to-analog conversion circuit group 150 corresponds to the number of the digital-to-analog conversion circuit group 150.
  • the number of shift registers included in the bit register group 110 is positively correlated.
  • the number of digital-to-analog conversion circuits included in each digital-to-analog conversion circuit group 150 is an integer multiple of the number of shift registers included in the shift register group 110 corresponding to the digital-to-analog conversion circuit group 150.
  • the scanning time of a row of sub-pixels P includes a data writing stage and a blanking stage.
  • the gate circuit 140 outputs the analog gray-scale signal from the digital-to-analog conversion circuit group 150 to drive the pixels
  • the circuit T performs data writing.
  • the gate circuit 140 outputs the first reference signal to precharge the data line DL so that the voltage of the signal on the data line DL is equal to the voltage of the first reference signal.
  • the voltage of the first reference signal is greater than the minimum voltage of the analog gray-scale signal and less than the maximum voltage of the analog gray-scale signal. That is, the voltage of the first reference signal is between the maximum value and the minimum value of the voltage of the analog gray-scale signal.
  • the range between the minimum value and the maximum value of the voltage of the analog gray-scale signal can be referred to as the amplitude range of the voltage of the analog gray-scale signal.
  • the amplitude range of the voltage of the analog gray scale signal is 0V-12V
  • the voltage of the first reference signal is 5V, which is between 0V-12V.
  • each data line DL Without precharging each data line DL, the time required for the voltage of the signal in each data line DL to change to the maximum, that is, the time required for the voltage of the signal in each data line DL to change from 0V to 12V, is Maximum rollover time.
  • each data line DL is precharged, so that the voltage of the signal on each data line DL is 5V.
  • the maximum change in the voltage of the signal in each data line DL is from 5V to 12V, that is, the time required for the voltage of the signal in each data line DL to change from 5V to 12V This is the maximum turning time. Since the maximum change range of the voltage of the signal in each data line DL is reduced, the maximum turning time of the voltage of the signal in each data line DL in the display panel 100 is shortened, and the refresh frequency of the display panel is increased.
  • the gate circuit 140 is electrically connected to the output terminal of the digital-to-analog conversion circuit group 150, the first reference signal terminal Vref1 and the second reference signal terminal Vref2.
  • the gating circuit 140 is configured to output the analog grayscale signal from the digital-to-analog conversion circuit group 150, or output the first reference signal transmitted by the first reference signal terminal Vref1, or output the second reference signal terminal Vref2 in different periods.
  • the second reference signal may be provided by the above-mentioned power supply circuit.
  • the scanning time of a row of sub-pixels P also includes a threshold voltage compensation stage.
  • the gate circuit 140 outputs the second reference signal.
  • the pixel driving circuit T may perform threshold voltage compensation on the driving transistor in the pixel driving circuit T according to the second reference signal.
  • the above-mentioned gating circuit 140 receives multiple signals (that is, the analog gray-scale signal, the first reference signal, and the second reference signal), and outputs one of the received multiple signals in a certain period of time, so as to realize the selection.
  • the gate function of the pass circuit 140 On this basis, all circuits that can implement the above-mentioned gating function can be used as the gating circuit 140 in the embodiment of the present disclosure.
  • the specific structure of the gating circuit 140 is not limited in the present disclosure, and those skilled in the art can refer to Set the actual situation.
  • the source driver 10 further includes a bandgap reference circuit electrically connected to the above-mentioned power supply circuit to receive the first reference signal or the second reference signal transmitted by the power supply circuit.
  • the bandgap reference circuit is also electrically connected to the first reference signal terminal Vref1 and the second reference signal terminal Vref2, and the bandgap reference circuit is configured to pass through the first reference signal terminal Vref1 and the second reference signal terminal Vref2 to the gate circuit, respectively.
  • 140 provides a first reference signal and a second reference signal.
  • the source driver 10 further includes a plurality of output buffer circuit groups 160.
  • each output buffer circuit group 160 is electrically connected to the gate circuit 140, and one output buffer circuit group 160 corresponds to one shift register group 110. Except for the output buffer circuit group 160 corresponding to the first shift register group, the other output buffer circuit groups 160 are electrically connected to the enable control circuit 130.
  • the output terminal of an output buffer circuit group 160 is electrically connected to a data line DL.
  • each output buffer circuit group 160 includes a plurality of output buffer circuits, the number of output buffer circuits included in each output buffer circuit group 160, and the shift register group 110 corresponding to the output buffer circuit group 160
  • the number of shift registers included is positively correlated.
  • the number of output buffer circuits included in each output buffer circuit group 160 is an integer multiple of the number of shift registers included in the shift register group 110 corresponding to the output buffer circuit group 160.
  • each shift register group 110 receives the first start signal DIO1 through the switch circuit 120.
  • the switch circuit that receives the first turn-on signal output by the enable control circuit 130 is the target switch circuit; it is electrically connected to the target switch circuit, and receives the shift of the first start signal DIO1 through the target switch circuit.
  • the bit register group 110 is a target shift register group.
  • the enable control circuit 130 is further configured to, under the control of the enable control signal from the timing controller 20, buffer the output corresponding to the target shift register group in the case of outputting the first on signal to the target switch circuit.
  • the circuit group 160 outputs the second turn-on signal or the second turn-off signal.
  • the output buffer circuit group 160 corresponding to the target shift register group is configured to output the analog gray scale signal transmitted by the gate circuit 140 or output the first reference signal in different periods under the control of the second turn-on signal; and , It stops working under the control of the second closing signal, that is, the output buffer circuit group 160 stops outputting the signal transmitted by the gate circuit 140.
  • the output buffer circuit group 160 corresponding to the target shift register group outputs analog grayscale signals under the control of the second turn-on signal; in the blanking of a row of sub-pixels P At this stage, the output buffer circuit group 160 corresponding to the target shift register group outputs the first reference signal under the control of the second turn-on signal.
  • the output buffer circuit group 160 corresponding to the first shift register group is configured to output the analog gray scale signal transmitted by the gate circuit 140 or output the first reference signal in different periods. It should be noted that the output buffer circuit group 160 corresponding to the first shift register group is not electrically connected to the enable control circuit 130, so it is not controlled by the signal output by the enable control circuit 130.
  • the output buffer circuit group 160 corresponding to the first shift register group outputs analog grayscale signals; in the blanking phase of a row of sub-pixels P, it is compared with the first shift register group.
  • the output buffer circuit group 160 corresponding to the bit register group outputs the first reference signal.
  • the second on signal or the second off signal received by the output buffer circuit group 160 is the first on signal received by the target switch circuit 120 electrically connected to the target shift register group 110 corresponding to the output buffer circuit group 160 Or the first closing signal is related.
  • the voltage of the first turn-on signal can be set lower than that of the second The voltage of the turn-on signal, the voltage of the first turn-off signal is lower than the voltage of the second turn-off signal, so as to ensure that both the output buffer circuit group 160 and the switch circuit 120 can be effectively turned on or off.
  • the output buffer circuit group 160 corresponding to the shift register group 110 when the shift register group 110 receives the first start signal DIO1 through the switch circuit 120 and is in the working state, the output buffer circuit group 160 corresponding to the shift register group 110 also starts to work. When the switch circuit 120 does not receive the first start signal DIO1 and is in an inoperative state, the output buffer circuit group 160 corresponding to the shift register group 110 also does not operate.
  • the switch circuit 120 electrically connected to the first-stage shift register in the second shift register group receives the first turn-on signal
  • the output buffer circuit group 160 corresponding to the second shift register group receives the second Turn-on signal, that is, when the second shift register group works, its corresponding output buffer circuit group 160 works
  • the switch circuit 120 electrically connected to the first-stage shift register in the second shift register group receives the first shift register group.
  • the output buffer circuit group 160 corresponding to the second shift register group receives the second close signal, that is, the second shift register group does not work, and the corresponding output buffer circuit group 160 does not work.
  • the source driver 10 can turn on or off the shift register set 110 through the switch circuit 120, and the output buffer circuit set 160 corresponding to the shift register set 110 is also turned on or off accordingly, thereby correcting
  • the number of data output channels of the source driver 10 is adjusted to adapt to the display panel 100 of various resolutions.
  • the corresponding output buffer circuit group 160 may not work under the control of the second off signal, so that the output buffer circuit group 160 does not need to work. The working state is always maintained, thereby reducing the power consumption of the source driver 10.
  • the output buffer circuit group 160 can improve the driving capability of the source driver 10, that is, the load capability of the source driver 10.
  • the output buffer circuit group 160 corresponding to the target shift register group is configured to be controlled by the second turn-on signal , Output the analog grayscale signal transmitted by the gating circuit 140 at different time periods, or output the first reference signal, or output the second reference signal; and, stop working under the control of the second off signal.
  • the scanning time of a row of sub-pixels P described above also includes a threshold voltage compensation stage.
  • the output buffer circuit group 160 corresponding to the target shift register group outputs analog grayscale signals under the control of the second turn-on signal; in the blanking of a row of sub-pixels P In the stage, the output buffer circuit group 160 corresponding to the target shift register group outputs the first reference signal under the control of the second turn-on signal; in the threshold voltage compensation stage of a row of sub-pixels P, the output corresponding to the target shift register group The buffer circuit group 160 outputs the second reference signal under the control of the second turn-on signal.
  • the output buffer circuit group 160 corresponding to the first shift register group is configured to output the analog gray scale signal transmitted by the gate circuit 140, or output the first reference signal, or output the second reference signal in different time periods.
  • the output buffer circuit group 160 corresponding to the first shift register group outputs analog grayscale signals; in the blanking phase of a row of sub-pixels P, it is compared with the first shift register group.
  • the output buffer circuit group 160 corresponding to the bit register group outputs the first reference signal; in the threshold voltage compensation phase of a row of sub-pixels P, the output buffer circuit group 160 corresponding to the first shift register group outputs the second reference signal.
  • the source driver 10 further includes a plurality of data latch circuit groups 170.
  • a data latch circuit group 170 corresponds to a shift register group 110 and a digital-to-analog conversion circuit group.
  • the data latch circuit group 170 is configured to store digitized image data from the corresponding shift register group 110, and output the stored digitized image to the corresponding digital-to-analog conversion circuit group 150 under the control of the drive control signal STB data.
  • the drive control signal STB can be provided by the timing controller 20.
  • the output of the data latch circuit group 170 is a parallel output. It can be understood that since the shift registers in the shift register group 110 sequentially sample and output the digitized image data, that is, the output of the shift register group 110 is a serial output, therefore, the data latch circuit group 170 sequentially The digitized image data output by the corresponding shift register group 110 is latched.
  • each data latch circuit group 170 includes a plurality of data latch circuits, and the number of data latch circuits included in each data latch circuit group 170 corresponds to the data latch circuit group 170 The number of shift registers included in the shift register group 110 is positively correlated.
  • the number of data latch circuits in the data latch circuit group 170 may be the number of shift registers in the shift register group 110 corresponding to the data latch circuit group 170 multiplied by the sample of the shift register group 110 The size of the data capacity. For example, if the data capacity sampled by the shift register group 110 is 80 bits, and the shift register group 110 includes 24 shift registers, the corresponding data latch circuit group 170 has at least 1920 data latch circuits. In this case, if the data is transmitted in 10 bits, there are 192 output channels corresponding to the shift register group 110 and the data latch circuit group 170.
  • the source driver 10 further includes a level conversion circuit 180, which is electrically connected to a plurality of data latch circuits 170 and a plurality of digital-to-analog conversion circuits. Between groups of 150.
  • the level conversion circuit 180 is configured to convert the low-level digitized image data from the data latch circuit group 170 into high-level digitized image data, and output it to the digital-to-analog data corresponding to the data latch circuit group 170 Switching circuit group 150.
  • the output of the level conversion circuit 180 is a parallel output.
  • the level conversion circuit 180 converts low-level digitized image data into high-level digitized image data, so as to be suitable for the voltage of the driving transistor in the pixel driving circuit T.
  • the source driver 10 further includes a data processor 190.
  • the data processor 190 is electrically connected to a plurality of shift register groups 110.
  • the data processor 190 is configured to preprocess the digitized image data from the timing controller 20 and output the preprocessed digitized image data to the plurality of shift register groups 110.
  • the pre-processing includes data reverse processing, serial-to-parallel conversion processing, and data exchange (SWAP) functions on the digitized image data.
  • SWAP data exchange
  • the data processor 190 processes digital signals. Compared with arranging the data processor 190 at the input end of the output buffer circuit group 160 to process analog signals, the speed and accuracy of signal processing can be improved. . In addition, arranging the data processor 190 in a low-voltage area can reduce the area of the transistor and reduce the size of the source driver 10 compared to arranging it in a high-voltage area.
  • the source driver 10 further includes a plurality of interface circuits 101.
  • a plurality of interface circuits 101 are electrically connected to the data processor 190.
  • the interface circuit 101 is configured to convert image data from the timing controller 20 into digitized image data, and output the converted digitized image data to the data processor 190.
  • the plurality of sub-pixels P include at least first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels, and the number of interface circuits 101 corresponding to each color sub-pixel is N.
  • the number of interface circuits 101 is 3N, and N is a positive integer.
  • N interface circuits 101 are used to receive the image data to be displayed by the first color sub-pixels
  • the other N interface circuits 101 are used to receive the image data to be displayed by the second color sub-pixels
  • the remaining N interface circuits 101 are used to receive The image data to be displayed by the third color sub-pixel.
  • the first color, the second color, and the third color are three primary colors.
  • the number of interface circuits 101 is 4N, and the N interface circuits 101 are used to receive the image data to be displayed by the first color sub-pixels.
  • N interface circuits 101 are used to receive the image data to be displayed by the second color sub-pixel, and the other N interface circuits 101 are used to receive the image data to be displayed by the third color sub-pixel, and the remaining N interface circuits 101 are used to receive the image data to be displayed by the third color sub-pixel.
  • the fourth color is white.
  • each interface circuit 101 may all have the same structure.
  • each of the multiple interface circuits 101 can be adjusted according to the position of the sub-pixel P in the display panel 100, which is not limited in the present disclosure.
  • the present disclosure does not limit the interface type of the interface circuit 101, and those skilled in the art can set it according to the actual situation.
  • the interface circuit 101 may include a Mini Low Voltage Differential Signaling (Mini-LVDS) interface, a Point-to-Point (P2P) interface, and the like.
  • Mini-LVDS Mini Low Voltage Differential Signaling
  • P2P Point-to-Point
  • the switch circuit 120 includes an inverter F, a first transmission gate 121 and a second transmission gate 122.
  • the first transfer gate 121 includes a first P-type transistor MP1 and a first N-type transistor MN1.
  • the gate of the first N-type transistor MN1 is electrically connected to the input terminal of the inverter F and the enable control circuit 130, and the gate of the first P-type transistor MP1 is electrically connected to the output terminal of the inverter F.
  • the shift register of the last stage in the n-1th shift register group is electrically connected to the first pole of the first P-type transistor MP1 and the first pole of the first N-type transistor MN1.
  • the first-stage shift register is electrically connected to the second pole of the first P-type transistor MP1 and the second pole of the first N-type transistor MN1, where n ⁇ 2 and is a positive integer.
  • the second transfer gate 122 includes a second P-type transistor MP2 and a second N-type transistor MN2.
  • the gate of the second P-type transistor MP2 is electrically connected to the input terminal of the inverter F and the enable control circuit 130, and the gate of the second N-type transistor MN2 is electrically connected to the output terminal of the inverter F.
  • the shift register of the last stage in the n-1th shift register group is electrically connected to the first pole of the second P-type transistor MP2 and the first pole of the second N-type transistor MN2.
  • the display panel 100 includes a plurality of cascaded source drivers 10, except for the last source driver 10, in each switch circuit 120 of the other source drivers 10, the second P-type transistor
  • the second electrode and the second electrode of the second N-type transistor are electrically connected to the next source driver 10; specifically, the second electrode of the second P-type transistor and the second electrode of the second N-type transistor are connected to the next source.
  • the first shift register in the first shift register group in the driver is electrically connected.
  • the "next source driver 10" refers to the next source driver 10 of the source driver 10 where the second P-type transistor and the second N-type transistor are located.
  • the second pole of the second P-type transistor and the second pole of the second N-type transistor may not be electrically connected to other devices, that is, in a floating state.
  • the second electrode of the second P-type transistor and the second electrode of the second N-type transistor may not be connected with other devices. Electrically connected, that is, in a floating state.
  • the first turn-on signal from the enable control circuit 130 is at a high level, the first N-type transistor MN1 is turned on, and the high-level first turn-on signal becomes low through the inverter F. Level, the first P-type transistor MP1 is turned on, and the second P-type transistor MP2 is turned off. The high-level first turn-on signal is changed to a low level through the inverter F, so that the second N-type transistor MN2 is turned off.
  • the first transmission gate 121 is opened, and the last shift register in the previous shift register group is connected to the first shift register in the next shift register group.
  • the latter shift register group receives the second start signal DIO2 output by the previous shift register group as the first start signal DIO1 of the latter shift register group, and the latter shift register group starts to work.
  • the first turn-off signal from the enable control circuit 130 is at a low level
  • the first N-type transistor MN1 is turned off, and the low-level first turn-off signal is changed to a high level through the inverter F, so that the first turn-off signal A P-type transistor MP1 is turned off.
  • the second P-type transistor MP2 is turned on, and the low-level first off signal is changed to a high level through the inverter F, so that the second N-type transistor MN1 is turned on.
  • the first transmission gate 121 is disconnected, and the last shift register in the previous shift register group is disconnected from the first shift register in the next shift register group. Turn on, so that the latter group of shift registers does not work.
  • the second transmission gate 122 is turned on, and the second start signal DIO2 output by the previous shift register group is transmitted to the first shift register group in the first shift register group in the next-level source driver through the second transmission gate 122.
  • the bit register is used as the first start signal DIO1 of the first shift register group in the next-level source driver, and the first shift register group starts to work.
  • the display panel 100 further includes a flexible printed circuit (Flexible Printed Circuit, FPC for short) and a printed circuit board (Printed Circuit Board, PCB for short), and the printed circuit board is bound to the display panel 100 through the flexible circuit board. (Bonding).
  • the timing controller 20 may be integrated on a printed circuit board, and the source driver 10 may be arranged on a flexible circuit board.
  • the display panel 100 further includes at least one of the grayscale controller 30, the power supply circuit and other components, at least one of the grayscale controller 30, the power supply circuit and other components may also be integrated on the printed circuit board. on.
  • the display panel 100 includes a plurality of sub-pixels P, at least one source driver, and a timing controller.
  • Each sub-pixel P includes a pixel driving circuit T.
  • the source driver 10 is the source driver 10 described in any one of the above embodiments.
  • the source driver 10 further includes a gate circuit 140 and a plurality of digital-to-analog conversion circuit groups 150
  • select The pass circuit 140 is electrically connected to at least a plurality of digital-to-analog conversion circuit groups 150 and the first reference signal terminal Vref1.
  • the scanning time of a row of sub-pixels P includes a data writing phase and a blanking phase.
  • the control method of the display panel 100 includes:
  • the enable control circuit 130 of the source driver 10 outputs the first on signal or the first off signal to the switch circuit 120 under the control of the enable control signal from the timing controller 20.
  • the shift register 110 of the source driver 10 samples the digitized image data and outputs the sampled digitized image data under the control of the first start signal DIO1 from the timing controller 20 or the previous shift register group.
  • the switch circuit 120 when the switch circuit 120 is turned on under the control of the first turn-on signal, the shift register of the last stage in the n-1th shift register group and the first stage in the nth shift register group are shifted. Register connection, the first start signal DIO1 of the nth shift register group is output by the n-1th shift register group, and the nth shift register group starts sampling. Under the control of the first closing signal, the switch circuit 120 disconnects the last stage of shift register in the n-1th shift register group from the first stage of shift register in the nth shift register group, and the nth shift register is disconnected from the first shift register in the nth shift register group. The bit register bank will not be sampled.
  • the first shift register group samples the digitized image data under the control of the first start signal DIO1 from the timing controller 20, and the last shift register in the first shift register group samples the digitized image data.
  • the second start signal DIO2 is output as the first start signal DIO1 of the second shift register group.
  • the last-stage shift register in the first shift register group is electrically connected to the first-stage shift register in the second shift register group through a switch circuit 120, when the switch circuit 120 is under the control of the first turn-on signal When it is turned on, the second shift register group will receive the second start signal DIO2 output by the first shift register group as the first start signal DIO1 to start sampling; when the switch circuit 120 receives the first When the signal is turned off, the second shift register group is disconnected from the first shift register group, and the second shift register group does not perform sampling.
  • the last shift register in the first shift register group is directly connected to the first shift register in the second shift register group, then at the end of the sampling of the first shift register group, the second shift register The bit register set directly starts sampling.
  • the digital-to-analog conversion circuit group 150 of the source driver 10 converts the digitized image data from the corresponding shift register group 110 into an analog gray-scale signal according to the gamma signal GMA from the gray-scale controller 30 , And output analog gray-scale signals.
  • the gate circuit 140 outputs the analog gray-scale signal from the digital-to-analog conversion circuit group 150, and the pixel driving circuit T receives the analog gray-scale signal from the source driver 10.
  • the gate circuit 140 outputs the first reference signal transmitted by the first reference signal terminal Vref1.
  • the gate circuit 140 is also electrically connected to the second reference signal terminal Vref2.
  • the scanning time of a row of sub-pixels P also includes a threshold voltage compensation stage.
  • the control method of the display panel 100 further includes: in the threshold voltage compensation stage, the gating circuit 140 outputs the second reference signal transmitted by the second reference signal terminal Vref2; the pixel driving circuit T receives the second reference signal to control the pixel driving circuit T
  • the drive transistors in the device perform threshold voltage compensation.
  • the pixel driving circuit T included in the sub-pixel P includes a first transistor M1, a second transistor M2, a driving transistor DT, and a capacitor C.
  • the gate of the first transistor M1 is connected to the first gate line G1
  • the first electrode of the first transistor M1 is connected to the data line DL
  • the second electrode of the first transistor M1 is connected to the gate of the driving transistor DT.
  • the gate of the second transistor M2 is connected to the second gate line G2, the first electrode of the second transistor M2 is connected to the detection signal line SL, and the second electrode of the second transistor M2 is connected to the second electrode of the driving transistor DT.
  • the first electrode of the driving transistor DT is connected to the first voltage terminal VDD
  • the second electrode of the driving transistor DT is connected to the first electrode of the light emitting device L
  • the second electrode of the light emitting device L is grounded.
  • the first electrode of the capacitor C is connected to the gate of the driving transistor DT
  • the second electrode of the capacitor C is connected to the second electrode of the driving transistor DT.
  • first transistor M1, the second transistor M2, and the driving transistor DT may be N-type transistors or P-type transistors; they may be enhancement-type transistors or depletion-type transistors;
  • the first electrode of M1, the second transistor M2, and the driving transistor DT may be the source and the second electrode may be the drain, or the first electrode of the above-mentioned transistor may be the drain and the second electrode may be the source. limited.
  • the present disclosure takes as an example that the first transistor M1, the second transistor M2 and the driving transistor DT are all N-type transistors.
  • the scanning time of a row of sub-pixels P includes: a blanking phase, a reset phase, a threshold voltage compensation phase, a data writing phase, and a light-emitting phase.
  • the first transistor M1 and the second transistor M2 are turned off, and the source driver 10 transmits the first reference signal output by the gate circuit 140 to the data line DL, so that the voltage of the signal in the data line DL is the same as that of the first reference signal.
  • the voltage V ref1 of the reference signal is the same.
  • the driving transistor DT is turned off, and the light emitting device L does not emit light.
  • the source driver 10 transmits the second reference signal output by the gate circuit 140 to the data line DL, so that the voltage of the signal in the data line DL is converted to the voltage Vref2 of the second reference signal.
  • the first transistor M1 is turned on, and the gate voltage Vg of the driving transistor DT reaches the voltage V ref2 of the second reference signal.
  • the second transistor M2 is turned on, and the signal from the detection signal line SL is transmitted to the source of the driving transistor DT through the second transistor M2, so that the source voltage V s of the driving transistor DT is the voltage V of the signal from the detection signal line SL SL .
  • the driving transistor DT is turned on.
  • the voltage of the first pole of the light-emitting device L is the voltage V SL of the signal from the detection signal line SL.
  • the voltage V SL of the signal from the detection signal line SL controls the light-emitting device L to not Glow. Based on this, the skilled artisan can satisfy the light emitting device does not emit light L condition, the voltage V ref2 is set to the second reference signal and the amplitude voltage V SL of the detection signal from the signal line SL.
  • the first transistor M1 remains on and the second transistor M2 is off.
  • the source voltage V s gradually changes from V SL in the reset phase Change to V ref2 -V th
  • the driving transistor DT is gradually turned off, that is, the gate-source voltage difference V gs of the driving transistor DT gradually changes from V ref2 -V SL to the threshold voltage V th of the driving transistor DT, thus completing the pairing of the driving transistor the threshold voltage V th DT detection, and to ensure that the subsequent write pixel data phase, capable of driving transistor DT is the threshold voltage V th compensated to eliminate the effects of the driving transistor DT is the threshold voltage V th of the actual driver.
  • the light emitting device L does not emit light.
  • the first transistor M1 is kept on, the second transistor M2 is off, and the source driver 10 transmits the analog grayscale signal output from the digital-to-analog conversion circuit 150 from the gate circuit 140 to the data line DL,
  • the analog gray-scale signal is written into the pixel driving circuit.
  • the voltage of the gate of the driving transistor DT is the voltage V data of the analog gray-scale signal, and at the same time, the analog gray-scale signal is stored in the capacitor C. In this case, the driving transistor DT is turned on.
  • the source voltage V s of the driving transistor DT V ref2 -V th
  • the gate voltage V g V data
  • K is the conductivity constant.
  • both the first transistor M1 and the second transistor M2 are turned off.
  • the capacitor C continuously discharges the gate of the driving transistor DT, the driving transistor DT remains on, and the light emitting device L emits light.
  • the transistors used in the circuits provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors can be used in the internal circuits of the display panel; in integrated circuit ICs, such as the source driver 10 and the timing controller 20, field effect transistors can be used.
  • control electrode of each transistor used in the circuit provided by the embodiment of the present disclosure is the gate of the transistor, one of the source and drain of the transistor on the first pole, and the other of the source and drain of the transistor on the second pole.
  • the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain, The second pole is the source.

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Abstract

一种源极驱动器（10），包括多个移位寄存器组（110）、使能控制电路（130）、以及至少一个开关电路（120）。每个移位寄存器组（110）包括多级移位寄存器（110A）。移位寄存器组（110）对数字化图像数据进行采样；第n个移位寄存器组（110）的第一起始信号由第n-1个移位寄存器组（110）输出，n≥2且n为正整数。使能控制电路（130）输出第一开启信号或第一关闭信号。至少一个开关电路（120）与使能控制电路（130）电连接。相邻两个移位寄存器组（110）中，前一个移位寄存器组（110）中最后一级移位寄存器与后一个移位寄存器组（110）中第一级移位寄存器之间通过一个开关电路（120）电连接。该源极驱动器（10）能够适应多种分辨率的显示面板（100），降低功耗。

Description

源极驱动器、显示面板及其控制方法、显示装置
本申请要求于2019年12月05日提交的、申请号为201911236632.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种源极驱动器、显示面板及其控制方法、显示装置。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置凭借其自发光、发光效率高、效应时间短、使用温度范围宽等特点，成为显示技术领域的主流显示装置之一。根据驱动方式，OLED显示装置可分为PMOLED(Passive matrix Organic Light-emitting Diode，无源矩阵有机发光二极管)显示装置和AMOLED(Active-Matrix Organic Light-emitting Diode，有源矩阵有机发光二极管)显示装置两大类。其中，AMOLED显示装置具有超轻薄、宽视角、低功耗、响应快、色彩逼真等特点，被广泛应用于手机、电视、平板等显示产品。并且，AMOLED发光效率高，适用于高清晰度大尺寸的显示产品。
公开内容
一方面，提供一种源极驱动器，包括依次级联的多个移位寄存器组、使能控制电路、以及至少一个开关电路。
每个移位寄存器组包括依次级联的多级移位寄存器。所述移位寄存器组被配置为，在第一起始信号的控制下，对数字化图像数据进行采样；第n个移位寄存器组的所述第一起始信号由第n-1个移位寄存器组输出，n≥2且n为正整数。
所述使能控制电路被配置为，在来自时序控制器的使能控制信号的控制下，输出第一开启信号或第一关闭信号。
至少一个开关电路与所述使能控制电路电连接。相邻两个所述移位寄存器组中，前一个移位寄存器组中最后一级移位寄存器与后一个移位寄存器组中第一级移位寄存器之间通过一个所述开关电路电连接；所述开关电路被配置为，在来自所述使能控制电路的所述第一开启信号的控制下，将所述前一个移位寄存器组与所述后一个移位寄存器组连通；以及，在来自所述使能控制电路的所述第一关闭信号的控制下，将所述前一个移位寄存器组与所述后一个移位寄存器组之间断开。
在一些实施例中，所述源极驱动器还包括多个数模转换电路组和选通电路。
一个数模转换电路组与一个所述移位寄存器组相对应。所述数模转换电路组被配置为，根据来自灰阶控制器的伽马信号，将来自与其对应的移位寄存器组的数字化图像数据，转换为模拟灰阶信号，并输出所述模拟灰阶信号。
选通电路至少与各所述数模转换电路组和第一参考信号端电连接。所述选通电路被配置为，在不同时段输出来自所述数模转换电路组的模拟灰阶信号，或者输出所述第一参考信号端所传输的第一参考信号。
在一些实施例中，所述选通电路还与第二参考信号端电连接。所述选通电路被配置为，在不同时段输出来自所述数模转换电路的模拟灰阶信号，或者输出所述第一参考信号端所传输的第一参考信号，或者输出所述第二参考信号端所传输的第二参考信号。
在一些实施例中，所述第一参考信号的电压大于所述模拟灰阶信号的最小电压，且小于所述模拟灰阶信号的最大电压。
在一些实施例中，所述源极驱动器还包括多个输出缓冲电路组，每个所述输出缓冲电路组与所述选通电路电连接，一个输出缓冲电路组与一个所述移位寄存器组相对应。除与第一个移位寄存器组对应的输出缓冲电路组外，其余输出缓冲电路与所述使能控制电路电连接。
所述至少一个开关电路中，接收所述使能控制电路所输出的第一开启信号的开关电路为目标开关电路。与所述目标开关电路电连接，且通过所述目标开关电路接收第一起始信号的移位寄存器组为目标移位寄存器组。
所述使能控制电路还被配置为，在向目标开关电路输出所述第一开启信号的情况下，在来自所述时序控制器的使能控制信号的控制下，向与所述目标移位寄存器组对应的输出缓冲电路组，输出第二开启信号或第二关闭信号。
与所述目标移位寄存器组对应的输出缓冲电路组被配置为，在所述第二开启信号的控制下，在不同时段输出所述选通电路所传输的所述模拟灰阶信号，或者输出所述第一参考信号；以及，在所述第二关闭信号的控制下停止工作。
与第一个移位寄存器组对应的输出缓冲电路组被配置为，在不同时段输出所述选通电路所传输的所述模拟灰阶信号，或者输出所述第一参 考信号。
在一些实施例中，在所述选通电路还与所述第二参考信号端电连接的情况下，与所述目标移位寄存器组对应的输出缓冲电路组被配置为，在所述第二开启信号的控制下，在不同时段输出所述选通电路所传输的所述模拟灰阶信号，或者输出所述第一参考信号，或者输出所述第二参考信号；以及，在所述第二关闭信号的控制下停止工作。
与第一个移位寄存器组对应的输出缓冲电路组被配置为，在不同时段输出所述选通电路所传输的所述模拟灰阶信号，或者输出所述第一参考信号，或者输出所述第二参考信号。
在一些实施例中，所述源极驱动器还包括多个数据锁存电路组，一个数据锁存电路组与一个所述移位寄存器组及一个数模转换电路组相对应。所述数据锁存电路组被配置为，存储来自与其对应的移位寄存器组输出的数字化图像数据，并在驱动控制信号的控制下向与其对应的数模转换电路组输出所存储的数字化图像数据。
在一些实施例中，每个所述数据锁存电路组包括多个数据锁存电路，每个所述数据锁存电路组所包括的数据锁存电路的数量，与该数据锁存电路组对应的移位寄存器组所包括的移位寄存器的数量正相关。
在一些实施例中，所述源极驱动器还包括电平转换电路，电连接于所述多个数据锁存电路组与所述多个数模转换电路组之间。所述电平转换电路被配置为，将来自所述数据锁存电路组的低电平的数字化图像数据，转化为高电平的数字化图像数据，并输出至与所述数据锁存电路组对应的所述数模转换电路组。
在一些实施例中，所述源极驱动器还包括数据处理器，与所述多个移位寄存器组电连接。所述数据处理器被配置为，对数字化图像数据进行预处理，并将经过预处理的数字化图像数据输出至所述多个移位寄存器组。
在一些实施例中，所述源极驱动器还包括多个接口电路，与所述数据处理器电连接。所述接口电路被配置为，将来自所述时序控制器的图像数据转换为数字化图像数据，并将转换得到的数字化图像数据输出至所述数据处理器。
在一些实施例中，所述开关电路包括反相器、第一传输门和第二传输门。
所述第一传输门包括第一P型晶体管和第一N型晶体管，所述第一N型晶体管的栅极与所述反相器的输入端和所述使能控制电路电连接， 所述第一P型晶体管的栅极与所述反相器的输出端电连接。
第n-1个移位寄存器组中最后一级移位寄存器与所述第一P型晶体管的第一极和所述第一N型晶体管的第一极电连接，第n个移位寄存器组中第一级移位寄存器与所述第一P型晶体管的第二极和所述第一N型晶体管的第二极电连接，n≥2。
所述第二传输门包括第二P型晶体管和第二N型晶体管，所述第二P型晶体管的栅极与所述反相器的输入端和所述使能控制电路电连接，所述第二N型晶体管的栅极与所述反相器的输出端电连接。
第n-1个移位寄存器组中最后一级移位寄存器与所述第二P型晶体管的第一极和所述第二N型晶体管的第一极电连接。
另一方面，提供一种显示面板，具有显示区和周边区。所述显示面板包括设置于所述周边区的至少一个源极驱动器，所述源极驱动器为上述任一实施例所述的源极驱动器，以及设置于所述周边区的时序控制器。
所述时序控制器与所述源极驱动器电连接。所述时序控制器被配置为，向一个所述源极驱动器的第一个移位寄存器组传输第一起始信号；以及，向各所述源极驱动器的使能控制电路传输使能控制信号。
在一些实施例中，在所述显示面板包括多个源极驱动器的情况下，所述多个源极驱动器依次级联；
所述开关电路被配置为，在来自所述使能控制电路的所述第一关闭信号的控制下，将所述前一个移位寄存器组与所述后一个移位寄存器组之间断开，并且将所述前一个移位寄存器组与下一个源极驱动器的第一个移位寄存器组连通。
在一些实施例中，所述显示面板还包括位于所述显示区的多个亚像素和多条数据线。每个亚像素包括像素驱动电路，所述源极驱动器通过至少一条数据线与多个所述像素驱动电路电连接。
另一方面，提供一种显示装置，包括上述任一实施例所述的显示面板。
另一方面，提供一种显示面板的控制方法，其中，所述显示面板包括多个亚像素、至少一个源极驱动器和时序控制器，每个所述亚像素包括像素驱动电路。所述源极驱动器为上述任一实施例所述的源极驱动器，所述源极驱动器还包括选通电路和多个数模转换电路组，所述选通电路至少与所述多个数模转换电路组和第一参考信号端电连接。
一行亚像素的扫描时间包括数据写入阶段和消隐阶段，所述显示面板的控制方法包括：
所述源极驱动器的使能控制电路在来自所述时序控制器的使能控制信号的控制下，向所述开关电路输出第一开启信号或第一关闭信号；
所述源极驱动器的移位寄存器组在来自所述时序控制器或者上一个移位寄存器组的的第一起始信号的控制下，对数字化图像数据进行采样，并输出采样得到的数字化图像数据；
所述源极驱动器的数模转换电路组根据来自灰阶控制器的伽马信号，将来自与其对应的移位寄存器组的数字化图像数据，转换为模拟灰阶信号，并输出所述模拟灰阶信号；
在所述数据写入阶段，所述选通电路输出来自所述数模转换电路组的模拟灰阶信号；所述像素驱动电路接收来自所述源极驱动器的模拟灰阶信号；
在所述消隐阶段，所述选通电路输出所述第一参考信号端所传输的第一参考信号。
在一些实施例中，所述选通电路还与第二参考信号端电连接，一行亚像素的扫描时间还包括阈值电压补偿阶段。所述显示面板的控制方法还包括：
在所述补偿阶段，所述选通电路输出所述第二参考信号端所传输的第二参考信号；所述像素驱动电路接收所述第二参考信号，以对所述像素驱动电路中的驱动晶体管进行阈值电压补偿。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开的一些实施例的显示面板的结构图；
图2为根据本公开的一些实施例的像素驱动电路的结构图；
图3为本公开的一些实施例的一种源极驱动器的结构图；
图4为图3中P处的局部放大图；
图5为根据本公开的一些实施例的另一种源极驱动器的结构图；
图6为根据本公开的一些实施例的又一种源极驱动器的结构图；
图7为根据本公开的一些实施例的又一种源极驱动器的结构图；
图8为根据本公开的一些实施例的又一种源极驱动器的结构图；
图9为根据本公开的一些实施例的开关电路的结构图；
图10为根据本公开的一些实施例的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“电连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“电连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本公开实施例提供了一种显示装置，如图10所示，显示装置200包括显示面板100。
在一些实施例中，显示装置200还包括框架、电路板、显示驱动IC(Integrated Circuit，简称IC)以及其他电子配件等。上述显示面板100设置 于框架内。
本公开实施例所提供的显示装置200可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
上述显示面板100可以为AMOLED显示面板。
在一些实施例中，如图1所示，显示面板100具有显示区AA(也称Active Area，中文名称为有源显示区)和周边区S。示例的，周边区S可围绕显示区AA一圈设置。
显示面板100包括位于显示区AA的多个亚像素P和多条数据线DL。需要说明的是，图1中以上述多个亚像素P呈阵列形式排列为例进行示意，但本公开的实施例不限于此，上述多个亚像素还可以以其他方式进行排布。
如图1所示，每个亚像素P包括像素驱动电路T。
在一些实施例中，如图2所示，亚像素P中还设置有发光器件L，像素驱动电路T与发光器件L电连接，以驱动发光器件L发光。示例的，发光器件L为OLED。
其中，像素驱动电路T一般由薄膜晶体管(Thin Film Transistor，简称TFT)、电容(Capacitance，简称C)等电子器件组成。例如，如图2所示，像素驱动电路T可以是由三个TFT和一个电容构成的3T1C结构的像素驱动电路。
在此基础上，在一些实施例中，如图1所示，显示面板100的周边区S设置有至少一个源极驱动器10和时序控制器20，时序控制器20与每个源极驱动器10电连接。
并且，源极驱动器10通过至少一条数据线DL与多个像素驱动电路T电连接，源极驱动器10被配置为接收数字化图像数据，并对数字化图像数据进行处理。其中，源极驱动器10对数字化图像数据进行处理的过程将在后面进行描述。
示例的，每个源极驱动器10可通过多条数据线DL与多个像素驱动电路T电连接，每条数据线DL的一端与源极驱动器10的一个数据输出通道(即向数据线DL输出数据的接口)电连接，另一端与多个像素驱动电路T电连接。
例如，如图1所示，每个源极驱动器10通过多条数据线DL与多列亚像素P中的各像素驱动电路T电连接，其中，一条数据线DL与一列亚像素P中的各像素驱动电路T电连接。
源极驱动器10的工作受时序控制器20的控制。若显示面板100包括一个源极驱动器10，则时序控制器20被配置为，向该源极驱动器10传输第一起始信号，以控制该源极驱动器10对所接收数字化图像数据进行处理。若显示面板100包括多个源极驱动器10，所述多个源极驱动器10依次级联，则时序控制器20被配置为，向级联的多个源极驱动器10中的第一个源极驱动器10传输第一起始信号，以控制该源极驱动器10对所接收数字化图像数据进行处理。
在一些实施例中，如图1所示，显示面板100的周边区S还设置有灰阶控制器30，灰阶控制器30与每个源极驱动器10和时序控制器20电连接。
灰阶控制器30被配置为，在根据来自时序控制器20的显示图像中亚像素的灰阶数据，向源极驱动器10输出伽马信号。
在上述的基础上，本公开实施例提供一种源极驱动器，如图3～图8所示，该源极驱动器10包括：依次级联的多个移位寄存器组110、至少一个开关电路120、以及使能控制电路130。
其中，如图3和图4所示，每个移位寄存器组110包括依次级联的多级移位寄存器110A。移位寄存器组110被配置为，在来自时序控制器20的第一起始信号DIO1的控制下，对数字化图像数据进行采样。
示例的，每个移位寄存器组110中移位寄存器110A的个数相同。
示例的，每个移位寄存器组110中移位寄存器110A的个数不完全相同。例如，至少有一个移位寄存器组110中移位寄存器110A的个数与其它移位寄存器组110中移位寄存器110A的个数不相同。
在此基础上，时序控制器20被配置为，向一个源极驱动器10的第一个移位寄存器组传输第一起始信号DIO1，以控制源极驱动器10中的移位寄存器组110对数字化图像数据进行采样；以及，向各源极驱动器10的使能控制电路130传输使能控制信号。若显示面板100包括一个源极驱动器10，则时序控制器20向该源极驱动器10的第一个移位寄存器组传输第一起始信号 DIO1。若显示面板100包括多个源极驱动器10，则时序控制器20向所述多个源极驱动器10中的一个源极驱动器10的第一个移位寄存器组传输第一起始信号DIO1。示例的，在所述多个源极驱动器10依次级联的情况下，时序控制器20向第一个源极驱动器10传输第一起始信号。
需要说明的是，在显示面板100包括多个依次级联的源极驱动器10的情况下，第一个源极驱动器中第一个移位寄存器组的第一起始信号DIO1来自于时序控制器20，除第一个源极驱动器，每个源极驱动器的第一个移位寄存器组的第一起始信号DIO1来自于上一个源极驱动器所输出的第二起始信号DIO2。
并且，每个移位寄存器组110中最后一级移位寄存器在采样结束后，输出第二起始信号DIO2，该第二起始信号DIO2作为下一个移位寄存器组的第一起始信号DIO1，即，第n个移位寄存器组的第一起始信号DIO1由第n-1个移位寄存器组输出，n≥2且n为正整数。
使能控制电路130被配置为，在来自时序控制器20的使能控制信号的控制下，输出第一开启信号或者第一关闭信号。第一开启信号和第一关闭信号被输出至开关电路120，用于控制开关电路120的工作状态。其中，关于开关电路的工作状态将在后面进行介绍。
其中，第一开启信号可以是高电平信号，第一关闭信号可以是低电平信号；或者，第一开启信号可以是低电平信号，第一关闭信号可以是高电平信号。第一开启信号和第一关闭信号是高电平信号还是低电平信号，这取决于开关电路120的工作状态所需要的电平信号是高电平信号还是低电平信号。
需要说明的是，使能控制电路130接收的来自时序控制器20的使能控制信号可以是高电平信号，也可以是低电平信号，这取决于使能控制电路130输出第一开启信号或者第一关闭信号所需要的电平信号是高电平信号还是低电平信号。根据上述可知，第一开启信号和第一关闭信号用于控制开关电路120的工作状态，开关电路120的工作状态与进行采样的移位寄存器组110的个数有关(后面进行介绍)；并且，进行采样的移位寄存器组110的个数越多，与源极驱动器10具有的数据输出通道个数越多，显示面板100的分辨率越大。因此，使能控制信号是高电平信号还是低电平信号，与显示面板100的分辨率、源极驱动器10具有的数据输出通道个数等因素有关。
每个开关电路120与使能控制电路130电连接。如图4所示，相邻两个移位寄存器组110中，前一个移位寄存器组中最后一级移位寄存器与后一个移位寄存器组中第一级移位寄存器之间通过一个开关电路120电连接。
开关电路120被配置为，在来自使能控制电路130的第一开启信号的控制下，将前一个移位寄存器组与后一个移位寄存器组连通，以将前一个移位寄存器组所输出的第二起始信号DIO2传输至后一个移位寄存器组，作为后一个移位寄存器组的第一起始信号DIO1(这是开关电路120的一种工作状态)；以及，在来自使能控制电路130的第一关闭信号的控制下，将前一个移位寄存器组与后一个移位寄存器组之间断开(这是开关电路120的另一种工作状态)。
可以理解的是，在开关电路120的个数为一个的情况下，该开关电路120可以位于任意一对相邻两个移位寄存器组之间(如图4所示)，即，第n-1个移位寄存器组中最后一级移位寄存器与第n个移位寄存器组中第一级移位寄存器之间通过一个开关电路120级联。在此情况下，第一个至第n-1个移位寄存器组依次级联，第n个至最后一个移位寄存器组依次级联。
在开关电路120有多个的情况下，可以是第奇数个移位寄存器组中最后一级移位寄存器和，与其相邻的第偶数个移位寄存器组中第一级移位寄存器之间，通过一个开关电路120电连接。例如，如图6所示，多个移位寄存器组110中最左侧的为第一个移位寄存器组，最右侧的为最后一个移位寄存器组，第一个移位寄存器组中最后一级移位寄存器与第二个移位寄存器组中第一级移位寄存器通过一个开关电路120电连接，第二个移位寄存器组中最后一级移位寄存器与第三个移位寄存器组中第一级移位寄存器直接连接。
或者，可以是第偶数个移位寄存器组中最后一级移位寄存器和，与其相邻的第奇数个移位寄存器组中第一级移位寄存器之间，通过一个开关电路120电连接。例如，如图7所示，多个移位寄存器组110中最左侧的为第一个移位寄存器组，最右侧的为最后一个移位寄存器组，第二个移位寄存器组中最后一级移位寄存器与第三个移位寄存器组中第一级移位寄存器通过一个开关电路120电连接，第一个移位寄存器组中最后一级移位寄存器与第二个移位寄存器组中第一级移位寄存器直接连接。
或者，如图8所示，每相邻两个移位寄存器组110中，前一个移位寄存器组中最后一级移位寄存器与后一个移位寄存器组中第一级移位寄存器之间通过一个开关电路120电连接。
可以理解的是，除了第一个移位寄存器组以外，其余各个移位寄存器组均可以通过开关电路120，与其前一个移位寄存器组级联。
在此基础上，第n-1个移位寄存器组在第一起始信号DIO1的控制下，对数字化图像数据进行采样，第n个移位寄存器组最后一级移位寄存器将采样 的数字化图像数据输出，并且输出的第二起始信号DIO2。
若第n-1个移位寄存器组和第n个移位寄存器组之间的开关电路120所接收的来自使能控制电路130的信号为第一开启信号，则开关电路120在第一开启信号的控制下，开关电路120将第n-1个移位寄存器组输出的第二起始信号DIO2传输至第n个移位寄存器组，作为第n个移位寄存器组的第一起始信号DIO1，控制第n个移位寄存器组对数字化图像数据进行采样。
在源极驱动器10中，若第n-1个移位寄存器组和第n个移位寄存器组之间的开关电路120所接收的来自使能控制电路130的信号为第一关闭信号，则开关电路120在第一关闭信号的控制下，开关电路120将第n-1个移位寄存器组输出的第二起始信号DIO2输出至与该源极驱动器10级联的下一级源极驱动器中第一个移位寄存器组，作为下一级源极驱动器中第一个移位寄存器组的第一起始信号DIO1。
可以理解的是，在显示面板100包括多个依次级联的源极驱动器10的情况下，除第一级源极驱动器，每级源极驱动器将其前一级源极驱动器输出的第二起始信号DIO2作为该源极驱动器中第一个移位寄存器组的第一起始信号DIO1。
示例的，源极驱动器10中第一个移位寄存器组和第二个移位寄存器组之间的开关电路120在第一关闭信号的控制下，第一个移位寄存器组输出的第二起始信号DIO2，不会传输至第二个移位寄存器组，而是传输至与该源极驱动器10级联的下一级源极驱动器10中第一个移位寄存器组，作为下一级源极驱动器10中第一个移位寄存器组的第一起始信号DIO1。在此情况下，该源极驱动器10从第二个至最后一个移位寄存器组均不工作，下一级源极驱动器10中第一个移位寄存器组开始进行采样。在源极驱动器10中第一个至最后一个移位寄存器组均进行采样的情况下，源极驱动器10中的开关电路120均处于开启状态，最后一个移位寄存器组在采样结束时输出第二起始信号DIO2，作为下一级源极驱动器中第一个移位寄存器组的第一起始信号DIO1，使得下一级源极驱动器中移位寄存器组逐级进行采样。
在相关技术中，源极驱动器包括多个移位寄存器，通过多个移位寄存器进行采样，其数据输出通道的个数是固定的。而本公开上述实施例，源极驱动器包括多个移位寄存器组110，且每个移位寄存器组110中包括多个移位寄存器(可理解为相关技术中的源极驱动器仅包括一个移位寄存器组)，可以通过开关电路120选择进行采样的移位寄存器组110的个数，从而对源极驱动器10的数据输出通道的个数进行调整：当显示面板100分辨率较大时，开 启较多的移位寄存器组110，增加源极驱动器10的数据输出通道；当显示面板100分辨率较小时，开启较少的移位寄存器组110，减少源极驱动器10的数据输出通道，从而使得源极驱动器10可以适应多种分辨率的显示面板100。
示例的，在每个移位寄存器组110中均有24级移位寄存器的情况下，第一个移位寄存器组在来自于时序控制器20的第一起始信号DIO1的控制下，从第一级至第24级移位寄存器依次进行采样，串行输出24个采样的数字化图像数据，并在第24级移位寄存器输出采样的数字化图像数据后输出第二起始信号DIO2，作为第二个移位寄存器组的第一起始信号DIO1。
进而，位于第一个移位寄存器组中第24级移位寄存器和第二个移位寄存器组中第一级移位寄存器之间的一个开关电路120，在第一开启信号的控制下导通，将由第一个移位寄存器组输出的第二起始信号DIO2作为第二个移位寄存器组的第一起始信号DIO1，传输至第二个移位寄存器组中第一级移位寄存器，使得第二个移位寄存器组中第一级至第24级移位寄存器依次进行采样，串行输出24个采样的数字化图像数据，并在第24级移位寄存器输出采样的数字化图像数据后输出第二起始信号DIO2，作为第三个移位寄存器组的第一起始信号DIO1。
在此基础上，如果位于第二个移位寄存器组中第24级移位寄存器和第三个移位寄存器组中第一级移位寄存器之间的一个开关电路120接收到第一关闭信号，则第三个移位寄存器组不会接收到由第二个移位寄存器组输出的第二起始信号DIO2，作为第三个移位寄存器组的第一起始信号DIO1，即，第三个移位寄存器组不工作，且从第三个至最后一个移位寄存器组均不会工作，该源极驱动器10只有第一个移位寄存器组和第二个移位寄存器组工作，输出48个采样的数字化图像数据。因此，可以通过开关电路120选取进行采样的移位寄存器组的个数，在选取n个移位寄存器组进行采样，且每个移位寄存器组包括m个移位寄存器(m为大于1的正整数)的情况下，源极驱动器10可以输出m×n个采样的数字化图像数据。
需要说明的是，上述的第一个移位寄存器组和最后一个移位寄存器组是相对的，移位寄存器组110中第一级移位寄存器和最后一级移位寄存器也是相对的，均是根据移位寄存器组的正向采样和反向采样而定。
例如，在源极驱动器10接收到的来自时序控制器20的方位信号SHL(Select High or Low)为高电平时，图8中的源极驱动器10中从第一个移位寄存器组至最后一个移位寄存器组依次进行正向采样，即，图8中的移位寄存器组110从左至右进行采样，在此情况下，第一个移位寄存器组中第一级 移位寄存器接收来自于时序控制器20的第一起始信号DIO1，第一个移位寄存器组中最后一级移位寄存器输出第二起始信号DIO2，作为第二个移位寄存器组的第一起始信号DIO1。
又例如，在方位信号SHL为低电平时，图9中的源极驱动器10中从最后一个移位寄存器组至第一个移位寄存器组依次进行反向采样，即，图9的中的移位寄存器组110从右至左进行采样，在此情况下，最后一个移位寄存器组中最后一级移位寄存器可以看成第一个移位寄存器组中第一级移位寄存器，接收来自于时序控制器20的第一起始信号DIO1，最后一个移位寄存器组中第一级移位寄存器可以看成第一个移位寄存器组中最后一级移位寄存器，输出第二起始信号DIO2。
综上所述，本公开的上述实施例，源极寄存器10包括依次级联的多个移位寄存器组110、至少一个开关电路120以及使能控制电路130，每个移位寄存器组110包括依次级联的多级移位寄存器，在相邻两个移位寄存器组110中，前一个移位寄存器组中最后一级移位寄存器与后一个移位寄存器组中第一级移位寄存器之间通过一个开关电路120电连接，可通过使能控制电路130所输出的第一开启信号或第一关闭信号控制开关电路120的开启或关闭，进而控制前一个移位寄存器组与后一个移位寄存器组连通或断开。因此，可通过控制开关电路120的工作状态选择进行采样的移位寄存器组110的个数，对源极驱动器10的数据输出通道的个数进行调整，当显示面板100分辨率较大时，开启多个移位寄存器组110，增加源极驱动器10的数据输出通道，当显示面板100分辨率较小时，开启较少的移位寄存器组110，减少源极驱动器10的数据输出通道，从而使得源极驱动器10可以适应各个分辨率的显示面板100，提高源极驱动器10的兼容性。
在一些实施例中，如图3～图8所示，源极驱动器10还包括选通电路140和多个数模转换电路组150。
其中，一个数模转换电路组150与一个移位寄存器组110相对应。
可以理解的是，数模转换电路组150和移位寄存器组110的数量相同。
数模转换电路组150被配置为，根据来自灰阶控制器30的伽马信号GMA，将来自与其对应的移位寄存器组110的数字化图像数据，转换为模拟灰阶信号并输出。
选通电路140至少与数模转换电路组150和第一参考信号端Vref1电连接。选通电路140被配置为，在不同时段输出来自数模转换电路组150的模拟灰阶信号，或者输出第一参考信号端Vref1所传输的第一参考信号。
其中，在一些实施例中，显示面板100还包括电源电路，电源电路用于向显示面板100中的多个部件(例如源极驱动器10、时序控制器20、灰阶控制器30等部件)提供电能。基于此，上述第一参考信号可以是由该电源电路提供。
在一些实施例中，数模转换电路组150包括多个数模转换电路，且每个数模转换电路组150所包括的数模转换电路的数量，与该数模转换电路组150对应的移位寄存器组110所包括的移位寄存器的数量正相关。例如，每个数模转换电路组150所包括的数模转换电路的数量，是与该数模转换电路组150对应的移位寄存器组110所包括的移位寄存器的数量的整数倍。
一行亚像素P的扫描时间包括数据写入阶段和消隐阶段，在此基础上，在数据写入阶段，选通电路140输出来自数模转换电路组150的模拟灰阶信号，以使像素驱动电路T进行数据写入。在消隐阶段，选通电路140输出第一参考信号，对数据线DL进行预充，使得数据线DL上的信号的电压等于第一参考信号的电压。
在一些实施例中，第一参考信号的电压大于模拟灰阶信号的最小电压，且小于模拟灰阶信号的最大电压。即，第一参考信号的电压介于模拟灰阶信号的电压的最大值和最小值之间。
可以理解的是，模拟灰阶信号的电压的最小值和最大值之间的范围，可称为模拟灰阶信号的电压的幅值范围。
示例的，模拟灰阶信号的电压的幅值范围为0V～12V，第一参考信号的电压为5V，介于0V～12V之间。
在未对各数据线DL进行预充的情况下，各数据线DL中信号的电压发生最大变化所需的时间，即各数据线DL中信号的电压由0V变换至12V所需的时间，为最大翻转时间。相较于此，本公开的上述实施例，在一行亚像素P的消隐阶段，对各数据线DL进行预充，使得各数据线DL上的信号的电压为5V，当来自数模转换电路组150的模拟灰阶信号传输至数据线DL时，各数据线DL中信号的电压发生最大变化是由5V变换至12V，即各数据线DL中信号的电压由5V变换至12V所需的时间为最大翻转时间，由于各数据线DL中信号的电压发生最大变化的范围缩小，因此缩短了显示面板100中的各数据线DL中信号的电压最大翻转的时间，提高了显示面板的刷新频率。
在一些实施例中，如图3～图8所示，选通电路140与数模转换电路组150的输出端、第一参考信号端Vref1和第二参考信号端Vref2电连接。
选通电路140被配置为，在不同时段输出来自数模转换电路组150的模 拟灰阶信号、或者输出第一参考信号端Vref1所传输的第一参考信号、或者输出第二参考信号端Vref2所传输的第二参考信号。第二参考信号可以是由上述电源电路提供。
在选通电路140还与第二参考信号端Vref2电连接的情况下，一行亚像素P的扫描时间还包括阈值电压补偿阶段。在阈值电压补偿阶段，选通电路140输出第二参考信号。在此情况下，像素驱动电路T可以根据第二参考信号对像素驱动电路T中的驱动晶体管进行阈值电压补偿。
需要说明的是，上述选通电路140接收多个信号(即模拟灰阶信号、第一参考信号和第二参考信号)，在某一时段输出接收的多个信号中的一个信号，以实现选通电路140的选通功能。在此基础上，能够实现上述的选通功能的电路均可以作为本公开实施例中的选通电路140，本公开在此对选通电路140的具体结构不做限定，本领域技术人员可以根据实际情况进行设置。
在此基础上，可选的，源极驱动器10还包括带隙基准电路，该带隙基准电路与上述电源电路电连接，以接收电源电路所传输的第一参考信号或第二参考信号。并且，带隙基准电路还与第一参考信号端Vref1和第二参考信号端Vref2电连接，带隙基准电路被配置为分别通过第一参考信号端Vref1和第二参考信号端Vref2向选通电路140提供第一参考信号和第二参考信号。
在一些实施例中，如图3～图8所示，源极驱动器10还包括多个输出缓冲电路组160。
其中，每个输出缓冲电路组160与选通电路140电连接，且一个输出缓冲电路组160与一个移位寄存器组110相对应。除与第一个移位寄存器组对应的输出缓冲电路组160外，其余输出缓冲电路组160与使能控制电路130电连接。
可以理解的是，输出缓冲电路组160与数模转换电路组150的数量相同。一个输出缓冲电路组160的输出端与一条数据线DL电连接。
在一些实施例中，每个输出缓冲电路组160包括多个输出缓冲电路，每个输出缓冲电路组160所包括的输出缓冲电路的数量，与该输出缓冲电路组160对应的移位寄存器组110所包括的移位寄存器的数量正相关。例如，每个输出缓冲电路组160所包括的输出缓冲电路的数量，是与该输出缓冲电路组160对应的移位寄存器组110所包括的移位寄存器的数量的整数倍。
需要说明的是，源极驱动器10所包括的全部移位寄存器组110中，并不一定每个移位寄存器组110均通过开关电路120接收第一起始信号 DIO1。以下称至少一个开关电路120中，接收使能控制电路130所输出的第一开启信号的开关电路为目标开关电路；与目标开关电路电连接，且通过目标开关电路接收第一起始信号DIO1的移位寄存器组110为目标移位寄存器组。
使能控制电路130还被配置为，在向目标开关电路输出第一开启信号的情况下，在来自时序控制器20的使能控制信号的控制下，向与目标移位寄存器组对应的输出缓冲电路组160，输出第二开启信号或者第二关闭信号。
与目标移位寄存器组对应的输出缓冲电路组160被配置为，在第二开启信号的控制下，在不同时段输出选通电路140所传输的模拟灰阶信号，或者输出第一参考信号；以及，在第二关闭信号的控制下停止工作，即输出缓冲电路组160停止输出选通电路140所传输的信号。
示例的，在一行亚像素P的数据写入阶段，与目标移位寄存器组对应的输出缓冲电路组160在第二开启信号的控制下，输出模拟灰阶信号；在一行亚像素P的消隐阶段，与目标移位寄存器组对应的输出缓冲电路组160在第二开启信号的控制下，输出第一参考信号。
与第一个移位寄存器组对应的输出缓冲电路组160被配置为，在不同时段输出选通电路140所传输的模拟灰阶信号，或者输出第一参考信号。需要说明的是，与第一个移位寄存器组对应的输出缓冲电路组160不与使能控制电路130电连接，因此其不受使能控制电路130所输出的信号的控制。
示例的，在一行亚像素P的数据写入阶段，与第一个移位寄存器组对应的输出缓冲电路组160输出模拟灰阶信号；在一行亚像素P的消隐阶段，与第一个移位寄存器组对应的输出缓冲电路组160输出第一参考信号。
需要说明的是，输出缓冲电路组160接收的第二开启信号或者第二关闭信号，与输出缓冲电路组160对应的目标移位寄存器组110所电连接的目标开关电路120接收的第一开启信号或者第一关闭信号有关。在一些实施例中，由于输出缓冲电路组160工作在源极驱动器10的高电压侧，开关电路120工作在源极驱动器10的低电压侧，因此可设置第一开启信号的电压低于第二开启信号的电压，第一关闭信号的电压低于第二关闭信号的电压，以保证输出缓冲电路组160和开关电路120均能有效地打开或关闭。
可以理解的是，当移位寄存器组110通过开关电路120接收第一起始信号DIO1处于工作状态时，该移位寄存器组110对应的输出缓冲电路组160也开始工作，当移位寄存器组110通过开关电路120未接收到第一起始信号DIO1 处于不工作状态时，该移位寄存器组110对应的输出缓冲电路组160也不工作。
例如，第二个移位寄存器组中第一级移位寄存器所电连接的开关电路120接收的是第一开启信号，第二个移位寄存器组对应的输出缓冲电路组160接收的是第二开启信号，即，第二个移位寄存器组工作，其对应的输出缓冲电路组160工作；第二个移位寄存器组中第一级移位寄存器所电连接的开关电路120接收的是第一关闭信号，第二个移位寄存器组对应的输出缓冲电路组160接收的是第二关闭信号，即，第二个移位寄存器组不工作，其对应的输出缓冲电路组160不工作。
在此基础上，源极驱动器10可以通过开关电路120，使得移位寄存器组110的开启或关闭，则与该移位寄存器组110对应的输出缓冲电路组160也相应的开启或关闭，从而对源极驱动器10的数据输出通道的个数进行调整，以适应各个分辨率的显示面板100。并且，当无需工作的移位寄存器组110在开关电路120的作用下处于关闭状态时，其对应的输出缓冲电路组160可以在第二关闭信号的控制下不工作，使得输出缓冲电路组160无需一直保持工作状态，从而降低源极驱动器10的功耗。
并且，输出缓冲电路组160可以提高源极驱动器10的驱动能力，即，源极驱动器10的带负载能力。
在一些实施例中，在选通电路140还与第二参考信号端Vref2电连接的情况下，与目标移位寄存器组对应的输出缓冲电路组160被配置为，在第二开启信号的控制下，在不同时段输出选通电路140所传输的模拟灰阶信号，或者输出第一参考信号，或者输出第二参考信号；以及，在第二关闭信号的控制下停止工作。并且，在选通电路140还与第二参考信号端Vref2电连接的情况下，前文所述的一行亚像素P的扫描时间还包括阈值电压补偿阶段。
示例的，在一行亚像素P的数据写入阶段，与目标移位寄存器组对应的输出缓冲电路组160在第二开启信号的控制下，输出模拟灰阶信号；在一行亚像素P的消隐阶段，与目标移位寄存器组对应的输出缓冲电路组160在第二开启信号的控制下，输出第一参考信号；在一行亚像素P的阈值电压补偿阶段，与目标移位寄存器组对应的输出缓冲电路组160在第二开启信号的控制下，输出第二参考信号。
与第一个移位寄存器组对应的输出缓冲电路组160被配置为，在不同时段输出选通电路140所传输的模拟灰阶信号，或者输出第一参考信 号，或者输出第二参考信号。
示例的，在一行亚像素P的数据写入阶段，与第一个移位寄存器组对应的输出缓冲电路组160输出模拟灰阶信号；在一行亚像素P的消隐阶段，与第一个移位寄存器组对应的输出缓冲电路组160输出第一参考信号；在一行亚像素P的阈值电压补偿阶段，与第一个移位寄存器组对应的输出缓冲电路组160输出第二参考信号。
在一些实施例中，如图3～图8所示，源极驱动器10还包括多个数据锁存电路组170。
其中，一个数据锁存电路组170与一个移位寄存器组110及一个数模转换电路组相对应。
可以理解的是，数据锁存电路组170与移位寄存器110的数量相同。
数据锁存电路组170被配置为，存储来自与其对应的移位寄存器组110的数字化图像数据，并在驱动控制信号STB的控制下向与其对应的数模转换电路组150输出所存储的数字化图像数据。其中，驱动控制信号STB可由时序控制器20提供。
需要说明的是，数据锁存电路组170的输出为并行输出。可以理解的是，由于移位寄存器组110中的移位寄存器依次对数据化图像数据进行采样和输出，即，移位寄存器组110的输出为串行输出，因此，数据锁存电路组170依次锁存对应的移位寄存器组110输出的数字化图像数据。
在一些实施例中，每个数据锁存电路组170包括多个数据锁存电路，且每个数据锁存电路组170所包括的数据锁存电路的数量，与该数据锁存电路组170对应的移位寄存器组110所包括的移位寄存器的数量正相关。
示例的，数据锁存电路组170中数据锁存电路的个数可以为该数据锁存电路组170对应的移位寄存器组110中移位寄存器的个数乘以该移位寄存器组110所采样的数据容量的大小。例如，移位寄存器组110所采样的数据容量为80bit，且该移位寄存器组110包括24个移位寄存器，则其对应的数据锁存电路组170中至少有1920个数据锁存电路，在此情况下，若数据以10bit传输，则该移位寄存器组110和数据锁存电路组170所对应的输出通道为192个。
在一些实施例中，如图3～图8所示，源极驱动器10还包括电平转换电路180，电平转换电路180电连接于多个数据锁存电路170组与多个数模转换电路组150之间。
电平转换电路180被配置为，将来自数据锁存电路组170的低电平的数 字化图像数据，转化为高电平的数字化图像数据，并输出至与数据锁存电路组170对应的数模转换电路组150。
需要说明的是，电平转换电路180的输出为并行输出。
可以理解的是，电平转换电路180将低电平的数字化图像数据转化为高电平的数字化图像数据，以适用于像素驱动电路T中驱动晶体管的电压。
在一些实施例中，如图3～图8所示，源极驱动器10还包括数据处理器190。
其中，数据处理器190与多个移位寄存器组110电连接。
数据处理器190被配置为，对来自于时序控制器20的数字化图像数据进行预处理，并将经过预处理的数字化图像数据输出至多个移位寄存器组110。
示例的，该预处理包括对数字化图像数据进行数据反向处理、串并转换处理、实现数据交换(SWAP)功能等。
可以理解的是，数据处理器190是对数字信号进行处理，相比于将数据处理器190设置在输出缓冲电路组160的输入端之前对模拟信号进行处理，能够提高对信号处理的速度和精度。并且，将数据处理器190设置在低电压区域，相比于设置在高电压区域，可以减小晶体管的面积，缩小源极驱动器10的尺寸。
在此基础上，在一些实施例中，如图3～图8所示，源极驱动器10还包括多个接口电路101。
其中，多个接口电路101与数据处理器190电连接。
接口电路101被配置为，将来自时序控制器20的图像数据转换为数字化图像数据，并将转换得到的数字化图像数据输出至数据处理器190。
可以理解的是，在多个亚像素P至少包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素，且每种颜色的亚像素所对应的接口电路101的数量为N个的情况下，接口电路101的个数为3N个，N为正整数。其中，N个接口电路101用于接收第一颜色亚像素所要显示的图像数据，另外N个接口电路101用于接收第二颜色亚像素所要显示的图像数据，其余N个接口电路101用于接收第三颜色亚像素所要显示的图像数据。例如，第一颜色、第二颜色和第三颜色为三基色。
同理，在多个亚像素还包括第四颜色亚像素的情况下，接口电路101的个数为4N个，其中，N个接口电路101用于接收第一颜色亚像素所要显示的图像数据，另外N个接口电路101用于接收第二颜色亚像素所要显示的图像数据，另外N个接口电路101用于接收第三颜色亚像素所要显示的图像数据， 其余N个接口电路101用于接收第四颜色亚像素所要显示的图像数据。例如，第四颜色为白色。
其中，各接口电路101可以均具有相同结构。
需要说明的是，多个接口电路101各自接收的图像数据可以根据显示面板100中亚像素P的位置进行调整，本公开在此不做限定。并且，本公开对接口电路101的接口类型也不做限定，本领域技术人员可以根据实际情况进行设置。
示例的，接口电路101可以包括微型低压差分信号(Mini Low Voltage Differential Signaling，简称Mini-LVDS)接口、点到点(Point-to-Point，简称P2P)接口等。
在一些实施例中，开关电路120包括反相器F、第一传输门121和第二传输门122。
如图9所示，第一传输门121包括第一P型晶体管MP1和第一N型晶体管MN1。
其中，第一N型晶体管MN1的栅极与反相器F的输入端和使能控制电路130电连接，第一P型晶体管MP1的栅极与反相器F的输出端电连接。
第n-1个移位寄存器组中最后一级移位寄存器与第一P型晶体管MP1的第一极和第一N型晶体管MN1的第一极电连接，第n个移位寄存器组中第一级移位寄存器与第一P型晶体管MP1的第二极和第一N型晶体管MN1的第二极电连接，n≥2且为正整数。
第二传输门122包括第二P型晶体管MP2和第二N型晶体管MN2。
第二P型晶体管MP2的栅极与反相器F的输入端和使能控制电路130电连接，第二N型晶体管MN2的栅极与反相器F的输出端电连接。
第n-1个移位寄存器组中最后一级移位寄存器与第二P型晶体管MP2的第一极和第二N型晶体管MN2的第一极电连接。
需要说明的是，在显示面板100包括多个级联的源极驱动器10的情况下，除最后一个源极驱动器10外，其余源极驱动器10的各开关电路120中，第二P型晶体管的第二极和第二N型晶体管的第二极与下一个源极驱动器10电连接；具体的，第二P型晶体管的第二极和第二N型晶体管的第二极与下一个源极驱动器中的第一个移位寄存器组中第一级移位寄存器电连接。其中，所述“下一个源极驱动器10”是指，该第二P型晶体管和该第二N型晶体管所在的源极驱动器10的下一个源极驱动器10。最后一个源极驱动器10的各开关电路120中，第二P型晶体管的第二极和第二N型 晶体管的第二极可以不与其他器件电连接，即处于浮置状态(Floating)。
在显示面板100包括一个源极驱动器10的情况下，该源极驱动器10的各开关电路120中，第二P型晶体管的第二极和第二N型晶体管的第二极可以不与其他器件电连接，即处于浮置状态。
可以理解的是，在来自使能控制电路130的第一开启信号为高电平的情况下，第一N型晶体管MN1开启，该高电平的第一开启信号通过反相器F变为低电平，使得第一P型晶体管MP1开启，第二P型晶体管MP2截止，该高电平的第一开启信号通过反相器F变为低电平，使得第二N型晶体管MN2截止。此时，相邻两个移位寄存器组110中，第一传输门121开启，前一个移位寄存器组中最后一级移位寄存器与后一个移位寄存器组中第一级移位寄存器连接，使得后一个移位寄存器组接收前一个移位寄存器组输出的第二起始信号DIO2，作为后一个移位寄存器组的第一起始信号DIO1，后一个移位寄存器组开始工作。
在来自使能控制电路130的第一关闭信号为低电平的情况下，第一N型晶体管MN1截止，该低电平的第一关闭信号通过反相器F变为高电平，使得第一P型晶体管MP1截止。第二P型晶体管MP2开启，该低电平的第一关闭信号通过反相器F变为高电平，使得第二N型晶体管MN1开启。此时，相邻两个移位寄存器组110中，第一传输门121断开，前一个移位寄存器组中最后一级移位寄存器与后一个移位寄存器组中第一级移位寄存器断开，使得后一个移位寄存器组不工作。第二传输门122开启，前一个移位寄存器组输出的第二起始信号DIO2通过第二传输门122，传输至下一级源极驱动器中的第一个移位寄存器组中第一级移位寄存器，作为该下一级源极驱动器中的第一个移位寄存器组的第一起始信号DIO1，该第一个移位寄存器组开始工作。
在一些实施例中，显示面板100还包括柔性线路板(Flexible Printed Circuit，简称FPC)和印制电路板(Printed Circuit Board，简称PCB)，印制电路板通过柔性线路板与显示面板100绑定(Bonding)。其中，时序控制器20可以集成在印制电路板上，源极驱动器10可以设置在柔性线路板上。此外，在显示面板100还包括灰阶控制器30、电源电路等部件中的至少一者的情况下，灰阶控制器30、电源电路等部件中的至少一者也可集成在印制电路板上。
在此基础上，本公开实施例提供一种显示面板的控制方法，如图1所示，显示面板100包括多个亚像素P、至少一个源极驱动器和时序控制器。每个亚像素P包括像素驱动电路T。
参考图3～图8，源极驱动器10为上述任一实施例所述的源极驱动器10， 在源极驱动器10还包括选通电路140和多个数模转换电路组150的情况下，选通电路140至少与多个数模转换电路组150和第一参考信号端Vref1电连接，一行亚像素P的扫描时间包括数据写入阶段和消隐阶段，显示面板100的控制方法包括：
源极驱动器10的使能控制电路130在来自时序控制器20的使能控制信号的控制下，向开关电路120输出第一开启信号或第一关闭信号。
源极驱动器10的移位寄存器110在来自时序控制器20或者上一个移位寄存器组的第一起始信号DIO1的控制下，对数字化图像数据进行采样，并输出采样得到的数字化图像数据。
可以理解的是，开关电路120在第一开启信号的控制下开启时，使得第n-1个移位寄存器组中最后一级移位寄存器与第n个移位寄存器组中第一级移位寄存器连接，第n个移位寄存器组的第一起始信号DIO1由第n-1个移位寄存器组输出，第n个移位寄存器组开始进行采样。开关电路120在第一关闭信号的控制下，第n-1个移位寄存器组中最后一级移位寄存器与第n个移位寄存器组中第一级移位寄存器断开，第n个移位寄存器组不会进行采样。
例如，第一个移位寄存器组在来自时序控制器20的第一起始信号DIO1的控制下，对数字化图像数据进行采样，在第一个移位寄存器组中最后一级移位寄存器在采样结束的同时输出第二起始信号DIO2，作为第二个移位寄存器组的第一起始信号DIO1。
如果第一个移位寄存器组中最后一级移位寄存器与第二个移位寄存器组中第一级移位寄存器通过一个开关电路120电连接，当开关电路120在第一开启信号的控制下开启时，第二个移位寄存器组才会接收到由第一个移位寄存器组输出的第二起始信号DIO2，作为第一起始信号DIO1，开始进行采样；当开关电路120接收到第一关闭信号时，第二个移位寄存器组与第一个移位寄存器组断开，第二个移位寄存器组不进行采样。
如果第一个移位寄存器组中最后一级移位寄存器与第二个移位寄存器组中第一级移位寄存器直接连接，那么在第一个移位寄存器组采样结束时，第二个移位寄存器组直接开始进行采样。
在此基础上，源极驱动器10的数模转换电路组150根据来自灰阶控制器30的伽马信号GMA，将来自与其对应的移位寄存器组110的数字化图像数据，转换为模拟灰阶信号，并输出模拟灰阶信号。
在数据写入阶段：选通电路140输出来自数模转换电路组150的模拟灰阶信号，像素驱动电路T接收来自源极驱动器10的模拟灰阶信号。
在消隐阶段：选通电路140输出第一参考信号端Vref1所传输的第一参考信号。
在此基础上，参考图3～图8，选通电路140还与第二参考信号端Vref2电连接，在此情况下，一行亚像素P的扫描时间还包括阈值电压补偿阶段。
显示面板100的控制方法还包括：在阈值电压补偿阶段，选通电路140输出第二参考信号端Vref2所传输的第二参考信号；像素驱动电路T接收第二参考信号，以对像素驱动电路T中的驱动晶体管进行阈值电压补偿。
以下，结合图2中的像素驱动电路T，对上述的显示面板100的每个亚像素P的驱动方法进行详细说明。
其中，如图2所示，亚像素P所包括的像素驱动电路T包括第一晶体管M1、第二晶体管M2、驱动晶体管DT以及电容C。其中，第一晶体管M1的栅极与第一栅线G1连接，第一晶体管M1的第一极与数据线DL连接，第一晶体管M1的第二极与驱动晶体管DT的栅极连接。第二晶体管M2的栅极与第二栅线G2连接，第二晶体管M2的第一极与侦测信号线SL连接，第二晶体管M2的第二极与驱动晶体管DT的第二极连接。驱动晶体管DT的第一极与第一电压端VDD连接，驱动晶体管DT的第二极与发光器件L的第一极连接，发光器件L的第二极接地。电容C的第一极与驱动晶体管DT的栅极连接，电容C的第二极与驱动晶体管DT的第二极连接。
需要说明的是，上述第一晶体管M1、第二晶体管M2和驱动晶体管DT可以为N型晶体管，也可以为P型晶体管；可以为增强型晶体管，也可以为耗尽型晶体管；上述第一晶体管M1、第二晶体管M2和驱动晶体管DT的第一极可以为源极，第二极可以为漏极，或者上述晶体管的第一极可以为漏极，第二极为源极，本公开对此不作限定。
此外，本公开以上述第一晶体管M1、第二晶体管M2和驱动晶体管DT均为N型晶体管为例进行说明。
在此基础上，一行亚像素P的扫描时间包括：消隐阶段、重置阶段、阈值电压补偿阶段、数据写入阶段、发光阶段。
在一行的消隐阶段，第一晶体管M1和第二晶体管M2截止，源极驱动器10将选通电路140输出的第一参考信号传输至数据线DL，使得数据线DL中信号的电压与第一参考信号的电压V ref1相同。此时，驱动晶体管DT截止，发光器件L不发光。
在一行的重置阶段：源极驱动器10将选通电路140输出的第二参考信号传输至数据线DL，使得数据线DL中信号的电压变换至第二参考信 号的电压V ref2。第一晶体管M1开启，驱动晶体管DT的栅极电压Vg达到第二参考信号的电压V ref2。第二晶体管M2开启，来自侦测信号线SL的信号通过第二晶体管M2传输至驱动晶体管DT的源极，使得驱动晶体管DT的源极电压V s为来自侦测信号线SL的信号的电压V SL。其中，当驱动晶体管DT的栅源电压差V gs＝V ref2-V SL大于驱动晶体管DT的阈值电压V th时，驱动晶体管DT的开启。
需要说明的是，发光器件L的第一极的电压为来自侦测信号线SL的信号的电压V SL，在重置阶段该来自侦测信号线SL的信号的电压V SL控制发光器件L不发光。在此基础上，本领域技术人员可以在满足发光器件L不发光的条件下，设定第二参考信号的电压V ref2和来自侦测信号线SL的信号的电压V SL的幅值。
在一行的阈值电压补偿阶段：第一晶体管M1保持开启，第二晶体管M2截止，此时，驱动晶体管DT的栅极电压V g＝V ref2，源极电压V s从重置阶段的V SL逐渐变化至V ref2-V th，驱动晶体管DT逐渐截止，即，驱动晶体管DT的栅源电压差V gs由V ref2-V SL逐渐变为驱动晶体管DT的阈值电压V th，从而完成了对驱动晶体管DT的阈值电压V th的侦测，并且保证了后续在像素数据写入阶段，能够驱动晶体管DT的阈值电压V th进行补偿，以消除驱动晶体管DT的阈值电压V th对实际驱动的影响。此时，发光器件L不发光。
在一行的数据写入阶段：第一晶体管M1保持开启，第二晶体管M2截止，源极驱动器10将选通电路140输出的来自数模转换电路150的模拟灰阶信号，传输至数据线DL，使得模拟灰阶信号写入像素驱动电路，此时，驱动晶体管DT的栅极的电压为模拟灰阶信号的电压V data，同时，该模拟灰阶信号存储至电容C。在此情况下，驱动晶体管DT开启。
在此基础上，驱动晶体管DT的源极电压V s＝V ref2-V th，栅极电压V g＝V data，此时流经驱动晶体管DT的驱动电流I＝K×(V gs-V th) 2＝K×(V data-V ref2+V th-V th) 2＝K×(V data-V ref2) 2，K为导电常数。可以看出，此时流经驱动晶体管DT的驱动电流I与驱动晶体管DT的阈值电压V th无关，从而实现了对驱动晶体管DT的阈值电压V th的补偿，消除了驱动晶体管DT的阈值电压V th对实际驱动的影响。
在一行的发光阶段：第一晶体管M1和第二晶体管M2均截止。电容C对驱动晶体管DT的栅极持续放电，驱动晶体管DT保持开启，发光器件L发光。
本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件。其中，在显示面板的内部电路中，例如像素驱动电路、移位寄存器电路，可以采用薄膜晶体管；在集成电路IC中，例如源极驱动器10、时序控制器20，可以采用场效应晶体管。
并且，本公开的实施例提供的电路所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种源极驱动器，包括：
    依次级联的多个移位寄存器组，每个移位寄存器组包括依次级联的多级移位寄存器；所述移位寄存器组被配置为，在第一起始信号的控制下，对数字化图像数据进行采样；第n个移位寄存器组的所述第一起始信号由第n-1个移位寄存器组输出，n≥2且n为正整数；
    使能控制电路；所述使能控制电路被配置为，在来自时序控制器的使能控制信号的控制下，输出第一开启信号或第一关闭信号；
    至少一个开关电路，与所述使能控制电路电连接；相邻两个所述移位寄存器组中，前一个移位寄存器组中最后一级移位寄存器与后一个移位寄存器组中第一级移位寄存器之间通过一个所述开关电路电连接；所述开关电路被配置为，在来自所述使能控制电路的所述第一开启信号的控制下，将所述前一个移位寄存器组与所述后一个移位寄存器组连通；以及，在来自所述使能控制电路的所述第一关闭信号的控制下，将所述前一个移位寄存器组与所述后一个移位寄存器组之间断开。
  2. 根据权利要求1所述的源极驱动器，还包括：
    多个数模转换电路组，一个数模转换电路组与一个所述移位寄存器组相对应；所述数模转换电路组被配置为，根据来自灰阶控制器的伽马信号，将来自与其对应的移位寄存器组的数字化图像数据，转换为模拟灰阶信号，并输出所述模拟灰阶信号；
    选通电路，至少与各所述数模转换电路组和第一参考信号端电连接；所述选通电路被配置为，在不同时段输出来自所述数模转换电路组的模拟灰阶信号，或者输出所述第一参考信号端所传输的第一参考信号。
  3. 根据权利要求2所述的源极驱动器，其中，所述选通电路还与第二参考信号端电连接；
    所述选通电路被配置为，在不同时段输出来自所述数模转换电路的模拟灰阶信号，或者输出所述第一参考信号端所传输的第一参考信号，或者输出所述第二参考信号端所传输的第二参考信号。
  4. 根据权利要求3所述的源极驱动器，所述第一参考信号的电压大于所述模拟灰阶信号的最小电压，且小于所述模拟灰阶信号的最大电压。
  5. 根据权利要求2～4中任一项所述的源极驱动器，还包括：
    多个输出缓冲电路组，每个输出缓冲电路组与所述选通电路电连接，一个输出缓冲电路组与一个所述移位寄存器组相对应；除与第一个移位 寄存器组对应的输出缓冲电路组外，其余输出缓冲电路组与所述使能控制电路电连接；
    所述至少一个开关电路中，接收所述使能控制电路所输出的第一开启信号的开关电路为目标开关电路；与所述目标开关电路电连接，且通过所述目标开关电路接收第一起始信号的移位寄存器组为目标移位寄存器组；
    所述使能控制电路还被配置为，在向所述目标开关电路输出所述第一开启信号的情况下，在来自所述时序控制器的使能控制信号的控制下，向与所述目标移位寄存器组对应的输出缓冲电路组输出第二开启信号或第二关闭信号；
    与所述目标移位寄存器组对应的输出缓冲电路组被配置为，在所述第二开启信号的控制下，在不同时段输出所述选通电路所传输的所述模拟灰阶信号，或者输出所述第一参考信号；以及，在所述第二关闭信号的控制下停止工作。
    与第一个移位寄存器组对应的输出缓冲电路组被配置为，在不同时段输出所述选通电路所传输的所述模拟灰阶信号，或者输出所述第一参考信号。
  6. 根据权利要求5所述的源极驱动器，其中，在所述选通电路还与所述第二参考信号端电连接的情况下，
    与所述目标移位寄存器组对应的输出缓冲电路组被配置为，在所述第二开启信号的控制下，在不同时段输出所述选通电路所传输的所述模拟灰阶信号，或者输出所述第一参考信号，或者输出所述第二参考信号；以及，在所述第二关闭信号的控制下停止工作。
    与第一个移位寄存器组对应的输出缓冲电路组被配置为，在不同时段输出所述选通电路所传输的所述模拟灰阶信号，或者输出所述第一参考信号，或者输出所述第二参考信号。
  7. 根据权利要求2～6中任一项所述的源极驱动器，还包括：
    多个数据锁存电路组，一个数据锁存电路组与一个所述移位寄存器组及一个数模转换电路组相对应；
    所述数据锁存电路组被配置为，存储来自与其对应的移位寄存器组的数字化图像数据，并在驱动控制信号的控制下向与其对应的数模转换电路组输出所存储的数字化图像数据。
  8. 根据权利要求7所述的源极驱动器，其中，每个所述数据锁存电 路组包括多个数据锁存电路，每个所述数据锁存电路组所包括的数据锁存电路的数量，与该数据锁存电路组对应的移位寄存器组所包括的移位寄存器的数量正相关。
  9. 根据权利要求7或8所述的源极驱动器，还包括：
    电平转换电路，电连接于所述多个数据锁存电路组与所述多个数模转换电路组之间；
    所述电平转换电路被配置为，将来自所述数据锁存电路组的低电平的数字化图像数据，转化为高电平的数字化图像数据，并输出至与所述数据锁存电路组对应的所述数模转换电路组。
  10. 根据权利要求1～9中任一项所述的源极驱动器，还包括：
    数据处理器，与所述多个移位寄存器组电连接；
    所述数据处理器被配置为，对数字化图像数据进行预处理，并将经过预处理的数字化图像数据输出至所述多个移位寄存器组。
  11. 根据权利要求10所述的源极驱动器，还包括：
    多个接口电路，与所述数据处理器电连接；
    所述接口电路被配置为，将来自所述时序控制器的图像数据转换为数字化图像数据，并将转换得到的数字化图像数据输出至所述数据处理器。
  12. 根据权利要求1～11中任一项所述的源极驱动器，其中，所述开关电路包括反相器、第一传输门和第二传输门；
    所述第一传输门包括第一P型晶体管和第一N型晶体管；
    所述第一N型晶体管的栅极与所述反相器的输入端和所述使能控制电路电连接，所述第一P型晶体管的栅极与所述反相器的输出端电连接；
    第n-1个移位寄存器组中最后一级移位寄存器与所述第一P型晶体管的第一极和所述第一N型晶体管的第一极电连接，第n个移位寄存器组中第一级移位寄存器与所述第一P型晶体管的第二极和所述第一N型晶体管的第二极电连接；
    所述第二传输门包括第二P型晶体管和第二N型晶体管；
    所述第二P型晶体管的栅极与所述反相器的输入端和所述使能控制电路电连接，所述第二N型晶体管的栅极与所述反相器的输出端电连接；
    第n-1个移位寄存器组中最后一级移位寄存器与所述第二P型晶体管的第一极和所述第二N型晶体管的第一极电连接。
  13. 一种显示面板，具有显示区和周边区；所述显示面板包括：
    设置于所述周边区的至少一个源极驱动器，所述源极驱动器为如权利要求1～12中任一项所述的源极驱动器；
    设置于所述周边区的时序控制器，所述时序控制器与所述源极驱动器电连接；所述时序控制器被配置为，向一个所述源极驱动器的第一个移位寄存器组传输第一起始信号；以及，向各所述源极驱动器的使能控制电路传输使能控制信号。
  14. 根据权利要求13所述的显示面板，其中，在所述显示面板包括多个源极驱动器的情况下，所述多个源极驱动器依次级联；
    所述开关电路被配置为，在来自所述使能控制电路的所述第一关闭信号的控制下，将所述前一个移位寄存器组与所述后一个移位寄存器组之间断开，并且将所述前一个移位寄存器组与下一个源极驱动器的第一个移位寄存器组连通。
  15. 根据权利要求13或14所述的显示面板，还包括：
    位于所述显示区的多个亚像素，每个亚像素包括像素驱动电路；
    多条数据线，所述源极驱动器通过至少一条数据线与多个所述像素驱动电路电连接。
  16. 一种显示装置，包括权利要求13～15中任一项所述的显示面板。
  17. 一种显示面板的控制方法，其中，所述显示面板包括多个亚像素、至少一个源极驱动器和时序控制器；每个亚像素包括像素驱动电路；
    所述源极驱动器为如权利要求1～12中任一项所述的源极驱动器；所述源极驱动器还包括选通电路和多个数模转换电路组，所述选通电路至少与所述多个数模转换电路组和第一参考信号端电连接；一行亚像素的扫描时间包括数据写入阶段和消隐阶段；
    所述显示面板的控制方法包括：
    所述源极驱动器的使能控制电路在来自所述时序控制器的使能控制信号的控制下，向所述开关电路输出第一开启信号或第一关闭信号；
    所述源极驱动器的移位寄存器组在来自所述时序控制器或者上一个移位寄存器组的第一起始信号的控制下，对数字化图像数据进行采样，并输出采样得到的数字化图像数据；
    所述源极驱动器的数模转换电路组根据来自灰阶控制器的伽马信号，将来自与其对应的移位寄存器组的数字化图像数据，转换为模拟灰阶信号，并输出所述模拟灰阶信号；
    在所述数据写入阶段，所述选通电路输出来自所述数模转换电路组 的模拟灰阶信号；所述像素驱动电路接收来自所述源极驱动器的模拟灰阶信号；
    在所述消隐阶段，所述选通电路输出所述第一参考信号端所传输的第一参考信号。
  18. 根据权利要求17所述的控制方法，其中，所述选通电路还与第二参考信号端电连接；一行亚像素的扫描时间还包括阈值电压补偿阶段；
    所述显示面板的控制方法还包括：
    在所述补偿阶段，所述选通电路输出所述第二参考信号端所传输的第二参考信号；所述像素驱动电路接收所述第二参考信号，以对所述像素驱动电路中的驱动晶体管进行阈值电压补偿。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110034166B (zh) 2019-03-26 2022-09-09 武汉华星光电半导体显示技术有限公司 有机发光二极管显示装置及其制造方法
CN110910834B (zh) 2019-12-05 2021-05-07 京东方科技集团股份有限公司 源极驱动器、显示面板及其控制方法、显示装置
CN111508448B (zh) * 2020-05-28 2022-03-18 京东方科技集团股份有限公司 显示面板及其控制方法
CN111599299B (zh) 2020-06-18 2023-12-12 京东方科技集团股份有限公司 电平转换电路、显示面板
CN112233604A (zh) 2020-10-15 2021-01-15 Tcl华星光电技术有限公司 显示面板及显示装置
CN113963664B (zh) * 2021-10-22 2022-12-09 晟合微电子(肇庆)有限公司 基于级联驱动芯片的显示方法、显示器及可读存储介质
CN114822409A (zh) 2022-06-24 2022-07-29 惠科股份有限公司 像素驱动电路、显示面板及显示装置
CN116486741B (zh) * 2023-03-31 2023-11-10 北京伽略电子股份有限公司 一种oled屏幕显示驱动电路
CN116301168B (zh) * 2023-05-22 2023-07-21 上海灵动微电子股份有限公司 带隙基准电路正常工作检测的标识电路
CN118298762B (zh) * 2024-06-06 2024-08-02 深圳市华星光电半导体显示技术有限公司 显示装置的画面调节方法及显示装置

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0493820A1 (en) * 1990-12-29 1992-07-08 Nec Corporation Driver circuit for liquid crystal display
CN1348167A (zh) * 2000-09-29 2002-05-08 株式会社东芝 液晶驱动电路和负载驱动电路
US20030043132A1 (en) * 2001-09-04 2003-03-06 Norio Nakamura Display device
CN1424821A (zh) * 2001-11-30 2003-06-18 夏普株式会社 信号线驱动电路和使用该电路的显示装置
CN1501706A (zh) * 2002-11-12 2004-06-02 夏普株式会社 数据信号线驱动方法、数据信号线驱动电路及显示装置
US20050068287A1 (en) * 2003-08-12 2005-03-31 Toppoly Optoelectronics Corp. Multi-resolution driver device
CN1766983A (zh) * 2004-10-28 2006-05-03 恩益禧电子股份有限公司 液晶显示设备及其驱动方法
CN1928635A (zh) * 2005-06-07 2007-03-14 三星电子株式会社 用于液晶显示器中的受控转变的设备和方法
US20070229438A1 (en) * 2006-04-04 2007-10-04 Dong Yong Shin Data driver and organic light emitting display using the same
CN100514417C (zh) * 2005-11-30 2009-07-15 三星移动显示器株式会社 数据驱动器、有机发光显示器和相应的驱动方法
CN101847378A (zh) * 2009-03-27 2010-09-29 北京京东方光电科技有限公司 源极驱动芯片
CN106157873A (zh) * 2016-08-31 2016-11-23 昆山工研院新型平板显示技术中心有限公司 一种栅极驱动装置、驱动方法及显示面板
CN110178174A (zh) * 2018-09-28 2019-08-27 华为技术有限公司 一种栅极驱动电路及其控制方法、移动终端
CN110910834A (zh) * 2019-12-05 2020-03-24 京东方科技集团股份有限公司 源极驱动器、显示面板及其控制方法、显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4679812B2 (ja) * 2002-11-07 2011-05-11 シャープ株式会社 走査方向制御回路および表示装置
TWI293446B (en) * 2004-11-30 2008-02-11 Himax Tech Ltd Power saving flat display and method thereof
US7907137B2 (en) * 2005-03-31 2011-03-15 Casio Computer Co., Ltd. Display drive apparatus, display apparatus and drive control method thereof
JP5238230B2 (ja) * 2007-11-27 2013-07-17 ルネサスエレクトロニクス株式会社 ドライバ及び表示装置
TW201133440A (en) * 2010-03-19 2011-10-01 Au Optronics Corp Shift register circuit and gate driving circuit
CN104637431B (zh) * 2015-02-05 2019-03-15 京东方科技集团股份有限公司 Goa电路及驱动方法、柔性显示设备及控制显示的方法
US9928809B2 (en) * 2016-02-02 2018-03-27 Innolux Corporation Display panel
TWI751987B (zh) * 2016-06-15 2022-01-11 日商半導體能源研究所股份有限公司 顯示裝置、顯示模組及電子裝置
CN108335660B (zh) * 2018-01-19 2020-07-31 武汉华星光电半导体显示技术有限公司 一种折叠显示面板的goa电路及驱动方法、折叠显示面板

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0493820A1 (en) * 1990-12-29 1992-07-08 Nec Corporation Driver circuit for liquid crystal display
CN1348167A (zh) * 2000-09-29 2002-05-08 株式会社东芝 液晶驱动电路和负载驱动电路
US20030043132A1 (en) * 2001-09-04 2003-03-06 Norio Nakamura Display device
CN1424821A (zh) * 2001-11-30 2003-06-18 夏普株式会社 信号线驱动电路和使用该电路的显示装置
CN1501706A (zh) * 2002-11-12 2004-06-02 夏普株式会社 数据信号线驱动方法、数据信号线驱动电路及显示装置
US20050068287A1 (en) * 2003-08-12 2005-03-31 Toppoly Optoelectronics Corp. Multi-resolution driver device
CN1766983A (zh) * 2004-10-28 2006-05-03 恩益禧电子股份有限公司 液晶显示设备及其驱动方法
CN1928635A (zh) * 2005-06-07 2007-03-14 三星电子株式会社 用于液晶显示器中的受控转变的设备和方法
CN100514417C (zh) * 2005-11-30 2009-07-15 三星移动显示器株式会社 数据驱动器、有机发光显示器和相应的驱动方法
US20070229438A1 (en) * 2006-04-04 2007-10-04 Dong Yong Shin Data driver and organic light emitting display using the same
CN101847378A (zh) * 2009-03-27 2010-09-29 北京京东方光电科技有限公司 源极驱动芯片
CN106157873A (zh) * 2016-08-31 2016-11-23 昆山工研院新型平板显示技术中心有限公司 一种栅极驱动装置、驱动方法及显示面板
CN110178174A (zh) * 2018-09-28 2019-08-27 华为技术有限公司 一种栅极驱动电路及其控制方法、移动终端
CN110910834A (zh) * 2019-12-05 2020-03-24 京东方科技集团股份有限公司 源极驱动器、显示面板及其控制方法、显示装置

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