WO2021102688A1 - 一种数据同步的方法以及装置 - Google Patents

一种数据同步的方法以及装置 Download PDF

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Publication number
WO2021102688A1
WO2021102688A1 PCT/CN2019/120976 CN2019120976W WO2021102688A1 WO 2021102688 A1 WO2021102688 A1 WO 2021102688A1 CN 2019120976 W CN2019120976 W CN 2019120976W WO 2021102688 A1 WO2021102688 A1 WO 2021102688A1
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WIPO (PCT)
Prior art keywords
retimer
state
buffer
time point
pin
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PCT/CN2019/120976
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English (en)
French (fr)
Inventor
苏海亮
聂耳
郭健
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980101283.XA priority Critical patent/CN114556870B/zh
Priority to PCT/CN2019/120976 priority patent/WO2021102688A1/zh
Publication of WO2021102688A1 publication Critical patent/WO2021102688A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks

Definitions

  • This application relates to the field of high-speed communication technology, and in particular to a method and device for data synchronization.
  • PCIe links are used to interconnect many different devices and computer systems.
  • PCIe links can have different widths.
  • a PCIe link can have 1 lane (also called physical lane), 2 lanes, 4 lanes, 8 lanes, or 16 lanes ( It can also be referred to as x1, x2, x4, x8 or x16) and so on.
  • x1, x2, x4, x8 or x16 16 lanes
  • a retimer was developed to allow the signals on each channel of the PCIe link to be retimed or re-synchronized and re-driven, that is, signal relay through the retimer And to filter out the jitter of the signal on the PCIe link.
  • PCIe links can have different types of channel numbers such as x1, x2, x4, x8, or x16
  • a retimer for a given width is usually used. For example, if there is a retimer in the PCIe link, the 8-channel PCIe link corresponds to the 8-channel retimer, and the 16-channel PCIe link corresponds to the 16-channel retimer.
  • the first aspect of the embodiments of the present application provides a data synchronization method and device for stacking multiple retimers into a PCIe link with a larger number of channels to transmit data, that is, the multiple retimers are transmitting
  • the data can follow the same adjustment rules for real-time synchronization adjustment of the transmitted data.
  • the first aspect of the embodiments of the present application provides a device, which specifically includes:
  • the first retimer also known as the master retimer
  • the second retimer also known as the slave retimer, which can be one or more
  • the timer includes a first deviation processing module
  • the second retimer includes a second deviation processing module.
  • the second retimer obtains the second time point when the data transmitted inside the second retimer (ie, the second transmission data) is transmitted to the second deviation processing module (the second retimer obtains the second time point
  • the step can be triggered and executed by a certain instruction, such as the instruction sent by the first retimer to the second retimer through the pin), and the second time point is sent to the first retimer through the pin, and the first retimer
  • the timer determines one according to the first time point (that is, the time point when the first transmission data transmitted inside the first retimer is transmitted to the first deviation processing module) and the second time point sent by the second retimer
  • the target time point (the target time point is after the first time point and the second time point), and the target time point is synchronized to the second retimer through the pin, and finally, the first deviation processing module and the second deviation processing
  • the modules simultaneously re-send the transmission data they have received at the target time point, so that the data transmission can be synchronized.
  • the first retimer and the second retimer can adjust the data being transmitted on each channel within the multiple retimers in real time and synchronously based on the same target time point, that is, make cross-
  • the transmission of retimer data on each channel can be synchronized and continuous, thereby meeting the higher bandwidth requirements of PCIe links without increasing additional costs and complexity.
  • the second deviation processing module is configured to obtain the second time point when the second transmission data is transmitted to the second deviation processing module, and to combine the The step of synchronizing to the first deviation processing module through the first pin at two time points can be triggered by the trigger instruction (which can be referred to as the first trigger instruction) sent by the first deviation processing module to the second deviation processing module through the first pin.
  • the first trigger instruction is used to instruct the second deviation processing module to obtain the second time point and synchronize the second time point to the first deviation processing module through the first pin.
  • the second deviation processing module is triggered by the first trigger instruction sent by the first deviation processing module through the first pin to execute the step of acquiring the second time point, which is flexible.
  • the above-mentioned first trigger instruction may be the transmission of the first transmission data obtained by the first deviation processing module to the first The first moment of the deviation processing module.
  • the first trigger instruction can also be the first moment in time, which is very simple.
  • the first retimer may also include a first Link negotiation state machine
  • the second retimer may also include a second link negotiation state machine.
  • the first link negotiation state machine and the second link negotiation state machine are used to perform link negotiation before the first deviation processing module determines the target time point.
  • the two retimers included in the device need to perform link negotiation before being used for data alignment.
  • the link negotiation first can be specifically: the second link negotiation state machine, which is specifically used to obtain the status of each physical channel in the second deviation processing module (such as which physical channels are transmitting parallel data streams) State, which physical channels transmit specific physical data streams, which physical channels transmit what data streams, etc.), this state can be called the second state, and then the second link negotiation state machine is also used to The two states are synchronized to the first link negotiation state machine through the second pin.
  • the first link negotiation state machine is specifically used to obtain the state of each physical channel in the first deviation processing module (which can be called the first link negotiation state machine). State), after that, the first link negotiation state machine is used to determine the jump moment according to the first state and the second state, and is used to further synchronize the jump moment to the second link negotiation state through the second pin In this way, the first link negotiation state machine and the second link negotiation state machine are also used to perform link negotiation at the time of jump. For example, the first link negotiation state machine may start timing after acquiring the second state, and after the timing reaches a certain period of time, the first link negotiation state machine and the second link negotiation state machine simultaneously perform link negotiation.
  • the second link negotiation state machine is specifically also used to obtain each physical device in the second deviation processing module.
  • the second state of the channel, and the step of synchronizing the second state to the first link negotiation state machine may be the first state sent by the first link negotiation state machine to the second link negotiation state machine through the second pin
  • the first state sent to the second link negotiation state machine via the second pin is used to instruct the second link negotiation state machine to perform the step of obtaining the second state.
  • the second link negotiation state machine is used to trigger the execution of the step of acquiring the second state by the first state sent by the first link negotiation state machine through the second pin, and is flexible Sex.
  • the first link negotiation state machine and the second link negotiation state machine are used to At the same time, the way of link negotiation may be: the first link negotiation state machine, which is specifically used to perform link negotiation according to the first state and the second state at the determined jumping moment; the second link negotiation state machine, which is specifically used At the same jumping moment, the link negotiation is performed according to the first state and the second state.
  • the first link negotiation state machine and the second link negotiation state machine can be fully consistent at the same time In order to achieve the purpose of combining two retimers into one link for link negotiation.
  • both the first link negotiation state machine and the second link negotiation state machine are used to obtain the first state and the second state. Therefore, at the same jump moment, the jump is defined according to the PCIe protocol.
  • the first link negotiation state machine and the second link negotiation state machine can be used to implement a fully synchronized jump mode, which is simple and convenient.
  • the first retimer may further include a first buffer
  • the second retimer may also include a second buffer; where the second buffer is used to determine the second character code ordered set (also known as SKP, a physical layer character defined in the PCIe protocol) Code) data state (may be called the fourth state), and synchronize the fourth state to the first buffer through the third pin.
  • the first buffer is also used to obtain the state of the first SKP data ( It can be called the third state).
  • the first buffer is used to determine the SKP addition and deletion rules according to the third state and the fourth state, and is used to further synchronize the determined SKP addition and deletion rules to the second buffer through the third pin In this way, the first buffer and the second buffer are also used to adjust the first transmission data and the second transmission data respectively according to the same SKP addition and deletion rules.
  • the second buffer is used to determine the fourth state of the second SKP data, and pass the fourth state through
  • the step of synchronizing the third pin to the first buffer can be executed by triggering a trigger command (which can be referred to as a second trigger command) sent by the first buffer to the second buffer through the third pin, and the second trigger command It is used to instruct the second buffer to perform the step of acquiring the fourth state and synchronizing the fourth state to the first buffer through the third pin.
  • the second buffer is triggered by the second trigger command sent by the first buffer through the third pin to execute the step of obtaining the fourth state, which is flexible.
  • the above-mentioned second trigger instruction may be the third state of the first SKP data acquired by the first buffer.
  • the second trigger instruction can also be in the third state, which is very simple.
  • the first buffer may include a first receiving buffer and a first sending buffer ;
  • the second buffer may include a second receiving buffer and a second sending buffer.
  • the first buffer and the second buffer may include various forms of buffers, which are flexible.
  • the second retimer may be a retimer It can also be multiple retimers, which is not limited here.
  • the device is not limited to only including two retimers, and more retimers may also be included to meet the requirements for various PCIe link widths.
  • the second aspect of the present application also provides a data synchronization method, which specifically includes:
  • the second retimer transmits the second transmission data in the second retimer to the second deviation processing module in the second retimer at the second time point to the first retimer through the first pin;
  • the first retimer determines the target time point according to the acquired first time point and the second time point, and synchronizes the target time point to the second retimer through the first pin, where the first time point is The time point when the first transmission data in the first retimer is transmitted to the first deviation processing module in the first retimer; finally, the first deviation processing module and the second deviation processing module respectively send the first transmission at the target time point
  • the data and the second transmission data are used to achieve the purpose of synchronizing and aligning the data.
  • the first retimer and the second retimer can adjust the data being transmitted on each channel within the multiple retimers in real time and synchronously based on the same target time point, that is, make cross-
  • the transmission of retimer data on each channel can be synchronized and continuous, thereby meeting the higher bandwidth requirements of PCIe links without increasing additional costs and complexity.
  • the second deviation processing module in the second retimer obtains the second transmission data through the first pin.
  • the method may further include: the first retimer sends a first trigger instruction to the second retimer through the first pin, and the first trigger instruction is used for Instruct the second retimer to execute the step of obtaining the second time point.
  • the second retimer is triggered by the first trigger instruction sent by the first retimer through the first pin to execute the step of acquiring the second time point, which is flexible.
  • the above-mentioned first trigger instruction may be the transmission of the first transmission data obtained by the first retimer to the first The first moment of the deviation processing module.
  • the first trigger instruction can also be the first moment in time, which is very simple.
  • the first retimer and the second retiming Before performing data alignment (that is, before the first retimer determines the target time point according to the acquired first time point and the second time point), it also needs to send the status of each physical channel used to transmit data to The first link negotiation state machine in the first retimer and the second link negotiation state machine in the second retimer make the first link negotiation state machine and the second link negotiation state machine in the first The deviation processing module performs link negotiation before determining the target time point.
  • the manner in which the first link negotiation state machine and the second link negotiation state machine perform link negotiation It can be: the second retimer obtains the second state of the channel used to transmit the second transmission data (such as which physical channels are in the state of transmitting parallel data streams, which physical channels transmit specific physical data streams, and which physical channels transmit What kind of data flow, etc.), and the second state is synchronized to the first retimer through the second pin; after that, the first retimer determines the jump according to the acquired first state and second state The transition time is synchronized to the second retimer through the second pin, where the first state is the state of the channel for transmitting the first transmission data in the first retimer; finally, the first link is negotiated The state machine and the second link negotiation state machine perform link negotiation at the jumping moment.
  • the first link negotiation state machine may start timing after acquiring the second state, and after the timing reaches a certain period
  • the method may further include: the first retimer sends the first state to the second link negotiation state machine through the second pin, and the first retimer sends the first state to the second link negotiation state machine through the second pin.
  • a state is used to trigger the second retimer to perform the step of obtaining the second state, and the first state sent to the second link negotiation state machine via the second pin is used to instruct the second link negotiation state machine to obtain the first state.
  • the second link negotiation state machine is triggered by the first state sent by the first link negotiation state machine through the second pin to execute the step of acquiring the second state, which is flexible.
  • the first link negotiation state machine and the second link negotiation state machine are performed simultaneously at the moment of jump
  • the way of link negotiation may be: the first link negotiation state machine performs link negotiation according to the first state and the second state at the determined jump moment; the second link negotiation state machine also performs link negotiation according to the first state at the same jump moment. The first state and the second state perform link negotiation.
  • the first link negotiation state machine and the second link negotiation state machine can simultaneously perform a completely consistent link negotiation mode, so as to achieve the purpose of combining two retimers into one link for link negotiation.
  • both the first link negotiation state machine and the second link negotiation state machine obtain the first state and the second state. Therefore, at the same jump moment, the jump is defined according to the PCIe protocol. In this way, the first link negotiation state machine and the second link negotiation state machine can realize a completely synchronized jump mode, which is simple and convenient.
  • the second retimer obtains the second retimer
  • the state of the second SKP data in the second buffer may be called the fourth state
  • the fourth state is synchronized to the first retimer through the third pin.
  • the first retimer will also Acquire the state of the first SKP data (which can be called the third state, which is the state of the first SKP data in the first buffer in the first retimer), and then the first retimer is based on The third state and the fourth state determine the SKP addition and deletion rules, and further synchronize the determined SKP addition and deletion rules to the second retimer through the third pin.
  • the first and second retimers are based on the The same SKP addition and deletion rules adjust the first transmission data and the second transmission data respectively.
  • the second trigger instruction may be the third state of the first SKP data acquired by the first buffer.
  • the second trigger instruction can also be in the third state, which is very simple.
  • the first buffer may include a first receiving buffer and a first sending buffer ;
  • the second buffer may include a second receiving buffer and a second sending buffer.
  • the first buffer and the second buffer may include various forms of buffers, which are flexible.
  • the second retimer may be a retimer It can also be multiple retimers, which is not limited here.
  • the device is not limited to only including two retimers, and more retimers may also be included to meet the requirements for various PCIe link widths.
  • the third aspect of the embodiments of the present application provides a device, which has the function of implementing the method of the foregoing second aspect or any one of the possible implementation manners of the second aspect.
  • This function can be realized by hardware, or by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above-mentioned functions.
  • the embodiments of the present application have the following advantages: the first retimer (also referred to as the master retimer) and the second retimer (also referred to as the slave retimer, which can be one or
  • the signals are transmitted to each other through pins.
  • the first retimer includes a first deviation processing module
  • the second retimer includes a second deviation processing module.
  • the second retimer obtains the second time point when the data transmitted inside the second retimer (ie, the second transmission data) is transmitted to the second deviation processing module (the second retimer obtains the second time point
  • the step can be triggered and executed by a certain instruction, such as the instruction sent by the first retimer to the second retimer through the pin), and the second time point is sent to the first retimer through the pin, and the first retimer
  • the timer determines one according to the first time point (that is, the time point when the first transmission data transmitted inside the first retimer is transmitted to the first deviation processing module) and the second time point sent by the second retimer
  • the target time point (the target time point is after the first time point and the second time point), and the target time point is synchronized to the second retimer through the pin, and finally, the first deviation processing module and the second deviation processing
  • the modules simultaneously re-send the transmission data they have received at the target time point, so that the data transmission can be synchronized.
  • the first retimer and the second retimer can adjust the data being transmitted on each channel within the multiple retimers in real time and synchronously based on the same target time point, that is, make the cross-retimer
  • the transmission of timer data on each channel can be synchronized and continuous, thereby meeting the higher bandwidth requirements of PCIe links without increasing additional costs and complexity.
  • Figure 1 is a schematic diagram of a PCIe link without a retimer
  • Figure 2 is a schematic diagram of a PCIe link with a retimer
  • Figure 3 is a schematic diagram of a PCIe link with multiple retimers
  • Figure 4 is a schematic diagram of a complete PCIe link formed by a retimer between a device and a device;
  • Figure 5 is a schematic diagram of the internal structure of the retimer
  • Figure 6 is a schematic diagram of the structure of multiple channels formed inside the retimer
  • FIG. 7 is a schematic diagram of various different types of PCIe links connected by multiple retimers through pins to broaden the link width according to an embodiment of the application;
  • FIG. 8 is a schematic diagram of two retimers implementing data synchronization through pin synchronization information according to an embodiment of the application.
  • FIG. 9 is a schematic diagram of the number of pins included in the first pin in an embodiment of the application.
  • FIG. 10 is a schematic diagram of data transmission in a channel according to an embodiment of the application.
  • FIG. 11 is a schematic diagram of data alignment in the deviation processing module of the retimer according to an embodiment of the application.
  • FIG. 12 is a schematic diagram of a pin signal according to an embodiment of the application.
  • FIG. 13 is a schematic diagram of a data synchronization method provided by an embodiment of this application.
  • the embodiments of the present application provide a data synchronization method and device, which are used to stack multiple retimers into a PCIe link with a larger number of channels to transmit data, that is, the multiple retimers can transmit data.
  • the multiple retimers can transmit data.
  • Retimer is a device similar to a physical layer chip.
  • the signal passes through the retimer, the signal can be reconstructed through the internal clock of the retimer, so that the signal transmission energy increases, and then the transmission continues.
  • the retimer is a device with internal clock data recovery (Clock Data Recovery, CDR). After the signal is recovered, the signal is sent out through its internal physical channel, which can reduce the jitter of the signal.
  • Figure 1 shows a PCIe link without retimer.
  • Device 1 and Device 2 are coupled together via Link A and Link B (Link A and Link B are divided according to the direction of data transmission, which is actually Integrated in a PCIe link, that is, link 1 and link 2 constitute a complete PCIe link between device 1 and device 2), the data that needs to be exchanged between device 1 and device 2 passes through link A and link Road B realizes high-speed transmission.
  • the PCIe link has a relatively limited length (to ensure high-speed transmission, the length of the PCIe link is limited). If the physical distance between device 1 and device 2 is too far, it will inevitably lead to a single PCIe The link is too long, which affects the efficiency of data transmission.
  • the data being transmitted on the PCIe link can be retimed or re-driven after resynchronization, as shown in Figure 2 with a retimer PCIe link
  • device 1 and device 2 are coupled to a retimer 01, which is coupled to device 1 through sub-link A01 and sub-link B02, and to the device through sub-link A02 and sub-link B01 2.
  • These sub-links constitute a complete PCIe link for data exchange between device 1 and device 2.
  • these sub-links also follow the PCIe protocol, and the retimer 01 can be configured to operate according to the protocol followed by the sub-links to implement data interaction between the device 1 and the device 2.
  • the PCIe link between device 1 and device 2 may also have two or more retimers. As shown in FIG. 3, there are multiple retimers. The PCIe link of the timer. These retimers are connected in sequence in a similar manner in series (as shown in Figure 3, retimer 1, retimer 2,..., retimer n, n ⁇ 2).
  • Retimer 1 retimer 2, ..., sub-link A1, sub-link A2, sub-link A3, ..., sub-link An, sub-link An+1, and sub-chain of retimer n Road B1, sub-link B2, ..., sub-link Bn-1, sub-link Bn, and sub-link Bn+1 constitute a complete PCIe link for data exchange between device 1 and device 2.
  • Device 1 the Central Processing Unit/Processor (CPU) board and Device 2 as the Input/Output (I/O) board as an example to illustrate the CPU board and I/O board in detail.
  • CPU Central Processing Unit/Processor
  • I/O Input/Output
  • the CPU board 401 is connected to the I/O board 403 through the backplane 402, where the retimer 4012 is placed in the CPU board 401 (the retimer can be It is set inside the device, or it can be set outside the device, and the details are not limited.
  • Figure 4 shows that the retimer is set inside the CPU board), and is connected to the CPU4011 in the CPU board 401, so that the CPU4011 and the retimer 4012 are connected
  • a sub-link 4013 of the entire PCIe link (for example, a 16-channel sub-link of PCIe) is formed in the middle.
  • the retimer 4012 is connected to the connector 404 on the backplane 402, and the connector 404 is connected to the The connector 405 is connected to form the entire PCIe sub-link 4021, the connector 405 is further connected to the retimer 4031 inside the I/O board 403, and the retimer 4031 is connected to the CPU4032 inside the I/O board 403 to form The entire PCIe sub-link 4033.
  • the above figures 2 to 4 introduce the application of the retimer in practice.
  • the following describes the internal structure of the retimer.
  • the device includes a serializer and deserializer (Serializer and De-serializer, Serdes) 501, a buffer 502, a deviation processing module 503, a link negotiation state machine 504, a buffer 505, and a serial/deserializer 506.
  • the above-mentioned devices in the retimer are explained in terms of the flow of data: the data stream is acquired by the serial/deserializer 501 (also called the receiving serial/deserializer 501) in the retimer. It is a serial data stream.
  • the serial/deserializer 501 After the serial/deserializer 501 obtains the serial data stream on the PCIe link, it will convert the serial data stream into a parallel data stream.
  • the parallel data stream is serialized/deserialized
  • the channel (Lane, which may also be referred to as a physical channel) of the device 501 performs transmission.
  • the serial/deserializer 601 as shown in FIG. 6 has N+1 physical channels (namely Lane0 to LaneN) for data transmission.
  • the parallel data streams being transmitted on the physical channels within the same retimer do not interact with each other, but the transmission synchronization must be maintained between the physical channels of the data streams being transmitted. It should also be noted that all physical channels inside the retimer are not required to be used when transmitting data streams. For example, for a x16 type retimer, only 10 of them can be used when transmitting data. The channel carries on the data transmission.
  • the serial/deserializer 501 After the serial/deserializer 501 processes the serial data stream into a parallel quantity stream, it will write the parallel data stream into the buffer 502 (also called the receiving buffer 502), and the buffer 502 is the data path Each physical channel corresponds to a buffer. For example, if there are 8 physical channels in the serial/deserializer 501, then the buffer 502 refers to the set of buffers corresponding to each physical channel (That is, there are 8 buffers), as shown in Figure 6, the serial/deserializer 601 has N+1 physical channels for data transmission, so the corresponding buffer 602 is buffer 10 to buffer 1N Collection.
  • the write clock of the buffer 502 is the clock recovered by the CDR in the serial/deserializer 501, and the read clock of the buffer 502 is the local working clock, that is, the read and write clock of the buffer 502 is an asynchronous clock, so it is written
  • the parallel data stream entering the buffer 502 may have a frequency offset.
  • the frequency offset processing must be performed first, that is, to ensure that the receive buffer corresponding to each physical channel that is transmitting data does not overflow (That is, no data is lost), the processing method is to ensure that the corresponding receive buffer does not overflow through the character code (SKP, a character code of the physical layer) addition and deletion rules (for example, in the corresponding receive buffer according to the preset rules) Delete SKP data).
  • SSP character code
  • Delete SKP data for example, in the corresponding receive buffer according to the preset rules
  • the offset processing module 503 also has the same number of physical channels as the serial/deserializer 501 (for example, the deviation processing module 603 in FIG. 6 has N+1 physical channels from Lane0 to LaneN) for receiving parallel data streams transmitted from each buffer included in the buffer 502, because the parallel data streams are composed of different.
  • the parallel data streams transmitted through different buffers will cause the deviation processing module 503 to send each buffer received due to the delay deviation, the length of the physical path, etc.
  • the data of is not synchronized (that is, there is first, and then does not arrive strictly synchronously).
  • One of the functions of the deviation processing module 503 is to align the parallel data streams acquired on each of its internal physical channels.
  • the deviation processing module 503 aligns the acquired data streams of each physical channel, it also needs to adjust the status of each physical channel (such as which physical channels are in the state of transmitting parallel data streams, and which physical channels are transmitting).
  • the specific physical data flow, which physical channels transmit which data flow, etc. are sent to the Link Training and Status State Machine (LTSSM) 504, and the link negotiation state machine 504 is based on the status of each physical channel Perform link negotiation (the method of link negotiation is clearly defined in the PCIe protocol, and will not be repeated here).
  • the link negotiation state machine 504 sends the negotiation result (eg, negotiation success, negotiation failure, etc.) to the deviation processing module 503.
  • the deviation processing module 503 will cache The parallel data streams on each physical channel acquired by the device 502 are aligned, and then the aligned parallel data streams are further written to the buffer 505 (also referred to as the sending buffer 505).
  • the buffer 505 is the transmission buffer of the data path.
  • Each physical channel corresponds to a buffer.
  • the buffer 505 is Refers to the set of buffers corresponding to each physical channel. As shown in FIG. 6, the serial/deserializer 601 has N+1 physical channels for data transmission, and the corresponding buffer 605 is the buffer 20 To the set of buffer 2N.
  • the parallel data stream acquired in the buffer 505 also has a frequency offset, so it also needs to perform frequency offset processing on the acquired parallel data stream, that is, to ensure that each physical channel that is transmitting data corresponds to the transmit buffer Continuous flow (that is, no data loss), its processing method is also to ensure that the corresponding transmission buffer is continuously flowed through SKP addition and deletion rules (for example, SKP data is added to the corresponding transmission buffer according to a preset rule).
  • serializer/deserializer 506 also referred to as the transmit serializer/deserializer 506
  • the serializer 506 also has the same number of physical channels as the serializer/deserializer 501 (for example, the serializer/deserializer 506 in FIG. 6 has N+1 physical channels from Lane0 to LaneN), and the serializer/deserializer 506 has N+1 physical channels.
  • the deserializer 506 converts the obtained parallel data streams on each physical channel into a serial data stream and then sends it out via the PCIe link.
  • the transmission of data stream within the retimer is carried out via multiple physical channels, and the data transmitted between the physical channels does not interact, but the data transmitted on each physical channel within the retimer needs to be synchronized .
  • the retimer can only synchronize the data transmitted on each physical channel within itself, and multiple retimers can only be connected in series (as shown in Figure 3) to extend the PCIe link. length.
  • the PCIe link requires more physical channels (for example, 32 channels)
  • the corresponding retimer in the PCIe link for example, the retimer has only 8 channels
  • the retimer needs to be replaced (for example, to a retimer with 32 channels). If there are more retimers connected in a series-like manner in the PCIe link, the replacement is more troublesome.
  • the embodiment of the present application provides a device.
  • the realization idea is that between multiple retimers, synchronization information is sent through pins, and then the status of the data transmitted within each retimer is synchronized in real time, so as to achieve The purpose of combining physical channels inside multiple retimers into a physical channel on a PCIe link.
  • Figure 7 It is assumed that each retimer in Figure 7 is a retimer for 4 physical channels.
  • the PCIe link formed at this time is a x4 PCIe link; as shown in (b), two retimers with 4 physical channels can transmit synchronization information through pin 01 to achieve x8 PCIe link Link; similarly, as shown in (c), four retimers each with 4 physical channels can realize the x16 type PCIe chain by transmitting synchronization information through pin 02, pin 03, and pin 04 Way; By using different numbers and different types of retimers to stack according to the above-mentioned realization ideas, it is possible to expand the existing PCIe link into a PCIe link with various physical channels that meets the needs of users. It should be noted that, in the foregoing implementation manner, pin 01, pin 02, pin 03, or pin 04 is a collection of one or more pins, and is not limited to only one pin.
  • the data stream is transmitted from device 1 to device 2 as For example, specifically explain the roles played by different modules in the first retimer and the second retimer in the synchronization process:
  • the device for data synchronization may specifically include a first retimer and a second retimer, where the first retimer includes a first deviation processing module 803 and a second retimer.
  • a second deviation processing module 703 is included.
  • the second deviation processing module 703 is used to obtain the time point ( It can be called the second time point), and the second time point is synchronized to the first deviation processing module 803 through the first pin.
  • the first deviation processing module 803 is also used to obtain the first retimer
  • the data (may be referred to as the first transmission data) to be transmitted to the first deviation processing module 803 (may be referred to as the first time point), after which, the first deviation processing module 803 is used for
  • the time point and the second time point determine a target time point, the target time point is the time point after the first time point and the second time point, and the target time point is further synchronized to the second time point through the first pin
  • the processing module 803 and the second deviation processing module 703 align the data transmitted by the respective internal physical channels at the target time point and then synchronize the data transmission.
  • the second deviation processing module 703 is used to obtain the second time point when the second transmission data is transmitted to the second deviation processing module 703, and pass the second time point through the second time point.
  • the step of synchronizing a pin to the first deviation processing module 803 can be executed by the triggering instruction (which may be referred to as the first triggering instruction) sent by the first deviation processing module 803 to the second deviation processing module 703 through the first pin,
  • the first trigger instruction is used to instruct the second deviation processing module 703 to obtain the second time point and synchronize the second time point to the first deviation processing module 803 through the first pin; it can also be the second deviation processing
  • the module obtains the second transmission data it automatically determines the second time point when the second transmission data is transmitted to the second deviation processing module 703, and automatically synchronizes the second time point to the first deviation processing through the first pin Module 803, specifically, the method for triggering the second deviation processing module 703 to acquire the second time point and sending the second time point to the first deviation processing module 80
  • the above-mentioned first trigger instruction may be the first time point at which the first transmission data acquired by the first deviation processing module 803 is transmitted to the first deviation processing module 803. It may be a target information generated immediately after the first deviation processing module 803 obtains the first time point, and the target information is used to instruct the second deviation processing module 703 to obtain the second time point and send the first deviation processing module 803 to the first deviation processing module 803.
  • the specific form of the first trigger instruction is not limited here.
  • the first pin may be one or multiple, and the first pin may also be a single-bit (bit) pin or a multi-bit tube. Feet, the specifics are not limited here.
  • the first pin includes pin 11, pin 12, pin 13, and pin 14.
  • the first deviation processing module 803 outputs two pins (ie, pin 11 and pin 12).
  • the second deviation processing module 703 obtains the information sent by the first deviation processing module 803 through pins 11 and 12, the second deviation processing module 703 outputs two pins (namely pin 13 and pin 14), and the first deviation processing
  • the module 803 obtains the information sent by the second deviation processing module 703 through the pin 13 and the pin 14.
  • the deviation processing module Since the internal deviation processing module of the retimer performs data alignment within a specific time, the deviation processing module obtains the protocol-specific characters carried by the data being transmitted on the physical channels (the protocol-specific characters represent the data of each physical channel). The flags that are issued at the same time, such as the training sequence ordered set TS1/TS2, are defined in the PCIe protocol and will not be repeated here), the deviation processing module performs data alignment according to the specific characters of the protocol, and then simultaneously aligns the data of each channel To transfer.
  • each module in the retimer e.g., deviation processing module, buffer, etc.
  • has 4 physical channels e.g., in Figure 10).
  • the protocol-specific character TS1 includes a COM and the following 15 8bits data.
  • the 4 physical channels are COMs that are sent at the same time, and when the data on the 4 physical channels are transmitted to the deviation processing module, the situation shown in Figure 10 may appear, namely COM is not aligned, and there is a deviation in the data between the physical channel and the physical channel (that is, the time when the data arrives at the deviation processing module is different), then the deviation processing is performed in the deviation processing module to make the data on each physical channel aligned, as shown in the figure 11 shows the protocol specific character TS1 carried by the aligned data. After that, the deviation processing module can transmit the aligned data to the next module in the retimer again.
  • the first deviation processing module 803 when the first transmission data transmitted through each physical channel in the first retimer is transmitted to the first deviation processing module 803, there will be a difference in sequence, then when the first deviation processing module 803 obtains the protocol specific character (may be referred to as the first protocol specific character A1) carried in the first transmitted data in the physical channel, it will determine to obtain the first protocol specific character A1 It is transmitted to the time point 1 of the first deviation processing module 803, and the time point 1 is synchronized to the second deviation processing module 703 through pin 11; when the first deviation processing module 803 obtains the last transmitted data in the physical channel When the carried protocol specific character (may be called the last protocol specific character A2), the time point 2 when the last protocol specific character A2 is transmitted to the first deviation processing module 803 is determined, and the time point 2 is passed The pin 12 is synchronized to the second deviation processing module 703. Similarly,
  • the second deviation processing module 703 When the second transmission data transmitted through each physical channel in the second retimer is transmitted to the second deviation processing module 703, there will also be a difference in sequence, then when the second deviation processing module 703 obtains the first in the physical channel When the protocol specific character (which can be called the first protocol specific character B1) carried in the transmitted data, the time point 3 when the first protocol specific character B1 is acquired and transmitted to the second deviation processing module 703 will be determined.
  • the protocol specific character which can be called the first protocol specific character B1
  • the time point 3 is synchronized to the first deviation processing module 803 through pin 13; when the second deviation processing module 703 obtains the protocol-specific characters carried in the last transmitted data in the physical channel (may be called the last protocol-specific When the character B2), the time point 4 when the last protocol-specific character B2 is transmitted to the second deviation processing module 703 is determined, and the time point 4 is synchronized to the first deviation processing module 803 through the pin 14.
  • the first deviation processing module 803 can determine whether the time difference between time point 1, time point 2, time point 3, and time point 4 is within the standard time difference specified in the agreement (if the calculated time difference is greater than the standard time difference specified in the agreement, then It means that there is an error or delay in data transmission, and the data cannot be aligned at this time).
  • the first deviation processing module 803 will determine a time point for data alignment (that is, the target time point), And the target time point is sent to the second deviation processing module 703 through pin 11 or pin 12, and then, when the target time point is reached, the first deviation processing module 803 and the second deviation processing module 703 simultaneously analyze the respective physical channels Align the data on the above, and then respectively send the data on each physical channel at the target time point at the same time, so as to achieve the purpose of synchronization and alignment of the data in the two retimers.
  • the first pin may also include only two pins, for example, it may only include pin 11 (or pin 12) and pin 13 (or pin 14), and the first deviation processing module 803 obtains Both time point 1 and time point 2 can be synchronized to the second deviation processing module 703 through pin 11 (or pin 12).
  • the time point 3 and time point 4 acquired by the second deviation processing module 703 are also both It can be synchronized to the first deviation processing module 803 through pin 13 (or pin 14).
  • the first pin may also include only one pin, and the first deviation processing module 803 and the second deviation processing module 703 can adopt a time-division multiplexing manner to combine time 1, time 2 with this pin. , Time 3, Time 4 are synchronized to the other party.
  • the number of pins included in the first pin and the specific method of synchronization are not limited here.
  • the first retimer and the second retimer respectively obtain the time point when the data transmitted on each physical channel of the other party is transmitted to the respective internal deviation processing module through the first pin, and the time point is determined by The first retimer determines a target time point according to each time point, and further synchronizes the target time point to the second retimer. When the target time point is reached, start all the physical channels of the cross-retimer The data alignment operation completes the alignment of the data on the physical channels in all retimers.
  • the first retimer may also specifically include the first link negotiation state machine 804 and the second Specifically, the dual timer may further include a second link negotiation state machine 704.
  • the first deviation processing module 803 and the second deviation processing module 703 need to respectively send the status of the physical channels used to transmit data to the first deviation processing module 803 and the second deviation processing module 703 before performing data alignment.
  • the second link negotiation state machine 704 is used to obtain the second deviation processing module
  • the status of each physical channel in 703 can be called the first
  • the second link negotiation state machine 704 is also used to synchronize the second state to the first link negotiation state machine 804 through the second pin.
  • the first link negotiation state machine 804 also uses After acquiring the state of each physical channel in the first deviation processing module 803 (may be referred to as the first state), the first link negotiation state machine 804 is used to determine the jumping time according to the first state and the second state , And used to further synchronize the jump moment to the second link negotiation state machine 704 through the second pin. In this way, the first link negotiation state machine 804 and the second link negotiation state machine 704 are also used for the jump Perform link negotiation at the same time at all times. For example, the first link negotiation state machine 804 may start timing after acquiring the second state, and after the timing reaches a certain period of time, the first link negotiation state machine 804 and the second link negotiation state machine 704 perform link negotiation at the same time.
  • the second link negotiation state machine 704 is used to obtain the second state of each physical channel in the second deviation processing module 703, and synchronize the second state to the first state.
  • the steps of the link negotiation state machine 804 can be executed by the first state trigger sent by the first link negotiation state machine 804 to the second link negotiation state machine 704 via the second pin, and sent to the second link negotiation state machine 704 via the second pin.
  • the first state of the link negotiation state machine 704 is used to instruct the second link negotiation state machine 704 to perform the step of obtaining the second state.
  • first link negotiation state machine 804 is also used to synchronize the first state to the second link negotiation state machine 704 through the second pin, since the link negotiation state machine in the retimer performs
  • the link negotiation method is clearly defined in the PCIe protocol, that is, the protocol clearly defines how to perform link negotiation according to the state of each different physical channel. Therefore, the first link negotiation state machine 804 and the second link negotiation state machine 804 are clearly defined in the protocol.
  • the manner in which the link negotiation state machine 704 is used for simultaneous link negotiation at the jumping moment may be: the first link negotiation state machine 804 is used for link negotiation according to the first state and the second state at the determined jumping moment ;
  • the second link negotiation state machine 704 is used for link negotiation according to the first state and the second state at the same jump moment.
  • the first link negotiation state machine 804 and the second link negotiation state machine 704 can perform a completely consistent link negotiation mode at the same time, so that the two retimers are combined into one link.
  • the second pin may be one pin or multiple pins, which is not specifically limited here. If the second pin is one pin, take a single bit pin as an example: the first link negotiation state machine 804 and the second link negotiation state machine 704 time-division multiplex the second pin, such as the first
  • the link negotiation state machine 804 first uses the second pin to transmit information (such as sending the first state to the second link negotiation state machine 704). After the transmission is completed, the second pin is released, and the second link negotiates the state.
  • the machine 704 uses the second pin to transmit information (such as sending the second state to the first link negotiation state machine 804).
  • the pin signal (that is, the signal transmitted through the second pin, such as the first state and the second state) is generated at 1GHz in the retimer, and transmitted at 100MHz on the second pin, then The state of each bit is valid for 10ns.
  • the pin level can be defaulted to be high (or the pin level can be defaulted to be low).
  • the first retimer control pin level is set to low level, the first The retimer has the right to use this pin, which means that a transmission command starts. For example, a 4bit address can be transmitted first, which represents the command type, and then a maximum of 16 bits of data can be sent.
  • the pin When the data transmission is completed, the pin is set A high level indicates that this transmission command is completed, and the first retimer surrenders the right to use the pin to the second retimer. If the second pin is multiple pins, then the time-division multiplexing method may not be used. In this case, an independent synchronization signal can be used.
  • the first link negotiation state machine 804 provides a pin to the second The link negotiation state machine 704 transmits synchronization signals, and the second link negotiation state machine 704 transmits synchronization signals to the first link negotiation state machine 804 through another pin.
  • Each group of synchronization signals can be a unit signal or a multi-bit signal. There is no limitation here.
  • the first retimer and the second retimer obtain the status of each physical channel of each other through the second pin (for example, the first state and the second state), and the first retimer
  • the timer determines a jump moment according to the status of all physical channels in the two retimers, and further synchronizes the jump moment to the second retimer.
  • the first retimer The first link negotiation state machine 804 in the timer and the second link negotiation state machine 704 in the second retimer start all the link negotiation across the retimers, so that the two retimers are combined into one chain. The purpose of link negotiation.
  • the first retimer includes the first deviation processing module 803 and/or the first link negotiation state machine 804, and the second retimer includes the second deviation processing module 703 and/or the second link negotiation state machine.
  • the first retimer may specifically include a first buffer
  • the second retimer may specifically include a second buffer.
  • the first buffer may specifically include a receiving buffer 802 and a sending buffer 805
  • the second buffer may specifically include a receiving buffer 702 and a sending buffer 705.
  • the buffer when the data in each retimer is transmitted to the respective internal buffer, the buffer also needs to perform frequency offset processing on the acquired data, that is, to ensure that each is The receive buffer corresponding to the physical channel for transmitting data does not overflow (that is, no data is lost), and at the same time, it is necessary to ensure that the transmit buffer corresponding to each physical channel that is transmitting data continuously flows (that is, no data is lost).
  • the processing method is to ensure that the corresponding receiving buffer does not overflow and the corresponding sending buffer is continuously flowed through SKP addition and deletion rules (for example, adding SKP data to the corresponding receiving buffer according to the preset rules, and in accordance with the preset rules in the corresponding Delete the SKP data from the transmit buffer).
  • SKP addition and deletion rules for example, adding SKP data to the corresponding receiving buffer according to the preset rules, and in accordance with the preset rules in the corresponding Delete the SKP data from the transmit buffer.
  • the buffer can obtain SKP data and ensure that the data in the buffer does not overflow or flow continuously according to the SKP addition and deletion rules (that is, how to deal with frequency offset). I will not repeat it here and implement it in this application.
  • the emphasis is on how the first retimer and the second retimer handle the frequency offset synchronously through the third pin.
  • the second buffer is used to determine the state of the second SKP data (may be called the fourth state), and the fourth state is synchronized to the first buffer through the third pin.
  • the first buffer is also used Obtain the state of the first SKP data (which can be called the third state).
  • the first buffer is used to determine the SKP addition and deletion rules according to the third state and the fourth state, and is used to further determine the SKP data through the third pin.
  • the SKP addition and deletion rules are synchronized to the second buffer, so that the first buffer and the second buffer are also used to adjust the first transmission data and the second transmission data respectively according to the same SKP addition and deletion rules.
  • the SKP addition and deletion rules can be synchronized to the receiving buffer 702 through the third pin.
  • the device 702 obtains the addition and deletion rule, it will also perform frequency offset processing in synchronization with the receiving buffer 802 according to the addition and deletion rule.
  • the SKP addition and deletion rule can be that the first retimer and the second retimer monitor the downline of the sending buffer 805 and the sending buffer 705 respectively.
  • the downline is divided into two levels, the first level plus one unit of SKP, and the second Add two units of SKP (adding two units of SKP can ensure coverage of the frequency offset defined by the protocol, and ensure that after adding SKP, the transmit buffer will be in a non-empty state, so that there is data in the transmit buffer, which can achieve continuous The purpose of the flow), other conditions do not increase.
  • the transmission buffer 805 determines the SKP addition and deletion rule
  • the SKP addition and deletion rule can be synchronized to the transmission buffer 705 through the third pin.
  • the transmission buffer 705 obtains the addition and deletion rule, it will also be combined with the SKP addition and deletion rule according to the third pin.
  • the receiving buffer 805 performs frequency offset processing synchronously.
  • the second buffer is used to determine the fourth state of the second SKP data
  • the step of synchronizing the fourth state to the first buffer through the third pin can be performed by
  • the first buffer is executed by triggering the trigger command (which can be called the second trigger command) sent to the second buffer through the third pin
  • the second trigger command is used to instruct the second buffer to execute the acquisition of the fourth buffer.
  • State and synchronize the fourth state to the first buffer through the third pin it can also be that once the second buffer acquires the second SKP data, it automatically determines the fourth state of the second SKP data, and
  • the fourth state is automatically synchronized to the first buffer through the third pin. Specifically, there is no way to trigger the second buffer to acquire the fourth state and send the fourth state to the first buffer through the third pin. Make a limit.
  • the above-mentioned second trigger instruction may be the third state of the first SKP data acquired by the first buffer, or the third state of the first SKP data acquired by the first buffer.
  • a target information generated immediately thereafter is used to instruct the second buffer to acquire the fourth state and send the fourth state to the first buffer.
  • the specific form of the second trigger instruction is not limited here.
  • the third pin may also be one pin or multiple pins. Specifically, here Not limited.
  • the first retimer and the second retimer respectively obtain the status (e.g., SKP data) received by their respective buffers (e.g., receive buffer and transmit buffer) through the third pin.
  • the third state and the fourth state) and the first retimer determines an SKP addition and deletion rule according to the status of the SKP data received by the buffers in the two retimers, and further synchronizes the SKP addition and deletion rule to
  • the second retimer, the first buffer in the first retimer and the second buffer in the second retimer simultaneously adjust their respective transmission data according to the SKP addition and deletion rules, so as to achieve two retimers
  • the devices for data synchronization described in the foregoing embodiments are all described by including two retimers as an example.
  • the device for data synchronization may also include More than two retimers, so as to achieve the purpose of synchronizing data in multiple retimers, that is, more retimers can be stacked in a similar manner as described above to achieve the purpose of expanding the width of the PCIe link .
  • the embodiment of the present application also provides a data synchronization method, which is specifically shown in FIG. 13.
  • the second retimer acquires a second time point.
  • the second retimer acquires the second time point when the second transmission data is transmitted to the second deviation processing module in the second retimer.
  • the second retimer sends the second time point to the first retimer through the first pin.
  • the second retimer synchronizes the acquired second time point to the first retimer through the first pin.
  • the first retimer determines the target time point through the first time point and the second time point.
  • the target time point can be determined according to the first time point and the second time point obtained by itself in advance.
  • a point in time is a point in time when the first transmission data in the first retimer is transmitted to the first deviation processing module in the first retimer.
  • the first retimer sends the target time point to the second retimer through the first pin.
  • the target time point is synchronized to the second retimer through the first pin. In this way, the target time point exists in both the first retimer and the second retimer.
  • the second retimer sends the second transmission data at the target time point.
  • the second retimer sends the second transmission data at the target time point according to the acquired target time point.
  • the first retimer sends the first transmission data at the target time point.
  • the first retimer will also send the first transmission data at the target time point.
  • step 1305 and step 1306 occur simultaneously, that is, the first retimer and the second retimer are both for the first transmission data transmitted internally at the target time point.
  • the second transmission data is sent, that is, the first retimer and the second retimer align the data transmitted on the respective physical channels at the target time point before sending it out.
  • the first retimer and the second retimer respectively obtain the time point when the data transmitted on each physical channel of the other party is transmitted to the respective internal deviation processing module through the first pin, and the time point is determined by The first retimer determines a target time point according to each time point, and further synchronizes the target time point to the second retimer. When the target time point is reached, start all the physical channels of the cross-retimer The data alignment operation completes the alignment of the data on the physical channels in all retimers.
  • the second time point when the second deviation processing module in the second retimer obtains the second transmission data is synchronized to the first time point through the first pin in the second retimer.
  • the method may further include: the first retimer sends a first trigger instruction to the second retimer through the first pin, and the first trigger instruction is used to instruct the second retimer to execute the acquisition of the second retimer. Steps at two moments.
  • the second deviation processing module in the second retimer obtains the second transmission data, it automatically determines the second time point when the second transmission data is transmitted to the second deviation processing module, and then the second retimer The second time point is automatically synchronized to the first retimer through the first pin. Specifically, the second time point is acquired for triggering the second retimer and the second time point is sent to the first retimer through the first pin. There is no restriction on the way of two hours.
  • the above-mentioned first trigger instruction may be the first time point when the first transmission data acquired by the first retimer is transmitted to the first deviation processing module, or it may be the first re-timer.
  • the timer obtains a target information generated immediately after the first time point, and the target information is used to instruct the second retimer to obtain the second time point and send the second time point to the first retimer.
  • this is correct
  • the specific form of the first trigger instruction is not limited.
  • the first retimer and the second retimer perform data alignment before data alignment (that is, after the first retimer acquires the first time point and the second time point) Before determining the target time point), it is also necessary to send the status of the respective physical channels used for data transmission to the first link negotiation state machine in the first retimer and the second link in the second retimer.
  • the negotiation state machine enables the first link negotiation state machine and the second link negotiation state machine to perform link negotiation before the first deviation processing module determines the target time point.
  • the manner in which the first link negotiation state machine and the second link negotiation state machine perform link negotiation may be: the second retimer obtains the information used to transmit the second transmission data
  • the second state of the channel (such as which physical channels are in the state of transmitting parallel data streams, which physical channels transmit specific physical data streams, which physical channels transmit what data streams, etc.), and pass the second state through the second state
  • the pin is synchronized to the first retimer; after that, the first retimer determines the jump time according to the acquired first state and the second state, and synchronizes the jump time to the second through the second pin
  • the retimer, where the first state is the state of the channel for transmitting the first transmission data in the first retimer; finally, the first link negotiation state machine and the second link negotiation state machine perform the link at the moment of jump Negotiation.
  • the first link negotiation state machine may start timing after acquiring the second state, and after the timing reaches a certain period of time, the first link negotiation state machine and the second link negotiation
  • the second state of the channel used to transmit the second transmission data is acquired in the second retimer, and the second state is synchronized to the first retimer through the second pin.
  • the method may further include: the first retimer sends the first state to the second link negotiation state machine through the second pin, and the first state is used to trigger the second retimer to execute the acquisition of the second state machine.
  • the first state sent to the second link negotiation state machine via the second pin is used to instruct the second link negotiation state machine to obtain the second state.
  • the way of link negotiation can be: the first link negotiation state machine performs link negotiation according to the first state and the second state at the determined jumping moment; the second link negotiation state machine is also at the same jumping moment Perform link negotiation according to the first state and the second state.
  • the first link negotiation state machine and The second link negotiation state machine can simultaneously perform a completely consistent link negotiation mode, so as to achieve the purpose of combining two retimers into one link for link negotiation.
  • the first retimer and the second retimer obtain the status of each physical channel of each other through the second pin (for example, the first state and the second state), and the first retimer
  • the timer determines a jump moment according to the status of all physical channels in the two retimers, and further synchronizes the jump moment to the second retimer.
  • the first retimer The first link negotiation state machine in the timer and the second link negotiation state machine in the second retimer start all link negotiation across the retimers, so that the two retimers are combined into one link. The purpose of link negotiation.
  • the first retimer and the second retimer also need to perform frequency offset processing on the data flowing through the buffers in each retimer, that is, to ensure that each is The receive buffer corresponding to the physical channel for transmitting data does not overflow (that is, no data is lost), and at the same time, it is necessary to ensure that the transmit buffer corresponding to each physical channel that is transmitting data continuously flows (that is, no data is lost).
  • the processing method is to ensure that the corresponding receiving buffer does not overflow and the corresponding sending buffer is continuously flowed through SKP addition and deletion rules (for example, adding SKP data to the corresponding receiving buffer according to the preset rules, and in accordance with the preset rules in the corresponding Delete the SKP data from the transmit buffer).
  • the second retimer obtains the state of the second SKP data in the second buffer in the second retimer (may be called the fourth state), and synchronizes the fourth state to the first retimer through the third pin.
  • the first retimer will also obtain the state of the first SKP data (may be called the third state, and the third state is the value of the first SKP data in the first buffer in the first retimer.
  • the first retimer determines the SKP addition and deletion rules according to the third and fourth states, and further synchronizes the determined SKP addition and deletion rules to the second retimer through the third pin. In this way, the first The retimer and the second retimer respectively adjust the first transmission data and the second transmission data according to the same SKP addition and deletion rules.
  • the second retimer determines the fourth state of the second SKP data in the second buffer in the second retimer, and passes the fourth state through the third pin
  • the method may further include: the first retimer may send a second trigger instruction to the second retimer through the third pin, and the second trigger instruction is used to instruct the second retimer
  • the retimer executes the step of obtaining the fourth state. It can also be that once the second retimer acquires the second SKP data, it automatically determines the fourth state of the second SKP data, and automatically synchronizes the fourth state to the first retimer through the third pin.
  • the manner in which the second retimer is triggered to obtain the fourth state and the fourth state is sent to the first retimer through the third pin is not limited here.
  • the above-mentioned second trigger instruction may be the third state of the first SKP data obtained by the first retimer, or it may be the third state after the first retimer obtains the third state.
  • a target information is generated immediately, and the target information is used to instruct the second retimer to acquire the fourth state and send the fourth state to the first retimer.
  • the specific form of the second trigger instruction is not limited here.
  • the first buffer may include a first receiving buffer and a first sending buffer
  • the second buffer may include a second receiving buffer and a second sending buffer.
  • the method for data synchronization described in the foregoing embodiment includes two retimers as an example for description.
  • the method for data synchronization may also include two The above retimer achieves the purpose of synchronizing data in multiple retimers, that is, more retimers can be stacked in a similar manner as described above to achieve the purpose of expanding the width of the PCIe link.
  • the first retimer and the second retimer respectively obtain the status (e.g., SKP data) received by their respective buffers (e.g., receive buffer and transmit buffer) through the third pin.
  • the third state and the fourth state) and the first retimer determines an SKP addition and deletion rule according to the status of the SKP data received by the buffers in the two retimers, and further synchronizes the SKP addition and deletion rule to
  • the second retimer, the first buffer in the first retimer and the second buffer in the second retimer simultaneously adjust their respective transmission data according to the SKP addition and deletion rules, so as to achieve two retimers

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Abstract

本申请实施例公开了一种数据同步的方法以及装置：通过使用不同通道数量的重定时器堆叠在一起以形成不同宽度的PCIe链路，为了保持同步操作，各个重定时器之间是通过管脚实现同步信息的交互，进而实时同步各个重定时器内部传输的数据的状态，即多个重定时器在传输数据时能遵守由管脚发送的相同的调整规则对所传输的数据进行实时的同步调整，从而达到多个重定时器内部的物理通道合并为一个PCIe链路上的物理通道的目的。

Description

一种数据同步的方法以及装置 技术领域
本申请涉及高速通信技术领域，尤其涉及一种数据同步的方法以及装置。
背景技术
在现代计算机系统中，高速串行计算机扩展总线标准(Peripheral Component Interface Express，PCIe)链路用于互连许多不同的设备和计算机系统。PCIe链路的特性之一是可以具有不同的宽度，如：一个PCIe链路可以具有1个通道(也可称为物理通道)、2个通道、4个通道、8个通道或16个通道(也可分别称为x1、x2、x4、x8或x16)等。通道数量越多，通信的总数据吞吐量也就成比例地增加。但使用PCIe链路的一个缺点是，PCIe链路具有相对有限的长度，这样才使得数据能够高速传输。为了达到更长距离的高速传输，就开发了重定时器(Retimer)，以允许PCIe链路的各个通道上的信号被重新定时或重新同步后被重新驱动，即通过重定时器进行信号中继以及滤除PCIe链路上信号的抖动。
由于PCIe链路可以具有x1、x2、x4、x8或x16等不同类型的通道数量，因此通常使用针对给定宽度的重定时器。例如，若PCIe链路中存在重定时器，8通道的PCIe链路对应使用的就是8通道的重定时器，16通道的PCIe链路对应使用的就是16通道的重定时器。
然而，若PCIe链路需要更多通道(如，32通道)，而该PCIe链路中对应的重定时器(如，该重定时器只有8通道)不能满足PCIe链路的带宽需求，就需要更换该重定时器(如，更换为具有32通道的重定时器)，非常不便利且灵活性差，并且具有更多通道数量的重定时器结构也会相对更复杂，其所需的空间也更大，这在一些空间受限的印刷电路板中的应用中具有局限性。
发明内容
本申请实施例第一方面提供了一种数据同步的方法以及装置，用于使得多个重定时器堆叠成一个通道数量更多的PCIe链路来传输数据，即该多个重定时器在传输数据时能遵守相同的调整规则对所传输的数据进行实时的同步调整。
有鉴于此，本申请实施例第一方面提供一种装置，具体包括：
第一重定时器(也可称为主重定时器)与第二重定时器(也可称为从重定时器，可以是一个或多个)之间通过管脚来互相传递信号，第一重定时器包括第一偏差处理模块，第二重定时器包括第二偏差处理模块。首先，第二重定时器获取到在第二重定时器内部传输的数据(即第二传输数据)传输至第二偏差处理模块的第二时刻点(第二重定时器获取第二时刻点的步骤可以由某个指令触发执行，如第一重定时器通过管脚向第二重定时器发送的指令)，并将该第二时刻点通过管脚发送至第一重定时器，第一重定时器根据第一时刻点(即在第一重定时器内部传输的第一传输数据传输至第一偏差处理模块的时刻点)以及由第二重定时器发送过来的第二时刻点确定出一个目标时刻点(该目标时刻点在第一时刻点以及第二时刻点之后)，并将这个目标时刻点通过管脚同步至第二重定时器，最后，第一偏差处理模块以及第二偏差处理模块在该目标时刻点同时将各自收到的传输数据再发送出 去，从而使得数据的传输实现同步。
在本申请上述实施方式中，第一重定时器以及第二重定时器能够基于相同的目标时刻点实时、同步的对多个重定时器内部正在各个通道上传输的数据进行调整，即使得跨重定时器的数据在各个通道上的传输都能保持同步和连续，从而在不增加额外成本和复杂度的前提下，满足了PCIe链路更高带宽的需求。
结合本申请第一方面，在本申请第一方面的第一种实施方式中，第二偏差处理模块用于获取第二传输数据传输至第二偏差处理模块的第二时刻点，并将该第二时刻点通过第一管脚同步至第一偏差处理模块的步骤可以由第一偏差处理模块通过第一管脚向第二偏差处理模块发送的触发指令(可称为第一触发指令)触发而执行，该第一触发指令就用于指示第二偏差处理模块获取第二时刻点并将该第二时刻点通过第一管脚同步至第一偏差处理模块的步骤。
在本申请上述实施方式中，阐述了第二偏差处理模块是由第一偏差处理模块通过第一管脚发送的第一触发指令触发执行获取第二时刻点的步骤的，具备灵活性。
结合本申请第一方面的第一种实施方式，在本申请第一方面的第二种实施方式中，上述第一触发指令可以是第一偏差处理模块获取到的第一传输数据传输至第一偏差处理模块的第一时刻点。
在本申请上述实施方式中，说明第一触发指令还可以是第一时刻点，非常简便。
结合本申请第一方面以及本申请第一方面的的第一种实施方式至第二种实施方式，在本申请第一方面的第三种实施方式中，第一重定时器还可以包括第一链路协商状态机，第二重定时器还可以包括第二链路协商状态机。其中，该第一链路协商状态机以及第二链路协商状态机用于在第一偏差处理模块确定目标时刻点之前先进行链路协商。
在本申请上述实施方式中，阐述了该装置中所包括的两个重定时器在用于数据对齐之前，还需要进行链路协商。
结合本申请实施例第一方面的第三种实施方式，在本申请第一方面的第四种实施方式中，该第一链路协商状态机以及第二链路协商状态机用于在第一偏差处理模块确定目标时刻点之前先进行链路协商具体可以是：第二链路协商状态机，具体用于获取第二偏差处理模块内各个物理通道的状态(如哪些物理通道处于传输并行数据流的状态、哪些物理通道传输了物理的特定数据流、哪些物理通道传输了什么样的数据流等)，该状态可称为第二状态，之后第二链路协商状态机还用于将该第二状态通过第二管脚同步至第一链路协商状态机，类似地，该第一链路协商状态机，具体用于获取第一偏差处理模块内各个物理通道的状态(可称为第一状态)，之后，该第一链路协商状态机就用于根据该第一状态以及第二状态确定跳转时刻，并用于进一步通过第二管脚将跳转时刻同步至第二链路协商状态机，这样，第一链路协商状态机以及第二链路协商状态机，还用于在跳转时刻同时进行链路协商。如，可以是第一链路协商状态机获取到第二状态后开始计时，计时达到特定时长后，第一链路协商状态机以及第二链路协商状态机同时进行链路协商。
在本申请上述实施方式中，具体阐述了装置中的两个重定时器内的第一链路协商状态机以及第二链路协商状态机具体如何用于通过第二管脚传递信息以进行链路协商，具备可 操作性。
结合本申请实施例第一方面的第四种实施方式，在本申请第一方面的第五种实施方式中，第二链路协商状态机，具体还用于获取第二偏差处理模块内各个物理通道的第二状态，并将该第二状态同步至第一链路协商状态机的步骤可以由第一链路协商状态机通过第二管脚向第二链路协商状态机发送的第一状态触发而执行，经由第二管脚发送至第二链路协商状态机的第一状态就用于指示第二链路协商状态机执行获取第二状态的步骤。
在本申请上述实施方式中，阐述了第二链路协商状态机是用于由第一链路协商状态机通过第二管脚发送的第一状态触发执行获取第二状态的步骤的，具备灵活性。
结合本申请实施例第一方面的第五种实施方式，在本申请第一方面的第六种实施方式中，第一链路协商状态机以及第二链路协商状态机用于在跳转时刻同时进行链路协商的方式可以是：第一链路协商状态机，具体用于在确定的跳转时刻根据第一状态以及第二状态进行链路协商；第二链路协商状态机，具体用于在同样的跳转时刻根据第一状态以及第二状态进行链路协商。根据PCIe协议的定义可知，只要确定了同样的跳转时刻(即保证两个链路协商状态机同步工作)，第一链路协商状态机以及第二链路协商状态机就可以同时进行完全一致的链路协商方式，从而达到两个重定时器合并为一个链路进行链路协商的目的。
在本申请上述实施方式中，第一链路协商状态机以及第二链路协商状态机都用于获取到第一状态和第二状态，因此在同样的跳转时刻，根据PCIe协议定义的跳转方式，第一链路协商状态机以及第二链路协商状态机就可以用于实现完全同步的跳转方式，简单方便。
结合本申请第一方面以及本申请第一方面的第一种实施方式至第六种实施方式，在本申请第一方面的第七种实施方式中，第一重定时器还可以包括第一缓存器，第二重定时器还可以包括第二缓存器；其中，第二缓存器，用于确定第二字符码有序集(也可称为SKP，PCIe协议中定义的一种物理层的字符码)数据的状态(可称为第四状态)，并将第四状态通过第三管脚同步至第一缓存器，类似地，第一缓存器，也用于获取第一SKP数据的状态(可称为第三状态)，之后，该第一缓存器就用于根据第三状态以及第四状态确定SKP增删规则，并用于进一步通过第三管脚将确定的SKP增删规则同步至第二缓存器，这样，第一缓存器以及第二缓存器，还用于根据所述相同的SKP增删规则分别调整第一传输数据以及第二传输数据。
在本申请上述实施方式中，具体阐述了装置中的两个重定时器内的第一缓存器以及第二缓存器如何用于通过第三管脚传递信息以同步处理频偏，具备可操作性。
结合本申请第一方面第七种实施方式，在本申请第一方面的第八种实施方式中，第二缓存器在用于确定第二SKP数据的第四状态，并将该第四状态通过第三管脚同步至第一缓存器的步骤可以由第一缓存器通过第三管脚向第二缓存器发送的触发指令(可称为第二触发指令)触发而执行，该第二触发指令就用于指示第二缓存器执行获取所述第四状态并将该第四状态通过第三管脚同步至第一缓存器的步骤。
在本申请上述实施方式中，阐述了第二缓存器是由第一缓存器通过第三管脚发送的第二触发指令触发执行获取第四状态的步骤的，具备灵活性。
结合本申请第一方面第八种实施方式，在本申请第一方面的第九种实施方式中，上述 第二触发指令可以是第一缓存器获取到的第一SKP数据的第三状态。
在本申请上述实施方式中，说明第二触发指令还可以是第三状态，非常简便。
结合本申请第一方面的第七种实施方式至第九种实施方式，在本申请第一方面的第十种实施方式中，第一缓存器可以包括第一接收缓存器以及第一发送缓存器；第二缓存器可以包括第二接收缓存器以及第二发送缓存器。
在本申请上述实施方式中，说明了第一缓存器以及第二缓存器可以包括多种形式的缓存器，具备灵活性。
结合本申请第一方面以及本申请第一方面的第一种实施方式至第十种实施方式，在本申请第一方面的第十一种实施方式中，第二重定时器可以是一个重定时器，也可以是多个重定时器，具体此处不做限定。
在本申请上述实施方式中，不局限于该装置只能包括两个重定时器，还可以包括更多个重定时器，以满足对各种PCIe链路宽度的需求。
本申请第二方面还提供了一种数据同步的方法，具体包括：
首先，第二重定时器通过第一管脚将第二重定时器内的第二传输数据传输至第二重定时器内第二偏差处理模块的第二时刻点同步至第一重定时器；之后，第一重定时器根据获取到的第一时刻点以及第二时刻点确定目标时刻点，并将目标时刻点通过第一管脚同步至第二重定时器，其中，第一时刻点为第一重定时器内的第一传输数据传输至第一重定时器内第一偏差处理模块的时刻点；最后，第一偏差处理模块以及第二偏差处理模块在目标时刻点分别发送第一传输数据以及第二传输数据，以实现同步对齐数据的目的。
在本申请上述实施方式中，第一重定时器以及第二重定时器能够基于相同的目标时刻点实时、同步的对多个重定时器内部正在各个通道上传输的数据进行调整，即使得跨重定时器的数据在各个通道上的传输都能保持同步和连续，从而在不增加额外成本和复杂度的前提下，满足了PCIe链路更高带宽的需求。
结合本申请第二方面，在本申请第二方面的第一种实施方式中，在第二重定时器通过第一管脚将第二重定时器内第二偏差处理模块获取到第二传输数据的第二时刻点同步至第一重定时器之前，该方法还可以包括：第一重定时器通过第一管脚向第二重定时器发送第一触发指令，该第一触发指令就用于指示第二重定时器执行获取第二时刻点的步骤。
在本申请上述实施方式中，阐述了第二重定时器是由第一重定时器通过第一管脚发送的第一触发指令触发执行获取第二时刻点的步骤的，具备灵活性。
结合本申请第二方面的第一种实施方式，在本申请第二方面的第二种实施方式中，上述第一触发指令可以是第一重定时器获取到的第一传输数据传输至第一偏差处理模块的第一时刻点。
在本申请上述实施方式中，说明第一触发指令还可以是第一时刻点，非常简便。
结合本申请第二方面以及本申请第二方面的的第一种实施方式至第二种实施方式，在本申请第二方面的第三种实施方式中，第一重定时器以及第二重定时器在进行数据对齐之前(即在第一重定时器根据获取到的第一时刻点以及第二时刻点确定目标时刻点之前)，还需要分别将各自用于传输数据的物理通道的状态发送至第一重定时器内的第一链路协商状 态机以及第二重定时器内的第二链路协商状态机，使得该第一链路协商状态机以及第二链路协商状态机在第一偏差处理模块确定目标时刻点之前先进行链路协商。
在本申请上述实施方式中，阐述了该装置中所包括的两个重定时器在数据对齐之前，还需要进行链路协商。
结合本申请实施例第二方面的第三种实施方式，在本申请第二方面的第四种实施方式中，第一链路协商状态机以及第二链路协商状态机进行链路协商的方式可以是：第二重定时器获取用于传输第二传输数据的通道的第二状态(如哪些物理通道处于传输并行数据流的状态、哪些物理通道传输了物理的特定数据流、哪些物理通道传输了什么样的数据流等)，并将第二状态通过第二管脚同步至第一重定时器；之后，由该第一重定时器根据获取到的第一状态以及第二状态确定跳转时刻，并通过第二管脚将该跳转时刻同步至第二重定时器，其中，第一状态为第一重定时器中传输第一传输数据的通道的状态；最后，第一链路协商状态机以及第二链路协商状态机在跳转时刻进行链路协商。如，可以是第一链路协商状态机获取到第二状态后开始计时，计时达到特定时长后，第一链路协商状态机以及第二链路协商状态机同时进行链路协商。
在本申请上述实施方式中，具体阐述了装置中的两个重定时器内的第一链路协商状态机以及第二链路协商状态机具体如何通过第二管脚传递信息以进行链路协商，具备可操作性。
结合本申请实施例第二方面的第四种实施方式，在本申请第二方面的第五种实施方式中，在第二重定时器获取传输第二传输数据的通道的第二状态，并将第二状态通过第二管脚同步至所述第一重定时器之前，该方法还可以包括：第一重定时器通过第二管脚向第二链路协商状态机发送第一状态，该第一状态用于触发第二重定时器执行获取第二状态的步骤，经由第二管脚发送至第二链路协商状态机的第一状态就用于指示第二链路协商状态机行获取第二状态的步骤。
在本申请上述实施方式中，阐述了第二链路协商状态机是由第一链路协商状态机通过第二管脚发送的第一状态触发执行获取第二状态的步骤的，具备灵活性。
结合本申请实施例第二方面的第五种实施方式，在本申请第二方面的第六种实施方式中，第一链路协商状态机以及第二链路协商状态机在跳转时刻同时进行链路协商的方式可以是：第一链路协商状态机在确定的跳转时刻根据第一状态以及第二状态进行链路协商；第二链路协商状态机也在同样的跳转时刻根据第一状态以及第二状态进行链路协商，根据PCIe协议的定义可知，只要确定了同样的跳转时刻(即保证两个链路协商状态机同步工作)，第一链路协商状态机以及第二链路协商状态机就可以同时进行完全一致的链路协商方式，从而达到两个重定时器合并为一个链路进行链路协商的目的。
在本申请上述实施方式中，第一链路协商状态机以及第二链路协商状态机内都获取由第一状态和第二状态，因此在同样的跳转时刻，根据PCIe协议定义的跳转方式，第一链路协商状态机以及第二链路协商状态机就可以实现完全同步的跳转方式，简单方便。
结合本申请第二方面以及本申请第二方面的第一种实施方式至第六种实施方式，在本申请第一方面的第七种实施方式中，第二重定时器获取第二重定时器中第二缓存器内的第 二SKP数据的状态(可称为第四状态)，并将第四状态通过第三管脚同步至第一重定时器，类似地，第一重定时器也将获取第一SKP数据的状态(可称为第三状态，该第三状态为第一重定时器中第一缓存器内的第一SKP数据的状态)，之后，该第一重定时器就根据第三状态以及第四状态确定SKP增删规则，并进一步通过第三管脚将确定的SKP增删规则同步至第二重定时器，这样，第一重定时器以及第二重定时器就根据所述相同的SKP增删规则分别调整第一传输数据以及第二传输数据。
在本申请上述实施方式中，具体阐述了装置中的两个重定时器内的第一缓存器以及第二缓存器如何通过第三管脚传递信息以同步处理频偏，具备可操作性。
结合本申请第二方面第八种实施方式，在本申请第二方面的第九种实施方式中，上述第二触发指令可以是第一缓存器获取到的第一SKP数据的第三状态。
在本申请上述实施方式中，说明第二触发指令还可以是第三状态，非常简便。
结合本申请第二方面的第七种实施方式至第九种实施方式，在本申请第二方面的第十种实施方式中，第一缓存器可以包括第一接收缓存器以及第一发送缓存器；第二缓存器可以包括第二接收缓存器以及第二发送缓存器。
在本申请上述实施方式中，说明了第一缓存器以及第二缓存器可以包括多种形式的缓存器，具备灵活性。
结合本申请第二方面以及本申请第二方面的第一种实施方式至第十种实施方式，在本申请第二方面的第十一种实施方式中，第二重定时器可以是一个重定时器，也可以是多个重定时器，具体此处不做限定。
在本申请上述实施方式中，不局限于该装置只能包括两个重定时器，还可以包括更多个重定时器，以满足对各种PCIe链路宽度的需求。
本申请实施例第三方面提供了一种装置，该装置具有实现上述第二方面或第二方面任意一种可能实现方式的方法的功能。该功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。该硬件或软件包括一个或多个与上述功能相对应的模块。
从以上技术方案可以看出，本申请实施例具有以下优点：第一重定时器(也可称为主重定时器)与第二重定时器(也可称为从重定时器，可以是一个或多个)之间通过管脚来互相传递信号，第一重定时器包括第一偏差处理模块，第二重定时器包括第二偏差处理模块。首先，第二重定时器获取到在第二重定时器内部传输的数据(即第二传输数据)传输至第二偏差处理模块的第二时刻点(第二重定时器获取第二时刻点的步骤可以由某个指令触发执行，如第一重定时器通过管脚向第二重定时器发送的指令)，并将该第二时刻点通过管脚发送至第一重定时器，第一重定时器根据第一时刻点(即在第一重定时器内部传输的第一传输数据传输至第一偏差处理模块的时刻点)以及由第二重定时器发送过来的第二时刻点确定出一个目标时刻点(该目标时刻点在第一时刻点以及第二时刻点之后)，并将这个目标时刻点通过管脚同步至第二重定时器，最后，第一偏差处理模块以及第二偏差处理模块在该目标时刻点同时将各自收到的传输数据再发送出去，从而使得数据的传输实现同步。在本申请实施例中，第一重定时器以及第二重定时器能够基于相同的目标时刻点实时、同步的对多个重定时器内部正在各个通道上传输的数据进行调整，即使得跨重定时器的数据 在各个通道上的传输都能保持同步和连续，从而在不增加额外成本和复杂度的前提下，满足了PCIe链路更高带宽的需求。
附图说明
图1为没有重定时器的PCIe链路的示意图；
图2为具有一个重定时器的PCIe链路的示意图；
图3为具有多个重定时器的PCIe链路的示意图；
图4为设备与设备之间通过重定时器构成完整PCIe链路的一个示意图；
图5为重定时器内部结构的一个示意图；
图6为重定时器内部形成的多个通道的结构示意图；
图7为本申请实施例各个不同类型的PCIe链路由多个重定时器通过管脚连接而拓宽链路宽度的示意图；
图8为本申请实施例两个重定时器通过管脚同步信息来实现数据同步的示意图；
图9为本申请实施例中第一管脚包括的管脚数量的示意图；
图10为本申请实施例数据在通道中传输的示意图；
图11为本申请实施例数据在重定时器的偏差处理模块实现数据对齐的示意图；
图12为本申请实施例管脚信号的一个示意图；
图13为本申请实施例提供的一种数据同步的方法的示意图。
具体实施方式
本申请实施例提供了一种数据同步的方法以及装置，用于使得多个重定时器堆叠成一个通道数量更多的PCIe链路来传输数据，即该多个重定时器在传输数据时能遵守相同的调整规则对所传输的数据进行实时的同步调整。
在介绍本申请实施例之前，首先对本申请实施例可能涉及到的一些系统架构、相关结构及一些在本申请实施例中可能出现的概念进行介绍，用于帮助理解本发明。应理解的是，本申请所阐述的相关系统架构、相关结构等仅示例出与本申请实施例相关的部分，并且以下的对其进行的说明以及相关的概念解释可能会因为本申请实施例的具体情况有所限制，但并不代表本申请仅能局限于该具体情况，在不同实施例的具体情况可能也会存在差异，具体此处不做限定。并且在本申请中，众所周知的结构和设备以框图的形式而不是详细地示出，以避免模糊本申请。
重定时器(Retimer)是类似于一个物理层芯片的器件，信号在经过重定时器的时候，通过重定时器内部的时钟可以重构信号，使得信号传输能量增加，然后再继续传输。也就是说，重定时器是内部具有时钟数据恢复(Clock Data Recover，CDR)的器件，实现信号的恢复之后，然后再通过其内部的物理通道把信号发送出去，从而可以减轻信号的抖动。
图1示出了没有重定时器的PCIe链路，设备1和设备2经由链路A和链路B耦合在一起(链路A和链路B是根据数据的传输方向进行划分，实际上是综合在一个PCIe链路，即链路1和链路2构成设备1和设备2之间的一个完整的PCIe链路)，设备1和设备2之间需要交互的数据就 通过链路A和链路B实现高速传输，由于PCIe链路具有相对有限的长度(为了保证高速传输，因此PCIe链路的长度有限)，若设备1和设备2之间的物理距离过于遥远，势必会导致单个的PCIe链路过长，从而影响数据的传输效率。为此，在设备1和设备2之间连接上重定时器，就可使得PCIe链路上正在传输的数据被重新定时或重新同步后被重新驱动，如图2示出了具有一个重定时器的PCIe链路，设备1和设备2耦合到一个重定时器01，该重定时器01通过子链路A01和子链路B02耦合到设备1，并通过子链路A02和子链路B01耦合到设备2，这些子链路就构成设备1与设备2之间数据交互的一个完整PCIe链路。并且，这些子链路同样遵循PCIe协议，重定时器01可配置为以子链路所遵循的协议操作以实现设备1和设备2之间的数据交互。类似地，为实现更远距离的高速传输，设备1和设备2之间的PCIe链路还可以具有两个或两个以上的重定时器，如图3所示，示出了具有多个重定时器的PCIe链路，这些重定时器通过类似串联的方式依次连接起来(如图3中的重定时器1、重定时器2、……、重定时器n，n≥2)，连接起重定时器1、重定时器2、……、重定时器n的子链路A1、子链路A2、子链路A3、……、子链路An、子链路An+1以及子链路B1、子链路B2、……、子链路Bn-1、子链路Bn、子链路Bn+1就构成设备1和设备2之间数据交互的一个完整PCIe链路。
为便于更进一步的理解，下面以设备1为中央处理器(Central Processing Unit/Processor，CPU)板、设备2为输入输出(Input/Output，I/O)板为例详细示意CPU板与I/O板如何通过重定时器形成一个PCIe链路，请参阅图4，CPU板401通过背板402和I/O板403连接，其中，重定时器4012置于CPU板401内(重定时器可以设置于设备内部，也可以设置于设备外部，具体不做限定。图4示意的是重定时器设置在CPU板内部)，并与CPU板401内的CPU4011连接，这样CPU4011与重定时器4012之间就形成整个PCIe链路的一个子链路4013(如，PCIe的16通道的子链路)，之后，重定时器4012再连接到背板402上的连接器404，连接器404再与连接器405进行连接以构成整个PCIe的子链路4021，连接器405再进一步与I/O板403内部的重定时器4031连接，重定时器4031再与I/O板403内部的CPU4032连接以构成整个PCIe的子链路4033。由于CPU4011与CPU4032之间的距离问题以及存在连接器404和405，因此CPU4011与CPU4032之间的数据交互不能直接进行。但由于在CPU板401和I/O板403内部分别设置有两个重定时器，这样CPU4011与CPU4032之间的数据交互就可以通过子链路4013、子链路4021、子链路4033构成的一个完整的PCIe链路(如，16通道的PCIe链路)来进行高速传输。
上述图2至图4对重定时器在实际中的应用进行了介绍，下面对重定时器的内部结构进行介绍，如图5所示，为重定时器内部的一个典型结构，该重定时器包括串行/解串器(Serializer and De-serializer，Serdes)501、缓存器502、偏差处理模块503、链路协商状态机504、缓存器505、串行/解串器506。以数据流的流向来对重定时器内部的上述各个器件进行说明：数据流在被重定时器内的串行/解串器501(也可称为接收串行/解串器501)获取之前是串行的数据流，串行/解串器501获取到PCIe链路上的串行数据流后，会将该串行数据流转变为并行数据流，并行数据流是通过串行/解串器501的通道(Lane，也可称为物理通道)进行传输的，如图6所示的串行/解串器601中具有N+1个用于传输数据的物理通道(即Lane0至LaneN)，若N＝1，则说明该重定时器为具有2个物理通道的重定时器(即 x2类型的重定时器)，若N＝7，则说明该重定时器为具有8个物理通道的重定时器(即x8类型的重定时器)，若N＝15，则说明该重定时器为具有16个物理通道的重定时器(即x16类型的重定时器)，重定时器内部有多少个物理通道，该重定时器就为对应类型(如，x1、x2、x8、x16等)的重定时器，具体此处不予赘述。需要说明的是，同一个重定时器内部的物理通道上正在传输的并行数据流互相之间是不交互的，但是各个正在传输的数据流的物理通道之间必须保持传输的同步。还需要说明的是，重定时器内部的所有物理通道在传输数据流时并不要求全部被使用，例如，对于一个x16类型的重定时器，在传输数据时，可以只使用其中的10个物理通道进行数据的传输。
串行/解串器501将串行的数据流处理成并行的数量流以后，就会将该并行数据流写入缓存器502(也可称为接收缓存器502)，缓存器502是数据通路的接收缓存，每个物理通道上都对应有一个缓存器，如，若串行/解串器501内有8个物理通道，那么缓存器502就是指对应每个物理通道上的缓存器的集合(即有8个缓存器)，如图6所示，串行/解串器601中具有N+1个用于传输数据的物理通道，那么对应的缓存器602就是缓存器10至缓存器1N的集合。由于缓存器502的写时钟是串行/解串器501中由CDR恢复出来的时钟，而缓存器502的读时钟是本地工作时钟，即缓存器502的读写时钟是异步时钟，因此被写入到缓存器502中的并行数据流会存在频偏。为消除频偏的影响，缓存器502从串行/解串器501接收到并行数据流后，要先进行频偏处理，即要保证每个正在传输数据的物理通道对应的接收缓存器不溢出(即不丢失数据)，其处理的方式是通过字符码(SKP，物理层的一种字符码)增删规则来保证对应的接收缓存器不溢出(如，按照预设规则在对应的接收缓存器中删除SKP数据)。
缓存器502对并行数据流进行频偏处理之后，进一步将并行数据流传输至偏差处理模块503，类似的，偏差处理模块503内也具有与串行/解串器501内数量相同的物理通道(如，图6中偏差处理模块603中具有Lane0至LaneN共N+1个物理通道)用于接收经由缓存器502包括的各个缓存器传输过来的并行数据流，由于并行数据流是由各个不同的物理通道所对应的缓存器传输至偏差处理模块503，那么经由不同缓存器所传输的并行数据流会由于时延偏差、物理路径的长短不同等原因导致偏差处理模块503接收到的各个缓存器发送的数据并不同步(即有先有后，并不会严格同步到达)，偏差处理模块503的作用之一就是将其内部各个物理通道上获取到的并行数据流对齐。
需要说明的是，偏差处理模块503在对获取到的各个物理通道的数据流进行对齐之前，还需要将各个物理通道的状态(如哪些物理通道处于传输并行数据流的状态、哪些物理通道传输了物理的特定数据流、哪些物理通道传输了什么样的数据流等)发送至链路协商状态机(Link Training and Status State Machine，LTSSM)504，由链路协商状态机504根据各个物理通道的状态进行链路协商(链路协商的方式在PCIe协议中都有明确定义，此处不予赘述)。之后，链路协商状态机504将协商结果(如，协商成功、协商失败等)发送至偏差处理模块503，若协商结果为协商成功，那么响应于该协商结果，偏差处理模块503会将从缓存器502获取到的各个物理通道上的并行数据流进行对齐，之后将对齐后的并行数据流进一步写入至缓存器505(也可称为发送缓存器505)。
与缓存器502类似，缓存器505是数据通路的发送缓存，每个物理通道上都对应有一个 缓存器，如，若串行/解串器501内有8个物理通道，那么缓存器505就是指对应每个物理通道上的缓存器的集合，如图6所示，串行/解串器601中具有N+1个用于传输数据的物理通道，那么对应的缓存器605就是缓存器20至缓存器2N的集合。类似地，缓存器505中获取到的并行数据流也存在频偏，因此其也需对获取到的并行数据流进行频偏处理，即要保证每个正在传输数据的物理通道对应的发送缓存器不断流(即不丢失数据)，其处理的方式也是通过SKP增删规则来保证对应的发送缓存器不断流(如，按照预设规则在对应的发送缓存器中增加SKP数据)。
缓存器505对并行数据流进行频偏处理之后，将进一步将并行数据流写入串行/解串器506(也可称为发送串行/解串器506)，类似的，串行/解串器506内也具有与串行/解串器501内数量相同的物理通道(如，图6中串行/解串器506中具有Lane0至LaneN共N+1个物理通道)，串行/解串器506将获取到的各个物理通道上的并行数据流转换为串行数据流后再经由PCIe链路发送出去。
由上述可知，数据流在重定时器内部的传输是经由多个物理通道进行的，并且各个物理通道之间传输的数据不交互，但重定时器内部各个物理通道上所传输的数据需要进行同步。目前，重定时器只能针对自身内部的各个物理通道上传输的数据进行同步，并且多个重定时器只能通过类似串联的连接方式(如图3所示的方式)以延长PCIe链路的长度。但在实际应用中，若PCIe链路需要更多物理通道(如，32通道)，而该PCIe链路中对应的重定时器(如，该重定时器只有8通道)不能满足PCIe链路的带宽需求，就需要更换该重定时器(如，更换为具有32通道的重定时器)，若PCIe链路中以类似串联的形式接入的重定时器越多，更换就越麻烦。
基于此，本申请实施例提供了一种装置，其实现思路是，在多个重定时器之间，通过管脚发送同步信息，进而实时同步各个重定时器内部传输的数据的状态，从而达到多个重定时器内部的物理通道合并为一个PCIe链路上的物理通道的目的。为便于理解，可参阅图7，假设图7中的每个重定时器均为4个物理通道的重定时器，若PCIe链路只要一个重定时器，如(a)中的连接方式，那么此时构成的PCIe链路就为x4类型的PCIe链路；如(b)所示，两个具有4个物理通道的重定时器通过管脚01进行同步信息的传递就可以实现x8类型的PCIe链路；类似地，如(c)所示，四个分别具有4个物理通道的重定时器通过管脚02、管脚03、管脚04进行同步信息的传递就可以实现x16类型的PCIe链路；通过采用不同数量、不同类型的重定时器按照上述所述的实现思路进行堆叠，就可以实现对已有的PCIe链路拓展成满足用户需求的具有各种物理通道的PCIe链路。需要说明的是，在上述实现方式中，管脚01、管脚02、管脚03或管脚04是一个或多个管脚的集合，并不限定只是一个管脚。
为便于理解，下面以两个重定时器为例，详细介绍本申请实施例所提供的一种装置如何通过管脚同步数据，具体请参阅图8，以数据流由设备1向设备2传输为例，具体阐述第一重定时器与第二重定时器内部各个不同模块在同步的过程中所起到的作用：
一、第一重定时器与第二重定时器如何通过第一管脚同步进行数据的对齐。
在本申请实施例中，该用于数据同步的装置具体可以包括第一重定时器以及第二重定时器，其中，第一重定时器包括有第一偏差处理模块803、第二重定时器包括有第二偏差处 理模块703，第二偏差处理模块703用于获取在第二重定时器内进行传输的数据(可称为第二传输数据)传输至第二偏差处理模块703的时刻点(可称为第二时刻点)，并将该第二时刻点通过第一管脚同步至第一偏差处理模块803，类似地，该第一偏差处理模块803也用于获取在第一重定时器内进行传输的数据(可称为第一传输数据)传输至第一偏差处理模块803的时刻点(可称为第一时刻点)，之后，第一偏差处理模块803就用于根据该第一时刻点以及第二时刻点确定一个目标时刻点，该目标时刻点为在该第一时刻点以及第二时刻点之后的时刻点，并进一步通过第一管脚将该目标时刻点同步至第二偏差处理模块703，这样，第一偏差处理模块703以及第二偏差处理模块803就可在达到该目标时刻点时分别将第一传输数据以及第二传输数据发送出去，也就是说，第一偏差处理模块803以及第二偏差处理模块703在目标时刻点将各自内部各个物理通道传输的数据进行对齐后再同步进行数据传输。
需要说明的是，在本申请的一些实施方式中，第二偏差处理模块703用于获取第二传输数据传输至第二偏差处理模块703的第二时刻点，并将该第二时刻点通过第一管脚同步至第一偏差处理模块803的步骤可以由第一偏差处理模块803通过第一管脚向第二偏差处理模块703发送的触发指令(可称为第一触发指令)触发而执行，该第一触发指令就用于指示第二偏差处理模块703获取第二时刻点并将该第二时刻点通过第一管脚同步至第一偏差处理模块803的步骤；也可以是第二偏差处理模块一旦获取到第二传输数据，就自动确定该第二传输数据传输至第二偏差处理模块703的第二时刻点，并自动通过该第一管脚将第二时刻点同步至第一偏差处理模块803，具体此处对触发第二偏差处理模块703获取第二时刻点并通过第一管脚向第一偏差处理模块803发送该第二时刻点的方式不做限定。
还需要说明的是，在本申请的一些实施方式中，上述第一触发指令可以是第一偏差处理模块803获取到的第一传输数据传输至第一偏差处理模块803的第一时刻点，也可以是第一偏差处理模块803获取到第一时刻点后随即生成的一个目标信息，该目标信息用于指示第二偏差处理模块703获取第二时刻点并向第一偏差处理模块803发送该第二时刻点，具体此处对第一触发指令的具体形式不做限定。
还需要说明的是，在本申请的一些实施方式中，第一管脚可以是一个，也可以是多个，第一管脚也可以是单比特(bit)管脚，也可以是多bit管脚，具体此处不做限定。
为便于理解上述方案，下面以第一管脚包括四个管脚进行信息同步为例，对第一偏差处理模块803以及第二偏差处理模块703对同步进行数据对齐的方式进行说明，详细示意图请参阅图9，第一管脚包括管脚11、管脚12、管脚13、管脚14，其中，第一偏差处理模块803输出两个管脚(即管脚11和管脚12)，第二偏差处理模块703通过管脚11和管脚12获取第一偏差处理模块803发送的信息，第二偏差处理模块703输出两个管脚(即管脚13和管脚14)，第一偏差处理模块803通过管脚13和管脚14获取第二偏差处理模块703发送的信息。由于重定时器内部偏差处理模块进行数据对齐的方式是在特定时间内，偏差处理模块获取到各个正在物理通道上传输的数据所携带的协议特定字符(该协议特定字符就表示各个物理通道的数据被同时发出的标志，如训练序列有序集TS1/TS2，其在PCIe协议中有定义，此处不予赘述)，偏差处理模块根据该协议特定字符进行数据对齐后再同时将各个通道的数据进行传输。以x4类型的单个重定时器为例进行说明：如图10所示，重定时器内各个模块(如，偏 差处理模块、缓存器等)内部均有4个物理通道(如，图10中的Lan0至Lan4)，每个物理通道内的数据由接收缓存器发出时，会在同时发出的时刻点在传输的数据上携带协议特定字符TS1，该协议特定字符TS1包括一个COM和后面15个8bit数据。在发送端(即重定时器的接收缓存器)，4个物理通道是同时发送的COM，4个物理通道上的数据传输至偏差处理模块时，可能会出现如图10所示的情形，即COM不对齐，物理通道与物理通道之间，数据存在偏差(即数据到达偏差处理模块的时间不同导致的)，那么在偏差处理模块中进行偏差处理使得各个物理通道上的数据被对齐，如图11所示即为对齐后的数据所携带的协议特定字符TS1，之后，偏差处理模块就可以将对齐后的数据再次传输至重定时器内的下一个模块。因此，在具有两个重定时器的情形中，当第一重定时器内通过各个物理通道进行传输的第一传输数据传输至第一偏差处理模块803时，也会有先后之差，那么当第一偏差处理模块803获取到物理通道中第一个传输的数据中携带的协议特定字符(可称为第一个协议特定字符A1)时，就会确定获取到该第一个协议特定字符A1传输至第一偏差处理模块803的时刻点1，并将该时刻点1通过管脚11同步至第二偏差处理模块703；当第一偏差处理模块803获取到物理通道中最后一个传输的数据中携带的协议特定字符(可称为最后一个协议特定字符A2)时，就会确定获取到该最后一个协议特定字符A2传输至第一偏差处理模块803的时刻点2，并将该时刻点2通过管脚12同步至第二偏差处理模块703。类似地，
当第二重定时器内通过各个物理通道进行传输的第二传输数据传输至第二偏差处理模块703时，同样会有先后之差，那么当第二偏差处理模块703获取到物理通道中第一个传输的数据中携带的协议特定字符(可称为第一个协议特定字符B1)时，就会确定获取到该第一个协议特定字符B1传输至第二偏差处理模块703的时刻点3，并将该时刻点3通过管脚13同步至第一偏差处理模块803；当第二偏差处理模块703获取到物理通道中最后一个传输的数据中携带的协议特定字符(可称为最后一个协议特定字符B2)时，就会确定获取到该最后一个协议特定字符B2传输至第二偏差处理模块703的时刻点4，并将该时刻点4通过管脚14同步至第一偏差处理模块803。之后，第一偏差处理模块803可以判断时刻点1、时刻点2、时刻点3、时刻点4之间的时间差是否在协议规定的标准时间差内(如果计算得到时间差大于协议规定的标准时间差，则说明数据传输出现错误或延迟，此时不可对数据进行对齐)，若确定计算得到的时间差小于标准时间差，那么第一偏差处理模块803将确定一个进行数据对齐的时刻点(即目标时刻点)，并将该目标时刻点通过管脚11或管脚12发送至第二偏差处理模块703，之后，等达到目标时刻点时，第一偏差处理模块803以及第二偏差处理模块703同时对各自物理通道上的数据进行对齐，再分别同时在该目标时刻点将各个物理通道上的数据发送出去，从而达到两个重定时器内的数据同步对齐的目的。
需要说明的是，第一管脚也可以只包括两个管脚，如可只包括管脚11(或管脚12)和管脚13(或管脚14)，第一偏差处理模块803获取到的时刻点1和时刻点2均可通过管脚11(或管脚12)同步至第二偏差处理模块703，类似地，第二偏差处理模块703获取到的时刻点3和时刻点4也均可通过管脚13(或管脚14)同步至第一偏差处理模块803。还需要说明的是，第一管脚也可以只包括一个管脚，第一偏差处理模块803以及第二偏差处理模块703可以采用分时复用的方式利用这一个管脚将时刻1、时刻2、时刻3、时刻4同步至对方，具体此处 对第一管脚所包括的管脚数量以及如何同步的具体方式不做限定。
在本申请上述实施方式中，第一重定时器和第二重定时器通过第一管脚分别获取到对方各个物理通道上传输的数据传输至各自内部的偏差处理模块时的时刻点，并由第一重定时器根据各时刻点确定出一个目标时刻点，并进一步将该目标时刻点同步至第二重定时器，当达到该目标时刻点时，启动所有跨重定时器的各个物理通道的数据对齐操作，完成所有重定时器内物理通道上数据的对齐。
二、第一重定时器与第二重定时器如何通过第二管脚同步进行链路协商。
第一重定时器除了包括有第一偏差处理模块803、第二重定时器除了包括有第二偏差处理模块703以外，第一重定时器具体还可以包括第一链路协商状态机804、第二重定时器具体还可以包括第二链路协商状态机704。需要说明的是，在本申请的一些实施方式中，第一偏差处理模块803以及第二偏差处理模块703在进行数据对齐之前，还需要分别将各自用于传输数据的物理通道的状态发送至第一链路协商状态机804以及第二链路协商状态机704，该第一链路协商状态机804以及第二链路协商状态机704用于在第一偏差处理模块803确定目标时刻点之前先进行链路协商。
下面对第一链路协商状态机804以及第二链路协商状态机704如何通过第二管脚同步进行链路协商进行说明：第二链路协商状态机704用于获取第二偏差处理模块703内各个物理通道的状态(如哪些物理通道处于传输并行数据流的状态、哪些物理通道传输了物理的特定数据流、哪些物理通道传输了什么样的数据流等)，该状态可称为第二状态，之后第二链路协商状态机704还用于将该第二状态通过第二管脚同步至第一链路协商状态机804，类似地，该第一链路协商状态机804也用于获取第一偏差处理模块803内各个物理通道的状态(可称为第一状态)，之后，该第一链路协商状态机804就用于根据该第一状态以及第二状态确定跳转时刻，并用于进一步通过第二管脚将跳转时刻同步至第二链路协商状态机704，这样，第一链路协商状态机804以及第二链路协商状态机704，还用于在跳转时刻同时进行链路协商。如，可以是第一链路协商状态机804获取到第二状态后开始计时，计时达到特定时长后，第一链路协商状态机804以及第二链路协商状态机704同时进行链路协商。
需要说明的是，在本申请的一些实施方式中，第二链路协商状态机704用于获取第二偏差处理模块703内各个物理通道的第二状态，并将该第二状态同步至第一链路协商状态机804的步骤可以由第一链路协商状态机804通过第二管脚向第二链路协商状态机704发送的第一状态触发而执行，经由第二管脚发送至第二链路协商状态机704的第一状态就用于指示第二链路协商状态机704执行获取第二状态的步骤。
还需要说明的是，若第一链路协商状态机804也用于将第一状态通过第二管脚同步至第二链路协商状态机704，由于重定时器内的链路协商状态机进行链路协商的方式在PCIe协议中都有明确定义，即协议中明确定义了如何根据各个不同的物理通道的状态进行何种形式的链路协商，因此第一链路协商状态机804以及第二链路协商状态机704用于在跳转时刻同时进行链路协商的方式可以是：第一链路协商状态机804用于在确定的跳转时刻根据第一状态以及第二状态进行链路协商；第二链路协商状态机704用于在同样的跳转时刻 根据第一状态以及第二状态进行链路协商，根据PCIe协议的定义可知，只要确定了同样的跳转时刻(即保证两个链路协商状态机同步工作)，第一链路协商状态机804以及第二链路协商状态机704就可以同时进行完全一致的链路协商方式，从而达到两个重定时器合并为一个链路进行链路协商的目的。
需要说明的是，在本申请的一些实施方式中，第二管脚可以是一个管脚，也可以是多个管脚，具体此处不做限定。若第二管脚为一个管脚时，以单bit管脚为例说明：第一链路协商状态机804以及第二链路协商状态机704分时复用该第二管脚，如第一链路协商状态机804先使用该第二管脚传输信息(如向第二链路协商状态机704发送第一状态)，传输完成后，释放该第二管脚，由第二链路协商状态机704使用该第二管脚传输信息(如向第一链路协商状态机804发送第二状态)。如图12所示，假设管脚信号(即通过第二管脚传输的信号，如第一状态、第二状态)在重定时器内以1GHz产生，在第二管脚上以100MHz传输，那么每bit的状态有效10ns。在本申请的一些实施方式中，可以默认管脚电平为高(也可以默认为管脚电平为低)，当第一重定时器控制管脚电平置为低电平时，则第一重定时器拥有对该管脚的使用权，此时意味着一个传输命令开始，如，可先传输4bit地址，代表命令类型，然后是发送最多16bit的数据，当数据传输完成后，管脚置高电平，表示本次传输命令完成，第一重定时器交出管脚的使用权给第二重定时器使用。若第二管脚为多个管脚时，那么也可以不采用分时复用的方式，此时就可以采用独立的同步信号，比如第一链路协商状态机804通过一个管脚给第二链路协商状态机704传输同步信号，第二链路协商状态机704通过另外一个管脚给第一链路协商状态机804传输同步信号，每组同步信号可以是单位信号或多位信号，具体此处不做限定。
在本申请上述实施方式中，第一重定时器和第二重定时器通过第二管脚分别获取到对方各个物理通道的状态(如，第一状态以及第二状态)，并由第一重定时器根据这两个重定时器内的所有物理通道的状态确定出一个跳转时刻，并进一步将该跳转时刻同步至第二重定时器，当达到该跳转时刻时，由第一重定时器内的第一链路协商状态机804和第二重定时器内的第二链路协商状态机704启动所有跨重定时器的链路协商，从而达到两个重定时器合并为一个链路进行链路协商的目的。
三、第一重定时器与第二重定时器如何通过第三管脚同步处理频偏。
第一重定时器除了包括有第一偏差处理模块803和/或第一链路协商状态机804、第二重定时器除了包括有第二偏差处理模块703和/或第二链路协商状态机704以外，第一重定时器具体还可以包括第一缓存器、第二重定时器具体还可以包括第二缓存器。如图8所示，第一缓存器具体可以包括接收缓存器802以及发送缓存器805，第二缓存器具体可以包括接收缓存器702以及发送缓存器705。需要说明的是，在本申请的一些实施方式中，各重定时器内的数据传输至各自内部的缓存器时，缓存器还需要对获取到的数据进行频偏处理，即要保证每个正在传输数据的物理通道对应的接收缓存器不溢出(即不丢失数据)，同时要保证每个正在传输数据的物理通道对应的发送缓存器不断流(即不丢失数据)。其处理的方式就是通过SKP增删规则来保证对应的接收缓存器不溢出以及对应的发送缓存器不断流(如，按照预设规则在对应的接收缓存器中增加SKP数据、按照预设规则在对应的发送缓存器中删除 SKP数据)。
需要说明的是，缓存器如何通过获取SKP数据并根据SKP增删规则保证缓存器内的数据不溢出或不断流是已有的(即如何处理频偏)，此处不予赘述，在本申请实施例中，重点阐述第一重定时器以及第二重定时器如何通过第三管脚同步处理频偏。首先，第二缓存器用于确定第二SKP数据的状态(可称为第四状态)，并将第四状态通过第三管脚同步至第一缓存器，类似地，第一缓存器也用于获取第一SKP数据的状态(可称为第三状态)，之后，该第一缓存器就用于根据第三状态以及第四状态确定SKP增删规则，并用于进一步通过第三管脚将确定的SKP增删规则同步至第二缓存器，这样，第一缓存器以及第二缓存器，还用于根据所述相同的SKP增删规则分别调整第一传输数据以及第二传输数据。
为便于理解，下面以图8为例对如何同步处理频偏详细进行说明：为了保证第一重定时器内的接收缓存器802、第二重定时器内的接收缓存器702不溢出，并且还要保证两个重定时器内的接收缓存器同步处理频偏，那么该SKP增删规则可以是接收缓存器802每收到一组SKP数据，则固定删除一个单位的SKP(即固定删除一个8bit的SKP数据，PCIe中协议有定义，此处不予赘述)，接收缓存器802确定了所述SKP增删规则之后，就可以通过第三管脚将该SKP增删规则同步至接收缓存器702，接收缓存器702获取到该增删规则后，也将根据该增删规则与接收缓存器802同步进行频偏处理。类似地，为了保证第一重定时器内的发送缓存器805、第二重定时器内的发送缓存器705不断流，并且还要保证两个重定时器内的发送缓存器同步处理频偏，那么该SKP增删规则可以是第一重定时器和第二重定时器分别监控发送缓存器805和发送缓存器705的下水线，下水线分两级，第一级加一个单位的SKP，第二级加两个单位的SKP(增加两个单位的SKP可以保证覆盖到协议定义的频偏，保证在增加SKP后，发送缓存器会是非空状态，这样发送缓存器内就有数据，可以达到不断流的目的)，其他情况不增加。发送缓存器805确定了所述SKP增删规则之后，就可以通过第三管脚将该SKP增删规则同步至发送缓存器705，发送缓存器705获取到该增删规则后，也将根据该增删规则与接收缓存器805同步进行频偏处理。
需要说明的是，在本申请的一些实施方式中，第二缓存器用于确定第二SKP数据的第四状态，并将该第四状态通过第三管脚同步至第一缓存器的步骤可以由第一缓存器通过第三管脚向第二缓存器发送的触发指令(可称为第二触发指令)触发而执行，该第二触发指令就用于指示第二缓存器执行获取所述第四状态并将该第四状态通过第三管脚同步至第一缓存器的步骤；也可以是第二缓存器一旦获取到第二SKP数据，就自动确定该第二SKP数据的第四状态，并自动通过该第三管脚将第四状态同步至第一缓存器，具体此处对触发第二缓存器获取第四状态并通过第三管脚向第一缓存器发送该第四状态的方式不做限定。
还需要说明的是，在本申请的一些实施方式中，上述第二触发指令可以是第一缓存器获取到的第一SKP数据的第三状态，也可以是第一缓存器获取到第三状态后随即生成的一个目标信息，该目标信息用于指示第二缓存器获取第四状态并向第一缓存器发送该第四状态，具体此处对第二触发指令的具体形式不做限定。
还需要说明的是，需要说明的是，在本申请的一些实施方式中，与上述第二管脚类似，第三管脚也可以是一个管脚，也可以是多个管脚，具体此处不做限定。
在本申请上述实施方式中，第一重定时器和第二重定时器通过第三管脚分别获取各自缓存器(如，接收缓存器、发送缓存器)接收到的SKP数据的状态(如，第三状态以及第四状态)，并由第一重定时器根据这两个重定时器内的缓存器接收到的SKP数据的状态确定出一个SKP增删规则，并进一步将该SKP增删规则同步至第二重定时器，由第一重定时器内的第一缓存器和第二重定时器内的第二缓存器同时根据该SKP增删规则分别调整各自的传输数据，从而达到两个重定时器合并为一个链路进行频偏处理的目的。
需要说明的是，上述实施例所述的用于数据同步的装置均是以包括两个重定时器为例进行说明的，在本申请的一些实施方式中，用于数据同步的装置还可以包括两个以上的重定时器，从而达到对多个重定时器内的数据进行同步的目的，即可以按照上述类似的方式将更多个重定时器进行堆叠，以实现拓展PCIe链路宽度的目的。
此外，本申请实施例还提供了一种数据同步的方法，具体如图13所示。
1301、第二重定时器获取第二时刻点。
首先，第二重定时器会获取到第二传输数据传输至第二重定时器内第二偏差处理模块的第二时刻点。
1302、第二重定时器通过第一管脚将第二时刻点发送至第一重定时器。
之后，第二重定时器通过第一管脚将获取到的该第二时刻点同步至第一重定时器。
1303、第一重定时器通过第一时刻点及第二时刻点确定目标时刻点。
第一重定时器获取到第二重定时器通过第一管脚发送的第一时刻点以后，就可以根据预先通过自身获取的第一时刻点以及第二时刻点确定目标时刻点，其中，第一时刻点为第一重定时器内的第一传输数据传输至第一重定时器内第一偏差处理模块的时刻点。
1304、第一重定时器通过第一管脚发送目标时刻点至第二重定时器。
第一重定时器确定好目标时刻点之后，会将该目标时刻点通过第一管脚同步至第二重定时器。这样，第一重定时器以及第二重定时器内就都存在该目标时刻点。
1305、第二重定时器在目标时刻点发送第二传输数据。
最后，第二重定时器根据获取到的目标时刻点在目标时刻点发送第二传输数据。
1306、第一重定时器在目标时刻点发送第一传输数据。
类似地，第一重定时器也会在目标时刻点发送第一传输数据。
需要说明的是，在本申请上述实施例中，步骤1305与步骤1306是同时发生的，即第一重定时器以及第二重定时器均是在目标时刻点对各自内部传输的第一传输数据以及第二传输数据进行发送，即第一重定时器以及第二重定时器在目标时刻点对各自物理通道上传输的数据进行对齐后再发送出去。
在本申请上述实施方式中，第一重定时器和第二重定时器通过第一管脚分别获取到对方各个物理通道上传输的数据传输至各自内部的偏差处理模块时的时刻点，并由第一重定时器根据各时刻点确定出一个目标时刻点，并进一步将该目标时刻点同步至第二重定时器，当达到该目标时刻点时，启动所有跨重定时器的各个物理通道的数据对齐操作，完成所有重定时器内物理通道上数据的对齐。
优选的，在本申请的一些实施方式中，在第二重定时器通过第一管脚将第二重定时器 内第二偏差处理模块获取到第二传输数据的第二时刻点同步至第一重定时器之前，所述方法还可以包括：第一重定时器通过第一管脚向第二重定时器发送第一触发指令，第一触发指令用于指示第二重定时器执行获取该第二时刻点的步骤。也可以是第二重定时器内的第二偏差处理模块一旦获取到第二传输数据，就自动确定该第二传输数据传输至第二偏差处理模块的第二时刻点，之后第二重定时器自动通过该第一管脚将第二时刻点同步至第一重定时器，具体此处对触发第二重定时器获取第二时刻点并通过第一管脚向第一重定时器发送该第二时刻点的方式不做限定。
优选的，在本申请的一些实施方式中，上述第一触发指令可以是第一重定时器获取到的第一传输数据传输至第一偏差处理模块的第一时刻点，也可以是第一重定时器获取到第一时刻点后随即生成的一个目标信息，该目标信息用于指示第二重定时器获取第二时刻点并向第一重定时器发送该第二时刻点，具体此处对第一触发指令的具体形式不做限定。
需要说明的是，在本申请的一些实施方式中，第一重定时器以及第二重定时器在进行数据对齐之前(即在第一重定时器根据获取到的第一时刻点以及第二时刻点确定目标时刻点之前)，还需要分别将各自用于传输数据的物理通道的状态发送至第一重定时器内的第一链路协商状态机以及第二重定时器内的第二链路协商状态机，使得该第一链路协商状态机以及第二链路协商状态机在第一偏差处理模块确定目标时刻点之前先进行链路协商。
优选的，在本申请的一些实施方式中，第一链路协商状态机以及第二链路协商状态机进行链路协商的方式可以是：第二重定时器获取用于传输第二传输数据的通道的第二状态(如哪些物理通道处于传输并行数据流的状态、哪些物理通道传输了物理的特定数据流、哪些物理通道传输了什么样的数据流等)，并将第二状态通过第二管脚同步至第一重定时器；之后，由该第一重定时器根据获取到的第一状态以及第二状态确定跳转时刻，并通过第二管脚将该跳转时刻同步至第二重定时器，其中，第一状态为第一重定时器中传输第一传输数据的通道的状态；最后，第一链路协商状态机以及第二链路协商状态机在跳转时刻进行链路协商。如，可以是第一链路协商状态机获取到第二状态后开始计时，计时达到特定时长后，第一链路协商状态机以及第二链路协商状态机同时进行链路协商。
优选的，在本申请的一些实施方式中，在第二重定时器获取用于传输第二传输数据的通道的第二状态，并将第二状态通过第二管脚同步至所述第一重定时器之前，所述方法还可以包括：第一重定时器通过第二管脚向第二链路协商状态机发送第一状态，该第一状态用于触发第二重定时器执行获取第二状态的步骤，经由第二管脚发送至第二链路协商状态机的第一状态就用于指示第二链路协商状态机行获取第二状态的步骤。
优选的，若第一链路协商状态机将第一状态通过第二管脚同步至第二链路协商状态机，由于重定时器内的链路协商状态机进行链路协商的方式在PCIe协议中都有明确定义，即协议中明确定义了如何根据各个不同的物理通道的状态进行何种形式的链路协商，因此第一链路协商状态机以及第二链路协商状态机在跳转时刻同时进行链路协商的方式可以是：第一链路协商状态机在确定的跳转时刻根据第一状态以及第二状态进行链路协商；第二链路协商状态机也在同样的跳转时刻根据第一状态以及第二状态进行链路协商，根据PCIe协议的定义可知，只要确定了同样的跳转时刻(即保证两个链路协商状态机同步工作)， 第一链路协商状态机以及第二链路协商状态机就可以同时进行完全一致的链路协商方式，从而达到两个重定时器合并为一个链路进行链路协商的目的。
在本申请上述实施方式中，第一重定时器和第二重定时器通过第二管脚分别获取到对方各个物理通道的状态(如，第一状态以及第二状态)，并由第一重定时器根据这两个重定时器内的所有物理通道的状态确定出一个跳转时刻，并进一步将该跳转时刻同步至第二重定时器，当达到该跳转时刻时，由第一重定时器内的第一链路协商状态机和第二重定时器内的第二链路协商状态机启动所有跨重定时器的链路协商，从而达到两个重定时器合并为一个链路进行链路协商的目的。
还需要说明的是，在本申请的一些实施方式中，第一重定时器与第二重定时器还需要对流经各个重定时器内缓存器的数据进行频偏处理，即要保证每个正在传输数据的物理通道对应的接收缓存器不溢出(即不丢失数据)，同时要保证每个正在传输数据的物理通道对应的发送缓存器不断流(即不丢失数据)。其处理的方式就是通过SKP增删规则来保证对应的接收缓存器不溢出以及对应的发送缓存器不断流(如，按照预设规则在对应的接收缓存器中增加SKP数据、按照预设规则在对应的发送缓存器中删除SKP数据)。首先，第二重定时器获取第二重定时器中第二缓存器内的第二SKP数据的状态(可称为第四状态)，并将第四状态通过第三管脚同步至第一重定时器，类似地，第一重定时器也将获取第一SKP数据的状态(可称为第三状态，该第三状态为第一重定时器中第一缓存器内的第一SKP数据的状态)，之后，该第一重定时器就根据第三状态以及第四状态确定SKP增删规则，并进一步通过第三管脚将确定的SKP增删规则同步至第二重定时器，这样，第一重定时器以及第二重定时器就根据所述相同的SKP增删规则分别调整第一传输数据以及第二传输数据。
优选的，在本申请的一些实施方式中，在第二重定时器确定第二重定时器中第二缓存器内的第二SKP数据的第四状态，并将第四状态通过第三管脚同步至第一重定时器之前，所述方法还可以包括：可以是第一重定时器通过第三管脚向第二重定时器发送第二触发指令，该第二触发指令用于指示第二重定时器执行获取第四状态的步骤。也可以是第二重定时器一旦获取到第二SKP数据，就自动确定该第二SKP数据的第四状态，并自动通过该第三管脚将第四状态同步至第一重定时器，具体此处对触发第二重定时器获取第四状态并通过第三管脚向第一重定时器发送该第四状态的方式不做限定。
优选的，在本申请的一些实施方式中，上述第二触发指令可以是第一重定时器获取到的第一SKP数据的第三状态，也可以是第一重定时器获取到第三状态后随即生成的一个目标信息，该目标信息用于指示第二重定时器获取第四状态并向第一重定时器发送该第四状态，具体此处对第二触发指令的具体形式不做限定。
优选的，在本申请的一些实施方式中，第一缓存器可以包括第一接收缓存器以及第一发送缓存器；第二缓存器可以包括第二接收缓存器以及第二发送缓存器。
还需要说明的是，上述实施例所述的数据同步的方法中包括两个重定时器为例进行说明的，在本申请的一些实施方式中，用于数据同步的方法中还可以包括两个以上的重定时器，从而达到对多个重定时器内的数据进行同步的目的，即可以按照上述类似的方式将更 多个重定时器进行堆叠，以实现拓展PCIe链路宽度的目的。
在本申请上述实施方式中，第一重定时器和第二重定时器通过第三管脚分别获取各自缓存器(如，接收缓存器、发送缓存器)接收到的SKP数据的状态(如，第三状态以及第四状态)，并由第一重定时器根据这两个重定时器内的缓存器接收到的SKP数据的状态确定出一个SKP增删规则，并进一步将该SKP增删规则同步至第二重定时器，由第一重定时器内的第一缓存器和第二重定时器内的第二缓存器同时根据该SKP增删规则分别调整各自的传输数据，从而达到两个重定时器合并为一个链路进行频偏处理的目的。
在上述实施例中，可以全部或部分地通过硬件、固件或者其任意组合来实现。

Claims (24)

  1. 一种装置，其特征在于，包括：
    第一重定时器以及第二重定时器，其中，所述第一重定时器包括第一偏差处理模块，所述第二重定时器包括第二偏差处理模块；
    所述第二偏差处理模块，用于获取第二传输数据传输至所述第二偏差处理模块的第二时刻点，并通过第一管脚将所述第二时刻点同步至所述第一偏差处理模块；
    所述第一偏差处理模块，用于根据获取到的第一时刻点以及所述第二时刻点确定目标时刻点，并将所述目标时刻点通过所述第一管脚同步至所述第二偏差处理模块，其中，所述第一时刻点为第一传输数据传输至所述第一偏差处理模块的时刻点；
    所述第一偏差处理模块以及所述第二偏差处理模块，还用于在所述目标时刻点分别发送所述第一传输数据以及所述第二传输数据。
  2. 根据权利要求1所述的装置，其特征在于，所述第一偏差处理模块还用于：
    通过所述第一管脚向所述第二偏差处理模块发送第一触发指令，所述第一触发指令用于指示所述第二偏差处理模块执行获取所述第二时刻点的步骤。
  3. 根据权利要求2所述的装置，其特征在于，所述第一触发指令包括：
    所述第一偏差处理模块获取到的所述第一时刻点。
  4. 根据权利要求1-3中任一项所述的装置，其特征在于，
    所述第一重定时器还包括第一链路协商状态机，所述第二重定时器还包括第二链路协商状态机；
    所述第一链路协商状态机以及所述第二链路协商状态机，用于在所述第一偏差处理模块确定所述目标时刻点之前进行链路协商。
  5. 根据权利要求4所述的装置，其特征在于，
    所述第二链路协商状态机，具体用于获取用于传输所述第二传输数据的通道的第二状态，并将所述第二状态通过第二管脚同步至所述第一链路协商状态机；
    所述第一链路协商状态机，具体用于根据获取到的第一状态以及所述第二状态确定跳转时刻，并通过所述第二管脚将所述跳转时刻同步至所述第二链路协商状态机，其中，所述第一状态为所述第一重定时器中传输所述第一传输数据的通道的状态；
    所述第一链路协商状态机以及所述第二链路协商状态机，还用于在所述跳转时刻进行链路协商。
  6. 根据权利要求5所述的装置，其特征在于，所述第一链路协商状态机，具体还用于：
    通过所述第二管脚向所述第二链路协商状态机发送所述第一状态，所述第一状态用于触发所述第二链路协商状态机执行获取所述第二状态的步骤。
  7. 根据权利要求6所述的装置，其特征在于，
    所述第一链路协商状态机，还用于在所述跳转时刻根据所述第一状态以及所述第二状态进行链路协商；
    所述第二链路协商状态机，还用于在所述跳转时刻根据所述第一状态以及所述第二状态进行链路协商。
  8. 根据权利要求1-7中任一项所述的装置，其特征在于，
    所述第一重定时器还包括第一缓存器，所述第二重定时器还包括第二缓存器；
    所述第二缓存器，用于确定第二字符码有序集SKP数据的第四状态，并将所述第四状态通过第三管脚同步至所述第一缓存器；
    所述第一缓存器，用于根据第三状态以及所述第四状态确定SKP增删规则，并通过所述第三管脚将所述SKP增删规则同步至所述第二缓存器，其中，所述第三状态为所述第一缓存器内第一SKP数据的状态；
    所述第一缓存器以及所述第二缓存器，还用于根据所述SKP增删规则分别调整所述第一传输数据以及所述第二传输数据。
  9. 根据权利要求8所述的装置，其特征在于，所述第一缓存器还用于：
    通过所述第三管脚向所述第二缓存器发送第二触发指令，所述第二触发指令用于指示所述第二缓存器执行获取所述第四状态的步骤。
  10. 根据权利要求9所述的装置，其特征在于，所述第二触发指令包括：
    所述第一缓存器获取到的所述第三状态。
  11. 根据权利要求8-10中任一项所述的装置，其特征在于，
    所述第一缓存器包括：第一接收缓存器以及第一发送缓存器；
    所述第二缓存器包括：第二接收缓存器以及第二发送缓存器。
  12. 根据权利要求1-11中任一项所述的装置，其特征在于，所述第二重定时器包括：
    一个或多个重定时器。
  13. 一种数据同步的方法，其特征在于，包括：
    第二重定时器通过第一管脚将所述第二重定时器内的第二传输数据传输至所述第二重定时器内第二偏差处理模块的第二时刻点同步至第一重定时器；
    所述第一重定时器根据获取到的第一时刻点以及所述第二时刻点确定目标时刻点，并将所述目标时刻点通过所述第一管脚同步至所述第二重定时器，其中，所述第一时刻点为所述第一重定时器内的第一传输数据传输至所述第一重定时器内第一偏差处理模块的时刻点；
    所述第一偏差处理模块以及所述第二偏差处理模块在所述目标时刻点分别发送所述第一传输数据以及所述第二传输数据。
  14. 根据权利要求13所述的方法，其特征在于，在所述第二重定时器通过第一管脚将所述第二重定时器内第二偏差处理模块获取到第二传输数据的第二时刻点同步至第一重定时器之前，所述方法还包括：
    所述第一重定时器通过所述第一管脚向所述第二重定时器发送第一触发指令，所述第一触发指令用于指示所述第二重定时器执行获取所述第二时刻点的步骤。
  15. 根据权利要求14所述的方法，其特征在于，所述第一触发指令包括：
    所述第一重定时器获取到的所述第一时刻点。
  16. 根据权利要求13-15中任一项所述的方法，其特征在于，在所述第一重定时器根据获取到的第一时刻点以及所述第二时刻点确定目标时刻点之前，所述方法还包括：
    所述第一重定时器内的第一链路协商状态机以及所述第二重定时器内的第二链路协商状态机进行链路协商。
  17. 根据权利要求16所述的方法，其特征在于，所述第一重定时器内的第一链路协商状态机以及所述第二重定时器内的第二链路协商状态机进行链路协商包括：
    所述第二重定时器获取用于传输所述第二传输数据的通道的第二状态，并将所述第二状态通过所述第二管脚同步至所述第一重定时器；
    所述第一重定时器根据获取到的第一状态以及所述第二状态确定跳转时刻，并通过所述第二管脚将所述跳转时刻同步至所述第二重定时器，其中，所述第一状态为所述第一重定时器中传输所述第一传输数据的通道的状态；
    所述第一链路协商状态机以及所述第二链路协商状态机在所述跳转时刻进行链路协商。
  18. 根据权利要求17所述的方法，其特征在于，在所述第二重定时器获取用于传输所述第二传输数据的通道的第二状态，并将所述第二状态通过所述第二管脚同步至所述第一重定时器之前，所述方法还包括：
    所述第一重定时器通过所述第二管脚向所述第二链路协商状态机发送所述第一状态，所述第一状态用于触发所述第二重定时器执行获取所述第二状态的步骤。
  19. 根据权利要求18所述的方法，其特征在于，所述第一链路协商状态机以及所述第二链路协商状态机在所述跳转时刻进行链路协商包括：
    所述第一链路协商状态机在所述跳转时刻根据所述第一状态以及所述第二状态进行链路协商；
    所述第二链路协商状态机在所述跳转时刻根据所述第一状态以及所述第二状态进行链路协商。
  20. 根据权利要求13-19中任一项所述的方法，其特征在于，所述方法还包括：
    所述第二重定时器获取第二重定时器中第二缓存器内的第二字符码SKP数据的第四状态，并将所述第四状态通过第三管脚同步至所述第一重定时器；
    所述第一重定时器根据获取到的第三状态以及所述第四状态确定SKP增删规则，并通过所述第三管脚将所述SKP增删规则同步至所述第二重定时器，其中，所述第三状态为所述第一重定时器中第一缓存器内的第一SKP数据的状态；
    所述第一重定时器以及所述第二重定时器根据所述SKP增删规则分别调整所述第一传输数据以及所述第二传输数据。
  21. 根据权利要求20所述的方法，其特征在于，在所述第二重定时器确定第二重定时器中第二缓存器内的第二字符码SKP数据的第四状态，并将所述第四状态通过第三管脚同步至所述第一重定时器之前，所述方法还包括：
    所述第一重定时器通过所述第三管脚向所述第二重定时器发送第二触发指令，所述第二触发指令用于指示所述第二重定时器执行获取所述第四状态的步骤。
  22. 根据权利要求21所述的方法，其特征在于，所述第二触发指令包括：
    所述第一重定时器获取到的所述第三状态。
  23. 根据权利要求20-22中任一项所述的方法，其特征在于，
    所述第一缓存器包括：第一接收缓存器以及第一发送缓存器；
    所述第二缓存器包括：第二接收缓存器以及第二发送缓存器。
  24. 根据权利要求13-23中任一项所述的方法，其特征在于，所述第二重定时器包括：一个或多个重定时器。
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