US20200334181A1 - Data transmission method and data transmission system - Google Patents
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- US20200334181A1 US20200334181A1 US16/918,711 US202016918711A US2020334181A1 US 20200334181 A1 US20200334181 A1 US 20200334181A1 US 202016918711 A US202016918711 A US 202016918711A US 2020334181 A1 US2020334181 A1 US 2020334181A1
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title description 3
- 238000011084 recovery Methods 0.000 claims description 3
- 238000012549 training Methods 0.000 description 6
- 101000805129 Homo sapiens Protein DPCD Proteins 0.000 description 4
- 102100037836 Protein DPCD Human genes 0.000 description 4
- 238000013459 approach Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000003190 augmentative effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/08—Time only switching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Definitions
- the present disclosure relates to a data transmission method that has DisplayPort (DP) and Universal Serial Bus Universal Serial Bus (USB) on USB Type-C connector.
- DP DisplayPort
- USB Universal Serial Bus Universal Serial Bus
- USB Type-C DP Alt Mode on USB Type-C enables concurrent transport of USB traffic (both USB3.x SS and USB2) and DP traffic over a standard USB Type-C connector.
- the USB Type-C connector supports 4 pairs of high-speed differential signaling with a bit rate up to 10 Gbps/pair and 2 pairs of pins for a USB2 differential signal (up to 480 Mbps), as depicted in FIG. 7 . Only one of the 2 pairs, named A 6 /A 7 and B 6 /B 7 in FIG. 7 , of USB2 pins is used for USB2 transport. The pair that is selected depends on the USB Type-C plug connector orientation.
- DP Alt Mode on USB Type-C specification enables either (1) 2 lanes of DP Main Link concurrent with USB3.x SS and USB2 or (2) 4 lanes of DP Main Link concurrent with USB2 without USB3.x SS.
- the present disclosure describes technology enabling the concurrent transport of USB traffic and DP 4 Lane equivalent traffic over USB Type-C connector without drawbacks such as requirements of more complex signal multiplexing/routing.
- a data transmission system includes a transmitter having a first switching re-timer and a receiver having a second switching re-timer.
- the first switching re-timer is configured to double a link rate per lane and halve the number of lanes
- the second switching re-timer is configured to halve the doubled link rate and double the halved number of lanes.
- a data transmission system includes a transmitter having a first switching re-timer and a receiver having a second switching re-timer.
- the first switching re-timer is configured to multiply a link rate per lane by M where M denotes an integer of 2 or more, and multiply the number of lanes by 1/M
- the second switching re-timer is configured to multiply the M-multiplied link rate by 1/M and multiply the 1/M-multiplied number of lanes by M.
- FIG. 1 illustrates DP Alt Mode on USB Type-C with Switches or Switching Re-timers
- FIG. 2 illustrates DP Alt Mode on USB Type-C with DP Link Rate Doubling/Having-Capable Switching Re-timers
- FIG. 3 illustrates Internal Paths of DP Re-timers with Link Rate Doubling/Halving Capabilities
- FIG. 4 illustrates Lane Multiplexing and De-multiplexing Alignment
- FIG. 5 illustrates DP Alt Mode Discovery and Configuration through USB PD Controllers
- FIG. 6 illustrates DP 2-lane Main Link Re-timing without Link Rate Doubling/Halving
- FIG. 7 illustrates the USB Type-C Connector Receptacle Interface.
- USB Type-C devices include switches to support a plug connector orientation flip-ability feature.
- the switches for DP Alt Mode on USB Type-C devices also have the ability to select either USB3.x SS signals or DP signals for Main Link Lane 2 and Lane 3 as shown in FIG. 1 .
- PHY signal re-timer capability (“switching re-timer”).
- DP Alt Mode on USB Type-C USB Host/DP Source is only able to support either (1) DP transport over 2 lanes of DP Main Link plus USB3.x SS transport or (2) DP transport over 4 lanes of DP Main Link without USB3.x SS transport.
- the Switching Re-timers are substituted with the Switching Re-timer with DP Link Rate Doubling/Lane Count Halving capability (“DP Link Rate Doubling re-timer”) on the USB Host/DP Source side and Switching Re-timer with DP Link Rate Halving/Lane Count Doubling capability (“DP Link Rate Halving re-timer”) on the USB Device/DP Sink side as shown FIG. 2 .
- DP Main Link data for Lane 0 and Lane 1 are multiplexed on one differential pair while DP Main Link data for Lane 2 and Lane 3 are multiplexed on the other differential pair reserved for DP main link transport in Type C Alt Mode, thus leaving the other two pairs available for USB3.x SS traffic only.
- the DP Link Rate Doubling re-timer recovers the link symbol clock (1 ⁇ _LSCLK) from a RX CDR (Clock to Data Recovery) circuit.
- the clock doubling circuit generates 2 ⁇ _LSCLK that is used by 2-lanes-to-1-lane multiplexing circuit that multiplexes 9-bit link symbols from Lane 0 and Lane 1 (or Lane 2 and Lane 3).
- the 2 ⁇ _LSCLK is also used both by ANSI8b/10b encoders and by TX PLL that generates 2 ⁇ serial bit clock for the serializer circuit.
- the DP Link Rate Halving re-timer recovers the 2 ⁇ link symbol clock (2 ⁇ _LSCLK) from RX CDR circuit.
- This recovered clock (2 ⁇ _LSCLK clock) is used to decode the doubled ANSI8b/10b incoming stream and initiate the 1-lane-to-2-lanes de-multiplexing function.
- the 1 ⁇ _LSCLK generated by the clock divider circuit is used by 1-lane-to-2-lanes de-multiplexing circuit to de-multiplexe the 9-bit link symbols to Lane 0 and Lane 1 (or Lane 2 and Lane 3).
- This 1 ⁇ _LSCLK is also used both by ANSI8b/10b encoders and by the TX PLL that generates 1 ⁇ serial bit clock for the serializer circuit to regenerate a standard DP bit stream.
- the DP Standard protocol mandates the periodic transmission of ANSI8b/10b K28.5 character (known as comma character) in the same link symbol clock cycles across all the lanes.
- Both the multiplexing circuit and the de-multiplexing circuit in the above re-timers use link symbol corresponding to ANSI8b/10b K28.5 (“K28.5 link symbol”) as a marker for multiplexing from/de-multiplexing to proper lanes as described below and shown in FIG. 4 .
- a switching re-timer has a companion USB PD controller that manages the DP Alt Mode capability discovery and configuration through USB PD communication over CC line on a USB Type-C connector pin.
- a USB PD controller controls the companion switching re-timer through an embedded communication channel such as I2C that is not exposed to USB Type-C connector pins as shown in FIG. 5 .
- the DP Link Rate Doubling/Halving re-timers discover each other through their companion USB PD controllers using USB PD VDM (Vendor Defined Message).
- the DP Link Rate Doubling/Halving re-timers declare themselves as LTTPR (Link Training Tunable PHY Repeater) as defined in DisplayPort Standard Ver. 1.4. They both declare the support of up to 4 Main Link lanes at up to HBR3 link rate (that is, up to 8.1 Gbps/lane).
- DP Link Rate Doubling re-timer on the DP Source side indicates the training at the 2 ⁇ serial bit rate over 2 lanes to the DP Link Rate Halving re-timer on the DP Sink side by setting Bit 4 of TRAINING_PATTERN_SET DPCD register (a debug mode enable bit that does not get set during a normal operation) in the AUX write transaction to that DPCD register at the beginning of DP Link Training.
- the DP Link Rate Doubling re-timer clears Bit 4 of TRAINING_PATTERN_SET DPCD register to 0 via the AUX write transaction to that DPCD register at the beginning of DP Link Training. With Bit 4 cleared to 0, the DP Link Rate Doubling re-timer disables the DP link rate doubling/lane count halving operation and the DP Link Rate Halving re-timer disables DP link rate halving/lane count doubling operation as shown in FIG. 6 .
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- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
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- General Physics & Mathematics (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 16/119,988, filed Aug. 31, 2018, and entitled “Data Transmission System and Data Transmission Method”, which claims the benefit of priority to U.S. Provisional Patent Application No. 62/570,879, filed Oct. 11, 2017, and entitled “DP Link Rate Doubling/Halving Bit-Level Re-Timers”. The aforementioned applications are incorporated herein by reference in their entirety.
- The present disclosure relates to a data transmission method that has DisplayPort (DP) and Universal Serial Bus Universal Serial Bus (USB) on USB Type-C connector.
- DP Alt Mode on USB Type-C enables concurrent transport of USB traffic (both USB3.x SS and USB2) and DP traffic over a standard USB Type-C connector. The USB Type-C connector supports 4 pairs of high-speed differential signaling with a bit rate up to 10 Gbps/pair and 2 pairs of pins for a USB2 differential signal (up to 480 Mbps), as depicted in
FIG. 7 . Only one of the 2 pairs, named A6/A7 and B6/B7 inFIG. 7 , of USB2 pins is used for USB2 transport. The pair that is selected depends on the USB Type-C plug connector orientation. - DP Alt Mode on USB Type-C specification enables either (1) 2 lanes of DP Main Link concurrent with USB3.x SS and USB2 or (2) 4 lanes of DP Main Link concurrent with USB2 without USB3.x SS.
- For applications such as AR (augmented reality) and VR (virtual reality), there is a growing desire to have the maximum-bandwidth DP transport of 4-lane Main Link at the highest DP link rate of 8.1 Gbps/lane (called HBR3 link rate) concurrent with USB3.1 SS transport. There is one approach that enables this concurrency by routing USB3.1 SS traffic to 2 pairs of USB2 pins on a USB Type-C connector while routing all 4 lanes of DP Main Link to the 4 pairs of high-speed differential signal pins. This approach, however, has the drawbacks as below:
- (1) Requires more complex signal multiplexing/routing
- (2) Requires tunneling of USB2 traffic through USB3.1 SS traffic
- (3) Requires a captive cable with USB Type-C plug connector only on one end
- The present disclosure describes technology enabling the concurrent transport of USB traffic and DP 4 Lane equivalent traffic over USB Type-C connector without drawbacks such as requirements of more complex signal multiplexing/routing.
- According to one aspect of the present disclosure, a data transmission system includes a transmitter having a first switching re-timer and a receiver having a second switching re-timer. The first switching re-timer is configured to double a link rate per lane and halve the number of lanes, and the second switching re-timer is configured to halve the doubled link rate and double the halved number of lanes.
- According to another aspect of the disclosure, a data transmission system includes a transmitter having a first switching re-timer and a receiver having a second switching re-timer. The first switching re-timer is configured to multiply a link rate per lane by M where M denotes an integer of 2 or more, and multiply the number of lanes by 1/M, and the second switching re-timer is configured to multiply the M-multiplied link rate by 1/M and multiply the 1/M-multiplied number of lanes by M.
-
FIG. 1 illustrates DP Alt Mode on USB Type-C with Switches or Switching Re-timers; -
FIG. 2 illustrates DP Alt Mode on USB Type-C with DP Link Rate Doubling/Having-Capable Switching Re-timers; -
FIG. 3 illustrates Internal Paths of DP Re-timers with Link Rate Doubling/Halving Capabilities; -
FIG. 4 illustrates Lane Multiplexing and De-multiplexing Alignment -
FIG. 5 illustrates DP Alt Mode Discovery and Configuration through USB PD Controllers; -
FIG. 6 illustrates DP 2-lane Main Link Re-timing without Link Rate Doubling/Halving; -
FIG. 7 illustrates the USB Type-C Connector Receptacle Interface. - USB Type-C devices include switches to support a plug connector orientation flip-ability feature. The switches for DP Alt Mode on USB Type-C devices also have the ability to select either USB3.x SS signals or DP signals for Main Link Lane 2 and
Lane 3 as shown inFIG. 1 . In order to avoid high-speed signal quality degradation over the switch, it is becoming common for the switch to have PHY signal re-timer capability (“switching re-timer”). - As depicted in
FIG. 7 , there are only four pairs of high-speed differential signal pins on a USB Type-C connector, DP Alt Mode on USB Type-C USB Host/DP Source is only able to support either (1) DP transport over 2 lanes of DP Main Link plus USB3.x SS transport or (2) DP transport over 4 lanes of DP Main Link without USB3.x SS transport. - With the disclosure described in this document, the Switching Re-timers are substituted with the Switching Re-timer with DP Link Rate Doubling/Lane Count Halving capability (“DP Link Rate Doubling re-timer”) on the USB Host/DP Source side and Switching Re-timer with DP Link Rate Halving/Lane Count Doubling capability (“DP Link Rate Halving re-timer”) on the USB Device/DP Sink side as shown
FIG. 2 . DP Main Link data for Lane 0 and Lane 1 are multiplexed on one differential pair while DP Main Link data for Lane 2 andLane 3 are multiplexed on the other differential pair reserved for DP main link transport in Type C Alt Mode, thus leaving the other two pairs available for USB3.x SS traffic only. - Internal paths of DP Link Rate Doubling re-timer and DP Link Rate Halving re-timer are shown in
FIG. 3 . - The DP Link Rate Doubling re-timer recovers the link symbol clock (1×_LSCLK) from a RX CDR (Clock to Data Recovery) circuit. The clock doubling circuit generates 2×_LSCLK that is used by 2-lanes-to-1-lane multiplexing circuit that multiplexes 9-bit link symbols from Lane 0 and Lane 1 (or Lane 2 and Lane 3). The 2×_LSCLK is also used both by ANSI8b/10b encoders and by TX PLL that generates 2× serial bit clock for the serializer circuit.
- The DP Link Rate Halving re-timer recovers the 2× link symbol clock (2×_LSCLK) from RX CDR circuit. This recovered clock (2×_LSCLK clock) is used to decode the doubled ANSI8b/10b incoming stream and initiate the 1-lane-to-2-lanes de-multiplexing function. Following this, the 1×_LSCLK generated by the clock divider circuit, is used by 1-lane-to-2-lanes de-multiplexing circuit to de-multiplexe the 9-bit link symbols to Lane 0 and Lane 1 (or Lane 2 and Lane 3). This 1×_LSCLK is also used both by ANSI8b/10b encoders and by the TX PLL that generates 1× serial bit clock for the serializer circuit to regenerate a standard DP bit stream.
- The DP Standard protocol mandates the periodic transmission of ANSI8b/10b K28.5 character (known as comma character) in the same link symbol clock cycles across all the lanes.
- Both the multiplexing circuit and the de-multiplexing circuit in the above re-timers use link symbol corresponding to ANSI8b/10b K28.5 (“K28.5 link symbol”) as a marker for multiplexing from/de-multiplexing to proper lanes as described below and shown in
FIG. 4 . -
- When the multiplexing circuit in the DP Link Rate Doubling re-timer receives the K28.5 link symbol from both Lane 0 and Lane 1 ANSI8b/10b Decoders in the same 1×_LSCLK cycle, it pushes K28.5 link symbol to ANSI8b/10b Encoder #0 ahead of K28.5 link symbol from Lane 1
- When the de-multiplexing circuit in the DP Link Rate Halving re-timer receives two consecutive K28.5 link symbols, it pushes the first K28.5 link symbol to Lane 0 ANSI8b/10b Encoder and the second K28.5 link symbol to Lane 1 ANSI8b/10b Encoder
- As per the DP Alt Mode on USB Type-C specification, a switching re-timer has a companion USB PD controller that manages the DP Alt Mode capability discovery and configuration through USB PD communication over CC line on a USB Type-C connector pin. A USB PD controller controls the companion switching re-timer through an embedded communication channel such as I2C that is not exposed to USB Type-C connector pins as shown in
FIG. 5 . - The DP Link Rate Doubling/Halving re-timers discover each other through their companion USB PD controllers using USB PD VDM (Vendor Defined Message).
- The DP Link Rate Doubling/Halving re-timers declare themselves as LTTPR (Link Training Tunable PHY Repeater) as defined in DisplayPort Standard Ver. 1.4. They both declare the support of up to 4 Main Link lanes at up to HBR3 link rate (that is, up to 8.1 Gbps/lane).
- When the DP Source initiates DP Link Training over 4 lanes of Main Link, DP Link Rate Doubling re-timer on the DP Source side indicates the training at the 2× serial bit rate over 2 lanes to the DP Link Rate Halving re-timer on the DP Sink side by setting Bit 4 of TRAINING_PATTERN_SET DPCD register (a debug mode enable bit that does not get set during a normal operation) in the AUX write transaction to that DPCD register at the beginning of DP Link Training.
- As the DP Link Rate Halving re-timer on the DP Sink side converts it back to 1× serial bit rate over 4 Main Link lanes, the conversion to 2× serial bit rate over 2 lanes between the DP Link Rate Doubling re-timer and the DP Link Rate halving re-timer is transparent to both DP Source and DP Sink.
- In case the DP Source initiates DP Link Training over either 2 lanes (Lanes 0 and 1) or 1 lane (Lane 0) of the Main Link, the DP Link Rate Doubling re-timer clears Bit 4 of TRAINING_PATTERN_SET DPCD register to 0 via the AUX write transaction to that DPCD register at the beginning of DP Link Training. With Bit 4 cleared to 0, the DP Link Rate Doubling re-timer disables the DP link rate doubling/lane count halving operation and the DP Link Rate Halving re-timer disables DP link rate halving/lane count doubling operation as shown in
FIG. 6 . - The present invention has been described in connection with the above description, it is not intended to limit the scope of the invention to the particular form set forth, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents as may be included within the spirit and scope of the inventions as defined by the appended claims.
Claims (25)
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US16/918,711 US20200334181A1 (en) | 2017-10-11 | 2020-07-01 | Data transmission method and data transmission system |
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US201762570879P | 2017-10-11 | 2017-10-11 | |
US16/119,988 US10713192B2 (en) | 2017-10-11 | 2018-08-31 | Data transmission system and data transmission method |
US16/918,711 US20200334181A1 (en) | 2017-10-11 | 2020-07-01 | Data transmission method and data transmission system |
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US16/119,988 Continuation US10713192B2 (en) | 2017-10-11 | 2018-08-31 | Data transmission system and data transmission method |
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US16/918,711 Abandoned US20200334181A1 (en) | 2017-10-11 | 2020-07-01 | Data transmission method and data transmission system |
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WO2017189796A1 (en) * | 2016-04-29 | 2017-11-02 | Megachips Technology America Corporation | Data transmission method and data transmission system |
WO2021006878A1 (en) * | 2019-07-09 | 2021-01-14 | Hewlett-Packard Development Company, L.P. | Routing and converting traffic based on communication protocols |
CN110677602B (en) * | 2019-09-30 | 2022-10-25 | 重庆惠科金扬科技有限公司 | Channel mode switching method and device of display equipment and display equipment |
TWI727480B (en) * | 2019-11-01 | 2021-05-11 | 瑞昱半導體股份有限公司 | Image processing chip |
TWI733535B (en) * | 2020-07-24 | 2021-07-11 | 技嘉科技股份有限公司 | Display system and display apparatus |
US11843376B2 (en) | 2021-05-12 | 2023-12-12 | Gowin Semiconductor Corporation | Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA) |
US11474969B1 (en) * | 2021-05-12 | 2022-10-18 | Gowin Semiconductor Corporation | Methods and apparatus for providing a serializer and deserializer (SERDES) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA) |
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US10169286B2 (en) * | 2014-10-21 | 2019-01-01 | Icron Technologies Corporation | Devices and methods for providing reduced bandwidth DisplayPort communication |
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US10713192B2 (en) | 2020-07-14 |
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