Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
  • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/04—Apparatus for manufacture or treatment
  • H10P72/0431—Apparatus for thermal treatment
  • H10P72/0432—Apparatus for thermal treatment mainly by conduction
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/04—Apparatus for manufacture or treatment
  • H10P72/0431—Apparatus for thermal treatment
  • H10P72/0434—Apparatus for thermal treatment mainly by convection
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
  • H10P72/0602—Temperature monitoring
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
  • H10P72/0616—Monitoring of warpages, curvatures, damages, defects or the like
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/72—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using electrostatic chucks
  • H10P72/722—Details of electrostatic chucks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
  • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
  • H10P72/7611—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
  • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
  • H10P72/7616—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating, a hardness or a material

Definitions

• Embodiments of the present disclosure relate generally to the field of semiconductor device fabrication, and more particularly to a deflectable platen for facilitating effective clamping of semiconductor wafers.
• Electrostatic clamping is preferable to mechanical clamping since mechanical clamping can damage and/or contaminate a semiconductor wafer.
• a platen to securely clamp a semiconductor wafer thereto via electrostatic clamping largely depends on the proximity of the bottom surface of the semiconductor wafer to the top surface of the platen. Ideally, these surfaces are planar and are disposed in flat, continuous contact with one another. In some cases, a semiconductor wafer may be warped (e.g., deflected up to 20 thousandths of an inch (thou)), resulting in a relatively large gap between a bottom surface of the semiconductor wafer and a top surface of a platen. This may result in weak or ineffective electrostatic clamping.
• thou thousandths of an inch
• An exemplary embodiment of a deflectable platen in accordance with the present disclosure may include an annular sidewall, a first layer coupled to the annular sidewall, the first layer having a first temperature control element associated therewith, and a second layer coupled to the annular sidewall and disposed in a parallel, spaced-apart relationship with the first layer to define a gap therebetween, the second layer having a second temperature control element associated therewith.
• An exemplary embodiment of a method of deflecting a platen in accordance with the present disclosure may include providing an annular sidewall, providing a first layer coupled to the annular sidewall, the first layer having a first temperature control element associated therewith, providing a second layer coupled to the annular sidewall and disposed in a parallel, spaced-apart relationship with the first layer to define a gap therebetween, the second layer having a second temperature control element associated therewith, and varying a temperature of at least one of the first and second layers using the first and second temperature control elements.
• FIG. 1A is a top view illustrating an exemplary embodiment of a deflectable platen in accordance with the present disclosure
• FIG. IB is a cross sectional side view illustrating the deflectable platen of
• FIG. 1A A first figure.
• FIG. 2A is a cross sectional side view illustrating the deflectable platen of
• FIGS. 1A and IB with a convex deflected semiconductor wafer disposed thereon;
• FIG. 2B is a cross sectional side view illustrating the deflectable platen of
• FIG. 2A in a convex deflected state
• FIG. 2C is a cross sectional side view illustrating the deflectable platen of
• FIGS. 1A and IB in a concave deflected state with a concave deflected semiconductor wafer disposed thereon;
• FIG. 3 is a flow diagram illustrating an exemplary embodiment of a method for deflecting a platen in accordance with the present disclosure.
• FIGS. 1A and IB a top view and a cross-sectional side view illustrating a deflectable platen 10 (hereinafter “the platen 10”) in accordance with an exemplary embodiment of the present disclosure are shown, respectively.
• the platen 10 may be elastically deformable (as further described below) for providing a close clearance relationship between a top surface of the platen 10 and a bottom surface of a warped or bowed semiconductor wafer disposed upon the platen 10 to facilitate effective clamping therebetween.
• the platen 10 may include a generally planar first layer 12 and a generally planar second layer 14 disposed in a parallel, vertically spaced apart relationship (i.e., spaced apart from one other in a direction parallel to the Y-axis shown in FIG. IB) to define a gap 15 therebetween.
• Circumferential edges of the first and second layers 12, 14 may be connected to an annular sidewall 16 surrounding the first and second layers 12, 14 as further described below.
• the first and second layers 12, 14 may be formed of a material having a coefficient of thermal expansion (CTE) in a range between 6.0 x 10 6 / °C and 8.0 x 10 6 / °C.
• CTE coefficient of thermal expansion
• the first and second layers 12, 14 may be formed of a ceramic, including, and not limited to, aluminum oxide, zirconia, or aluminum nitride.
• the present disclosure is not limited in this regard.
• the first and/or second layers 12, 14 may alternatively be formed of other relatively high or low CTE materials including, and not limited to, aluminum, silver, copper and their alloys, or quartz.
• the sidewall 16 of the platen 10 may be formed of a dielectric material having a relatively low CTE or a CTE similar to the CTE of the material of the first and second layers 12, 14.
• the sidewall 16 may be formed of a material having a CTE less than 6.0 x 10 6 / °C (e.g., between 2.0 x 10 6 / °C and 4.0 x 10 6 / °C).
• the sidewall 16 may be formed of a ceramic such as aluminum nitride or aluminum oxide.
• the present disclosure is not limited in this regard.
• the sidewall 16 may alternatively be formed of other dielectric materials, including, and not limited to, other ceramics and various composite materials.
• the sidewall 16 may be connected to the edges of the first and second layers 12, 14 by brazing, welding, thermally-resistant adhesives, various mechanical fasteners, glass bonding, and/or other techniques suitable for bonding or fastening the material of the sidewall 16 to the materials of the first and second layers 12, 14. As will be described in greater detail below, the sidewall 16 may mechanically translate expansion and contraction of the first and second layers 12, 14 to one another.
• the first and second layers 12, 14 may include respective first and second heating elements 20, 22 associated therewith.
• the first and second heating elements 20, 22 may be embedded within the first and second layers 12, 14.
• the first and second heating elements 20, 22 may include one or more wires, cables, plates, tapes, etc. connected to one or more sources of electrical power (now shown).
• the first and second heating elements 20, 22 may be independently operable for selectively and independently heating the first and second layers 20, 22.
• the first and second heating elements 20, 22 may heat the first and second layers 12, 14, respectively, to temperatures in excess of 800 degrees Celsius (e.g., in a range of 800 degrees Celsius to 1200 degrees Celsius).
• the present disclosure is not limited in this regard.
• the gap 15 separating the first and second layers 12, 14 may be held at or near vacuum and may thus provide thermal separation between the first and second layers 12, 14. Particularly, the gap 15 may prevent all or most of the heat generated by the first heating element 20 from being communicated to the second layer 14 and may prevent all or most of the heat generated by the second heating element 22 from being communicated to the first layer 12.
• the platen 10 may additionally or alternatively include one or more layers of thermally insulating material disposed between the first and second layers 12, 14.
• the second layer 14 of the platen 10 may have a plurality of electrodes 23 associated therewith.
• the electrodes 23 may be embedded within the second layer 14.
• the electrodes 23 may be embedded within a separate layer of dielectric material disposed atop the second layer 14.
• the present disclosure is not limited in this regard.
• the electrodes 23 may be connected to a source of electrical power (not shown) and may be arranged and configured to operate in the manner of a conventional electrostatic clamp familiar to those of skill in the art. Particularly, by applying an electrical voltage across the electrodes 23, an electrical field can be generated and may hold a semiconductor wafer to the platen 10 via electrostatic force.
• the strength of the electrostatic force acting on the wafer will depend partly on the proximity of the wafer to the electrodes 23. Ideally, the contour of the bottom surface of the wafer will match or nearly match the contour of the top surface of the platen 10 (e.g., if these surfaces are planar or nearly planar), thus establishing a shortest possible distance between the electrodes 23 and the wafer to provide strong electrostatic coupling therebetween.
• a wafer such as the semiconductor wafer 24 (hereinafter “the wafer 24”) shown in FIG.
• the resulting gap 25 between the wafer 24 and the platen 10 may attenuate the electrostatic force acting on the wafer 24, thus resulting in poor electrostatic clamping between the platen 10 and the wafer 24.
• the electrodes 23 may be omitted, and the wafer 24 may be secured to the top surface of the platen 10 using a mechanical clamp 27 (shown in dashed lines in FIG. IB) of a variety familiar to those of ordinary skill in the art.
• a mechanical clamp 27 shown in dashed lines in FIG. IB
• the contour of the bottom surface of the wafer 24 will ideally match or nearly match the contour of the top surface of the platen 10 (e.g., if these surfaces are planar or nearly planar) to facilitate optimal contact and secure mechanical coupling therebetween, as well as to facilitate optimal thermal coupling between the platen 10 and the wafer 24.
• Good thermal coupling may be desirable if the platen 10 is configured to heat or cool wafers disposed thereon (e.g., heat transfer via inert gas introduced between the platen 10 and the wafer 24). If the wafer 24 is warped or bowed, the resulting gap 25 between the wafer 24 and the platen 10 may be detrimental to secure mechanical clamping and/or to establishing effective thermal coupling between the wafer 24 and the platen 10.
• the platen 10 is shown in a convex deflected state.
• the second heating element 22 is activated, and the first heating element 20 is not activated or is activated at lower power, resulting in heating of the second layer 14 while the first layer 12 is unheated or is heated to a lower temperature than the second layer 14.
• the second layer 14 may exhibit thermal expansion in accordance with its CTE.
• the expansion of the second layer 14 in the radial direction may cause the upper portion of the sidewall 16 to deflect outwardly, in- tum causing the edges of the first and second layers 12, 14 to be pulled or deflected downwardly, resulting in a convex deflection of the platen 10 as shown in FIG. 2B.
• the contour of the top surface of the platen 10 may be made to more closely match the contour of the bottom surface of the wafer 24 to reduce the size of the gap 25 therebetween relative to the undeflected state of the platen 10 shown in FIG. 2A.
• the smaller gap 25 and closer proximity of the electrodes 23 to the wafer 24 facilitated by the deflected platen 10 provide a stronger electrostatic force acting on the wafer 24 relative to the electrostatic force applied by the undeflected platen 10 shown in FIG. 2A, thus resulting in better electrostatic coupling between the platen 10 and the wafer 24.
• the smaller gap 25 achieved by the deflected platen 10 facilitates more secure clamping of the wafer 24 to the platen 10 and better thermal coupling between the platen 10 and the wafer 24 relative to the undeflected platen 10 shown in FIG. 2A.
• the platen 10 may also be deflected in the concave direction to accommodate bowed or warped semiconductor wafers presenting a convex surface to the top surface of the platen 10.
• the platen 10 is shown in a concave deflected state with a concave deflected semiconductor wafer 28 (hereinafter “the wafer 28”) disposed thereon.
• the first heating element 20 is activated and the second heating element 22 is not activated (or active at a lower power), resulting in heating of the first layer 12 relative to the second layer 14.
• the first layer 12 may exhibit thermal expansion in accordance with its CTE.
• the expansion of the first layer 12 in the radial direction may cause the lower portion of the sidewall 16 to deflect outwardly, in-turn causing the edges of the first and second layers 12, 14 to be pulled or deflected upwardly, resulting in a concave deflection of the platen 10 as shown in FIG. 2C.
• the contour of the top surface of the platen 10 may be made to more closely match the contour of the bottom surface of the wafer 28, thus resulting in better electrostatic or mechanical coupling between the platen 10 and the wafer 28 as described above.
• the first and second layers 12, 14 may be heated to temperatures between 300 degrees Celsius and 800 degrees Celsius to achieve a target amount of deflection.
• the platen 10 may exhibit a convex deflection of 18 thou when the second layer is heated to a temperature of 500 degrees Celsius and may exhibit a convex deflection of 18 thou when the first layer is heated to a temperature of 500 degrees Celsius.
• the present disclosure is not limited in this regard.
• the degree of deflection in the platen 10 will depend on a number of factors, including, and not limited to, the CTEs of the first and second layers 12, 14, the amount of heat applied to the first and second layers 12, 14, the diameters of the first and second layers 12, 14, and the thicknesses of the first and second layers 12, 14.
• the deflection stress on the first and second layers is the deflection stress on the first and second layers
• the platen 10 may return to its original, generally planar state as shown in FIG. IB.
• the platen 10 may be controllably deflected to varying degrees (e.g., from 0 to 20 thou) in either direction (i.e., concave or convex) to match or approach the contours of wafers having various degrees of deflection disposed thereon to provide effective electrostatic or mechanical clamping therebetween.
• the deflection of an incoming wafer may be measured (e.g., via contact sensors, image analysis, etc.) and a controller 29 operatively coupled to the platen 10 may, upon receiving data representing the measured deflection of the wafer, dictate operation of the first and second heating elements 20, 22 to deflect the platen 10 to match or approach the contour of the incoming wafer.
• first and second heating elements 20, 22 for controllably and selectively heating the first and second layers 12, 14
• first and second heating elements 20, 22 described above and shown in the figures may instead be cooling elements for controllably and selectively cooling the first and second layers 12, 14.
• first and second heating elements 20, 22 may alternatively be referred to herein as “cooling elements 20, 22” or, more generically, as “temperature control elements 20, 22.” Cooling elements may be, or may include, various channels, conduits, tubes, pipes, ducts, etc.
• the cooling elements 20, 22 may be used to cool the first and/or the second layers 12, 14 to temperatures in a range between 0 degrees Celsius and -150 degrees Celsius, for example.
• the cooled layer may exhibit thermal contraction in accordance with its CTE.
• the contraction of the cooled layer in the radial direction may cause the sidewall 16 to be deflected, in-tum causing the edges of the first and second layers 12, 14 to be pulled or deflected upwardly or downwardly depending on the layer being cooled, resulting in a concave or convex deflection of the platen 10 as shown in FIGS. 2B and 2C.
• the first and second layers 12, 14 may include heating elements and cooling elements like those described above.
• FIG. 3 a flow diagram illustrating an exemplary method for deflecting a platen in accordance with the present disclosure is shown. The method will now be described in conjunction with the illustrations of the platen 10 shown in FIGS. 1A- 2C.
• the first layer 12 and the second layer 14 may be provided and may be coupled to the annular sidewall 16, such as by brazing, welding, thermally-resistant adhesives, various mechanical fasteners, glass bonding, and/or other techniques suitable for bonding or fastening the material of the sidewall 16 to the materials of the first and second layers 12, 14.
• the first layer 12 and the second layer 14 may be disposed in a parallel, spaced-apart relationship defining the gap 15 therebetween, and the gap 15 may be held at or near vacuum to provide thermal insulation between the first and second layers 12, 14.
• the first and second layers 12, 14 may include respective first and second temperature control elements 20, 22 associated therewith (e.g., embedded therein).
• the second layer 14 may be provided with the electrodes 23 associated therewith (e.g., embedded therein) for facilitating electrostatic clamping of wafers to the platen 10.
• the electrodes 23 may be omitted and the mechanical clamp 27 may be implemented.
• the deflection of an incoming wafer may be measured (e.g., via contact sensors, imaging, etc.) and the controller 29 operatively coupled to the platen 10 may, upon receiving data representing the measured deflection of the wafer, dictate operation of the first and second temperature control elements 20, 22 to deflect the platen 10 to match or approach the contour of the incoming wafer.
• the second temperature control element 22 may, at block 130a of the exemplary method, be activated to heat the second layer 14 relative to the first layer 12. When heated, the second layer 14 may exhibit thermal expansion in accordance with its CTE.
• the expansion of the second layer 14 in the radial direction may cause the upper portion of the sidewall 16 to deflect outwardly, in-turn causing the edges of the first and second layers 12, 14 to be pulled or deflected downwardly, resulting in a convex deflection of the platen 10 as shown in FIG. 2B.
• the contour of the top surface of the platen 10 may be made to more closely match the contour of the bottom surface of the incoming wafer.
• the first temperature control element 20 may, at block 130b of the exemplary method, be activated to heat the first layer 12 relative to the second layer 14. When heated, the first layer 12 may exhibit thermal expansion in accordance with its CTE.
• the expansion of the first layer 12 in the radial direction may cause the lower portion of the sidewall 16 to deflect outwardly, in- turn causing the edges of the first and second layers 12, 14 to be pulled or deflected upwardly, resulting in a concave deflection of the platen 10 as shown in FIG. 2C.
• the contour of the top surface of the platen 10 may be made to more closely match the contour of the incoming wafer.
• the first temperature control element 20 may, at block 130c of the exemplary method, be activated to cool the first layer 12 relative to the second layer 14.
• the first layer 12 may exhibit thermal contraction in accordance with its CTE.
• the contraction of the first layer 12 in the radial direction may cause the lower portion of the sidewall 16 to deflect inwardly, in-turn causing the edges of the first and second layers 12, 14 to be pulled or deflected downwardly, resulting in a convex deflection of the platen 10 as shown in FIG. 2B.
• the contour of the top surface of the platen 10 may be made to more closely match the contour of the incoming wafer.
• the second temperature control element 22 may, at block 130d of the exemplary method, be activated to cool the second layer 14 relative to the first layer 12.
• the second layer 14 may exhibit thermal contraction in accordance with its CTE.
• the contraction of the second layer 14 in the radial direction may cause the upper portion of the sidewall 16 to deflect inwardly, in-tum causing the edges of the first and second layers 12, 14 to be pulled or deflected upwardly, resulting in a concave deflection of the platen 10 as shown in FIG. 2C.
• the contour of the top surface of the platen 10 may be made to more closely match the contour of the bottom surface of the incoming wafer.
• the above- described deflectable platen 10 provides distinct advantages relative to conventional platens.
• the platen 10 can be selectively and dynamically deflected through the controlled application of heat (or cooling) to the first and second layers 12, 14 to rapidly and conveniently facilitate effective clamping with wafers having various degrees of concave or convex deflection.
• the ability of the platen 10 conform to the contour of a wafer disposed thereon facilities effective thermal communication between the platen 10 and the wafer (e.g., for heating and/or cooling the wafer).

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• Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

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• 2019
  • 2019-11-05 US US16/674,340 patent/US11133213B2/en active Active
• 2020
  • 2020-10-24 JP JP2022525211A patent/JP7801215B2/ja active Active
  • 2020-10-24 CN CN202080076072.8A patent/CN114631177B/zh active Active
  • 2020-10-24 KR KR1020227018492A patent/KR20220093176A/ko active Pending
  • 2020-10-24 WO PCT/US2020/057234 patent/WO2021091708A1/en not_active Ceased
  • 2020-10-29 TW TW109137685A patent/TWI873213B/zh active

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